git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s

   1 /*\r
   2  * FreeRTOS Kernel V10.2.1\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /* Including FreeRTOSConfig.h here will cause build errors if the header file\r
  29 contains code not understood by the assembler - for example the 'extern' keyword.\r
  30 To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\r
  31 the code is included in C files but excluded by the preprocessor in assembly\r
  32 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\r
  33 #include "FreeRTOSConfig.h"\r
  34 \r
  35         EXTERN pxCurrentTCB\r
  36         EXTERN vTaskSwitchContext\r
  37         EXTERN vPortSVCHandler_C\r
  38 \r
  39         PUBLIC xIsPrivileged\r
  40         PUBLIC vResetPrivilege\r
  41         PUBLIC vRestoreContextOfFirstTask\r
  42         PUBLIC vRaisePrivilege\r
  43         PUBLIC vStartFirstTask\r
  44         PUBLIC ulSetInterruptMask\r
  45         PUBLIC vClearInterruptMask\r
  46         PUBLIC PendSV_Handler\r
  47         PUBLIC SVC_Handler\r
  48 /*-----------------------------------------------------------*/\r
  49 \r
  50 /*---------------- Unprivileged Functions -------------------*/\r
  51 \r
  52 /*-----------------------------------------------------------*/\r
  53 \r
  54         SECTION .text:CODE:NOROOT(2)\r
  55         THUMB\r
  56 /*-----------------------------------------------------------*/\r
  57 \r
  58 xIsPrivileged:\r
  59         mrs r0, control                                                 /* r0 = CONTROL. */\r
  60         tst r0, #1                                                              /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
  61         ite ne\r
  62         movne r0, #0                                                    /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
  63         moveq r0, #1                                                    /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
  64         bx lr                                                                   /* Return. */\r
  65 /*-----------------------------------------------------------*/\r
  66 \r
  67 vResetPrivilege:\r
  68         mrs r0, control                                                 /* r0 = CONTROL. */\r
  69         orr r0, r0, #1                                                  /* r0 = r0 | 1. */\r
  70         msr control, r0                                                 /* CONTROL = r0. */\r
  71         bx lr                                                                   /* Return to the caller. */\r
  72 /*-----------------------------------------------------------*/\r
  73 \r
  74 /*----------------- Privileged Functions --------------------*/\r
  75 \r
  76 /*-----------------------------------------------------------*/\r
  77 \r
  78         SECTION privileged_functions:CODE:NOROOT(2)\r
  79         THUMB\r
  80 /*-----------------------------------------------------------*/\r
  81 \r
  82 vRestoreContextOfFirstTask:\r
  83         ldr  r2, =pxCurrentTCB                                  /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  84         ldr  r1, [r2]                                                   /* Read pxCurrentTCB. */\r
  85         ldr  r0, [r1]                                                   /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  86 \r
  87 #if ( configENABLE_MPU == 1 )\r
  88         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */\r
  89         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  90         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
  91         bic r4, r4, #1                                                  /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
  92         str r4, [r2]                                                    /* Disable MPU. */\r
  93 \r
  94         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
  95         ldr r3, [r1]                                                    /* r3 = *r1 i.e. r3 = MAIR0. */\r
  96         ldr r2, =0xe000edc0                                             /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
  97         str r3, [r2]                                                    /* Program MAIR0. */\r
  98         ldr r2, =0xe000ed98                                             /* r2 = 0xe000ed98 [Location of RNR]. */\r
  99         movs r3, #4                                                             /* r3 = 4. */\r
 100         str r3, [r2]                                                    /* Program RNR = 4. */\r
 101         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 102         ldr r2, =0xe000ed9c                                             /* r2 = 0xe000ed9c [Location of RBAR]. */\r
 103         ldmia r1!, {r4-r11}                                             /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 104         stmia r2!, {r4-r11}                                             /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 105 \r
 106         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 107         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 108         orr r4, r4, #1                                                  /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 109         str r4, [r2]                                                    /* Enable MPU. */\r
 110         dsb                                                                             /* Force memory writes before continuing. */\r
 111 #endif /* configENABLE_MPU */\r
 112 \r
 113 #if ( configENABLE_MPU == 1 )\r
 114         ldm  r0!, {r1-r3}                                               /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
 115         msr  psplim, r1                                                 /* Set this task's PSPLIM value. */\r
 116         msr  control, r2                                                /* Set this task's CONTROL value. */\r
 117         adds r0, #32                                                    /* Discard everything up to r0. */\r
 118         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 119         isb\r
 120         bx   r3                                                                 /* Finally, branch to EXC_RETURN. */\r
 121 #else /* configENABLE_MPU */\r
 122         ldm  r0!, {r1-r2}                                               /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
 123         msr  psplim, r1                                                 /* Set this task's PSPLIM value. */\r
 124         movs r1, #2                                                             /* r1 = 2. */\r
 125         msr  CONTROL, r1                                                /* Switch to use PSP in the thread mode. */\r
 126         adds r0, #32                                                    /* Discard everything up to r0. */\r
 127         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 128         isb\r
 129         bx   r2                                                                 /* Finally, branch to EXC_RETURN. */\r
 130 #endif /* configENABLE_MPU */\r
 131 /*-----------------------------------------------------------*/\r
 132 \r
 133 vRaisePrivilege:\r
 134         mrs  r0, control                                                /* Read the CONTROL register. */\r
 135         bic r0, r0, #1                                                  /* Clear the bit 0. */\r
 136         msr  control, r0                                                /* Write back the new CONTROL value. */\r
 137         bx lr                                                                   /* Return to the caller. */\r
 138 /*-----------------------------------------------------------*/\r
 139 \r
 140 vStartFirstTask:\r
 141         ldr r0, =0xe000ed08                                             /* Use the NVIC offset register to locate the stack. */\r
 142         ldr r0, [r0]                                                    /* Read the VTOR register which gives the address of vector table. */\r
 143         ldr r0, [r0]                                                    /* The first entry in vector table is stack pointer. */\r
 144         msr msp, r0                                                             /* Set the MSP back to the start of the stack. */\r
 145         cpsie i                                                                 /* Globally enable interrupts. */\r
 146         cpsie f\r
 147         dsb\r
 148         isb\r
 149         svc 2                                                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
 150 /*-----------------------------------------------------------*/\r
 151 \r
 152 ulSetInterruptMask:\r
 153         mrs r0, basepri                                                 /* r0 = basepri. Return original basepri value. */\r
 154         mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
 155         msr basepri, r1                                                 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 156         dsb\r
 157         isb\r
 158         bx lr                                                                   /* Return. */\r
 159 /*-----------------------------------------------------------*/\r
 160 \r
 161 vClearInterruptMask:\r
 162         msr basepri, r0                                                 /* basepri = ulMask. */\r
 163         dsb\r
 164         isb\r
 165         bx lr                                                                   /* Return. */\r
 166 /*-----------------------------------------------------------*/\r
 167 \r
 168 PendSV_Handler:\r
 169         mrs r0, psp                                                             /* Read PSP in r0. */\r
 170 #if ( configENABLE_FPU == 1 )\r
 171         tst lr, #0x10                                                   /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 172         it eq\r
 173         vstmdbeq r0!, {s16-s31}                                 /* Store the FPU registers which are not saved automatically. */\r
 174 #endif /* configENABLE_FPU */\r
 175 #if ( configENABLE_MPU == 1 )\r
 176         mrs r1, psplim                                                  /* r1 = PSPLIM. */\r
 177         mrs r2, control                                                 /* r2 = CONTROL. */\r
 178         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */\r
 179         stmdb r0!, {r1-r11}                                             /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
 180 #else /* configENABLE_MPU */\r
 181         mrs r2, psplim                                                  /* r2 = PSPLIM. */\r
 182         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */\r
 183         stmdb r0!, {r2-r11}                                             /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
 184 #endif /* configENABLE_MPU */\r
 185 \r
 186         ldr r2, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 187         ldr r1, [r2]                                                    /* Read pxCurrentTCB. */\r
 188         str r0, [r1]                                                    /* Save the new top of stack in TCB. */\r
 189 \r
 190         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
 191         msr basepri, r0                                                 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 192         dsb\r
 193         isb\r
 194         bl vTaskSwitchContext\r
 195         mov r0, #0                                                              /* r0 = 0. */\r
 196         msr basepri, r0                                                 /* Enable interrupts. */\r
 197 \r
 198         ldr r2, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 199         ldr r1, [r2]                                                    /* Read pxCurrentTCB. */\r
 200         ldr r0, [r1]                                                    /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
 201 \r
 202 #if ( configENABLE_MPU == 1 )\r
 203         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */\r
 204         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 205         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 206         bic r4, r4, #1                                                  /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
 207         str r4, [r2]                                                    /* Disable MPU. */\r
 208 \r
 209         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
 210         ldr r3, [r1]                                                    /* r3 = *r1 i.e. r3 = MAIR0. */\r
 211         ldr r2, =0xe000edc0                                             /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 212         str r3, [r2]                                                    /* Program MAIR0. */\r
 213         ldr r2, =0xe000ed98                                             /* r2 = 0xe000ed98 [Location of RNR]. */\r
 214         movs r3, #4                                                             /* r3 = 4. */\r
 215         str r3, [r2]                                                    /* Program RNR = 4. */\r
 216         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 217         ldr r2, =0xe000ed9c                                             /* r2 = 0xe000ed9c [Location of RBAR]. */\r
 218         ldmia r1!, {r4-r11}                                             /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 219         stmia r2!, {r4-r11}                                             /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 220 \r
 221         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 222         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 223         orr r4, r4, #1                                                  /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 224         str r4, [r2]                                                    /* Enable MPU. */\r
 225         dsb                                                                             /* Force memory writes before continuing. */\r
 226 #endif /* configENABLE_MPU */\r
 227 \r
 228 #if ( configENABLE_MPU == 1 )\r
 229         ldmia r0!, {r1-r11}                                             /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
 230 #else /* configENABLE_MPU */\r
 231         ldmia r0!, {r2-r11}                                             /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
 232 #endif /* configENABLE_MPU */\r
 233 \r
 234 #if ( configENABLE_FPU == 1 )\r
 235         tst r3, #0x10                                                   /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 236         it eq\r
 237         vldmiaeq r0!, {s16-s31}                                 /* Restore the FPU registers which are not restored automatically. */\r
 238 #endif /* configENABLE_FPU */\r
 239 \r
 240  #if ( configENABLE_MPU == 1 )\r
 241         msr psplim, r1                                                  /* Restore the PSPLIM register value for the task. */\r
 242         msr control, r2                                                 /* Restore the CONTROL register value for the task. */\r
 243 #else /* configENABLE_MPU */\r
 244         msr psplim, r2                                                  /* Restore the PSPLIM register value for the task. */\r
 245 #endif /* configENABLE_MPU */\r
 246         msr psp, r0                                                             /* Remember the new top of stack for the task. */\r
 247         bx r3\r
 248 /*-----------------------------------------------------------*/\r
 249 \r
 250 SVC_Handler:\r
 251         tst lr, #4\r
 252         ite eq\r
 253         mrseq r0, msp\r
 254         mrsne r0, psp\r
 255         b vPortSVCHandler_C\r
 256 /*-----------------------------------------------------------*/\r
 257 \r
 258         END\r