2 * FreeRTOS Kernel V10.0.0
\r
3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software. If you wish to use our Amazon
\r
14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
\r
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
23 * http://www.FreeRTOS.org
\r
24 * http://aws.amazon.com/freertos
\r
26 * 1 tab == 4 spaces!
\r
29 /*-----------------------------------------------------------
\r
30 * Implementation of functions defined in portable.h for the ARM CM4F port.
\r
31 *----------------------------------------------------------*/
\r
34 #include <intrinsics.h>
\r
36 /* Scheduler includes. */
\r
37 #include "FreeRTOS.h"
\r
41 #error This port can only be used when the project options are configured to enable hardware floating point support.
\r
44 #if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
\r
45 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
\r
48 #ifndef configSYSTICK_CLOCK_HZ
\r
49 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
\r
50 /* Ensure the SysTick is clocked at the same frequency as the core. */
\r
51 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
\r
53 /* The way the SysTick is clocked is not modified in case it is not the same
\r
55 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
\r
58 /* Constants required to manipulate the core. Registers first... */
\r
59 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
\r
60 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
\r
61 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
\r
62 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
\r
63 /* ...then bits in the registers. */
\r
64 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
\r
65 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
\r
66 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
\r
67 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
\r
68 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
\r
70 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
\r
72 #define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
\r
73 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
\r
74 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
\r
76 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
\r
77 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
\r
79 /* Constants required to check the validity of an interrupt priority. */
\r
80 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
\r
81 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
\r
82 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
\r
83 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
\r
84 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
\r
85 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
\r
86 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
\r
87 #define portPRIGROUP_SHIFT ( 8UL )
\r
89 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
\r
90 #define portVECTACTIVE_MASK ( 0xFFUL )
\r
92 /* Constants required to manipulate the VFP. */
\r
93 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
\r
94 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
\r
96 /* Constants required to set up the initial stack. */
\r
97 #define portINITIAL_XPSR ( 0x01000000 )
\r
98 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
\r
100 /* The systick is a 24-bit counter. */
\r
101 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
\r
103 /* A fiddle factor to estimate the number of SysTick counts that would have
\r
104 occurred while the SysTick counter is stopped during tickless idle
\r
106 #define portMISSED_COUNTS_FACTOR ( 45UL )
\r
108 /* For strict compliance with the Cortex-M spec the task start address should
\r
109 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
\r
110 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
\r
113 * Setup the timer to generate the tick interrupts. The implementation in this
\r
114 * file is weak to allow application writers to change the timer used to
\r
115 * generate the tick interrupt.
\r
117 void vPortSetupTimerInterrupt( void );
\r
120 * Exception handlers.
\r
122 void xPortSysTickHandler( void );
\r
125 * Start first task is a separate function so it can be tested in isolation.
\r
127 extern void vPortStartFirstTask( void );
\r
132 extern void vPortEnableVFP( void );
\r
135 * Used to catch tasks that attempt to return from their implementing function.
\r
137 static void prvTaskExitError( void );
\r
139 /*-----------------------------------------------------------*/
\r
141 /* Each task maintains its own interrupt status in the critical nesting
\r
143 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
\r
146 * The number of SysTick increments that make up one tick period.
\r
148 #if( configUSE_TICKLESS_IDLE == 1 )
\r
149 static uint32_t ulTimerCountsForOneTick = 0;
\r
150 #endif /* configUSE_TICKLESS_IDLE */
\r
153 * The maximum number of tick periods that can be suppressed is limited by the
\r
154 * 24 bit resolution of the SysTick timer.
\r
156 #if( configUSE_TICKLESS_IDLE == 1 )
\r
157 static uint32_t xMaximumPossibleSuppressedTicks = 0;
\r
158 #endif /* configUSE_TICKLESS_IDLE */
\r
161 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
\r
162 * power functionality only.
\r
164 #if( configUSE_TICKLESS_IDLE == 1 )
\r
165 static uint32_t ulStoppedTimerCompensation = 0;
\r
166 #endif /* configUSE_TICKLESS_IDLE */
\r
169 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
\r
170 * FreeRTOS API functions are not called from interrupts that have been assigned
\r
171 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
173 #if( configASSERT_DEFINED == 1 )
\r
174 static uint8_t ucMaxSysCallPriority = 0;
\r
175 static uint32_t ulMaxPRIGROUPValue = 0;
\r
176 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
\r
177 #endif /* configASSERT_DEFINED */
\r
179 /*-----------------------------------------------------------*/
\r
182 * See header file for description.
\r
184 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
186 /* Simulate the stack frame as it would be created by a context switch
\r
189 /* Offset added to account for the way the MCU uses the stack on entry/exit
\r
190 of interrupts, and to ensure alignment. */
\r
193 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
195 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
\r
197 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
\r
199 /* Save code space by skipping register initialisation. */
\r
200 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
201 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
203 /* A save method is being used that requires each task to maintain its
\r
204 own exec return value. */
\r
206 *pxTopOfStack = portINITIAL_EXC_RETURN;
\r
208 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
\r
210 return pxTopOfStack;
\r
212 /*-----------------------------------------------------------*/
\r
214 static void prvTaskExitError( void )
\r
216 /* A function that implements a task must not exit or attempt to return to
\r
217 its caller as there is nothing to return to. If a task wants to exit it
\r
218 should instead call vTaskDelete( NULL ).
\r
220 Artificially force an assert() to be triggered if configASSERT() is
\r
221 defined, then stop here so application writers can catch the error. */
\r
222 configASSERT( uxCriticalNesting == ~0UL );
\r
223 portDISABLE_INTERRUPTS();
\r
226 /*-----------------------------------------------------------*/
\r
229 * See header file for description.
\r
231 BaseType_t xPortStartScheduler( void )
\r
233 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
\r
234 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
\r
235 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
\r
237 /* This port can be used on all revisions of the Cortex-M7 core other than
\r
238 the r0p1 parts. r0p1 parts should use the port from the
\r
239 /source/portable/GCC/ARM_CM7/r0p1 directory. */
\r
240 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
\r
241 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
\r
243 #if( configASSERT_DEFINED == 1 )
\r
245 volatile uint32_t ulOriginalPriority;
\r
246 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
\r
247 volatile uint8_t ucMaxPriorityValue;
\r
249 /* Determine the maximum priority from which ISR safe FreeRTOS API
\r
250 functions can be called. ISR safe functions are those that end in
\r
251 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
\r
252 ensure interrupt entry is as fast and simple as possible.
\r
254 Save the interrupt priority value that is about to be clobbered. */
\r
255 ulOriginalPriority = *pucFirstUserPriorityRegister;
\r
257 /* Determine the number of priority bits available. First write to all
\r
259 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
261 /* Read the value back to see how many bits stuck. */
\r
262 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
\r
264 /* Use the same mask on the maximum system call priority. */
\r
265 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
\r
267 /* Calculate the maximum acceptable priority group value for the number
\r
268 of bits read back. */
\r
269 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
\r
270 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
\r
272 ulMaxPRIGROUPValue--;
\r
273 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
\r
276 #ifdef __NVIC_PRIO_BITS
\r
278 /* Check the CMSIS configuration that defines the number of
\r
279 priority bits matches the number of priority bits actually queried
\r
280 from the hardware. */
\r
281 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
\r
285 #ifdef configPRIO_BITS
\r
287 /* Check the FreeRTOS configuration that defines the number of
\r
288 priority bits matches the number of priority bits actually queried
\r
289 from the hardware. */
\r
290 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
\r
294 /* Shift the priority group value back to its position within the AIRCR
\r
296 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
\r
297 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
\r
299 /* Restore the clobbered interrupt priority register to its original
\r
301 *pucFirstUserPriorityRegister = ulOriginalPriority;
\r
303 #endif /* conifgASSERT_DEFINED */
\r
305 /* Make PendSV and SysTick the lowest priority interrupts. */
\r
306 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
\r
307 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
\r
309 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
311 vPortSetupTimerInterrupt();
\r
313 /* Initialise the critical nesting count ready for the first task. */
\r
314 uxCriticalNesting = 0;
\r
316 /* Ensure the VFP is enabled - it should be anyway. */
\r
319 /* Lazy save always. */
\r
320 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
\r
322 /* Start the first task. */
\r
323 vPortStartFirstTask();
\r
325 /* Should not get here! */
\r
328 /*-----------------------------------------------------------*/
\r
330 void vPortEndScheduler( void )
\r
332 /* Not implemented in ports where there is nothing to return to.
\r
333 Artificially force an assert. */
\r
334 configASSERT( uxCriticalNesting == 1000UL );
\r
336 /*-----------------------------------------------------------*/
\r
338 void vPortEnterCritical( void )
\r
340 portDISABLE_INTERRUPTS();
\r
341 uxCriticalNesting++;
\r
343 /* This is not the interrupt safe version of the enter critical function so
\r
344 assert() if it is being called from an interrupt context. Only API
\r
345 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
346 the critical nesting count is 1 to protect against recursive calls if the
\r
347 assert function also uses a critical section. */
\r
348 if( uxCriticalNesting == 1 )
\r
350 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
\r
353 /*-----------------------------------------------------------*/
\r
355 void vPortExitCritical( void )
\r
357 configASSERT( uxCriticalNesting );
\r
358 uxCriticalNesting--;
\r
359 if( uxCriticalNesting == 0 )
\r
361 portENABLE_INTERRUPTS();
\r
364 /*-----------------------------------------------------------*/
\r
366 void xPortSysTickHandler( void )
\r
368 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
\r
369 executes all interrupts must be unmasked. There is therefore no need to
\r
370 save and then restore the interrupt mask value as its value is already
\r
372 portDISABLE_INTERRUPTS();
\r
374 /* Increment the RTOS tick. */
\r
375 if( xTaskIncrementTick() != pdFALSE )
\r
377 /* A context switch is required. Context switching is performed in
\r
378 the PendSV interrupt. Pend the PendSV interrupt. */
\r
379 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
382 portENABLE_INTERRUPTS();
\r
384 /*-----------------------------------------------------------*/
\r
386 #if( configUSE_TICKLESS_IDLE == 1 )
\r
388 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
\r
390 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
\r
391 TickType_t xModifiableIdleTime;
\r
393 /* Make sure the SysTick reload value does not overflow the counter. */
\r
394 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
396 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
399 /* Stop the SysTick momentarily. The time the SysTick is stopped for
\r
400 is accounted for as best it can be, but using the tickless mode will
\r
401 inevitably result in some tiny drift of the time maintained by the
\r
402 kernel with respect to calendar time. */
\r
403 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
\r
405 /* Calculate the reload value required to wait xExpectedIdleTime
\r
406 tick periods. -1 is used because this code will execute part way
\r
407 through one of the tick periods. */
\r
408 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
\r
409 if( ulReloadValue > ulStoppedTimerCompensation )
\r
411 ulReloadValue -= ulStoppedTimerCompensation;
\r
414 /* Enter a critical section but don't use the taskENTER_CRITICAL()
\r
415 method as that will mask interrupts that should exit sleep mode. */
\r
416 __disable_interrupt();
\r
420 /* If a context switch is pending or a task is waiting for the scheduler
\r
421 to be unsuspended then abandon the low power entry. */
\r
422 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
424 /* Restart from whatever is left in the count register to complete
\r
425 this tick period. */
\r
426 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
428 /* Restart SysTick. */
\r
429 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
431 /* Reset the reload register to the value required for normal tick
\r
433 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
435 /* Re-enable interrupts - see comments above __disable_interrupt()
\r
437 __enable_interrupt();
\r
441 /* Set the new reload value. */
\r
442 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
444 /* Clear the SysTick count flag and set the count value back to
\r
446 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
448 /* Restart SysTick. */
\r
449 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
451 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
\r
452 set its parameter to 0 to indicate that its implementation contains
\r
453 its own wait for interrupt or wait for event instruction, and so wfi
\r
454 should not be executed again. However, the original expected idle
\r
455 time variable must remain unmodified, so a copy is taken. */
\r
456 xModifiableIdleTime = xExpectedIdleTime;
\r
457 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
458 if( xModifiableIdleTime > 0 )
\r
464 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
466 /* Re-enable interrupts to allow the interrupt that brought the MCU
\r
467 out of sleep mode to execute immediately. see comments above
\r
468 __disable_interrupt() call above. */
\r
469 __enable_interrupt();
\r
473 /* Disable interrupts again because the clock is about to be stopped
\r
474 and interrupts that execute while the clock is stopped will increase
\r
475 any slippage between the time maintained by the RTOS and calendar
\r
477 __disable_interrupt();
\r
481 /* Disable the SysTick clock without reading the
\r
482 portNVIC_SYSTICK_CTRL_REG register to ensure the
\r
483 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
\r
484 the time the SysTick is stopped for is accounted for as best it can
\r
485 be, but using the tickless mode will inevitably result in some tiny
\r
486 drift of the time maintained by the kernel with respect to calendar
\r
488 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
\r
490 /* Determine if the SysTick clock has already counted to zero and
\r
491 been set back to the current reload value (the reload back being
\r
492 correct for the entire expected idle time) or if the SysTick is yet
\r
493 to count to zero (in which case an interrupt other than the SysTick
\r
494 must have brought the system out of sleep mode). */
\r
495 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
497 uint32_t ulCalculatedLoadValue;
\r
499 /* The tick interrupt is already pending, and the SysTick count
\r
500 reloaded with ulReloadValue. Reset the
\r
501 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
503 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
505 /* Don't allow a tiny value, or values that have somehow
\r
506 underflowed because the post sleep hook did something
\r
507 that took too long. */
\r
508 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
510 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
513 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
515 /* As the pending tick will be processed as soon as this
\r
516 function exits, the tick value maintained by the tick is stepped
\r
517 forward by one less than the time spent waiting. */
\r
518 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
522 /* Something other than the tick interrupt ended the sleep.
\r
523 Work out how long the sleep lasted rounded to complete tick
\r
524 periods (not the ulReload value which accounted for part
\r
526 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
528 /* How many complete tick periods passed while the processor
\r
530 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
532 /* The reload value is set to whatever fraction of a single tick
\r
534 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
537 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
538 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
540 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
541 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
542 vTaskStepTick( ulCompleteTickPeriods );
\r
543 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
545 /* Exit with interrpts enabled. */
\r
546 __enable_interrupt();
\r
550 #endif /* configUSE_TICKLESS_IDLE */
\r
551 /*-----------------------------------------------------------*/
\r
554 * Setup the systick timer to generate the tick interrupts at the required
\r
557 __weak void vPortSetupTimerInterrupt( void )
\r
559 /* Calculate the constants required to configure the tick interrupt. */
\r
560 #if( configUSE_TICKLESS_IDLE == 1 )
\r
562 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
563 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
564 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
566 #endif /* configUSE_TICKLESS_IDLE */
\r
568 /* Stop and clear the SysTick. */
\r
569 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
570 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
572 /* Configure SysTick to interrupt at the requested rate. */
\r
573 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
574 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
576 /*-----------------------------------------------------------*/
\r
578 #if( configASSERT_DEFINED == 1 )
\r
580 void vPortValidateInterruptPriority( void )
\r
582 uint32_t ulCurrentInterrupt;
\r
583 uint8_t ucCurrentPriority;
\r
585 /* Obtain the number of the currently executing interrupt. */
\r
586 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
\r
588 /* Is the interrupt number a user defined interrupt? */
\r
589 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
591 /* Look up the interrupt's priority. */
\r
592 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
594 /* The following assertion will fail if a service routine (ISR) for
\r
595 an interrupt that has been assigned a priority above
\r
596 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
597 function. ISR safe FreeRTOS API functions must *only* be called
\r
598 from interrupts that have been assigned a priority at or below
\r
599 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
601 Numerically low interrupt priority numbers represent logically high
\r
602 interrupt priorities, therefore the priority of the interrupt must
\r
603 be set to a value equal to or numerically *higher* than
\r
604 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
606 Interrupts that use the FreeRTOS API must not be left at their
\r
607 default priority of zero as that is the highest possible priority,
\r
608 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
609 and therefore also guaranteed to be invalid.
\r
611 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
612 interrupt entry is as fast and simple as possible.
\r
614 The following links provide detailed information:
\r
615 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
616 http://www.freertos.org/FAQHelp.html */
\r
617 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
620 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
621 that define each interrupt's priority to be split between bits that
\r
622 define the interrupt's pre-emption priority bits and bits that define
\r
623 the interrupt's sub-priority. For simplicity all bits must be defined
\r
624 to be pre-emption priority bits. The following assertion will fail if
\r
625 this is not the case (if some bits represent a sub-priority).
\r
627 If the application only uses CMSIS libraries for interrupt
\r
628 configuration then the correct setting can be achieved on all Cortex-M
\r
629 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
630 scheduler. Note however that some vendor specific peripheral libraries
\r
631 assume a non-zero priority group setting, in which cases using a value
\r
632 of zero will result in unpredictable behaviour. */
\r
633 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
636 #endif /* configASSERT_DEFINED */
\r