2 * FreeRTOS Kernel V10.2.0
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the ARM CM4F port.
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30 *----------------------------------------------------------*/
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33 #include <intrinsics.h>
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35 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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36 all the API functions to use the MPU wrappers. That should only be done when
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37 task.h is included from an application file. */
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38 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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40 /* Scheduler includes. */
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41 #include "FreeRTOS.h"
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44 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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46 #warning This is not yet a documented port as it has not been fully tested, so no demo projects that use this port are provided.
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49 #error This port can only be used when the project options are configured to enable hardware floating point support.
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52 #if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
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53 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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56 #ifndef configSYSTICK_CLOCK_HZ
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57 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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58 /* Ensure the SysTick is clocked at the same frequency as the core. */
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59 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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61 /* The way the SysTick is clocked is not modified in case it is not the same
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63 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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66 /* Constants required to manipulate the core. Registers first... */
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67 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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68 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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69 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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70 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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71 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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72 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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73 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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75 /* Constants required to access and manipulate the MPU. */
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76 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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77 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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78 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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79 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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80 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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81 #define portMPU_ENABLE ( 0x01UL )
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82 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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83 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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84 #define portMPU_REGION_VALID ( 0x10UL )
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85 #define portMPU_REGION_ENABLE ( 0x01UL )
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86 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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87 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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89 /* ...then bits in the registers. */
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90 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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91 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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92 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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93 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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94 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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96 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
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98 #define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
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99 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
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100 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
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102 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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103 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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104 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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106 /* Constants required to check the validity of an interrupt priority. */
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107 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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108 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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109 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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110 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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111 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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112 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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113 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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114 #define portPRIGROUP_SHIFT ( 8UL )
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116 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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117 #define portVECTACTIVE_MASK ( 0xFFUL )
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119 /* Constants required to manipulate the VFP. */
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120 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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121 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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123 /* Constants required to set up the initial stack. */
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124 #define portINITIAL_XPSR ( 0x01000000 )
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125 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
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126 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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127 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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129 /* Offsets in the stack to the parameters when inside the SVC handler. */
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130 #define portOFFSET_TO_PC ( 6 )
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132 /* The systick is a 24-bit counter. */
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133 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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135 /* A fiddle factor to estimate the number of SysTick counts that would have
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136 occurred while the SysTick counter is stopped during tickless idle
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138 #define portMISSED_COUNTS_FACTOR ( 45UL )
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140 /* For strict compliance with the Cortex-M spec the task start address should
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141 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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142 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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145 * Configure a number of standard MPU regions that are used by all tasks.
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147 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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150 * Return the smallest MPU region size that a given number of bytes will fit
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151 * into. The region size is returned as the value that should be programmed
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152 * into the region attribute register for that region.
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154 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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157 * Setup the timer to generate the tick interrupts. The implementation in this
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158 * file is weak to allow application writers to change the timer used to
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159 * generate the tick interrupt.
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161 void vPortSetupTimerInterrupt( void );
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164 * Exception handlers.
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166 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
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169 * Start first task is a separate function so it can be tested in isolation.
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171 extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
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176 extern void vPortEnableVFP( void );
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179 * The C portion of the SVC handler.
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181 void vPortSVCHandler_C( uint32_t *pulParam );
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184 * Called from the SVC handler used to start the scheduler.
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186 extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
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189 * @brief Calls the port specific code to raise the privilege.
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191 * @return pdFALSE if privilege was raised, pdTRUE otherwise.
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193 extern BaseType_t xPortRaisePrivilege( void );
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196 * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
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197 * code to reset the privilege, otherwise does nothing.
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199 extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
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200 /*-----------------------------------------------------------*/
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202 /* Each task maintains its own interrupt status in the critical nesting
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204 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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207 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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208 * FreeRTOS API functions are not called from interrupts that have been assigned
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209 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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211 #if( configASSERT_DEFINED == 1 )
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212 static uint8_t ucMaxSysCallPriority = 0;
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213 static uint32_t ulMaxPRIGROUPValue = 0;
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214 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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215 #endif /* configASSERT_DEFINED */
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217 /*-----------------------------------------------------------*/
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220 * See header file for description.
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222 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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224 /* Simulate the stack frame as it would be created by a context switch
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227 /* Offset added to account for the way the MCU uses the stack on entry/exit
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228 of interrupts, and to ensure alignment. */
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231 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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233 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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235 *pxTopOfStack = ( StackType_t ) 0; /* LR */
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237 /* Save code space by skipping register initialisation. */
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238 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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239 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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241 /* A save method is being used that requires each task to maintain its
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242 own exec return value. */
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244 *pxTopOfStack = portINITIAL_EXC_RETURN;
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246 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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248 if( xRunPrivileged == pdTRUE )
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250 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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254 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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257 return pxTopOfStack;
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259 /*-----------------------------------------------------------*/
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261 void vPortSVCHandler_C( uint32_t *pulParam )
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263 uint8_t ucSVCNumber;
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265 /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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266 xPSR. The first argument (r0) is pulParam[ 0 ]. */
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267 ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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268 switch( ucSVCNumber )
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270 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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271 vPortRestoreContextOfFirstTask();
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274 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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275 /* Barriers are normally not required
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276 but do ensure the code is completely
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277 within the specified behaviour for the
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279 __asm volatile( "dsb" ::: "memory" );
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280 __asm volatile( "isb" );
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284 case portSVC_RAISE_PRIVILEGE : __asm volatile
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286 " mrs r1, control \n" /* Obtain current control value. */
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287 " bic r1, r1, #1 \n" /* Set privilege bit. */
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288 " msr control, r1 \n" /* Write back new control value. */
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293 default : /* Unknown SVC call. */
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297 /*-----------------------------------------------------------*/
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300 * See header file for description.
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302 BaseType_t xPortStartScheduler( void )
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304 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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305 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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306 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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308 /* This port can be used on all revisions of the Cortex-M7 core other than
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309 the r0p1 parts. r0p1 parts should use the port from the
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310 /source/portable/GCC/ARM_CM7/r0p1 directory. */
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311 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
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312 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
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314 #if( configASSERT_DEFINED == 1 )
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316 volatile uint32_t ulOriginalPriority;
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317 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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318 volatile uint8_t ucMaxPriorityValue;
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320 /* Determine the maximum priority from which ISR safe FreeRTOS API
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321 functions can be called. ISR safe functions are those that end in
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322 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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323 ensure interrupt entry is as fast and simple as possible.
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325 Save the interrupt priority value that is about to be clobbered. */
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326 ulOriginalPriority = *pucFirstUserPriorityRegister;
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328 /* Determine the number of priority bits available. First write to all
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330 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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332 /* Read the value back to see how many bits stuck. */
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333 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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335 /* Use the same mask on the maximum system call priority. */
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336 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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338 /* Calculate the maximum acceptable priority group value for the number
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339 of bits read back. */
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340 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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341 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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343 ulMaxPRIGROUPValue--;
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344 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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347 #ifdef __NVIC_PRIO_BITS
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349 /* Check the CMSIS configuration that defines the number of
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350 priority bits matches the number of priority bits actually queried
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351 from the hardware. */
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352 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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356 #ifdef configPRIO_BITS
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358 /* Check the FreeRTOS configuration that defines the number of
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359 priority bits matches the number of priority bits actually queried
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360 from the hardware. */
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361 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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365 /* Shift the priority group value back to its position within the AIRCR
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367 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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368 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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370 /* Restore the clobbered interrupt priority register to its original
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372 *pucFirstUserPriorityRegister = ulOriginalPriority;
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374 #endif /* conifgASSERT_DEFINED */
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376 /* Make PendSV and SysTick the lowest priority interrupts. */
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377 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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378 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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380 /* Configure the regions in the MPU that are common to all tasks. */
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383 /* Start the timer that generates the tick ISR. Interrupts are disabled
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385 vPortSetupTimerInterrupt();
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387 /* Initialise the critical nesting count ready for the first task. */
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388 uxCriticalNesting = 0;
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390 /* Ensure the VFP is enabled - it should be anyway. */
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393 /* Lazy save always. */
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394 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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396 /* Start the first task. */
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397 vPortStartFirstTask();
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399 /* Should not get here! */
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402 /*-----------------------------------------------------------*/
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404 void vPortEndScheduler( void )
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406 /* Not implemented in ports where there is nothing to return to.
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407 Artificially force an assert. */
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408 configASSERT( uxCriticalNesting == 1000UL );
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410 /*-----------------------------------------------------------*/
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412 void vPortEnterCritical( void )
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414 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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416 portDISABLE_INTERRUPTS();
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417 uxCriticalNesting++;
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419 vPortResetPrivilege( xRunningPrivileged );
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421 /* This is not the interrupt safe version of the enter critical function so
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422 assert() if it is being called from an interrupt context. Only API
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423 functions that end in "FromISR" can be used in an interrupt. Only assert if
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424 the critical nesting count is 1 to protect against recursive calls if the
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425 assert function also uses a critical section. */
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426 if( uxCriticalNesting == 1 )
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428 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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431 /*-----------------------------------------------------------*/
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433 void vPortExitCritical( void )
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435 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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437 configASSERT( uxCriticalNesting );
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439 uxCriticalNesting--;
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440 if( uxCriticalNesting == 0 )
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442 portENABLE_INTERRUPTS();
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445 vPortResetPrivilege( xRunningPrivileged );
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447 /*-----------------------------------------------------------*/
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449 void xPortSysTickHandler( void )
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451 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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452 executes all interrupts must be unmasked. There is therefore no need to
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453 save and then restore the interrupt mask value as its value is already
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455 portDISABLE_INTERRUPTS();
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457 /* Increment the RTOS tick. */
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458 if( xTaskIncrementTick() != pdFALSE )
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460 /* A context switch is required. Context switching is performed in
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461 the PendSV interrupt. Pend the PendSV interrupt. */
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462 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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465 portENABLE_INTERRUPTS();
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467 /*-----------------------------------------------------------*/
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470 * Setup the systick timer to generate the tick interrupts at the required
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473 __weak void vPortSetupTimerInterrupt( void )
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475 /* Stop and clear the SysTick. */
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476 portNVIC_SYSTICK_CTRL_REG = 0UL;
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477 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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479 /* Configure SysTick to interrupt at the requested rate. */
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480 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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481 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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483 /*-----------------------------------------------------------*/
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485 static void prvSetupMPU( void )
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487 extern uint32_t __privileged_functions_end__[];
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488 extern uint32_t __FLASH_segment_start__[];
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489 extern uint32_t __FLASH_segment_end__[];
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490 extern uint32_t __privileged_data_start__[];
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491 extern uint32_t __privileged_data_end__[];
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493 /* Check the expected MPU is present. */
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494 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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496 /* First setup the entire flash for unprivileged read only access. */
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497 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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498 ( portMPU_REGION_VALID ) |
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499 ( portUNPRIVILEGED_FLASH_REGION );
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501 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
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502 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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503 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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504 ( portMPU_REGION_ENABLE );
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506 /* Setup the first 16K for privileged only access (even though less
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507 than 10K is actually being used). This is where the kernel code is
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509 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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510 ( portMPU_REGION_VALID ) |
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511 ( portPRIVILEGED_FLASH_REGION );
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513 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
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514 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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515 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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516 ( portMPU_REGION_ENABLE );
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518 /* Setup the privileged data RAM region. This is where the kernel data
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520 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
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521 ( portMPU_REGION_VALID ) |
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522 ( portPRIVILEGED_RAM_REGION );
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524 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
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525 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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526 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
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527 ( portMPU_REGION_ENABLE );
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529 /* By default allow everything to access the general peripherals. The
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530 system peripherals and registers are protected. */
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531 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
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532 ( portMPU_REGION_VALID ) |
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533 ( portGENERAL_PERIPHERALS_REGION );
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535 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
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536 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
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537 ( portMPU_REGION_ENABLE );
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539 /* Enable the memory fault exception. */
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540 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
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542 /* Enable the MPU with the background region configured. */
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543 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
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546 /*-----------------------------------------------------------*/
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548 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
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550 uint32_t ulRegionSize, ulReturnValue = 4;
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552 /* 32 is the smallest region size, 31 is the largest valid value for
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554 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
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556 if( ulActualSizeInBytes <= ulRegionSize )
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566 /* Shift the code by one before returning so it can be written directly
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567 into the the correct bit position of the attribute register. */
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568 return ( ulReturnValue << 1UL );
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570 /*-----------------------------------------------------------*/
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572 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
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574 extern uint32_t __SRAM_segment_start__[];
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575 extern uint32_t __SRAM_segment_end__[];
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576 extern uint32_t __privileged_data_start__[];
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577 extern uint32_t __privileged_data_end__[];
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581 if( xRegions == NULL )
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583 /* No MPU regions are specified so allow access to all RAM. */
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584 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
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585 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
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586 ( portMPU_REGION_VALID ) |
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587 ( portSTACK_REGION );
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589 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
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590 ( portMPU_REGION_READ_WRITE ) |
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591 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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592 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
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593 ( portMPU_REGION_ENABLE );
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595 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
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596 just removed the privileged only parameters. */
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597 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
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598 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
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599 ( portMPU_REGION_VALID ) |
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600 ( portSTACK_REGION + 1 );
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602 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
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603 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
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604 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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605 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
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606 ( portMPU_REGION_ENABLE );
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608 /* Invalidate all other regions. */
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609 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
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611 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
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612 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
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617 /* This function is called automatically when the task is created - in
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618 which case the stack region parameters will be valid. At all other
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619 times the stack parameters will not be valid and it is assumed that the
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620 stack region has already been configured. */
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621 if( ulStackDepth > 0 )
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623 /* Define the region that allows access to the stack. */
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624 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
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625 ( ( uint32_t ) pxBottomOfStack ) |
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626 ( portMPU_REGION_VALID ) |
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627 ( portSTACK_REGION ); /* Region number. */
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629 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
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630 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
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631 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
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632 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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633 ( portMPU_REGION_ENABLE );
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638 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
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640 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
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642 /* Translate the generic region definition contained in
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643 xRegions into the CM3 specific MPU settings that are then
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644 stored in xMPUSettings. */
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645 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
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646 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
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647 ( portMPU_REGION_VALID ) |
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648 ( portSTACK_REGION + ul ); /* Region number. */
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650 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
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651 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
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652 ( xRegions[ lIndex ].ulParameters ) |
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653 ( portMPU_REGION_ENABLE );
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657 /* Invalidate the region. */
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658 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
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659 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
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666 /*-----------------------------------------------------------*/
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668 #if( configASSERT_DEFINED == 1 )
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670 void vPortValidateInterruptPriority( void )
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672 uint32_t ulCurrentInterrupt;
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673 uint8_t ucCurrentPriority;
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675 /* Obtain the number of the currently executing interrupt. */
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676 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
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678 /* Is the interrupt number a user defined interrupt? */
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679 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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681 /* Look up the interrupt's priority. */
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682 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
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684 /* The following assertion will fail if a service routine (ISR) for
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685 an interrupt that has been assigned a priority above
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686 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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687 function. ISR safe FreeRTOS API functions must *only* be called
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688 from interrupts that have been assigned a priority at or below
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689 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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691 Numerically low interrupt priority numbers represent logically high
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692 interrupt priorities, therefore the priority of the interrupt must
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693 be set to a value equal to or numerically *higher* than
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694 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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696 Interrupts that use the FreeRTOS API must not be left at their
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697 default priority of zero as that is the highest possible priority,
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698 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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699 and therefore also guaranteed to be invalid.
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701 FreeRTOS maintains separate thread and ISR API functions to ensure
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702 interrupt entry is as fast and simple as possible.
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704 The following links provide detailed information:
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705 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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706 http://www.freertos.org/FAQHelp.html */
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707 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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710 /* Priority grouping: The interrupt controller (NVIC) allows the bits
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711 that define each interrupt's priority to be split between bits that
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712 define the interrupt's pre-emption priority bits and bits that define
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713 the interrupt's sub-priority. For simplicity all bits must be defined
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714 to be pre-emption priority bits. The following assertion will fail if
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715 this is not the case (if some bits represent a sub-priority).
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717 If the application only uses CMSIS libraries for interrupt
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718 configuration then the correct setting can be achieved on all Cortex-M
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719 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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720 scheduler. Note however that some vendor specific peripheral libraries
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721 assume a non-zero priority group setting, in which cases using a value
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722 of zero will result in unpredictable behaviour. */
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723 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
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726 #endif /* configASSERT_DEFINED */
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projects / freertos / blob