2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the ARM CM4F port.
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30 *----------------------------------------------------------*/
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33 #include <intrinsics.h>
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35 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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36 * all the API functions to use the MPU wrappers. That should only be done when
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37 * task.h is included from an application file. */
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38 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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40 /* Scheduler includes. */
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41 #include "FreeRTOS.h"
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44 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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47 #error This port can only be used when the project options are configured to enable hardware floating point support.
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50 #if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
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51 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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54 #ifndef configSYSTICK_CLOCK_HZ
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55 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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56 /* Ensure the SysTick is clocked at the same frequency as the core. */
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57 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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59 /* The way the SysTick is clocked is not modified in case it is not the same
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61 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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64 /* Constants required to manipulate the core. Registers first... */
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65 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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66 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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67 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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68 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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69 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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70 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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71 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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73 /* Constants required to access and manipulate the MPU. */
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74 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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75 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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76 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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77 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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78 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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79 #define portMPU_ENABLE ( 0x01UL )
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80 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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81 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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82 #define portMPU_REGION_VALID ( 0x10UL )
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83 #define portMPU_REGION_ENABLE ( 0x01UL )
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84 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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85 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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87 /* ...then bits in the registers. */
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88 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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89 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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90 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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91 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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92 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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94 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
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96 #define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
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97 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
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98 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
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100 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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101 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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102 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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104 /* Constants required to check the validity of an interrupt priority. */
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105 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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106 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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107 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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108 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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109 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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110 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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111 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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112 #define portPRIGROUP_SHIFT ( 8UL )
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114 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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115 #define portVECTACTIVE_MASK ( 0xFFUL )
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117 /* Constants required to manipulate the VFP. */
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118 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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119 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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121 /* Constants required to set up the initial stack. */
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122 #define portINITIAL_XPSR ( 0x01000000 )
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123 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
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124 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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125 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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127 /* Offsets in the stack to the parameters when inside the SVC handler. */
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128 #define portOFFSET_TO_PC ( 6 )
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130 /* The systick is a 24-bit counter. */
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131 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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133 /* A fiddle factor to estimate the number of SysTick counts that would have
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134 occurred while the SysTick counter is stopped during tickless idle
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136 #define portMISSED_COUNTS_FACTOR ( 45UL )
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138 /* For strict compliance with the Cortex-M spec the task start address should
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139 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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140 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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143 * Configure a number of standard MPU regions that are used by all tasks.
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145 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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148 * Return the smallest MPU region size that a given number of bytes will fit
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149 * into. The region size is returned as the value that should be programmed
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150 * into the region attribute register for that region.
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152 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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155 * Setup the timer to generate the tick interrupts. The implementation in this
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156 * file is weak to allow application writers to change the timer used to
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157 * generate the tick interrupt.
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159 void vPortSetupTimerInterrupt( void );
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162 * Exception handlers.
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164 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
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167 * Start first task is a separate function so it can be tested in isolation.
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169 extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
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174 extern void vPortEnableVFP( void );
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177 * The C portion of the SVC handler.
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179 void vPortSVCHandler_C( uint32_t *pulParam );
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182 * Called from the SVC handler used to start the scheduler.
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184 extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
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187 * @brief Calls the port specific code to raise the privilege.
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189 * @return pdFALSE if privilege was raised, pdTRUE otherwise.
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191 extern BaseType_t xPortRaisePrivilege( void );
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194 * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
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195 * code to reset the privilege, otherwise does nothing.
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197 extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
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198 /*-----------------------------------------------------------*/
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200 /* Each task maintains its own interrupt status in the critical nesting
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202 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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205 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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206 * FreeRTOS API functions are not called from interrupts that have been assigned
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207 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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209 #if( configASSERT_DEFINED == 1 )
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210 static uint8_t ucMaxSysCallPriority = 0;
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211 static uint32_t ulMaxPRIGROUPValue = 0;
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212 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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213 #endif /* configASSERT_DEFINED */
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215 /*-----------------------------------------------------------*/
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218 * See header file for description.
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220 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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222 /* Simulate the stack frame as it would be created by a context switch
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225 /* Offset added to account for the way the MCU uses the stack on entry/exit
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226 * of interrupts, and to ensure alignment. */
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229 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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231 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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233 *pxTopOfStack = ( StackType_t ) 0; /* LR */
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235 /* Save code space by skipping register initialisation. */
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236 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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237 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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239 /* A save method is being used that requires each task to maintain its
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240 * own exec return value. */
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242 *pxTopOfStack = portINITIAL_EXC_RETURN;
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244 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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246 if( xRunPrivileged == pdTRUE )
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248 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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252 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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255 return pxTopOfStack;
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257 /*-----------------------------------------------------------*/
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259 void vPortSVCHandler_C( uint32_t *pulParam )
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261 uint8_t ucSVCNumber;
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263 #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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264 extern uint32_t __syscalls_flash_start__[];
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265 extern uint32_t __syscalls_flash_end__[];
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266 #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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268 /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
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269 * argument (r0) is pulParam[ 0 ]. */
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270 ulPC = pulParam[ portOFFSET_TO_PC ];
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271 ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
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272 switch( ucSVCNumber )
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274 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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275 vPortRestoreContextOfFirstTask();
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278 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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279 /* Barriers are normally not required
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280 * but do ensure the code is completely
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281 * within the specified behaviour for the
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283 __asm volatile( "dsb" ::: "memory" );
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284 __asm volatile( "isb" );
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288 #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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289 case portSVC_RAISE_PRIVILEGE : /* Only raise the privilege, if the
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290 * svc was raised from any of the
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292 if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
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293 ulPC <= ( uint32_t ) __syscalls_flash_end__ )
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297 " mrs r1, control \n" /* Obtain current control value. */
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298 " bic r1, r1, #1 \n" /* Set privilege bit. */
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299 " msr control, r1 \n" /* Write back new control value. */
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305 case portSVC_RAISE_PRIVILEGE : __asm volatile
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307 " mrs r1, control \n" /* Obtain current control value. */
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308 " bic r1, r1, #1 \n" /* Set privilege bit. */
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309 " msr control, r1 \n" /* Write back new control value. */
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313 #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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315 default : /* Unknown SVC call. */
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319 /*-----------------------------------------------------------*/
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322 * See header file for description.
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324 BaseType_t xPortStartScheduler( void )
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326 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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327 * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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328 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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330 /* This port can be used on all revisions of the Cortex-M7 core other than
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331 * the r0p1 parts. r0p1 parts should use the port from the
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332 * /source/portable/GCC/ARM_CM7/r0p1 directory. */
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333 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
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334 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
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336 #if( configASSERT_DEFINED == 1 )
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338 volatile uint32_t ulOriginalPriority;
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339 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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340 volatile uint8_t ucMaxPriorityValue;
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342 /* Determine the maximum priority from which ISR safe FreeRTOS API
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343 * functions can be called. ISR safe functions are those that end in
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344 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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345 * ensure interrupt entry is as fast and simple as possible.
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347 Save the interrupt priority value that is about to be clobbered. */
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348 ulOriginalPriority = *pucFirstUserPriorityRegister;
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350 /* Determine the number of priority bits available. First write to all
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351 * possible bits. */
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352 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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354 /* Read the value back to see how many bits stuck. */
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355 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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357 /* Use the same mask on the maximum system call priority. */
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358 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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360 /* Calculate the maximum acceptable priority group value for the number
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361 * of bits read back. */
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362 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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363 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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365 ulMaxPRIGROUPValue--;
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366 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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369 #ifdef __NVIC_PRIO_BITS
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371 /* Check the CMSIS configuration that defines the number of
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372 * priority bits matches the number of priority bits actually queried
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373 * from the hardware. */
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374 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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378 #ifdef configPRIO_BITS
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380 /* Check the FreeRTOS configuration that defines the number of
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381 * priority bits matches the number of priority bits actually queried
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382 * from the hardware. */
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383 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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387 /* Shift the priority group value back to its position within the AIRCR
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389 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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390 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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392 /* Restore the clobbered interrupt priority register to its original
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394 *pucFirstUserPriorityRegister = ulOriginalPriority;
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396 #endif /* conifgASSERT_DEFINED */
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398 /* Make PendSV and SysTick the lowest priority interrupts. */
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399 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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400 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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402 /* Configure the regions in the MPU that are common to all tasks. */
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405 /* Start the timer that generates the tick ISR. Interrupts are disabled
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407 vPortSetupTimerInterrupt();
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409 /* Initialise the critical nesting count ready for the first task. */
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410 uxCriticalNesting = 0;
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412 /* Ensure the VFP is enabled - it should be anyway. */
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415 /* Lazy save always. */
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416 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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418 /* Start the first task. */
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419 vPortStartFirstTask();
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421 /* Should not get here! */
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424 /*-----------------------------------------------------------*/
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426 void vPortEndScheduler( void )
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428 /* Not implemented in ports where there is nothing to return to.
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429 * Artificially force an assert. */
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430 configASSERT( uxCriticalNesting == 1000UL );
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432 /*-----------------------------------------------------------*/
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434 void vPortEnterCritical( void )
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436 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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438 portDISABLE_INTERRUPTS();
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439 uxCriticalNesting++;
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441 vPortResetPrivilege( xRunningPrivileged );
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443 /* This is not the interrupt safe version of the enter critical function so
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444 * assert() if it is being called from an interrupt context. Only API
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445 * functions that end in "FromISR" can be used in an interrupt. Only assert if
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446 * the critical nesting count is 1 to protect against recursive calls if the
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447 * assert function also uses a critical section. */
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448 if( uxCriticalNesting == 1 )
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450 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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453 /*-----------------------------------------------------------*/
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455 void vPortExitCritical( void )
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457 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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459 configASSERT( uxCriticalNesting );
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461 uxCriticalNesting--;
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462 if( uxCriticalNesting == 0 )
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464 portENABLE_INTERRUPTS();
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467 vPortResetPrivilege( xRunningPrivileged );
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469 /*-----------------------------------------------------------*/
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471 void xPortSysTickHandler( void )
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473 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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474 * executes all interrupts must be unmasked. There is therefore no need to
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475 * save and then restore the interrupt mask value as its value is already
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477 portDISABLE_INTERRUPTS();
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479 /* Increment the RTOS tick. */
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480 if( xTaskIncrementTick() != pdFALSE )
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482 /* A context switch is required. Context switching is performed in
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483 * the PendSV interrupt. Pend the PendSV interrupt. */
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484 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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487 portENABLE_INTERRUPTS();
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489 /*-----------------------------------------------------------*/
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492 * Setup the systick timer to generate the tick interrupts at the required
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495 __weak void vPortSetupTimerInterrupt( void )
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497 /* Stop and clear the SysTick. */
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498 portNVIC_SYSTICK_CTRL_REG = 0UL;
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499 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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501 /* Configure SysTick to interrupt at the requested rate. */
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502 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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503 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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505 /*-----------------------------------------------------------*/
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507 static void prvSetupMPU( void )
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509 extern uint32_t __privileged_functions_end__[];
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510 extern uint32_t __FLASH_segment_start__[];
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511 extern uint32_t __FLASH_segment_end__[];
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512 extern uint32_t __privileged_data_start__[];
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513 extern uint32_t __privileged_data_end__[];
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515 /* Check the expected MPU is present. */
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516 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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518 /* First setup the entire flash for unprivileged read only access. */
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519 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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520 ( portMPU_REGION_VALID ) |
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521 ( portUNPRIVILEGED_FLASH_REGION );
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523 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
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524 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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525 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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526 ( portMPU_REGION_ENABLE );
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528 /* Setup the first 16K for privileged only access (even though less
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529 * than 10K is actually being used). This is where the kernel code is
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531 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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532 ( portMPU_REGION_VALID ) |
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533 ( portPRIVILEGED_FLASH_REGION );
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535 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
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536 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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537 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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538 ( portMPU_REGION_ENABLE );
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540 /* Setup the privileged data RAM region. This is where the kernel data
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542 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
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543 ( portMPU_REGION_VALID ) |
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544 ( portPRIVILEGED_RAM_REGION );
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546 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
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547 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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548 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
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549 ( portMPU_REGION_ENABLE );
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551 /* By default allow everything to access the general peripherals. The
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552 * system peripherals and registers are protected. */
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553 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
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554 ( portMPU_REGION_VALID ) |
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555 ( portGENERAL_PERIPHERALS_REGION );
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557 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
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558 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
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559 ( portMPU_REGION_ENABLE );
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561 /* Enable the memory fault exception. */
\r
562 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
\r
564 /* Enable the MPU with the background region configured. */
\r
565 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
\r
568 /*-----------------------------------------------------------*/
\r
570 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
\r
572 uint32_t ulRegionSize, ulReturnValue = 4;
\r
574 /* 32 is the smallest region size, 31 is the largest valid value for
\r
575 * ulReturnValue. */
\r
576 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
578 if( ulActualSizeInBytes <= ulRegionSize )
\r
588 /* Shift the code by one before returning so it can be written directly
\r
589 * into the the correct bit position of the attribute register. */
\r
590 return ( ulReturnValue << 1UL );
\r
592 /*-----------------------------------------------------------*/
\r
594 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
596 extern uint32_t __SRAM_segment_start__[];
\r
597 extern uint32_t __SRAM_segment_end__[];
\r
598 extern uint32_t __privileged_data_start__[];
\r
599 extern uint32_t __privileged_data_end__[];
\r
603 if( xRegions == NULL )
\r
605 /* No MPU regions are specified so allow access to all RAM. */
\r
606 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
607 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
608 ( portMPU_REGION_VALID ) |
\r
609 ( portSTACK_REGION );
\r
611 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
612 ( portMPU_REGION_READ_WRITE ) |
\r
613 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
614 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
615 ( portMPU_REGION_ENABLE );
\r
617 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
618 * just removed the privileged only parameters. */
\r
619 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
620 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
621 ( portMPU_REGION_VALID ) |
\r
622 ( portSTACK_REGION + 1 );
\r
624 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
625 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
626 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
627 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
628 ( portMPU_REGION_ENABLE );
\r
630 /* Invalidate all other regions. */
\r
631 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
633 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
634 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
639 /* This function is called automatically when the task is created - in
\r
640 * which case the stack region parameters will be valid. At all other
\r
641 * times the stack parameters will not be valid and it is assumed that the
\r
642 * stack region has already been configured. */
\r
643 if( ulStackDepth > 0 )
\r
645 /* Define the region that allows access to the stack. */
\r
646 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
647 ( ( uint32_t ) pxBottomOfStack ) |
\r
648 ( portMPU_REGION_VALID ) |
\r
649 ( portSTACK_REGION ); /* Region number. */
\r
651 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
652 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
653 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
654 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
655 ( portMPU_REGION_ENABLE );
\r
660 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
662 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
664 /* Translate the generic region definition contained in
\r
665 * xRegions into the CM3 specific MPU settings that are then
\r
666 * stored in xMPUSettings. */
\r
667 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
668 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
669 ( portMPU_REGION_VALID ) |
\r
670 ( portSTACK_REGION + ul ); /* Region number. */
\r
672 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
673 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
674 ( xRegions[ lIndex ].ulParameters ) |
\r
675 ( portMPU_REGION_ENABLE );
\r
679 /* Invalidate the region. */
\r
680 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
681 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
688 /*-----------------------------------------------------------*/
\r
690 #if( configASSERT_DEFINED == 1 )
\r
692 void vPortValidateInterruptPriority( void )
\r
694 uint32_t ulCurrentInterrupt;
\r
695 uint8_t ucCurrentPriority;
\r
697 /* Obtain the number of the currently executing interrupt. */
\r
698 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
\r
700 /* Is the interrupt number a user defined interrupt? */
\r
701 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
703 /* Look up the interrupt's priority. */
\r
704 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
706 /* The following assertion will fail if a service routine (ISR) for
\r
707 * an interrupt that has been assigned a priority above
\r
708 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
709 * function. ISR safe FreeRTOS API functions must *only* be called
\r
710 * from interrupts that have been assigned a priority at or below
\r
711 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
713 * Numerically low interrupt priority numbers represent logically high
\r
714 * interrupt priorities, therefore the priority of the interrupt must
\r
715 * be set to a value equal to or numerically *higher* than
\r
716 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
718 * Interrupts that use the FreeRTOS API must not be left at their
\r
719 * default priority of zero as that is the highest possible priority,
\r
720 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
721 * and therefore also guaranteed to be invalid.
\r
723 * FreeRTOS maintains separate thread and ISR API functions to ensure
\r
724 * interrupt entry is as fast and simple as possible.
\r
726 * The following links provide detailed information:
\r
727 * http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
728 * http://www.freertos.org/FAQHelp.html */
\r
729 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
732 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
733 * that define each interrupt's priority to be split between bits that
\r
734 * define the interrupt's pre-emption priority bits and bits that define
\r
735 * the interrupt's sub-priority. For simplicity all bits must be defined
\r
736 * to be pre-emption priority bits. The following assertion will fail if
\r
737 * this is not the case (if some bits represent a sub-priority).
\r
739 * If the application only uses CMSIS libraries for interrupt
\r
740 * configuration then the correct setting can be achieved on all Cortex-M
\r
741 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
742 * scheduler. Note however that some vendor specific peripheral libraries
\r
743 * assume a non-zero priority group setting, in which cases using a value
\r
744 * of zero will result in unpredictable behaviour. */
\r
745 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
748 #endif /* configASSERT_DEFINED */
\r
749 /*-----------------------------------------------------------*/
\r