2 * FreeRTOS Kernel V10.0.0
\r
3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software. If you wish to use our Amazon
\r
14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
\r
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
23 * http://www.FreeRTOS.org
\r
24 * http://aws.amazon.com/freertos
\r
26 * 1 tab == 4 spaces!
\r
29 /*-----------------------------------------------------------
\r
30 * Implementation of functions defined in portable.h for the ARM CM4F port.
\r
31 *----------------------------------------------------------*/
\r
34 #include <intrinsics.h>
\r
36 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
\r
37 all the API functions to use the MPU wrappers. That should only be done when
\r
38 task.h is included from an application file. */
\r
39 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
\r
41 /* Scheduler includes. */
\r
42 #include "FreeRTOS.h"
\r
45 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
\r
47 #warning This is not yet a documented port as it has not been fully tested, so no demo projects that use this port are provided.
\r
50 #error This port can only be used when the project options are configured to enable hardware floating point support.
\r
53 #if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
\r
54 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
\r
57 #ifndef configSYSTICK_CLOCK_HZ
\r
58 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
\r
59 /* Ensure the SysTick is clocked at the same frequency as the core. */
\r
60 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
\r
62 /* The way the SysTick is clocked is not modified in case it is not the same
\r
64 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
\r
67 /* Constants required to manipulate the core. Registers first... */
\r
68 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
\r
69 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
\r
70 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
\r
71 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
\r
72 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
\r
73 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
\r
74 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
\r
76 /* Constants required to access and manipulate the MPU. */
\r
77 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
\r
78 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
\r
79 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
\r
80 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
\r
81 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
\r
82 #define portMPU_ENABLE ( 0x01UL )
\r
83 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
\r
84 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
\r
85 #define portMPU_REGION_VALID ( 0x10UL )
\r
86 #define portMPU_REGION_ENABLE ( 0x01UL )
\r
87 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
\r
88 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
\r
90 /* ...then bits in the registers. */
\r
91 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
\r
92 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
\r
93 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
\r
94 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
\r
95 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
\r
97 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
\r
99 #define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
\r
100 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
\r
101 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
\r
103 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
\r
104 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
\r
105 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
\r
107 /* Constants required to check the validity of an interrupt priority. */
\r
108 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
\r
109 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
\r
110 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
\r
111 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
\r
112 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
\r
113 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
\r
114 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
\r
115 #define portPRIGROUP_SHIFT ( 8UL )
\r
117 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
\r
118 #define portVECTACTIVE_MASK ( 0xFFUL )
\r
120 /* Constants required to manipulate the VFP. */
\r
121 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
\r
122 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
\r
124 /* Constants required to set up the initial stack. */
\r
125 #define portINITIAL_XPSR ( 0x01000000 )
\r
126 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
\r
127 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
\r
128 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
\r
130 /* Offsets in the stack to the parameters when inside the SVC handler. */
\r
131 #define portOFFSET_TO_PC ( 6 )
\r
133 /* The systick is a 24-bit counter. */
\r
134 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
\r
136 /* A fiddle factor to estimate the number of SysTick counts that would have
\r
137 occurred while the SysTick counter is stopped during tickless idle
\r
139 #define portMISSED_COUNTS_FACTOR ( 45UL )
\r
141 /* For strict compliance with the Cortex-M spec the task start address should
\r
142 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
\r
143 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
\r
146 * Configure a number of standard MPU regions that are used by all tasks.
\r
148 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
\r
151 * Return the smallest MPU region size that a given number of bytes will fit
\r
152 * into. The region size is returned as the value that should be programmed
\r
153 * into the region attribute register for that region.
\r
155 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
\r
158 * Checks to see if being called from the context of an unprivileged task, and
\r
159 * if so raises the privilege level and returns false - otherwise does nothing
\r
160 * other than return true.
\r
162 extern BaseType_t xPortRaisePrivilege( void );
\r
165 * Setup the timer to generate the tick interrupts. The implementation in this
\r
166 * file is weak to allow application writers to change the timer used to
\r
167 * generate the tick interrupt.
\r
169 void vPortSetupTimerInterrupt( void );
\r
172 * Exception handlers.
\r
174 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
\r
177 * Start first task is a separate function so it can be tested in isolation.
\r
179 extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
\r
184 extern void vPortEnableVFP( void );
\r
187 * The C portion of the SVC handler.
\r
189 void vPortSVCHandler_C( uint32_t *pulParam );
\r
192 * Called from the SVC handler used to start the scheduler.
\r
194 extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
\r
196 /*-----------------------------------------------------------*/
\r
198 /* Each task maintains its own interrupt status in the critical nesting
\r
200 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
\r
203 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
\r
204 * FreeRTOS API functions are not called from interrupts that have been assigned
\r
205 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
207 #if( configASSERT_DEFINED == 1 )
\r
208 static uint8_t ucMaxSysCallPriority = 0;
\r
209 static uint32_t ulMaxPRIGROUPValue = 0;
\r
210 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
\r
211 #endif /* configASSERT_DEFINED */
\r
213 /*-----------------------------------------------------------*/
\r
216 * See header file for description.
\r
218 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
\r
220 /* Simulate the stack frame as it would be created by a context switch
\r
223 /* Offset added to account for the way the MCU uses the stack on entry/exit
\r
224 of interrupts, and to ensure alignment. */
\r
227 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
229 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
\r
231 *pxTopOfStack = ( StackType_t ) 0; /* LR */
\r
233 /* Save code space by skipping register initialisation. */
\r
234 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
235 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
237 /* A save method is being used that requires each task to maintain its
\r
238 own exec return value. */
\r
240 *pxTopOfStack = portINITIAL_EXC_RETURN;
\r
242 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
\r
244 if( xRunPrivileged == pdTRUE )
\r
246 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
\r
250 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
\r
253 return pxTopOfStack;
\r
255 /*-----------------------------------------------------------*/
\r
257 void vPortSVCHandler_C( uint32_t *pulParam )
\r
259 uint8_t ucSVCNumber;
\r
261 /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
\r
262 xPSR. The first argument (r0) is pulParam[ 0 ]. */
\r
263 ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
\r
264 switch( ucSVCNumber )
\r
266 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
\r
267 vPortRestoreContextOfFirstTask();
\r
270 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
271 /* Barriers are normally not required
\r
272 but do ensure the code is completely
\r
273 within the specified behaviour for the
\r
275 __asm volatile( "dsb" ::: "memory" );
\r
276 __asm volatile( "isb" );
\r
280 case portSVC_RAISE_PRIVILEGE : __asm volatile
\r
282 " mrs r1, control \n" /* Obtain current control value. */
\r
283 " bic r1, r1, #1 \n" /* Set privilege bit. */
\r
284 " msr control, r1 \n" /* Write back new control value. */
\r
289 default : /* Unknown SVC call. */
\r
293 /*-----------------------------------------------------------*/
\r
296 * See header file for description.
\r
298 BaseType_t xPortStartScheduler( void )
\r
300 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
\r
301 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
\r
302 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
\r
304 /* This port can be used on all revisions of the Cortex-M7 core other than
\r
305 the r0p1 parts. r0p1 parts should use the port from the
\r
306 /source/portable/GCC/ARM_CM7/r0p1 directory. */
\r
307 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
\r
308 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
\r
310 #if( configASSERT_DEFINED == 1 )
\r
312 volatile uint32_t ulOriginalPriority;
\r
313 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
\r
314 volatile uint8_t ucMaxPriorityValue;
\r
316 /* Determine the maximum priority from which ISR safe FreeRTOS API
\r
317 functions can be called. ISR safe functions are those that end in
\r
318 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
\r
319 ensure interrupt entry is as fast and simple as possible.
\r
321 Save the interrupt priority value that is about to be clobbered. */
\r
322 ulOriginalPriority = *pucFirstUserPriorityRegister;
\r
324 /* Determine the number of priority bits available. First write to all
\r
326 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
328 /* Read the value back to see how many bits stuck. */
\r
329 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
\r
331 /* Use the same mask on the maximum system call priority. */
\r
332 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
\r
334 /* Calculate the maximum acceptable priority group value for the number
\r
335 of bits read back. */
\r
336 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
\r
337 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
\r
339 ulMaxPRIGROUPValue--;
\r
340 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
\r
343 #ifdef __NVIC_PRIO_BITS
\r
345 /* Check the CMSIS configuration that defines the number of
\r
346 priority bits matches the number of priority bits actually queried
\r
347 from the hardware. */
\r
348 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
\r
352 #ifdef configPRIO_BITS
\r
354 /* Check the FreeRTOS configuration that defines the number of
\r
355 priority bits matches the number of priority bits actually queried
\r
356 from the hardware. */
\r
357 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
\r
361 /* Shift the priority group value back to its position within the AIRCR
\r
363 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
\r
364 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
\r
366 /* Restore the clobbered interrupt priority register to its original
\r
368 *pucFirstUserPriorityRegister = ulOriginalPriority;
\r
370 #endif /* conifgASSERT_DEFINED */
\r
372 /* Make PendSV and SysTick the lowest priority interrupts. */
\r
373 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
\r
374 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
\r
376 /* Configure the regions in the MPU that are common to all tasks. */
\r
379 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
381 vPortSetupTimerInterrupt();
\r
383 /* Initialise the critical nesting count ready for the first task. */
\r
384 uxCriticalNesting = 0;
\r
386 /* Ensure the VFP is enabled - it should be anyway. */
\r
389 /* Lazy save always. */
\r
390 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
\r
392 /* Start the first task. */
\r
393 vPortStartFirstTask();
\r
395 /* Should not get here! */
\r
398 /*-----------------------------------------------------------*/
\r
400 void vPortEndScheduler( void )
\r
402 /* Not implemented in ports where there is nothing to return to.
\r
403 Artificially force an assert. */
\r
404 configASSERT( uxCriticalNesting == 1000UL );
\r
406 /*-----------------------------------------------------------*/
\r
408 void vPortEnterCritical( void )
\r
410 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
\r
412 portDISABLE_INTERRUPTS();
\r
413 uxCriticalNesting++;
\r
415 vPortResetPrivilege( xRunningPrivileged );
\r
417 /* This is not the interrupt safe version of the enter critical function so
\r
418 assert() if it is being called from an interrupt context. Only API
\r
419 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
420 the critical nesting count is 1 to protect against recursive calls if the
\r
421 assert function also uses a critical section. */
\r
422 if( uxCriticalNesting == 1 )
\r
424 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
\r
427 /*-----------------------------------------------------------*/
\r
429 void vPortExitCritical( void )
\r
431 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
\r
433 configASSERT( uxCriticalNesting );
\r
435 uxCriticalNesting--;
\r
436 if( uxCriticalNesting == 0 )
\r
438 portENABLE_INTERRUPTS();
\r
441 vPortResetPrivilege( xRunningPrivileged );
\r
443 /*-----------------------------------------------------------*/
\r
445 void xPortSysTickHandler( void )
\r
447 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
\r
448 executes all interrupts must be unmasked. There is therefore no need to
\r
449 save and then restore the interrupt mask value as its value is already
\r
451 portDISABLE_INTERRUPTS();
\r
453 /* Increment the RTOS tick. */
\r
454 if( xTaskIncrementTick() != pdFALSE )
\r
456 /* A context switch is required. Context switching is performed in
\r
457 the PendSV interrupt. Pend the PendSV interrupt. */
\r
458 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
461 portENABLE_INTERRUPTS();
\r
463 /*-----------------------------------------------------------*/
\r
466 * Setup the systick timer to generate the tick interrupts at the required
\r
469 __weak void vPortSetupTimerInterrupt( void )
\r
471 /* Stop and clear the SysTick. */
\r
472 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
473 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
475 /* Configure SysTick to interrupt at the requested rate. */
\r
476 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
477 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
479 /*-----------------------------------------------------------*/
\r
481 static void prvSetupMPU( void )
\r
483 extern uint32_t __privileged_functions_end__[];
\r
484 extern uint32_t __FLASH_segment_start__[];
\r
485 extern uint32_t __FLASH_segment_end__[];
\r
486 extern uint32_t __privileged_data_start__[];
\r
487 extern uint32_t __privileged_data_end__[];
\r
489 /* Check the expected MPU is present. */
\r
490 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
\r
492 /* First setup the entire flash for unprivileged read only access. */
\r
493 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
494 ( portMPU_REGION_VALID ) |
\r
495 ( portUNPRIVILEGED_FLASH_REGION );
\r
497 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
\r
498 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
499 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
500 ( portMPU_REGION_ENABLE );
\r
502 /* Setup the first 16K for privileged only access (even though less
\r
503 than 10K is actually being used). This is where the kernel code is
\r
505 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
506 ( portMPU_REGION_VALID ) |
\r
507 ( portPRIVILEGED_FLASH_REGION );
\r
509 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
\r
510 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
511 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
512 ( portMPU_REGION_ENABLE );
\r
514 /* Setup the privileged data RAM region. This is where the kernel data
\r
516 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
517 ( portMPU_REGION_VALID ) |
\r
518 ( portPRIVILEGED_RAM_REGION );
\r
520 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
521 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
522 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
523 ( portMPU_REGION_ENABLE );
\r
525 /* By default allow everything to access the general peripherals. The
\r
526 system peripherals and registers are protected. */
\r
527 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
\r
528 ( portMPU_REGION_VALID ) |
\r
529 ( portGENERAL_PERIPHERALS_REGION );
\r
531 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
\r
532 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
\r
533 ( portMPU_REGION_ENABLE );
\r
535 /* Enable the memory fault exception. */
\r
536 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
\r
538 /* Enable the MPU with the background region configured. */
\r
539 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
\r
542 /*-----------------------------------------------------------*/
\r
544 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
\r
546 uint32_t ulRegionSize, ulReturnValue = 4;
\r
548 /* 32 is the smallest region size, 31 is the largest valid value for
\r
550 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
552 if( ulActualSizeInBytes <= ulRegionSize )
\r
562 /* Shift the code by one before returning so it can be written directly
\r
563 into the the correct bit position of the attribute register. */
\r
564 return ( ulReturnValue << 1UL );
\r
566 /*-----------------------------------------------------------*/
\r
568 void vPortResetPrivilege( BaseType_t xRunningPrivileged )
\r
570 if( xRunningPrivileged != pdTRUE )
\r
572 __asm volatile ( " mrs r0, control \n" \
\r
573 " orr r0, r0, #1 \n" \
\r
574 " msr control, r0 \n" \
\r
575 :::"r0", "memory" );
\r
578 /*-----------------------------------------------------------*/
\r
580 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
582 extern uint32_t __SRAM_segment_start__[];
\r
583 extern uint32_t __SRAM_segment_end__[];
\r
584 extern uint32_t __privileged_data_start__[];
\r
585 extern uint32_t __privileged_data_end__[];
\r
589 if( xRegions == NULL )
\r
591 /* No MPU regions are specified so allow access to all RAM. */
\r
592 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
593 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
594 ( portMPU_REGION_VALID ) |
\r
595 ( portSTACK_REGION );
\r
597 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
598 ( portMPU_REGION_READ_WRITE ) |
\r
599 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
600 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
601 ( portMPU_REGION_ENABLE );
\r
603 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
604 just removed the privileged only parameters. */
\r
605 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
606 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
607 ( portMPU_REGION_VALID ) |
\r
608 ( portSTACK_REGION + 1 );
\r
610 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
611 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
612 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
613 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
614 ( portMPU_REGION_ENABLE );
\r
616 /* Invalidate all other regions. */
\r
617 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
619 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
620 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
625 /* This function is called automatically when the task is created - in
\r
626 which case the stack region parameters will be valid. At all other
\r
627 times the stack parameters will not be valid and it is assumed that the
\r
628 stack region has already been configured. */
\r
629 if( ulStackDepth > 0 )
\r
631 /* Define the region that allows access to the stack. */
\r
632 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
633 ( ( uint32_t ) pxBottomOfStack ) |
\r
634 ( portMPU_REGION_VALID ) |
\r
635 ( portSTACK_REGION ); /* Region number. */
\r
637 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
638 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
639 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
640 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
641 ( portMPU_REGION_ENABLE );
\r
646 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
648 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
650 /* Translate the generic region definition contained in
\r
651 xRegions into the CM3 specific MPU settings that are then
\r
652 stored in xMPUSettings. */
\r
653 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
654 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
655 ( portMPU_REGION_VALID ) |
\r
656 ( portSTACK_REGION + ul ); /* Region number. */
\r
658 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
659 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
660 ( xRegions[ lIndex ].ulParameters ) |
\r
661 ( portMPU_REGION_ENABLE );
\r
665 /* Invalidate the region. */
\r
666 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
667 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
674 /*-----------------------------------------------------------*/
\r
676 #if( configASSERT_DEFINED == 1 )
\r
678 void vPortValidateInterruptPriority( void )
\r
680 uint32_t ulCurrentInterrupt;
\r
681 uint8_t ucCurrentPriority;
\r
683 /* Obtain the number of the currently executing interrupt. */
\r
684 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
\r
686 /* Is the interrupt number a user defined interrupt? */
\r
687 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
689 /* Look up the interrupt's priority. */
\r
690 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
692 /* The following assertion will fail if a service routine (ISR) for
\r
693 an interrupt that has been assigned a priority above
\r
694 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
695 function. ISR safe FreeRTOS API functions must *only* be called
\r
696 from interrupts that have been assigned a priority at or below
\r
697 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
699 Numerically low interrupt priority numbers represent logically high
\r
700 interrupt priorities, therefore the priority of the interrupt must
\r
701 be set to a value equal to or numerically *higher* than
\r
702 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
704 Interrupts that use the FreeRTOS API must not be left at their
\r
705 default priority of zero as that is the highest possible priority,
\r
706 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
707 and therefore also guaranteed to be invalid.
\r
709 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
710 interrupt entry is as fast and simple as possible.
\r
712 The following links provide detailed information:
\r
713 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
714 http://www.freertos.org/FAQHelp.html */
\r
715 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
718 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
719 that define each interrupt's priority to be split between bits that
\r
720 define the interrupt's pre-emption priority bits and bits that define
\r
721 the interrupt's sub-priority. For simplicity all bits must be defined
\r
722 to be pre-emption priority bits. The following assertion will fail if
\r
723 this is not the case (if some bits represent a sub-priority).
\r
725 If the application only uses CMSIS libraries for interrupt
\r
726 configuration then the correct setting can be achieved on all Cortex-M
\r
727 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
728 scheduler. Note however that some vendor specific peripheral libraries
\r
729 assume a non-zero priority group setting, in which cases using a value
\r
730 of zero will result in unpredictable behaviour. */
\r
731 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
734 #endif /* configASSERT_DEFINED */
\r