2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Implementation of functions defined in portable.h for the ARM CM4F port.
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31 *----------------------------------------------------------*/
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34 #include <intrinsics.h>
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36 /* Scheduler includes. */
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37 #include "FreeRTOS.h"
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41 #error This port can only be used when the project options are configured to enable hardware floating point support.
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44 #if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
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45 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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48 #ifndef configSYSTICK_CLOCK_HZ
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49 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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50 /* Ensure the SysTick is clocked at the same frequency as the core. */
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51 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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53 /* The way the SysTick is clocked is not modified in case it is not the same
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55 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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58 /* Constants required to manipulate the core. Registers first... */
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59 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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60 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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61 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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62 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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63 /* ...then bits in the registers. */
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64 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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65 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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66 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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67 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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68 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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70 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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71 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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73 /* Constants required to check the validity of an interrupt priority. */
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74 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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75 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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76 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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77 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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78 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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79 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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80 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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81 #define portPRIGROUP_SHIFT ( 8UL )
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83 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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84 #define portVECTACTIVE_MASK ( 0xFFUL )
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86 /* Constants required to manipulate the VFP. */
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87 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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88 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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90 /* Constants required to set up the initial stack. */
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91 #define portINITIAL_XPSR ( 0x01000000 )
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92 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
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94 /* The systick is a 24-bit counter. */
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95 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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97 /* A fiddle factor to estimate the number of SysTick counts that would have
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98 occurred while the SysTick counter is stopped during tickless idle
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100 #define portMISSED_COUNTS_FACTOR ( 45UL )
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102 /* For strict compliance with the Cortex-M spec the task start address should
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103 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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104 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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107 * Setup the timer to generate the tick interrupts. The implementation in this
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108 * file is weak to allow application writers to change the timer used to
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109 * generate the tick interrupt.
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111 void vPortSetupTimerInterrupt( void );
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114 * Exception handlers.
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116 void xPortSysTickHandler( void );
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119 * Start first task is a separate function so it can be tested in isolation.
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121 extern void vPortStartFirstTask( void );
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126 extern void vPortEnableVFP( void );
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129 * Used to catch tasks that attempt to return from their implementing function.
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131 static void prvTaskExitError( void );
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133 /*-----------------------------------------------------------*/
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135 /* Each task maintains its own interrupt status in the critical nesting
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137 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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140 * The number of SysTick increments that make up one tick period.
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142 #if( configUSE_TICKLESS_IDLE == 1 )
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143 static uint32_t ulTimerCountsForOneTick = 0;
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144 #endif /* configUSE_TICKLESS_IDLE */
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147 * The maximum number of tick periods that can be suppressed is limited by the
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148 * 24 bit resolution of the SysTick timer.
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150 #if( configUSE_TICKLESS_IDLE == 1 )
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151 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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152 #endif /* configUSE_TICKLESS_IDLE */
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155 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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156 * power functionality only.
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158 #if( configUSE_TICKLESS_IDLE == 1 )
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159 static uint32_t ulStoppedTimerCompensation = 0;
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160 #endif /* configUSE_TICKLESS_IDLE */
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163 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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164 * FreeRTOS API functions are not called from interrupts that have been assigned
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165 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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167 #if( configASSERT_DEFINED == 1 )
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168 static uint8_t ucMaxSysCallPriority = 0;
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169 static uint32_t ulMaxPRIGROUPValue = 0;
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170 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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171 #endif /* configASSERT_DEFINED */
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173 /*-----------------------------------------------------------*/
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176 * See header file for description.
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178 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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180 /* Simulate the stack frame as it would be created by a context switch
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183 /* Offset added to account for the way the MCU uses the stack on entry/exit
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184 of interrupts, and to ensure alignment. */
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187 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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189 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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191 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
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193 /* Save code space by skipping register initialisation. */
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194 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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195 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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197 /* A save method is being used that requires each task to maintain its
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198 own exec return value. */
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200 *pxTopOfStack = portINITIAL_EXC_RETURN;
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202 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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204 return pxTopOfStack;
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206 /*-----------------------------------------------------------*/
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208 static void prvTaskExitError( void )
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210 /* A function that implements a task must not exit or attempt to return to
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211 its caller as there is nothing to return to. If a task wants to exit it
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212 should instead call vTaskDelete( NULL ).
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214 Artificially force an assert() to be triggered if configASSERT() is
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215 defined, then stop here so application writers can catch the error. */
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216 configASSERT( uxCriticalNesting == ~0UL );
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217 portDISABLE_INTERRUPTS();
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220 /*-----------------------------------------------------------*/
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223 * See header file for description.
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225 BaseType_t xPortStartScheduler( void )
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227 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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228 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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229 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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231 #if( configASSERT_DEFINED == 1 )
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233 volatile uint32_t ulOriginalPriority;
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234 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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235 volatile uint8_t ucMaxPriorityValue;
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237 /* Determine the maximum priority from which ISR safe FreeRTOS API
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238 functions can be called. ISR safe functions are those that end in
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239 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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240 ensure interrupt entry is as fast and simple as possible.
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242 Save the interrupt priority value that is about to be clobbered. */
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243 ulOriginalPriority = *pucFirstUserPriorityRegister;
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245 /* Determine the number of priority bits available. First write to all
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247 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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249 /* Read the value back to see how many bits stuck. */
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250 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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252 /* Use the same mask on the maximum system call priority. */
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253 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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255 /* Calculate the maximum acceptable priority group value for the number
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256 of bits read back. */
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257 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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258 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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260 ulMaxPRIGROUPValue--;
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261 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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264 #ifdef __NVIC_PRIO_BITS
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266 /* Check the CMSIS configuration that defines the number of
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267 priority bits matches the number of priority bits actually queried
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268 from the hardware. */
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269 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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273 #ifdef configPRIO_BITS
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275 /* Check the FreeRTOS configuration that defines the number of
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276 priority bits matches the number of priority bits actually queried
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277 from the hardware. */
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278 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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282 /* Shift the priority group value back to its position within the AIRCR
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284 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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285 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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287 /* Restore the clobbered interrupt priority register to its original
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289 *pucFirstUserPriorityRegister = ulOriginalPriority;
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291 #endif /* conifgASSERT_DEFINED */
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293 /* Make PendSV and SysTick the lowest priority interrupts. */
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294 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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295 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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297 /* Start the timer that generates the tick ISR. Interrupts are disabled
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299 vPortSetupTimerInterrupt();
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301 /* Initialise the critical nesting count ready for the first task. */
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302 uxCriticalNesting = 0;
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304 /* Ensure the VFP is enabled - it should be anyway. */
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307 /* Lazy save always. */
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308 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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310 /* Start the first task. */
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311 vPortStartFirstTask();
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313 /* Should not get here! */
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316 /*-----------------------------------------------------------*/
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318 void vPortEndScheduler( void )
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320 /* Not implemented in ports where there is nothing to return to.
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321 Artificially force an assert. */
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322 configASSERT( uxCriticalNesting == 1000UL );
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324 /*-----------------------------------------------------------*/
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326 void vPortEnterCritical( void )
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328 portDISABLE_INTERRUPTS();
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329 uxCriticalNesting++;
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331 /* This is not the interrupt safe version of the enter critical function so
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332 assert() if it is being called from an interrupt context. Only API
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333 functions that end in "FromISR" can be used in an interrupt. Only assert if
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334 the critical nesting count is 1 to protect against recursive calls if the
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335 assert function also uses a critical section. */
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336 if( uxCriticalNesting == 1 )
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338 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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341 /*-----------------------------------------------------------*/
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343 void vPortExitCritical( void )
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345 configASSERT( uxCriticalNesting );
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346 uxCriticalNesting--;
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347 if( uxCriticalNesting == 0 )
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349 portENABLE_INTERRUPTS();
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352 /*-----------------------------------------------------------*/
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354 void xPortSysTickHandler( void )
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356 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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357 executes all interrupts must be unmasked. There is therefore no need to
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358 save and then restore the interrupt mask value as its value is already
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360 portDISABLE_INTERRUPTS();
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362 /* Increment the RTOS tick. */
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363 if( xTaskIncrementTick() != pdFALSE )
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365 /* A context switch is required. Context switching is performed in
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366 the PendSV interrupt. Pend the PendSV interrupt. */
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367 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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370 portENABLE_INTERRUPTS();
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372 /*-----------------------------------------------------------*/
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374 #if( configUSE_TICKLESS_IDLE == 1 )
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376 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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378 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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379 TickType_t xModifiableIdleTime;
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381 /* Make sure the SysTick reload value does not overflow the counter. */
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382 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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384 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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387 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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388 is accounted for as best it can be, but using the tickless mode will
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389 inevitably result in some tiny drift of the time maintained by the
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390 kernel with respect to calendar time. */
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391 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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393 /* Calculate the reload value required to wait xExpectedIdleTime
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394 tick periods. -1 is used because this code will execute part way
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395 through one of the tick periods. */
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396 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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397 if( ulReloadValue > ulStoppedTimerCompensation )
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399 ulReloadValue -= ulStoppedTimerCompensation;
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402 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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403 method as that will mask interrupts that should exit sleep mode. */
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404 __disable_interrupt();
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408 /* If a context switch is pending or a task is waiting for the scheduler
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409 to be unsuspended then abandon the low power entry. */
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410 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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412 /* Restart from whatever is left in the count register to complete
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413 this tick period. */
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414 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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416 /* Restart SysTick. */
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417 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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419 /* Reset the reload register to the value required for normal tick
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421 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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423 /* Re-enable interrupts - see comments above __disable_interrupt()
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425 __enable_interrupt();
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429 /* Set the new reload value. */
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430 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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432 /* Clear the SysTick count flag and set the count value back to
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434 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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436 /* Restart SysTick. */
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437 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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439 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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440 set its parameter to 0 to indicate that its implementation contains
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441 its own wait for interrupt or wait for event instruction, and so wfi
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442 should not be executed again. However, the original expected idle
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443 time variable must remain unmodified, so a copy is taken. */
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444 xModifiableIdleTime = xExpectedIdleTime;
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445 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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446 if( xModifiableIdleTime > 0 )
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452 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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454 /* Re-enable interrupts to allow the interrupt that brought the MCU
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455 out of sleep mode to execute immediately. see comments above
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456 __disable_interrupt() call above. */
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457 __enable_interrupt();
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461 /* Disable interrupts again because the clock is about to be stopped
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462 and interrupts that execute while the clock is stopped will increase
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463 any slippage between the time maintained by the RTOS and calendar
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465 __disable_interrupt();
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469 /* Disable the SysTick clock without reading the
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470 portNVIC_SYSTICK_CTRL_REG register to ensure the
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471 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
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472 the time the SysTick is stopped for is accounted for as best it can
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473 be, but using the tickless mode will inevitably result in some tiny
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474 drift of the time maintained by the kernel with respect to calendar
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476 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
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478 /* Determine if the SysTick clock has already counted to zero and
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479 been set back to the current reload value (the reload back being
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480 correct for the entire expected idle time) or if the SysTick is yet
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481 to count to zero (in which case an interrupt other than the SysTick
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482 must have brought the system out of sleep mode). */
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483 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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485 uint32_t ulCalculatedLoadValue;
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487 /* The tick interrupt is already pending, and the SysTick count
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488 reloaded with ulReloadValue. Reset the
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489 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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491 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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493 /* Don't allow a tiny value, or values that have somehow
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494 underflowed because the post sleep hook did something
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495 that took too long. */
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496 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
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498 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
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501 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
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503 /* As the pending tick will be processed as soon as this
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504 function exits, the tick value maintained by the tick is stepped
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505 forward by one less than the time spent waiting. */
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506 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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510 /* Something other than the tick interrupt ended the sleep.
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511 Work out how long the sleep lasted rounded to complete tick
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512 periods (not the ulReload value which accounted for part
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514 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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516 /* How many complete tick periods passed while the processor
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518 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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520 /* The reload value is set to whatever fraction of a single tick
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522 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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525 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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526 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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528 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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529 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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530 vTaskStepTick( ulCompleteTickPeriods );
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531 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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533 /* Exit with interrpts enabled. */
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534 __enable_interrupt();
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538 #endif /* configUSE_TICKLESS_IDLE */
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539 /*-----------------------------------------------------------*/
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542 * Setup the systick timer to generate the tick interrupts at the required
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545 __weak void vPortSetupTimerInterrupt( void )
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547 /* Calculate the constants required to configure the tick interrupt. */
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548 #if( configUSE_TICKLESS_IDLE == 1 )
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550 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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551 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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552 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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554 #endif /* configUSE_TICKLESS_IDLE */
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556 /* Stop and clear the SysTick. */
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557 portNVIC_SYSTICK_CTRL_REG = 0UL;
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558 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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560 /* Configure SysTick to interrupt at the requested rate. */
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561 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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562 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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564 /*-----------------------------------------------------------*/
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566 #if( configASSERT_DEFINED == 1 )
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568 void vPortValidateInterruptPriority( void )
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570 uint32_t ulCurrentInterrupt;
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571 uint8_t ucCurrentPriority;
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573 /* Obtain the number of the currently executing interrupt. */
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574 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
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576 /* Is the interrupt number a user defined interrupt? */
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577 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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579 /* Look up the interrupt's priority. */
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580 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
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582 /* The following assertion will fail if a service routine (ISR) for
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583 an interrupt that has been assigned a priority above
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584 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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585 function. ISR safe FreeRTOS API functions must *only* be called
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586 from interrupts that have been assigned a priority at or below
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587 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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589 Numerically low interrupt priority numbers represent logically high
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590 interrupt priorities, therefore the priority of the interrupt must
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591 be set to a value equal to or numerically *higher* than
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592 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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594 Interrupts that use the FreeRTOS API must not be left at their
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595 default priority of zero as that is the highest possible priority,
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596 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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597 and therefore also guaranteed to be invalid.
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599 FreeRTOS maintains separate thread and ISR API functions to ensure
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600 interrupt entry is as fast and simple as possible.
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602 The following links provide detailed information:
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603 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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604 http://www.freertos.org/FAQHelp.html */
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605 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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608 /* Priority grouping: The interrupt controller (NVIC) allows the bits
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609 that define each interrupt's priority to be split between bits that
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610 define the interrupt's pre-emption priority bits and bits that define
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611 the interrupt's sub-priority. For simplicity all bits must be defined
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612 to be pre-emption priority bits. The following assertion will fail if
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613 this is not the case (if some bits represent a sub-priority).
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615 If the application only uses CMSIS libraries for interrupt
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616 configuration then the correct setting can be achieved on all Cortex-M
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617 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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618 scheduler. Note however that some vendor specific peripheral libraries
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619 assume a non-zero priority group setting, in which cases using a value
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620 of zero will result in unpredictable behaviour. */
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621 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
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624 #endif /* configASSERT_DEFINED */
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