1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port source for AVR32 UC3.
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6 * - Compiler: IAR EWAVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 * FreeRTOS Kernel V10.0.0
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17 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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19 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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20 * this software and associated documentation files (the "Software"), to deal in
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21 * the Software without restriction, including without limitation the rights to
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22 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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23 * the Software, and to permit persons to whom the Software is furnished to do so,
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24 * subject to the following conditions:
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26 * The above copyright notice and this permission notice shall be included in all
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27 * copies or substantial portions of the Software. If you wish to use our Amazon
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28 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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30 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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31 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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32 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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33 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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34 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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35 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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37 * http://www.FreeRTOS.org
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38 * http://aws.amazon.com/freertos
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40 * 1 tab == 4 spaces!
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44 /* Scheduler includes. */
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45 #include "FreeRTOS.h"
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48 /* AVR32 UC3 includes. */
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49 #include <avr32/io.h>
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50 #include <intrinsics.h>
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57 #if( configTICK_USE_TC==1 )
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62 /* Constants required to setup the task context. */
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63 #define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
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64 #define portINSTRUCTION_SIZE ( ( StackType_t ) 0 )
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66 /* Each task maintains its own critical nesting variable. */
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67 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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68 volatile uint32_t ulCriticalNesting = 9999UL;
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70 #if( configTICK_USE_TC==0 )
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71 static void prvScheduleNextTick( void );
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73 static void prvClearTcInt( void );
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76 /* Setup the timer to generate the tick interrupts. */
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77 static void prvSetupTimerInterrupt( void );
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79 /*-----------------------------------------------------------*/
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82 * Low-level initialization routine called during startup, before the main
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85 int __low_level_init(void)
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88 #pragma segment = "HEAP"
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92 /* Enable exceptions. */
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93 ENABLE_ALL_EXCEPTIONS();
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95 /* Initialize interrupt handling. */
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96 INTC_init_interrupts();
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100 /* Initialize the heap used by malloc. */
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101 for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); )
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103 *pxMem++ = 0xA5A5A5A5;
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108 /* Code section present if and only if the debug trace is activated. */
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111 static const gpio_map_t DBG_USART_GPIO_MAP =
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113 { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
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114 { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
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117 static const usart_options_t DBG_USART_OPTIONS =
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119 .baudrate = configDBG_USART_BAUDRATE,
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121 .paritytype = USART_NO_PARITY,
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122 .stopbits = USART_1_STOPBIT,
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123 .channelmode = USART_NORMAL_CHMODE
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126 /* Initialize the USART used for the debug trace with the configured parameters. */
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127 extern volatile avr32_usart_t *volatile stdio_usart_base;
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128 stdio_usart_base = configDBG_USART;
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129 gpio_enable_module( DBG_USART_GPIO_MAP,
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130 sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
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131 usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
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135 /* Request initialization of data segments. */
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138 /*-----------------------------------------------------------*/
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140 /* Added as there is no such function in FreeRTOS. */
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141 void *pvPortRealloc( void *pv, size_t xWantedSize )
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147 pvReturn = realloc( pv, xWantedSize );
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153 /*-----------------------------------------------------------*/
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155 /* The cooperative scheduler requires a normal IRQ service routine to
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156 simply increment the system tick. */
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157 /* The preemptive scheduler is defined as "naked" as the full context is saved
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158 on entry as part of the context switch. */
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159 #pragma shadow_registers = full // Naked.
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160 static void vTick( void )
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162 /* Save the context of the interrupted task. */
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163 portSAVE_CONTEXT_OS_INT();
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165 #if( configTICK_USE_TC==1 )
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166 /* Clear the interrupt flag. */
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169 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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170 clock cycles from now. */
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171 prvScheduleNextTick();
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174 /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
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175 calls in a critical section . */
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176 portENTER_CRITICAL();
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177 xTaskIncrementTick();
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178 portEXIT_CRITICAL();
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180 /* Restore the context of the "elected task". */
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181 portRESTORE_CONTEXT_OS_INT();
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183 /*-----------------------------------------------------------*/
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185 #pragma shadow_registers = full // Naked.
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186 void SCALLYield( void )
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188 /* Save the context of the interrupted task. */
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189 portSAVE_CONTEXT_SCALL();
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190 vTaskSwitchContext();
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191 portRESTORE_CONTEXT_SCALL();
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193 /*-----------------------------------------------------------*/
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195 /* The code generated by the GCC compiler uses the stack in different ways at
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196 different optimisation levels. The interrupt flags can therefore not always
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197 be saved to the stack. Instead the critical section nesting level is stored
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198 in a variable, which is then saved as part of the stack context. */
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199 #pragma optimize = no_inline
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200 void vPortEnterCritical( void )
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202 /* Disable interrupts */
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203 portDISABLE_INTERRUPTS();
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205 /* Now interrupts are disabled ulCriticalNesting can be accessed
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206 directly. Increment ulCriticalNesting to keep a count of how many times
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207 portENTER_CRITICAL() has been called. */
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208 ulCriticalNesting++;
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210 /*-----------------------------------------------------------*/
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212 #pragma optimize = no_inline
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213 void vPortExitCritical( void )
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215 if(ulCriticalNesting > portNO_CRITICAL_NESTING)
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217 ulCriticalNesting--;
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218 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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220 /* Enable all interrupt/exception. */
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221 portENABLE_INTERRUPTS();
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225 /*-----------------------------------------------------------*/
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228 * Initialise the stack of a task to look exactly as if a call to
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229 * portSAVE_CONTEXT had been called.
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231 * See header file for description.
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233 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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235 /* Setup the initial stack of the task. The stack is set exactly as
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236 expected by the portRESTORE_CONTEXT() macro. */
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238 /* When the task starts, it will expect to find the function parameter in R12. */
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240 *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */
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241 *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */
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242 *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */
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243 *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */
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244 *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */
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245 *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */
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246 *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
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247 *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */
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248 *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */
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249 *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */
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250 *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */
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251 *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */
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252 *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */
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253 *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
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254 *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
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255 *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
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256 *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
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258 return pxTopOfStack;
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260 /*-----------------------------------------------------------*/
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262 BaseType_t xPortStartScheduler( void )
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264 /* Start the timer that generates the tick ISR. Interrupts are disabled
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266 prvSetupTimerInterrupt();
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268 /* Start the first task. */
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269 portRESTORE_CONTEXT();
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271 /* Should not get here! */
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274 /*-----------------------------------------------------------*/
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276 void vPortEndScheduler( void )
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278 /* It is unlikely that the AVR32 port will require this function as there
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279 is nothing to return to. */
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281 /*-----------------------------------------------------------*/
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283 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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284 clock cycles from now. */
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285 #if( configTICK_USE_TC==0 )
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286 static void prvScheduleFirstTick(void)
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290 lCycles = Get_system_register(AVR32_COUNT);
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291 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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292 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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293 // generation feature does not get disabled.
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298 Set_system_register(AVR32_COMPARE, lCycles);
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301 #pragma optimize = no_inline
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302 static void prvScheduleNextTick(void)
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304 uint32_t lCycles, lCount;
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306 lCycles = Get_system_register(AVR32_COMPARE);
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307 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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308 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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309 // generation feature does not get disabled.
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314 lCount = Get_system_register(AVR32_COUNT);
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315 if( lCycles < lCount )
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316 { // We missed a tick, recover for the next.
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317 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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319 Set_system_register(AVR32_COMPARE, lCycles);
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322 #pragma optimize = no_inline
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323 static void prvClearTcInt(void)
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325 AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
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328 /*-----------------------------------------------------------*/
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330 /* Setup the timer to generate the tick interrupts. */
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331 static void prvSetupTimerInterrupt(void)
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333 #if( configTICK_USE_TC==1 )
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335 volatile avr32_tc_t *tc = &AVR32_TC;
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337 // Options for waveform genration.
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338 tc_waveform_opt_t waveform_opt =
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340 .channel = configTICK_TC_CHANNEL, /* Channel selection. */
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342 .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
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343 .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
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344 .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
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345 .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
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347 .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
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348 .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
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349 .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
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350 .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
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352 .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
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353 .enetrg = FALSE, /* External event trigger enable. */
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354 .eevt = 0, /* External event selection. */
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355 .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
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356 .cpcdis = FALSE, /* Counter disable when RC compare. */
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357 .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
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359 .burst = FALSE, /* Burst signal selection. */
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360 .clki = FALSE, /* Clock inversion. */
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361 .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
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364 tc_interrupt_t tc_interrupt =
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378 /* Disable all interrupt/exception. */
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379 portDISABLE_INTERRUPTS();
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381 /* Register the compare interrupt handler to the interrupt controller and
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382 enable the compare interrupt. */
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384 #if( configTICK_USE_TC==1 )
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386 INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
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388 /* Initialize the timer/counter. */
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389 tc_init_waveform(tc, &waveform_opt);
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391 /* Set the compare triggers.
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392 Remember TC counter is 16-bits, so counting second is not possible!
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393 That's why we configure it to count ms. */
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394 tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
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396 tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
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398 /* Start the timer/counter. */
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399 tc_start(tc, configTICK_TC_CHANNEL);
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403 INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
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404 prvScheduleFirstTick();
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