1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port header for AVR32 UC3.
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6 * - Compiler: IAR EWAVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 * FreeRTOS Kernel V10.3.0
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17 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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19 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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20 * this software and associated documentation files (the "Software"), to deal in
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21 * the Software without restriction, including without limitation the rights to
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22 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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23 * the Software, and to permit persons to whom the Software is furnished to do so,
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24 * subject to the following conditions:
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26 * The above copyright notice and this permission notice shall be included in all
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27 * copies or substantial portions of the Software.
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29 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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30 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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31 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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32 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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33 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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34 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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36 * http://www.FreeRTOS.org
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37 * http://aws.amazon.com/freertos
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39 * 1 tab == 4 spaces!
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47 /*-----------------------------------------------------------
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48 * Port specific definitions.
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50 * The settings in this file configure FreeRTOS correctly for the
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51 * given hardware and compiler.
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53 * These settings should not be altered.
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54 *-----------------------------------------------------------
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56 #include <avr32/io.h>
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58 #include "compiler.h"
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65 /* Type definitions. */
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66 #define portCHAR char
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67 #define portFLOAT float
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68 #define portDOUBLE double
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69 #define portLONG long
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70 #define portSHORT short
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71 #define portSTACK_TYPE uint32_t
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72 #define portBASE_TYPE long
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74 typedef portSTACK_TYPE StackType_t;
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75 typedef long BaseType_t;
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76 typedef unsigned long UBaseType_t;
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79 #define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS )
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80 #define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS )
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81 #define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS )
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83 #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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85 #if( configUSE_16_BIT_TICKS == 1 )
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86 typedef uint16_t TickType_t;
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87 #define portMAX_DELAY ( TickType_t ) 0xffff
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89 typedef uint32_t TickType_t;
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90 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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92 /*-----------------------------------------------------------*/
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94 /* Architecture specifics. */
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95 #define portSTACK_GROWTH ( -1 )
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96 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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97 #define portBYTE_ALIGNMENT 4
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98 #define portNOP() {__asm__ __volatile__ ("nop");}
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99 /*-----------------------------------------------------------*/
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102 /*-----------------------------------------------------------*/
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104 /* INTC-specific. */
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105 #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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106 #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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108 #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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109 #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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111 #define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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112 #define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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117 * Activated if and only if configDBG is nonzero.
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118 * Prints a formatted string to stdout.
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119 * The current source file name and line number are output with a colon before
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120 * the formatted string.
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121 * A carriage return and a linefeed are appended to the output.
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122 * stdout is redirected to the USART configured by configDBG_USART.
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123 * The parameters are the same as for the standard printf function.
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124 * There is no return value.
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125 * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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126 * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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129 #define portDBG_TRACE(...) \
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131 fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \
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132 printf(__VA_ARGS__); \
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133 fputs("\r\n", stdout); \
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136 #define portDBG_TRACE(...)
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140 /* Critical section management. */
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141 #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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142 #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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145 extern void vPortEnterCritical( void );
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146 extern void vPortExitCritical( void );
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148 #define portENTER_CRITICAL() vPortEnterCritical();
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149 #define portEXIT_CRITICAL() vPortExitCritical();
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152 /* Added as there is no such function in FreeRTOS. */
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153 extern void *pvPortRealloc( void *pv, size_t xSize );
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154 /*-----------------------------------------------------------*/
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157 /*=============================================================================================*/
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160 * Restore Context for cases other than INTi.
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162 #define portRESTORE_CONTEXT() \
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164 extern volatile uint32_t ulCriticalNesting; \
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165 extern volatile void *volatile pxCurrentTCB; \
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167 __asm__ __volatile__ ( \
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168 /* Set SP to point to new stack */ \
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169 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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170 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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171 "ld.w r0, r8[0] \n\t"\
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172 "ld.w sp, r0[0] \n\t"\
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174 /* Restore ulCriticalNesting variable */ \
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175 "ld.w r0, sp++ \n\t"\
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176 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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177 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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178 "st.w r8[0], r0 \n\t"\
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180 /* Restore R0..R7 */ \
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181 "ldm sp++, r0-r7 \n\t"\
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182 /* R0-R7 should not be used below this line */ \
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183 /* Skip PC and SR (will do it at the end) */ \
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184 "sub sp, -2*4 \n\t"\
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185 /* Restore R8..R12 and LR */ \
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186 "ldm sp++, r8-r12, lr \n\t"\
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188 "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\
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189 "mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\
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191 "ld.w r0, sp[-9*4] \n\t"\
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193 "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
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196 /* Force import of global symbols from assembly */ \
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197 ulCriticalNesting; \
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203 * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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204 * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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206 * Had to make different versions because registers saved on the system stack
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207 * are not the same between INT0..3 exceptions and the scall exception.
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210 // Task context stack layout:
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227 // ulCriticalNesting
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228 // (*) automatically done for INT0..INT3, but not for SCALL
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231 * The ISR used for the scheduler tick depends on whether the cooperative or
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232 * the preemptive scheduler is being used.
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234 #if configUSE_PREEMPTION == 0
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237 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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239 #define portSAVE_CONTEXT_OS_INT() \
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241 /* Save R0..R7 */ \
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242 __asm__ __volatile__ ("stm --sp, r0-r7"); \
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244 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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245 /* there is also no context save. */ \
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249 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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251 #define portRESTORE_CONTEXT_OS_INT() \
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253 __asm__ __volatile__ ( \
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254 /* Restore R0..R7 */ \
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255 "ldm sp++, r0-r7 \n\t"\
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257 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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258 /* there is also no context restore. */ \
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266 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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268 #define portSAVE_CONTEXT_OS_INT() \
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270 extern volatile uint32_t ulCriticalNesting; \
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271 extern volatile void *volatile pxCurrentTCB; \
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273 /* When we come here */ \
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274 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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276 __asm__ __volatile__ ( \
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277 /* Save R0..R7 */ \
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278 "stm --sp, r0-r7 \n\t"\
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280 /* Save ulCriticalNesting variable - R0 is overwritten */ \
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281 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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282 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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283 "ld.w r0, r8[0] \n\t"\
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284 "st.w --sp, r0 \n\t"\
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286 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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287 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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288 /* level and allow other lower interrupt level to occur). */ \
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289 /* In this case we don't want to do a task switch because we don't know what the stack */ \
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290 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
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291 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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292 /* will just be restoring the interrupt handler, no way!!! */ \
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293 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
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294 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
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295 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
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296 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
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297 "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
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299 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
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300 /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
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301 /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
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302 /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
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303 /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
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304 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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305 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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306 "ld.w r0, r8[0] \n\t"\
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307 "st.w r0[0], sp \n"\
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309 "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
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314 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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316 #define portRESTORE_CONTEXT_OS_INT() \
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318 extern volatile uint32_t ulCriticalNesting; \
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319 extern volatile void *volatile pxCurrentTCB; \
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321 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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322 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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323 /* level and allow other lower interrupt level to occur). */ \
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324 /* In this case we don't want to do a task switch because we don't know what the stack */ \
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325 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
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326 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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327 /* will just be restoring the interrupt handler, no way!!! */ \
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328 __asm__ __volatile__ ( \
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329 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
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330 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
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331 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
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332 "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \
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336 /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
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337 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
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338 portENTER_CRITICAL(); \
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339 vTaskSwitchContext(); \
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340 portEXIT_CRITICAL(); \
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342 /* Restore all registers */ \
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344 __asm__ __volatile__ ( \
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345 /* Set SP to point to new stack */ \
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346 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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347 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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348 "ld.w r0, r8[0] \n\t"\
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349 "ld.w sp, r0[0] \n"\
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351 "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
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353 /* Restore ulCriticalNesting variable */ \
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354 "ld.w r0, sp++ \n\t"\
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355 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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356 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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357 "st.w r8[0], r0 \n\t"\
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359 /* Restore R0..R7 */ \
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360 "ldm sp++, r0-r7 \n\t"\
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362 /* Now, the stack should be R8..R12, LR, PC and SR */ \
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366 /* Force import of global symbols from assembly */ \
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367 ulCriticalNesting; \
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375 * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
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377 * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
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380 #define portSAVE_CONTEXT_SCALL() \
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382 extern volatile uint32_t ulCriticalNesting; \
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383 extern volatile void *volatile pxCurrentTCB; \
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385 /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
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386 /* If SR[M2:M0] == 001 */ \
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387 /* PC and SR are on the stack. */ \
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388 /* Else (other modes) */ \
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389 /* Nothing on the stack. */ \
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391 /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
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392 /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
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393 /* in an interrupt|exception handler. */ \
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395 __asm__ __volatile__ ( \
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396 /* in order to save R0-R7 */ \
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397 "sub sp, 6*4 \n\t"\
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398 /* Save R0..R7 */ \
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399 "stm --sp, r0-r7 \n\t"\
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401 /* in order to save R8-R12 and LR */ \
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402 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
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403 "sub r7, sp,-16*4 \n\t"\
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404 /* Copy PC and SR in other places in the stack. */ \
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405 "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
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406 "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
\r
407 "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
\r
408 "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
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410 /* Save R8..R12 and LR on the stack. */ \
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411 "stm --r7, r8-r12, lr \n\t"\
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413 /* Arriving here we have the following stack organizations: */ \
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414 /* R8..R12, LR, PC, SR, R0..R7. */ \
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416 /* Now we can finalize the save. */ \
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418 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
419 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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420 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
421 "ld.w r0, r8[0] \n\t"\
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425 /* Disable the its which may cause a context switch (i.e. cause a change of */ \
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426 /* pxCurrentTCB). */ \
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427 /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
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428 /* critical section because it is a global structure. */ \
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429 portENTER_CRITICAL(); \
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431 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
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432 __asm__ __volatile__ ( \
\r
433 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
434 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
435 "ld.w r0, r8[0] \n\t"\
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441 * portRESTORE_CONTEXT() for SupervisorCALL exception.
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443 #define portRESTORE_CONTEXT_SCALL() \
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445 extern volatile uint32_t ulCriticalNesting; \
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446 extern volatile void *volatile pxCurrentTCB; \
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448 /* Restore all registers */ \
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450 /* Set SP to point to new stack */ \
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451 __asm__ __volatile__ ( \
\r
452 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
453 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
454 "ld.w r0, r8[0] \n\t"\
\r
458 /* Leave pxCurrentTCB variable access critical section */ \
\r
459 portEXIT_CRITICAL(); \
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461 __asm__ __volatile__ ( \
\r
462 /* Restore ulCriticalNesting variable */ \
\r
463 "ld.w r0, sp++ \n\t"\
\r
464 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
465 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
466 "st.w r8[0], r0 \n\t"\
\r
468 /* skip PC and SR */ \
\r
469 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
470 "sub r7, sp, -10*4 \n\t"\
\r
471 /* Restore r8-r12 and LR */ \
\r
472 "ldm r7++, r8-r12, lr \n\t"\
\r
474 /* RETS will take care of the extra PC and SR restore. */ \
\r
475 /* So, we have to prepare the stack for this. */ \
\r
476 "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
\r
477 "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
\r
478 "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
\r
479 "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
\r
481 /* Restore R0..R7 */ \
\r
482 "ldm sp++, r0-r7 \n\t"\
\r
484 "sub sp, -6*4 \n\t"\
\r
489 /* Force import of global symbols from assembly */ \
\r
490 ulCriticalNesting; \
\r
496 * The ISR used depends on whether the cooperative or
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497 * the preemptive scheduler is being used.
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499 #if configUSE_PREEMPTION == 0
\r
502 * ISR entry and exit macros. These are only required if a task switch
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503 * is required from the ISR.
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505 #define portENTER_SWITCHING_ISR() \
\r
507 /* Save R0..R7 */ \
\r
508 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
510 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
511 /* there is also no context save. */ \
\r
515 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
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517 #define portEXIT_SWITCHING_ISR() \
\r
519 __asm__ __volatile__ ( \
\r
520 /* Restore R0..R7 */ \
\r
521 "ldm sp++, r0-r7 \n\t"\
\r
523 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
524 /* there is also no context restore. */ \
\r
532 * ISR entry and exit macros. These are only required if a task switch
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533 * is required from the ISR.
\r
535 #define portENTER_SWITCHING_ISR() \
\r
537 extern volatile uint32_t ulCriticalNesting; \
\r
538 extern volatile void *volatile pxCurrentTCB; \
\r
540 /* When we come here */ \
\r
541 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\r
543 __asm__ __volatile__ ( \
\r
544 /* Save R0..R7 */ \
\r
545 "stm --sp, r0-r7 \n\t"\
\r
547 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
548 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
549 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
550 "ld.w r0, r8[0] \n\t"\
\r
551 "st.w --sp, r0 \n\t"\
\r
553 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
554 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
555 /* level and allow other lower interrupt level to occur). */ \
\r
556 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
557 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
558 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
559 /* will just be restoring the interrupt handler, no way!!! */ \
\r
560 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
561 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
562 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
563 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
564 "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
\r
566 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
567 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
568 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
569 "ld.w r0, r8[0] \n\t"\
\r
570 "st.w r0[0], sp \n"\
\r
572 "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
\r
578 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
580 #define portEXIT_SWITCHING_ISR() \
\r
582 extern volatile uint32_t ulCriticalNesting; \
\r
583 extern volatile void *volatile pxCurrentTCB; \
\r
585 __asm__ __volatile__ ( \
\r
586 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
587 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
588 /* level and allow other lower interrupt level to occur). */ \
\r
589 /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
\r
590 /* did not previously save SP in its TCB. */ \
\r
591 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
592 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
593 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
594 "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
\r
596 /* If a switch is required then we just need to call */ \
\r
597 /* vTaskSwitchContext() as the context has already been */ \
\r
599 "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
\r
600 "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \
\r
603 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
\r
604 portENTER_CRITICAL(); \
\r
605 vTaskSwitchContext(); \
\r
606 portEXIT_CRITICAL(); \
\r
608 __asm__ __volatile__ ( \
\r
609 "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
610 /* Restore the context of which ever task is now the highest */ \
\r
611 /* priority that is ready to run. */ \
\r
613 /* Restore all registers */ \
\r
615 /* Set SP to point to new stack */ \
\r
616 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
617 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
618 "ld.w r0, r8[0] \n\t"\
\r
619 "ld.w sp, r0[0] \n"\
\r
621 "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
623 /* Restore ulCriticalNesting variable */ \
\r
624 "ld.w r0, sp++ \n\t"\
\r
625 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
626 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
627 "st.w r8[0], r0 \n\t"\
\r
629 /* Restore R0..R7 */ \
\r
630 "ldm sp++, r0-r7 \n\t"\
\r
632 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
636 /* Force import of global symbols from assembly */ \
\r
637 ulCriticalNesting; \
\r
644 #define portYIELD() {__asm__ __volatile__ ("scall");}
\r
646 /* Task function macros as described on the FreeRTOS.org WEB site. */
\r
647 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
648 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
654 #endif /* PORTMACRO_H */
\r
projects / freertos / blob