1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port header for AVR32 UC3.
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6 * - Compiler: IAR EWAVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
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19 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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27 ***************************************************************************
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28 >>! NOTE: The modification to the GPL is included to allow you to !<<
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29 >>! distribute a combined work that includes FreeRTOS without being !<<
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30 >>! obliged to provide the source code for proprietary components !<<
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31 >>! outside of the FreeRTOS kernel. !<<
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32 ***************************************************************************
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34 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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35 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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36 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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37 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * FreeRTOS provides completely free yet professionally developed, *
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42 * robust, strictly quality controlled, supported, and cross *
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43 * platform software that is more than just the market leader, it *
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44 * is the industry's de facto standard. *
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46 * Help yourself get started quickly while simultaneously helping *
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47 * to support the FreeRTOS project by purchasing a FreeRTOS *
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48 * tutorial book, reference manual, or both: *
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49 * http://www.FreeRTOS.org/Documentation *
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51 ***************************************************************************
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53 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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54 the FAQ page "My application does not run, what could be wrong?". Have you
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55 defined configASSERT()?
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57 http://www.FreeRTOS.org/support - In return for receiving this top quality
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58 embedded software for free we request you assist our global community by
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59 participating in the support forum.
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61 http://www.FreeRTOS.org/training - Investing in training allows your team to
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62 be as productive as possible as early as possible. Now you can receive
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63 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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64 Ltd, and the world's leading authority on the world's leading RTOS.
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66 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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67 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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68 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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70 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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71 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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73 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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74 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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75 licenses offer ticketed support, indemnification and commercial middleware.
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77 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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78 engineered and independently SIL3 certified version for use in safety and
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79 mission critical applications that require provable dependability.
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89 /*-----------------------------------------------------------
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90 * Port specific definitions.
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92 * The settings in this file configure FreeRTOS correctly for the
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93 * given hardware and compiler.
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95 * These settings should not be altered.
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96 *-----------------------------------------------------------
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98 #include <avr32/io.h>
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100 #include "compiler.h"
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107 /* Type definitions. */
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108 #define portCHAR char
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109 #define portFLOAT float
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110 #define portDOUBLE double
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111 #define portLONG long
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112 #define portSHORT short
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113 #define portSTACK_TYPE uint32_t
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114 #define portBASE_TYPE long
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116 typedef portSTACK_TYPE StackType_t;
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117 typedef long BaseType_t;
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118 typedef unsigned long UBaseType_t;
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121 #define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS )
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122 #define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS )
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123 #define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS )
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125 #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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127 #if( configUSE_16_BIT_TICKS == 1 )
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128 typedef uint16_t TickType_t;
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129 #define portMAX_DELAY ( TickType_t ) 0xffff
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131 typedef uint32_t TickType_t;
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132 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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134 /*-----------------------------------------------------------*/
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136 /* Architecture specifics. */
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137 #define portSTACK_GROWTH ( -1 )
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138 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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139 #define portBYTE_ALIGNMENT 4
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140 #define portNOP() {__asm__ __volatile__ ("nop");}
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141 /*-----------------------------------------------------------*/
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144 /*-----------------------------------------------------------*/
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146 /* INTC-specific. */
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147 #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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148 #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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150 #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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151 #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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153 #define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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154 #define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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159 * Activated if and only if configDBG is nonzero.
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160 * Prints a formatted string to stdout.
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161 * The current source file name and line number are output with a colon before
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162 * the formatted string.
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163 * A carriage return and a linefeed are appended to the output.
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164 * stdout is redirected to the USART configured by configDBG_USART.
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165 * The parameters are the same as for the standard printf function.
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166 * There is no return value.
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167 * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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168 * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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171 #define portDBG_TRACE(...) \
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173 fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \
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174 printf(__VA_ARGS__); \
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175 fputs("\r\n", stdout); \
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178 #define portDBG_TRACE(...)
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182 /* Critical section management. */
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183 #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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184 #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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187 extern void vPortEnterCritical( void );
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188 extern void vPortExitCritical( void );
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190 #define portENTER_CRITICAL() vPortEnterCritical();
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191 #define portEXIT_CRITICAL() vPortExitCritical();
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194 /* Added as there is no such function in FreeRTOS. */
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195 extern void *pvPortRealloc( void *pv, size_t xSize );
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196 /*-----------------------------------------------------------*/
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199 /*=============================================================================================*/
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202 * Restore Context for cases other than INTi.
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204 #define portRESTORE_CONTEXT() \
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206 extern volatile uint32_t ulCriticalNesting; \
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207 extern volatile void *volatile pxCurrentTCB; \
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209 __asm__ __volatile__ ( \
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210 /* Set SP to point to new stack */ \
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211 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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212 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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213 "ld.w r0, r8[0] \n\t"\
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214 "ld.w sp, r0[0] \n\t"\
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216 /* Restore ulCriticalNesting variable */ \
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217 "ld.w r0, sp++ \n\t"\
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218 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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219 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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220 "st.w r8[0], r0 \n\t"\
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222 /* Restore R0..R7 */ \
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223 "ldm sp++, r0-r7 \n\t"\
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224 /* R0-R7 should not be used below this line */ \
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225 /* Skip PC and SR (will do it at the end) */ \
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226 "sub sp, -2*4 \n\t"\
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227 /* Restore R8..R12 and LR */ \
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228 "ldm sp++, r8-r12, lr \n\t"\
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230 "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\
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231 "mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\
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233 "ld.w r0, sp[-9*4] \n\t"\
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235 "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
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238 /* Force import of global symbols from assembly */ \
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239 ulCriticalNesting; \
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245 * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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246 * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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248 * Had to make different versions because registers saved on the system stack
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249 * are not the same between INT0..3 exceptions and the scall exception.
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252 // Task context stack layout:
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269 // ulCriticalNesting
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270 // (*) automatically done for INT0..INT3, but not for SCALL
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273 * The ISR used for the scheduler tick depends on whether the cooperative or
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274 * the preemptive scheduler is being used.
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276 #if configUSE_PREEMPTION == 0
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279 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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281 #define portSAVE_CONTEXT_OS_INT() \
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283 /* Save R0..R7 */ \
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284 __asm__ __volatile__ ("stm --sp, r0-r7"); \
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286 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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287 /* there is also no context save. */ \
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291 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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293 #define portRESTORE_CONTEXT_OS_INT() \
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295 __asm__ __volatile__ ( \
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296 /* Restore R0..R7 */ \
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297 "ldm sp++, r0-r7 \n\t"\
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299 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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300 /* there is also no context restore. */ \
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308 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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310 #define portSAVE_CONTEXT_OS_INT() \
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312 extern volatile uint32_t ulCriticalNesting; \
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313 extern volatile void *volatile pxCurrentTCB; \
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315 /* When we come here */ \
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316 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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318 __asm__ __volatile__ ( \
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319 /* Save R0..R7 */ \
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320 "stm --sp, r0-r7 \n\t"\
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322 /* Save ulCriticalNesting variable - R0 is overwritten */ \
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323 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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324 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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325 "ld.w r0, r8[0] \n\t"\
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326 "st.w --sp, r0 \n\t"\
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328 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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329 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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330 /* level and allow other lower interrupt level to occur). */ \
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331 /* In this case we don't want to do a task switch because we don't know what the stack */ \
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332 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
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333 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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334 /* will just be restoring the interrupt handler, no way!!! */ \
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335 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
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336 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
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337 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
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338 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
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339 "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
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341 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
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342 /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
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343 /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
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344 /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
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345 /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
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346 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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347 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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348 "ld.w r0, r8[0] \n\t"\
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349 "st.w r0[0], sp \n"\
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351 "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
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356 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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358 #define portRESTORE_CONTEXT_OS_INT() \
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360 extern volatile uint32_t ulCriticalNesting; \
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361 extern volatile void *volatile pxCurrentTCB; \
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363 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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364 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
365 /* level and allow other lower interrupt level to occur). */ \
\r
366 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
367 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
368 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
369 /* will just be restoring the interrupt handler, no way!!! */ \
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370 __asm__ __volatile__ ( \
\r
371 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
372 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
373 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
374 "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \
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378 /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
\r
379 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
\r
380 portENTER_CRITICAL(); \
\r
381 vTaskSwitchContext(); \
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382 portEXIT_CRITICAL(); \
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384 /* Restore all registers */ \
\r
386 __asm__ __volatile__ ( \
\r
387 /* Set SP to point to new stack */ \
\r
388 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
389 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
390 "ld.w r0, r8[0] \n\t"\
\r
391 "ld.w sp, r0[0] \n"\
\r
393 "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
395 /* Restore ulCriticalNesting variable */ \
\r
396 "ld.w r0, sp++ \n\t"\
\r
397 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
398 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
399 "st.w r8[0], r0 \n\t"\
\r
401 /* Restore R0..R7 */ \
\r
402 "ldm sp++, r0-r7 \n\t"\
\r
404 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
408 /* Force import of global symbols from assembly */ \
\r
409 ulCriticalNesting; \
\r
417 * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
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419 * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
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422 #define portSAVE_CONTEXT_SCALL() \
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424 extern volatile uint32_t ulCriticalNesting; \
\r
425 extern volatile void *volatile pxCurrentTCB; \
\r
427 /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
\r
428 /* If SR[M2:M0] == 001 */ \
\r
429 /* PC and SR are on the stack. */ \
\r
430 /* Else (other modes) */ \
\r
431 /* Nothing on the stack. */ \
\r
433 /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
\r
434 /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
\r
435 /* in an interrupt|exception handler. */ \
\r
437 __asm__ __volatile__ ( \
\r
438 /* in order to save R0-R7 */ \
\r
439 "sub sp, 6*4 \n\t"\
\r
440 /* Save R0..R7 */ \
\r
441 "stm --sp, r0-r7 \n\t"\
\r
443 /* in order to save R8-R12 and LR */ \
\r
444 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
445 "sub r7, sp,-16*4 \n\t"\
\r
446 /* Copy PC and SR in other places in the stack. */ \
\r
447 "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
\r
448 "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
\r
449 "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
\r
450 "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
\r
452 /* Save R8..R12 and LR on the stack. */ \
\r
453 "stm --r7, r8-r12, lr \n\t"\
\r
455 /* Arriving here we have the following stack organizations: */ \
\r
456 /* R8..R12, LR, PC, SR, R0..R7. */ \
\r
458 /* Now we can finalize the save. */ \
\r
460 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
461 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
462 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
463 "ld.w r0, r8[0] \n\t"\
\r
467 /* Disable the its which may cause a context switch (i.e. cause a change of */ \
\r
468 /* pxCurrentTCB). */ \
\r
469 /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
\r
470 /* critical section because it is a global structure. */ \
\r
471 portENTER_CRITICAL(); \
\r
473 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
474 __asm__ __volatile__ ( \
\r
475 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
476 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
477 "ld.w r0, r8[0] \n\t"\
\r
483 * portRESTORE_CONTEXT() for SupervisorCALL exception.
\r
485 #define portRESTORE_CONTEXT_SCALL() \
\r
487 extern volatile uint32_t ulCriticalNesting; \
\r
488 extern volatile void *volatile pxCurrentTCB; \
\r
490 /* Restore all registers */ \
\r
492 /* Set SP to point to new stack */ \
\r
493 __asm__ __volatile__ ( \
\r
494 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
495 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
496 "ld.w r0, r8[0] \n\t"\
\r
500 /* Leave pxCurrentTCB variable access critical section */ \
\r
501 portEXIT_CRITICAL(); \
\r
503 __asm__ __volatile__ ( \
\r
504 /* Restore ulCriticalNesting variable */ \
\r
505 "ld.w r0, sp++ \n\t"\
\r
506 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
507 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
508 "st.w r8[0], r0 \n\t"\
\r
510 /* skip PC and SR */ \
\r
511 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
512 "sub r7, sp, -10*4 \n\t"\
\r
513 /* Restore r8-r12 and LR */ \
\r
514 "ldm r7++, r8-r12, lr \n\t"\
\r
516 /* RETS will take care of the extra PC and SR restore. */ \
\r
517 /* So, we have to prepare the stack for this. */ \
\r
518 "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
\r
519 "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
\r
520 "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
\r
521 "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
\r
523 /* Restore R0..R7 */ \
\r
524 "ldm sp++, r0-r7 \n\t"\
\r
526 "sub sp, -6*4 \n\t"\
\r
531 /* Force import of global symbols from assembly */ \
\r
532 ulCriticalNesting; \
\r
538 * The ISR used depends on whether the cooperative or
\r
539 * the preemptive scheduler is being used.
\r
541 #if configUSE_PREEMPTION == 0
\r
544 * ISR entry and exit macros. These are only required if a task switch
\r
545 * is required from the ISR.
\r
547 #define portENTER_SWITCHING_ISR() \
\r
549 /* Save R0..R7 */ \
\r
550 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
552 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
553 /* there is also no context save. */ \
\r
557 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
559 #define portEXIT_SWITCHING_ISR() \
\r
561 __asm__ __volatile__ ( \
\r
562 /* Restore R0..R7 */ \
\r
563 "ldm sp++, r0-r7 \n\t"\
\r
565 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
566 /* there is also no context restore. */ \
\r
574 * ISR entry and exit macros. These are only required if a task switch
\r
575 * is required from the ISR.
\r
577 #define portENTER_SWITCHING_ISR() \
\r
579 extern volatile uint32_t ulCriticalNesting; \
\r
580 extern volatile void *volatile pxCurrentTCB; \
\r
582 /* When we come here */ \
\r
583 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\r
585 __asm__ __volatile__ ( \
\r
586 /* Save R0..R7 */ \
\r
587 "stm --sp, r0-r7 \n\t"\
\r
589 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
590 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
591 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
592 "ld.w r0, r8[0] \n\t"\
\r
593 "st.w --sp, r0 \n\t"\
\r
595 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
596 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
597 /* level and allow other lower interrupt level to occur). */ \
\r
598 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
599 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
600 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
601 /* will just be restoring the interrupt handler, no way!!! */ \
\r
602 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
603 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
604 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
605 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
606 "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
\r
608 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
609 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
610 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
611 "ld.w r0, r8[0] \n\t"\
\r
612 "st.w r0[0], sp \n"\
\r
614 "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
\r
620 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
622 #define portEXIT_SWITCHING_ISR() \
\r
624 extern volatile uint32_t ulCriticalNesting; \
\r
625 extern volatile void *volatile pxCurrentTCB; \
\r
627 __asm__ __volatile__ ( \
\r
628 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
629 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
630 /* level and allow other lower interrupt level to occur). */ \
\r
631 /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
\r
632 /* did not previously save SP in its TCB. */ \
\r
633 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
634 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
635 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
636 "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
\r
638 /* If a switch is required then we just need to call */ \
\r
639 /* vTaskSwitchContext() as the context has already been */ \
\r
641 "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
\r
642 "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \
\r
645 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
\r
646 portENTER_CRITICAL(); \
\r
647 vTaskSwitchContext(); \
\r
648 portEXIT_CRITICAL(); \
\r
650 __asm__ __volatile__ ( \
\r
651 "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
652 /* Restore the context of which ever task is now the highest */ \
\r
653 /* priority that is ready to run. */ \
\r
655 /* Restore all registers */ \
\r
657 /* Set SP to point to new stack */ \
\r
658 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
659 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
660 "ld.w r0, r8[0] \n\t"\
\r
661 "ld.w sp, r0[0] \n"\
\r
663 "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
665 /* Restore ulCriticalNesting variable */ \
\r
666 "ld.w r0, sp++ \n\t"\
\r
667 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
668 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
669 "st.w r8[0], r0 \n\t"\
\r
671 /* Restore R0..R7 */ \
\r
672 "ldm sp++, r0-r7 \n\t"\
\r
674 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
678 /* Force import of global symbols from assembly */ \
\r
679 ulCriticalNesting; \
\r
686 #define portYIELD() {__asm__ __volatile__ ("scall");}
\r
688 /* Task function macros as described on the FreeRTOS.org WEB site. */
\r
689 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
690 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
696 #endif /* PORTMACRO_H */
\r
projects / freertos / blob