2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
5 ***************************************************************************
\r
7 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
8 * Complete, revised, and edited pdf reference manuals are also *
\r
11 * Purchasing FreeRTOS documentation will not only help you, by *
\r
12 * ensuring you get running as quickly as possible and with an *
\r
13 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
14 * the FreeRTOS project to continue with its mission of providing *
\r
15 * professional grade, cross platform, de facto standard solutions *
\r
16 * for microcontrollers - completely free of charge! *
\r
18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
20 * Thank you for using FreeRTOS, and thank you for your support! *
\r
22 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
31 distribute a combined work that includes FreeRTOS without being obliged to
\r
32 provide the source code for proprietary components outside of the FreeRTOS
\r
33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 ***************************************************************************
\r
46 * Having a problem? Start by reading the FAQ "My application does *
\r
47 * not run, what could be wrong? *
\r
49 * http://www.FreeRTOS.org/FAQHelp.html *
\r
51 ***************************************************************************
\r
54 http://www.FreeRTOS.org - Documentation, training, latest information,
\r
55 license and contact details.
\r
57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
58 including FreeRTOS+Trace - an indispensable productivity tool.
\r
60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
61 the code with commercial support, indemnification, and middleware, under
\r
62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
63 provide a safety engineered and independently SIL3 certified version under
\r
64 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
67 /*-----------------------------------------------------------
\r
68 * Implementation of functions defined in portable.h for the Philips ARM7 port.
\r
69 *----------------------------------------------------------*/
\r
74 + Bug fix - The prescale value for the timer setup is now written to T0PR
\r
75 instead of T0PC. This bug would have had no effect unless a prescale
\r
76 value was actually used.
\r
79 /* Standard includes. */
\r
81 #include <intrinsics.h>
\r
83 /* Scheduler includes. */
\r
84 #include "FreeRTOS.h"
\r
87 /* Constants required to setup the tick ISR. */
\r
88 #define portENABLE_TIMER ( ( unsigned char ) 0x01 )
\r
89 #define portPRESCALE_VALUE 0x00
\r
90 #define portINTERRUPT_ON_MATCH ( ( unsigned long ) 0x01 )
\r
91 #define portRESET_COUNT_ON_MATCH ( ( unsigned long ) 0x02 )
\r
93 /* Constants required to setup the initial stack. */
\r
94 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
\r
95 #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
\r
96 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
\r
98 /* Constants required to setup the PIT. */
\r
99 #define portPIT_CLOCK_DIVISOR ( ( unsigned long ) 16 )
\r
100 #define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS )
\r
102 /* Constants required to handle interrupts. */
\r
103 #define portTIMER_MATCH_ISR_BIT ( ( unsigned char ) 0x01 )
\r
104 #define portCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
\r
106 /* Constants required to handle critical sections. */
\r
107 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
\r
110 #define portINT_LEVEL_SENSITIVE 0
\r
111 #define portPIT_ENABLE ( ( unsigned short ) 0x1 << 24 )
\r
112 #define portPIT_INT_ENABLE ( ( unsigned short ) 0x1 << 25 )
\r
114 /* Constants required to setup the VIC for the tick ISR. */
\r
115 #define portTIMER_VIC_CHANNEL ( ( unsigned long ) 0x0004 )
\r
116 #define portTIMER_VIC_CHANNEL_BIT ( ( unsigned long ) 0x0010 )
\r
117 #define portTIMER_VIC_ENABLE ( ( unsigned long ) 0x0020 )
\r
119 /*-----------------------------------------------------------*/
\r
121 /* Setup the PIT to generate the tick interrupts. */
\r
122 static void prvSetupTimerInterrupt( void );
\r
124 /* ulCriticalNesting will get set to zero when the first task starts. It
\r
125 cannot be initialised to 0 as this will cause interrupts to be enabled
\r
126 during the kernel initialisation process. */
\r
127 unsigned long ulCriticalNesting = ( unsigned long ) 9999;
\r
129 /*-----------------------------------------------------------*/
\r
132 * Initialise the stack of a task to look exactly as if a call to
\r
133 * portSAVE_CONTEXT had been called.
\r
135 * See header file for description.
\r
137 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
139 portSTACK_TYPE *pxOriginalTOS;
\r
141 pxOriginalTOS = pxTopOfStack;
\r
143 /* Setup the initial stack of the task. The stack is set exactly as
\r
144 expected by the portRESTORE_CONTEXT() macro. */
\r
146 /* First on the stack is the return address - which in this case is the
\r
147 start of the task. The offset is added to make the return address appear
\r
148 as it would within an IRQ ISR. */
\r
149 *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
\r
152 *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
\r
154 *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
\r
156 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
\r
158 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
\r
160 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
\r
162 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
\r
164 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
\r
166 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
\r
168 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
\r
170 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
\r
172 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
\r
174 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
\r
176 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
\r
178 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
\r
181 /* When the task starts is will expect to find the function parameter in
\r
183 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
\r
186 /* The status register is set for system mode, with interrupts enabled. */
\r
187 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
\r
189 if( ( ( unsigned long ) pxCode & 0x01UL ) != 0x00UL )
\r
191 /* We want the task to start in thumb mode. */
\r
192 *pxTopOfStack |= portTHUMB_MODE_BIT;
\r
197 /* Interrupt flags cannot always be stored on the stack and will
\r
198 instead be stored in a variable, which is then saved as part of the
\r
200 *pxTopOfStack = portNO_CRITICAL_NESTING;
\r
202 return pxTopOfStack;
\r
204 /*-----------------------------------------------------------*/
\r
206 portBASE_TYPE xPortStartScheduler( void )
\r
208 extern void vPortStartFirstTask( void );
\r
210 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
212 prvSetupTimerInterrupt();
\r
214 /* Start the first task. */
\r
215 vPortStartFirstTask();
\r
217 /* Should not get here! */
\r
220 /*-----------------------------------------------------------*/
\r
222 void vPortEndScheduler( void )
\r
224 /* It is unlikely that the ARM port will require this function as there
\r
225 is nothing to return to. */
\r
227 /*-----------------------------------------------------------*/
\r
229 #if configUSE_PREEMPTION == 0
\r
231 /* The cooperative scheduler requires a normal IRQ service routine to
\r
232 simply increment the system tick. */
\r
233 static __arm __irq void vPortNonPreemptiveTick( void );
\r
234 static __arm __irq void vPortNonPreemptiveTick( void )
\r
236 /* Increment the tick count - which may wake some tasks but as the
\r
237 preemptive scheduler is not being used any woken task is not given
\r
238 processor time no matter what its priority. */
\r
239 vTaskIncrementTick();
\r
241 /* Ready for the next interrupt. */
\r
242 T0IR = portTIMER_MATCH_ISR_BIT;
\r
243 VICVectAddr = portCLEAR_VIC_INTERRUPT;
\r
248 /* This function is called from an asm wrapper, so does not require the __irq
\r
250 void vPortPreemptiveTick( void );
\r
251 void vPortPreemptiveTick( void )
\r
253 /* Increment the tick counter. */
\r
254 vTaskIncrementTick();
\r
256 /* The new tick value might unblock a task. Ensure the highest task that
\r
257 is ready to execute is the task that will execute when the tick ISR
\r
259 vTaskSwitchContext();
\r
261 /* Ready for the next interrupt. */
\r
262 T0IR = portTIMER_MATCH_ISR_BIT;
\r
263 VICVectAddr = portCLEAR_VIC_INTERRUPT;
\r
268 /*-----------------------------------------------------------*/
\r
270 static void prvSetupTimerInterrupt( void )
\r
272 unsigned long ulCompareMatch;
\r
274 /* A 1ms tick does not require the use of the timer prescale. This is
\r
275 defaulted to zero but can be used if necessary. */
\r
276 T0PR = portPRESCALE_VALUE;
\r
278 /* Calculate the match value required for our wanted tick rate. */
\r
279 ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
\r
281 /* Protect against divide by zero. Using an if() statement still results
\r
282 in a warning - hence the #if. */
\r
283 #if portPRESCALE_VALUE != 0
\r
285 ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
\r
289 T0MR0 = ulCompareMatch;
\r
291 /* Generate tick with timer 0 compare match. */
\r
292 T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
\r
294 /* Setup the VIC for the timer. */
\r
295 VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
\r
296 VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
\r
298 /* The ISR installed depends on whether the preemptive or cooperative
\r
299 scheduler is being used. */
\r
300 #if configUSE_PREEMPTION == 1
\r
302 extern void ( vPortPreemptiveTickEntry )( void );
\r
304 VICVectAddr0 = ( unsigned long ) vPortPreemptiveTickEntry;
\r
308 extern void ( vNonPreemptiveTick )( void );
\r
310 VICVectAddr0 = ( long ) vPortNonPreemptiveTick;
\r
314 VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
\r
316 /* Start the timer - interrupts are disabled when this function is called
\r
317 so it is okay to do this here. */
\r
318 T0TCR = portENABLE_TIMER;
\r
320 /*-----------------------------------------------------------*/
\r
322 void vPortEnterCritical( void )
\r
324 /* Disable interrupts first! */
\r
325 __disable_interrupt();
\r
327 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
328 directly. Increment ulCriticalNesting to keep a count of how many times
\r
329 portENTER_CRITICAL() has been called. */
\r
330 ulCriticalNesting++;
\r
332 /*-----------------------------------------------------------*/
\r
334 void vPortExitCritical( void )
\r
336 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
338 /* Decrement the nesting count as we are leaving a critical section. */
\r
339 ulCriticalNesting--;
\r
341 /* If the nesting level has reached zero then interrupts should be
\r
343 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
345 __enable_interrupt();
\r
349 /*-----------------------------------------------------------*/
\r