2 * FreeRTOS Kernel V10.1.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the SH2A port.
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30 *----------------------------------------------------------*/
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32 /* Standard C includes. */
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35 /* Scheduler includes. */
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36 #include "FreeRTOS.h"
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39 /* Library includes. */
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42 /* Hardware specifics. */
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43 #include "machine.h"
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45 /*-----------------------------------------------------------*/
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47 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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48 PSW is set with U and I set, and PM and IPL clear. */
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49 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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51 /* The peripheral clock is divided by this value before being supplying the
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53 #if ( configUSE_TICKLESS_IDLE == 0 )
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54 /* If tickless idle is not used then the divisor can be fixed. */
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55 #define portCLOCK_DIVISOR 8UL
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56 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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57 #define portCLOCK_DIVISOR 512UL
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58 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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59 #define portCLOCK_DIVISOR 128UL
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60 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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61 #define portCLOCK_DIVISOR 32UL
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63 #define portCLOCK_DIVISOR 8UL
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67 /* Keys required to lock and unlock access to certain system registers
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69 #define portUNLOCK_KEY 0xA50B
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70 #define portLOCK_KEY 0xA500
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72 /*-----------------------------------------------------------*/
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75 * Function to start the first task executing - written in asm code as direct
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76 * access to registers is required.
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78 extern void prvStartFirstTask( void );
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81 * The tick ISR handler. The peripheral used is configured by the application
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82 * via a hook/callback function.
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84 __interrupt static void prvTickISR( void );
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87 * Sets up the periodic ISR used for the RTOS tick using the CMT.
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88 * The application writer can define configSETUP_TICK_INTERRUPT() (in
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89 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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90 * in place of prvSetupTimerInterrupt().
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92 static void prvSetupTimerInterrupt( void );
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93 #ifndef configSETUP_TICK_INTERRUPT
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94 /* The user has not provided their own tick interrupt configuration so use
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95 the definition in this file (which uses the interval timer). */
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96 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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97 #endif /* configSETUP_TICK_INTERRUPT */
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100 * Called after the sleep mode registers have been configured, prvSleep()
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101 * executes the pre and post sleep macros, and actually calls the wait
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104 #if configUSE_TICKLESS_IDLE == 1
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105 static void prvSleep( TickType_t xExpectedIdleTime );
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106 #endif /* configUSE_TICKLESS_IDLE */
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108 /*-----------------------------------------------------------*/
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110 extern void *pxCurrentTCB;
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112 /*-----------------------------------------------------------*/
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114 /* Calculate how many clock increments make up a single tick period. */
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115 static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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117 #if configUSE_TICKLESS_IDLE == 1
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119 /* Holds the maximum number of ticks that can be suppressed - which is
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120 basically how far into the future an interrupt can be generated. Set
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121 during initialisation. This is the maximum possible value that the
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122 compare match register can hold divided by ulMatchValueForOneTick. */
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123 static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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125 /* Flag set from the tick interrupt to allow the sleep processing to know if
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126 sleep mode was exited because of a tick interrupt, or an interrupt
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127 generated by something else. */
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128 static volatile uint32_t ulTickFlag = pdFALSE;
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130 /* The CMT counter is stopped temporarily each time it is re-programmed.
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131 The following constant offsets the CMT counter match value by the number of
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132 CMT counts that would typically be missed while the counter was stopped to
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133 compensate for the lost time. The large difference between the divided CMT
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134 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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135 equal zero - and be optimised away. */
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136 static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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140 /*-----------------------------------------------------------*/
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143 * See header file for description.
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145 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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147 /* Offset to end up on 8 byte boundary. */
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150 /* R0 is not included as it is the stack pointer. */
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151 *pxTopOfStack = 0x00;
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153 *pxTopOfStack = 0x00;
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155 *pxTopOfStack = portINITIAL_PSW;
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157 *pxTopOfStack = ( StackType_t ) pxCode;
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159 /* When debugging it can be useful if every register is set to a known
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160 value. Otherwise code space can be saved by just setting the registers
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161 that need to be set. */
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162 #ifdef USE_FULL_REGISTER_INITIALISATION
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165 *pxTopOfStack = 0x12345678; /* r15. */
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167 *pxTopOfStack = 0xaaaabbbb;
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169 *pxTopOfStack = 0xdddddddd;
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171 *pxTopOfStack = 0xcccccccc;
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173 *pxTopOfStack = 0xbbbbbbbb;
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175 *pxTopOfStack = 0xaaaaaaaa;
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177 *pxTopOfStack = 0x99999999;
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179 *pxTopOfStack = 0x88888888;
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181 *pxTopOfStack = 0x77777777;
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183 *pxTopOfStack = 0x66666666;
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185 *pxTopOfStack = 0x55555555;
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187 *pxTopOfStack = 0x44444444;
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189 *pxTopOfStack = 0x33333333;
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191 *pxTopOfStack = 0x22222222;
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196 /* Leave space for the registers that will get popped from the stack
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197 when the task first starts executing. */
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198 pxTopOfStack -= 15;
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202 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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204 *pxTopOfStack = 0x12345678; /* Accumulator. */
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206 *pxTopOfStack = 0x87654321; /* Accumulator. */
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208 return pxTopOfStack;
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210 /*-----------------------------------------------------------*/
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212 BaseType_t xPortStartScheduler( void )
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214 /* Use pxCurrentTCB just so it does not get optimised away. */
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215 if( pxCurrentTCB != NULL )
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217 /* Call an application function to set up the timer that will generate
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218 the tick interrupt. This way the application can decide which
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219 peripheral to use. If tickless mode is used then the default
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220 implementation defined in this file (which uses CMT0) should not be
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222 configSETUP_TICK_INTERRUPT();
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224 /* Enable the software interrupt. */
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225 _IEN( _ICU_SWINT ) = 1;
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227 /* Ensure the software interrupt is clear. */
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228 _IR( _ICU_SWINT ) = 0;
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230 /* Ensure the software interrupt is set to the kernel priority. */
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231 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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233 /* Start the first task. */
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234 prvStartFirstTask();
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237 /* Execution should not reach here as the tasks are now running!
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238 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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239 a warning about a statically declared function not being referenced in the
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240 case that the application writer has provided their own tick interrupt
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241 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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242 their own routine will be called in place of prvSetupTimerInterrupt()). */
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243 prvSetupTimerInterrupt();
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245 /* Should not get here. */
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248 /*-----------------------------------------------------------*/
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250 #pragma vector = configTICK_VECTOR
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251 __interrupt static void prvTickISR( void )
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253 /* Re-enable interrupts. */
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254 __enable_interrupt();
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256 /* Increment the tick, and perform any processing the new tick value
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258 __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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260 if( xTaskIncrementTick() != pdFALSE )
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265 __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
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267 #if configUSE_TICKLESS_IDLE == 1
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269 /* The CPU woke because of a tick. */
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270 ulTickFlag = pdTRUE;
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272 /* If this is the first tick since exiting tickless mode then the CMT
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273 compare match value needs resetting. */
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274 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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278 /*-----------------------------------------------------------*/
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280 void vPortEndScheduler( void )
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282 /* Not implemented in ports where there is nothing to return to.
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283 Artificially force an assert. */
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284 configASSERT( pxCurrentTCB == NULL );
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286 /*-----------------------------------------------------------*/
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288 static void prvSetupTimerInterrupt( void )
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291 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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297 SYSTEM.PRCR.WORD = portLOCK_KEY;
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299 /* Interrupt on compare match. */
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300 CMT0.CMCR.BIT.CMIE = 1;
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302 /* Set the compare match value. */
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303 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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305 /* Divide the PCLK. */
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306 #if portCLOCK_DIVISOR == 512
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308 CMT0.CMCR.BIT.CKS = 3;
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310 #elif portCLOCK_DIVISOR == 128
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312 CMT0.CMCR.BIT.CKS = 2;
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314 #elif portCLOCK_DIVISOR == 32
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316 CMT0.CMCR.BIT.CKS = 1;
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318 #elif portCLOCK_DIVISOR == 8
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320 CMT0.CMCR.BIT.CKS = 0;
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324 #error Invalid portCLOCK_DIVISOR setting
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329 /* Enable the interrupt... */
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330 _IEN( _CMT0_CMI0 ) = 1;
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332 /* ...and set its priority to the application defined kernel priority. */
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333 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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335 /* Start the timer. */
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336 CMT.CMSTR0.BIT.STR0 = 1;
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338 /*-----------------------------------------------------------*/
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340 #if configUSE_TICKLESS_IDLE == 1
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342 static void prvSleep( TickType_t xExpectedIdleTime )
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344 /* Allow the application to define some pre-sleep processing. */
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345 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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347 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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348 means the application defined code has already executed the WAIT
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350 if( xExpectedIdleTime > 0 )
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352 __wait_for_interrupt();
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355 /* Allow the application to define some post sleep processing. */
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356 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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359 #endif /* configUSE_TICKLESS_IDLE */
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360 /*-----------------------------------------------------------*/
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362 #if configUSE_TICKLESS_IDLE == 1
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364 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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366 uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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367 eSleepModeStatus eSleepAction;
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369 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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371 /* Make sure the CMT reload value does not overflow the counter. */
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372 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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374 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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377 /* Calculate the reload value required to wait xExpectedIdleTime tick
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379 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
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380 if( ulMatchValue > ulStoppedTimerCompensation )
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382 /* Compensate for the fact that the CMT is going to be stopped
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384 ulMatchValue -= ulStoppedTimerCompensation;
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387 /* Stop the CMT momentarily. The time the CMT is stopped for is
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388 accounted for as best it can be, but using the tickless mode will
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389 inevitably result in some tiny drift of the time maintained by the
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390 kernel with respect to calendar time. */
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391 CMT.CMSTR0.BIT.STR0 = 0;
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392 while( CMT.CMSTR0.BIT.STR0 == 1 )
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394 /* Nothing to do here. */
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397 /* Critical section using the global interrupt bit as the i bit is
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398 automatically reset by the WAIT instruction. */
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399 __disable_interrupt();
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401 /* The tick flag is set to false before sleeping. If it is true when
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402 sleep mode is exited then sleep mode was probably exited because the
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403 tick was suppressed for the entire xExpectedIdleTime period. */
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404 ulTickFlag = pdFALSE;
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406 /* If a context switch is pending then abandon the low power entry as
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407 the context switch might have been pended by an external interrupt that
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408 requires processing. */
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409 eSleepAction = eTaskConfirmSleepModeStatus();
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410 if( eSleepAction == eAbortSleep )
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412 /* Restart tick. */
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413 CMT.CMSTR0.BIT.STR0 = 1;
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414 __enable_interrupt();
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416 else if( eSleepAction == eNoTasksWaitingTimeout )
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418 /* Protection off. */
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419 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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421 /* Ready for software standby with all clocks stopped. */
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422 SYSTEM.SBYCR.BIT.SSBY = 1;
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424 /* Protection on. */
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425 SYSTEM.PRCR.WORD = portLOCK_KEY;
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427 /* Sleep until something happens. Calling prvSleep() will
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428 automatically reset the i bit in the PSW. */
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429 prvSleep( xExpectedIdleTime );
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431 /* Restart the CMT. */
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432 CMT.CMSTR0.BIT.STR0 = 1;
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436 /* Protection off. */
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437 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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439 /* Ready for deep sleep mode. */
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440 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
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441 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
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442 SYSTEM.SBYCR.BIT.SSBY = 0;
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444 /* Protection on. */
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445 SYSTEM.PRCR.WORD = portLOCK_KEY;
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447 /* Adjust the match value to take into account that the current
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448 time slice is already partially complete. */
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449 ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
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450 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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452 /* Restart the CMT to count up to the new match value. */
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454 CMT.CMSTR0.BIT.STR0 = 1;
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456 /* Sleep until something happens. Calling prvSleep() will
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457 automatically reset the i bit in the PSW. */
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458 prvSleep( xExpectedIdleTime );
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460 /* Stop CMT. Again, the time the SysTick is stopped for is
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461 accounted for as best it can be, but using the tickless mode will
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462 inevitably result in some tiny drift of the time maintained by the
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463 kernel with respect to calendar time. */
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464 CMT.CMSTR0.BIT.STR0 = 0;
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465 while( CMT.CMSTR0.BIT.STR0 == 1 )
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467 /* Nothing to do here. */
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470 ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
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472 if( ulTickFlag != pdFALSE )
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474 /* The tick interrupt has already executed, although because
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475 this function is called with the scheduler suspended the actual
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476 tick processing will not occur until after this function has
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477 exited. Reset the match value with whatever remains of this
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479 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
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480 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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482 /* The tick interrupt handler will already have pended the tick
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483 processing in the kernel. As the pending tick will be
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484 processed as soon as this function exits, the tick value
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485 maintained by the tick is stepped forward by one less than the
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486 time spent sleeping. The actual stepping of the tick appears
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487 later in this function. */
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488 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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492 /* Something other than the tick interrupt ended the sleep.
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493 How many complete tick periods passed while the processor was
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495 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
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497 /* The match value is set to whatever fraction of a single tick
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499 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
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500 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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503 /* Restart the CMT so it runs up to the match value. The match value
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504 will get set to the value required to generate exactly one tick period
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505 the next time the CMT interrupt executes. */
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507 CMT.CMSTR0.BIT.STR0 = 1;
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509 /* Wind the tick forward by the number of tick periods that the CPU
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510 remained in a low power state. */
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511 vTaskStepTick( ulCompleteTickPeriods );
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515 #endif /* configUSE_TICKLESS_IDLE */
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