2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Implementation of functions defined in portable.h for the SH2A port.
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31 *----------------------------------------------------------*/
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33 /* Standard C includes. */
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36 /* Scheduler includes. */
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37 #include "FreeRTOS.h"
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40 /* Library includes. */
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43 /* Hardware specifics. */
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44 #include "machine.h"
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46 /*-----------------------------------------------------------*/
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48 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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49 PSW is set with U and I set, and PM and IPL clear. */
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50 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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52 /* The peripheral clock is divided by this value before being supplying the
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54 #if ( configUSE_TICKLESS_IDLE == 0 )
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55 /* If tickless idle is not used then the divisor can be fixed. */
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56 #define portCLOCK_DIVISOR 8UL
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57 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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58 #define portCLOCK_DIVISOR 512UL
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59 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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60 #define portCLOCK_DIVISOR 128UL
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61 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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62 #define portCLOCK_DIVISOR 32UL
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64 #define portCLOCK_DIVISOR 8UL
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68 /* Keys required to lock and unlock access to certain system registers
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70 #define portUNLOCK_KEY 0xA50B
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71 #define portLOCK_KEY 0xA500
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73 /*-----------------------------------------------------------*/
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76 * Function to start the first task executing - written in asm code as direct
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77 * access to registers is required.
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79 extern void prvStartFirstTask( void );
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82 * The tick ISR handler. The peripheral used is configured by the application
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83 * via a hook/callback function.
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85 __interrupt static void prvTickISR( void );
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88 * Sets up the periodic ISR used for the RTOS tick using the CMT.
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89 * The application writer can define configSETUP_TICK_INTERRUPT() (in
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90 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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91 * in place of prvSetupTimerInterrupt().
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93 static void prvSetupTimerInterrupt( void );
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94 #ifndef configSETUP_TICK_INTERRUPT
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95 /* The user has not provided their own tick interrupt configuration so use
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96 the definition in this file (which uses the interval timer). */
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97 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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98 #endif /* configSETUP_TICK_INTERRUPT */
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101 * Called after the sleep mode registers have been configured, prvSleep()
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102 * executes the pre and post sleep macros, and actually calls the wait
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105 #if configUSE_TICKLESS_IDLE == 1
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106 static void prvSleep( TickType_t xExpectedIdleTime );
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107 #endif /* configUSE_TICKLESS_IDLE */
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109 /*-----------------------------------------------------------*/
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111 extern void *pxCurrentTCB;
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113 /*-----------------------------------------------------------*/
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115 /* Calculate how many clock increments make up a single tick period. */
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116 static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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118 #if configUSE_TICKLESS_IDLE == 1
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120 /* Holds the maximum number of ticks that can be suppressed - which is
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121 basically how far into the future an interrupt can be generated. Set
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122 during initialisation. This is the maximum possible value that the
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123 compare match register can hold divided by ulMatchValueForOneTick. */
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124 static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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126 /* Flag set from the tick interrupt to allow the sleep processing to know if
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127 sleep mode was exited because of a tick interrupt, or an interrupt
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128 generated by something else. */
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129 static volatile uint32_t ulTickFlag = pdFALSE;
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131 /* The CMT counter is stopped temporarily each time it is re-programmed.
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132 The following constant offsets the CMT counter match value by the number of
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133 CMT counts that would typically be missed while the counter was stopped to
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134 compensate for the lost time. The large difference between the divided CMT
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135 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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136 equal zero - and be optimised away. */
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137 static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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141 /*-----------------------------------------------------------*/
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144 * See header file for description.
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146 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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148 /* Offset to end up on 8 byte boundary. */
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151 /* R0 is not included as it is the stack pointer. */
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152 *pxTopOfStack = 0x00;
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154 *pxTopOfStack = 0x00;
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156 *pxTopOfStack = portINITIAL_PSW;
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158 *pxTopOfStack = ( StackType_t ) pxCode;
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160 /* When debugging it can be useful if every register is set to a known
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161 value. Otherwise code space can be saved by just setting the registers
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162 that need to be set. */
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163 #ifdef USE_FULL_REGISTER_INITIALISATION
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166 *pxTopOfStack = 0x12345678; /* r15. */
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168 *pxTopOfStack = 0xaaaabbbb;
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170 *pxTopOfStack = 0xdddddddd;
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172 *pxTopOfStack = 0xcccccccc;
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174 *pxTopOfStack = 0xbbbbbbbb;
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176 *pxTopOfStack = 0xaaaaaaaa;
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178 *pxTopOfStack = 0x99999999;
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180 *pxTopOfStack = 0x88888888;
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182 *pxTopOfStack = 0x77777777;
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184 *pxTopOfStack = 0x66666666;
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186 *pxTopOfStack = 0x55555555;
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188 *pxTopOfStack = 0x44444444;
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190 *pxTopOfStack = 0x33333333;
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192 *pxTopOfStack = 0x22222222;
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197 /* Leave space for the registers that will get popped from the stack
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198 when the task first starts executing. */
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199 pxTopOfStack -= 15;
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203 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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205 *pxTopOfStack = 0x12345678; /* Accumulator. */
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207 *pxTopOfStack = 0x87654321; /* Accumulator. */
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209 return pxTopOfStack;
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211 /*-----------------------------------------------------------*/
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213 BaseType_t xPortStartScheduler( void )
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215 /* Use pxCurrentTCB just so it does not get optimised away. */
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216 if( pxCurrentTCB != NULL )
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218 /* Call an application function to set up the timer that will generate
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219 the tick interrupt. This way the application can decide which
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220 peripheral to use. If tickless mode is used then the default
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221 implementation defined in this file (which uses CMT0) should not be
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223 configSETUP_TICK_INTERRUPT();
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225 /* Enable the software interrupt. */
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226 _IEN( _ICU_SWINT ) = 1;
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228 /* Ensure the software interrupt is clear. */
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229 _IR( _ICU_SWINT ) = 0;
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231 /* Ensure the software interrupt is set to the kernel priority. */
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232 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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234 /* Start the first task. */
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235 prvStartFirstTask();
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238 /* Execution should not reach here as the tasks are now running!
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239 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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240 a warning about a statically declared function not being referenced in the
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241 case that the application writer has provided their own tick interrupt
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242 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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243 their own routine will be called in place of prvSetupTimerInterrupt()). */
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244 prvSetupTimerInterrupt();
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246 /* Should not get here. */
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249 /*-----------------------------------------------------------*/
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251 #pragma vector = configTICK_VECTOR
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252 __interrupt static void prvTickISR( void )
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254 /* Re-enable interrupts. */
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255 __enable_interrupt();
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257 /* Increment the tick, and perform any processing the new tick value
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259 __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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261 if( xTaskIncrementTick() != pdFALSE )
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266 __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
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268 #if configUSE_TICKLESS_IDLE == 1
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270 /* The CPU woke because of a tick. */
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271 ulTickFlag = pdTRUE;
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273 /* If this is the first tick since exiting tickless mode then the CMT
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274 compare match value needs resetting. */
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275 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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279 /*-----------------------------------------------------------*/
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281 void vPortEndScheduler( void )
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283 /* Not implemented in ports where there is nothing to return to.
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284 Artificially force an assert. */
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285 configASSERT( pxCurrentTCB == NULL );
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287 /*-----------------------------------------------------------*/
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289 static void prvSetupTimerInterrupt( void )
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292 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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298 SYSTEM.PRCR.WORD = portLOCK_KEY;
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300 /* Interrupt on compare match. */
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301 CMT0.CMCR.BIT.CMIE = 1;
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303 /* Set the compare match value. */
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304 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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306 /* Divide the PCLK. */
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307 #if portCLOCK_DIVISOR == 512
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309 CMT0.CMCR.BIT.CKS = 3;
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311 #elif portCLOCK_DIVISOR == 128
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313 CMT0.CMCR.BIT.CKS = 2;
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315 #elif portCLOCK_DIVISOR == 32
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317 CMT0.CMCR.BIT.CKS = 1;
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319 #elif portCLOCK_DIVISOR == 8
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321 CMT0.CMCR.BIT.CKS = 0;
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325 #error Invalid portCLOCK_DIVISOR setting
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330 /* Enable the interrupt... */
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331 _IEN( _CMT0_CMI0 ) = 1;
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333 /* ...and set its priority to the application defined kernel priority. */
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334 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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336 /* Start the timer. */
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337 CMT.CMSTR0.BIT.STR0 = 1;
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339 /*-----------------------------------------------------------*/
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341 #if configUSE_TICKLESS_IDLE == 1
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343 static void prvSleep( TickType_t xExpectedIdleTime )
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345 /* Allow the application to define some pre-sleep processing. */
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346 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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348 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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349 means the application defined code has already executed the WAIT
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351 if( xExpectedIdleTime > 0 )
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353 __wait_for_interrupt();
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356 /* Allow the application to define some post sleep processing. */
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357 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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360 #endif /* configUSE_TICKLESS_IDLE */
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361 /*-----------------------------------------------------------*/
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363 #if configUSE_TICKLESS_IDLE == 1
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365 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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367 uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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368 eSleepModeStatus eSleepAction;
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370 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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372 /* Make sure the CMT reload value does not overflow the counter. */
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373 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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375 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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378 /* Calculate the reload value required to wait xExpectedIdleTime tick
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380 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
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381 if( ulMatchValue > ulStoppedTimerCompensation )
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383 /* Compensate for the fact that the CMT is going to be stopped
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385 ulMatchValue -= ulStoppedTimerCompensation;
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388 /* Stop the CMT momentarily. The time the CMT is stopped for is
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389 accounted for as best it can be, but using the tickless mode will
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390 inevitably result in some tiny drift of the time maintained by the
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391 kernel with respect to calendar time. */
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392 CMT.CMSTR0.BIT.STR0 = 0;
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393 while( CMT.CMSTR0.BIT.STR0 == 1 )
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395 /* Nothing to do here. */
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398 /* Critical section using the global interrupt bit as the i bit is
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399 automatically reset by the WAIT instruction. */
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400 __disable_interrupt();
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402 /* The tick flag is set to false before sleeping. If it is true when
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403 sleep mode is exited then sleep mode was probably exited because the
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404 tick was suppressed for the entire xExpectedIdleTime period. */
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405 ulTickFlag = pdFALSE;
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407 /* If a context switch is pending then abandon the low power entry as
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408 the context switch might have been pended by an external interrupt that
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409 requires processing. */
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410 eSleepAction = eTaskConfirmSleepModeStatus();
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411 if( eSleepAction == eAbortSleep )
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413 /* Restart tick. */
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414 CMT.CMSTR0.BIT.STR0 = 1;
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415 __enable_interrupt();
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417 else if( eSleepAction == eNoTasksWaitingTimeout )
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419 /* Protection off. */
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420 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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422 /* Ready for software standby with all clocks stopped. */
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423 SYSTEM.SBYCR.BIT.SSBY = 1;
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425 /* Protection on. */
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426 SYSTEM.PRCR.WORD = portLOCK_KEY;
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428 /* Sleep until something happens. Calling prvSleep() will
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429 automatically reset the i bit in the PSW. */
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430 prvSleep( xExpectedIdleTime );
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432 /* Restart the CMT. */
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433 CMT.CMSTR0.BIT.STR0 = 1;
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437 /* Protection off. */
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438 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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440 /* Ready for deep sleep mode. */
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441 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
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442 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
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443 SYSTEM.SBYCR.BIT.SSBY = 0;
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445 /* Protection on. */
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446 SYSTEM.PRCR.WORD = portLOCK_KEY;
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448 /* Adjust the match value to take into account that the current
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449 time slice is already partially complete. */
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450 ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
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451 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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453 /* Restart the CMT to count up to the new match value. */
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455 CMT.CMSTR0.BIT.STR0 = 1;
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457 /* Sleep until something happens. Calling prvSleep() will
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458 automatically reset the i bit in the PSW. */
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459 prvSleep( xExpectedIdleTime );
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461 /* Stop CMT. Again, the time the SysTick is stopped for is
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462 accounted for as best it can be, but using the tickless mode will
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463 inevitably result in some tiny drift of the time maintained by the
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464 kernel with respect to calendar time. */
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465 CMT.CMSTR0.BIT.STR0 = 0;
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466 while( CMT.CMSTR0.BIT.STR0 == 1 )
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468 /* Nothing to do here. */
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471 ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
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473 if( ulTickFlag != pdFALSE )
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475 /* The tick interrupt has already executed, although because
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476 this function is called with the scheduler suspended the actual
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477 tick processing will not occur until after this function has
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478 exited. Reset the match value with whatever remains of this
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480 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
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481 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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483 /* The tick interrupt handler will already have pended the tick
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484 processing in the kernel. As the pending tick will be
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485 processed as soon as this function exits, the tick value
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486 maintained by the tick is stepped forward by one less than the
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487 time spent sleeping. The actual stepping of the tick appears
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488 later in this function. */
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489 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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493 /* Something other than the tick interrupt ended the sleep.
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494 How many complete tick periods passed while the processor was
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496 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
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498 /* The match value is set to whatever fraction of a single tick
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500 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
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501 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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504 /* Restart the CMT so it runs up to the match value. The match value
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505 will get set to the value required to generate exactly one tick period
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506 the next time the CMT interrupt executes. */
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508 CMT.CMSTR0.BIT.STR0 = 1;
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510 /* Wind the tick forward by the number of tick periods that the CPU
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511 remained in a low power state. */
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512 vTaskStepTick( ulCompleteTickPeriods );
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516 #endif /* configUSE_TICKLESS_IDLE */
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