2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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30 Changes between V1.2.4 and V1.2.5
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32 + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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33 interrupt flag setting. Using the two bits defined within
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34 portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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35 before the test was performed.
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39 + Set the interrupt vector address to 0x08. Previously it was at the
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40 incorrect address for compatibility mode of 0x18.
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44 + PCLATU and PCLATH are now saved as part of the context. This allows
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45 function pointers to be used within tasks. Thanks to Javier Espeche
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46 for the enhancement.
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50 + TABLAT is now saved as part of the task context.
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54 + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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55 value and does not write to the register.
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58 /* Scheduler include files. */
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59 #include "FreeRTOS.h"
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62 /* MPLAB library include file. */
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65 /*-----------------------------------------------------------
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66 * Implementation of functions defined in portable.h for the PIC port.
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67 *----------------------------------------------------------*/
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69 /* Hardware setup for tick. */
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70 #define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
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72 /* Initial interrupt enable state for newly created tasks. This value is
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73 copied into INTCON when a task switches in for the first time. */
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74 #define portINITAL_INTERRUPT_STATE 0xc0
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76 /* Just the bit within INTCON for the global interrupt flag. */
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77 #define portGLOBAL_INTERRUPT_FLAG 0x80
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79 /* Constant used for context switch macro when we require the interrupt
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80 enable state to be unchanged when the interrupted task is switched back in. */
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81 #define portINTERRUPTS_UNCHANGED 0x00
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83 /* Some memory areas get saved as part of the task context. These memory
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84 area's get used by the compiler for temporary storage, especially when
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85 performing mathematical operations, or when using 32bit data types. This
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86 constant defines the size of memory area which must be saved. */
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87 #define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
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89 /* We require the address of the pxCurrentTCB variable, but don't want to know
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90 any details of its type. */
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92 extern volatile TCB_t * volatile pxCurrentTCB;
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94 /* IO port constants. */
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95 #define portBIT_SET ( ( uint8_t ) 1 )
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96 #define portBIT_CLEAR ( ( uint8_t ) 0 )
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99 * The serial port ISR's are defined in serial.c, but are called from portable
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100 * as they use the same vector as the tick ISR.
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102 void vSerialTxISR( void );
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103 void vSerialRxISR( void );
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106 * Perform hardware setup to enable ticks.
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108 static void prvSetupTimerInterrupt( void );
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111 * ISR to maintain the tick, and perform tick context switches if the
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112 * preemptive scheduler is being used.
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114 static void prvTickISR( void );
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117 * ISR placed on the low priority vector. This calls the appropriate ISR for
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118 * the actual interrupt.
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120 static void prvLowInterrupt( void );
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123 * Macro that pushes all the registers that make up the context of a task onto
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124 * the stack, then saves the new top of stack into the TCB.
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126 * If this is called from an ISR then the interrupt enable bits must have been
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127 * set for the ISR to ever get called. Therefore we want to save the INTCON
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128 * register with the enable bits forced to be set - and ucForcedInterruptFlags
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129 * must contain these bit settings. This means the interrupts will again be
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130 * enabled when the interrupted task is switched back in.
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132 * If this is called from a manual context switch (i.e. from a call to yield),
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133 * then we want to save the INTCON so it is restored with its current state,
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134 * and ucForcedInterruptFlags must be 0. This allows a yield from within
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135 * a critical section.
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137 * The compiler uses some locations at the bottom of the memory for temporary
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138 * storage during math and other computations. This is especially true if
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139 * 32bit data types are utilised (as they are by the scheduler). The .tmpdata
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140 * and MATH_DATA sections have to be stored in there entirety as part of a task
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141 * context. This macro stores from data address 0x00 to
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142 * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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143 * applications but you should check the map file for your project to ensure
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144 * this is sufficient for your needs. It is not clear whether this size is
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145 * fixed for all compilations or has the potential to be program specific.
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147 #define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
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150 /* Save the status and WREG registers first, as these will get modified \
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151 by the operations below. */ \
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152 MOVFF WREG, PREINC1 \
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153 MOVFF STATUS, PREINC1 \
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154 /* Save the INTCON register with the appropriate bits forced if \
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155 necessary - as described above. */ \
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156 MOVFF INTCON, WREG \
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157 IORLW ucForcedInterruptFlags \
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158 MOVFF WREG, PREINC1 \
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161 portDISABLE_INTERRUPTS(); \
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164 /* Store the necessary registers to the stack. */ \
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165 MOVFF BSR, PREINC1 \
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166 MOVFF FSR2L, PREINC1 \
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167 MOVFF FSR2H, PREINC1 \
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168 MOVFF FSR0L, PREINC1 \
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169 MOVFF FSR0H, PREINC1 \
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170 MOVFF TABLAT, PREINC1 \
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171 MOVFF TBLPTRU, PREINC1 \
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172 MOVFF TBLPTRH, PREINC1 \
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173 MOVFF TBLPTRL, PREINC1 \
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174 MOVFF PRODH, PREINC1 \
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175 MOVFF PRODL, PREINC1 \
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176 MOVFF PCLATU, PREINC1 \
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177 MOVFF PCLATH, PREINC1 \
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178 /* Store the .tempdata and MATH_DATA areas as described above. */ \
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181 MOVFF POSTINC0, PREINC1 \
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182 MOVFF POSTINC0, PREINC1 \
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183 MOVFF POSTINC0, PREINC1 \
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184 MOVFF POSTINC0, PREINC1 \
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185 MOVFF POSTINC0, PREINC1 \
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186 MOVFF POSTINC0, PREINC1 \
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187 MOVFF POSTINC0, PREINC1 \
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188 MOVFF POSTINC0, PREINC1 \
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189 MOVFF POSTINC0, PREINC1 \
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190 MOVFF POSTINC0, PREINC1 \
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191 MOVFF POSTINC0, PREINC1 \
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192 MOVFF POSTINC0, PREINC1 \
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193 MOVFF POSTINC0, PREINC1 \
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194 MOVFF POSTINC0, PREINC1 \
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195 MOVFF POSTINC0, PREINC1 \
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196 MOVFF POSTINC0, PREINC1 \
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197 MOVFF POSTINC0, PREINC1 \
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198 MOVFF POSTINC0, PREINC1 \
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199 MOVFF POSTINC0, PREINC1 \
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200 MOVFF INDF0, PREINC1 \
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201 MOVFF FSR0L, PREINC1 \
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202 MOVFF FSR0H, PREINC1 \
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203 /* Store the hardware stack pointer in a temp register before we \
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205 MOVFF STKPTR, FSR0L \
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208 /* Store each address from the hardware stack. */ \
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209 while( STKPTR > ( uint8_t ) 0 ) \
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212 MOVFF TOSL, PREINC1 \
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213 MOVFF TOSH, PREINC1 \
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214 MOVFF TOSU, PREINC1 \
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220 /* Store the number of addresses on the hardware stack (from the \
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221 temporary register). */ \
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222 MOVFF FSR0L, PREINC1 \
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223 MOVF PREINC1, 1, 0 \
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226 /* Save the new top of the software stack in the TCB. */ \
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228 MOVFF pxCurrentTCB, FSR0L \
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229 MOVFF pxCurrentTCB + 1, FSR0H \
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230 MOVFF FSR1L, POSTINC0 \
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231 MOVFF FSR1H, POSTINC0 \
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234 /*-----------------------------------------------------------*/
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237 * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
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240 #define portRESTORE_CONTEXT() \
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243 /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
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244 MOVFF pxCurrentTCB, FSR0L \
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245 MOVFF pxCurrentTCB + 1, FSR0H \
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247 /* De-reference FSR0 to set the address it holds into FSR1. \
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248 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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249 MOVFF POSTINC0, FSR1L \
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250 MOVFF POSTINC0, FSR1H \
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252 /* How many return addresses are there on the hardware stack? Discard \
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253 the first byte as we are pointing to the next free space. */ \
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254 MOVFF POSTDEC1, FSR0L \
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255 MOVFF POSTDEC1, FSR0L \
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258 /* Fill the hardware stack from our software stack. */ \
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261 while( STKPTR < FSR0L ) \
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265 MOVF POSTDEC1, 0, 0 \
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267 MOVF POSTDEC1, 0, 0 \
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269 MOVF POSTDEC1, 0, 0 \
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275 /* Restore the .tmpdata and MATH_DATA memory. */ \
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276 MOVFF POSTDEC1, FSR0H \
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277 MOVFF POSTDEC1, FSR0L \
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278 MOVFF POSTDEC1, POSTDEC0 \
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279 MOVFF POSTDEC1, POSTDEC0 \
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280 MOVFF POSTDEC1, POSTDEC0 \
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281 MOVFF POSTDEC1, POSTDEC0 \
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282 MOVFF POSTDEC1, POSTDEC0 \
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283 MOVFF POSTDEC1, POSTDEC0 \
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284 MOVFF POSTDEC1, POSTDEC0 \
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285 MOVFF POSTDEC1, POSTDEC0 \
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286 MOVFF POSTDEC1, POSTDEC0 \
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287 MOVFF POSTDEC1, POSTDEC0 \
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288 MOVFF POSTDEC1, POSTDEC0 \
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289 MOVFF POSTDEC1, POSTDEC0 \
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290 MOVFF POSTDEC1, POSTDEC0 \
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291 MOVFF POSTDEC1, POSTDEC0 \
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292 MOVFF POSTDEC1, POSTDEC0 \
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293 MOVFF POSTDEC1, POSTDEC0 \
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294 MOVFF POSTDEC1, POSTDEC0 \
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295 MOVFF POSTDEC1, POSTDEC0 \
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296 MOVFF POSTDEC1, POSTDEC0 \
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297 MOVFF POSTDEC1, INDF0 \
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298 /* Restore the other registers forming the tasks context. */ \
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299 MOVFF POSTDEC1, PCLATH \
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300 MOVFF POSTDEC1, PCLATU \
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301 MOVFF POSTDEC1, PRODL \
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302 MOVFF POSTDEC1, PRODH \
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303 MOVFF POSTDEC1, TBLPTRL \
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304 MOVFF POSTDEC1, TBLPTRH \
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305 MOVFF POSTDEC1, TBLPTRU \
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306 MOVFF POSTDEC1, TABLAT \
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307 MOVFF POSTDEC1, FSR0H \
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308 MOVFF POSTDEC1, FSR0L \
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309 MOVFF POSTDEC1, FSR2H \
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310 MOVFF POSTDEC1, FSR2L \
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311 MOVFF POSTDEC1, BSR \
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312 /* The next byte is the INTCON register. Read this into WREG as some \
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313 manipulation is required. */ \
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314 MOVFF POSTDEC1, WREG \
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317 /* From the INTCON register, only the interrupt enable bits form part \
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318 of the tasks context. It is perfectly legitimate for another task to \
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319 have modified any other bits. We therefore only restore the top two bits. \
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321 if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
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324 MOVFF POSTDEC1, STATUS \
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325 MOVFF POSTDEC1, WREG \
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326 /* Return enabling interrupts. */ \
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333 MOVFF POSTDEC1, STATUS \
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334 MOVFF POSTDEC1, WREG \
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335 /* Return without effecting interrupts. The context may have \
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336 been saved from a critical region. */ \
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341 /*-----------------------------------------------------------*/
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344 * See header file for description.
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346 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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348 uint32_t ulAddress;
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351 /* Place a few bytes of known values on the bottom of the stack.
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352 This is just useful for debugging. */
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354 *pxTopOfStack = 0x11;
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356 *pxTopOfStack = 0x22;
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358 *pxTopOfStack = 0x33;
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362 /* Simulate how the stack would look after a call to vPortYield() generated
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365 First store the function parameters. This is where the task will expect to
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366 find them when it starts running. */
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367 ulAddress = ( uint32_t ) pvParameters;
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368 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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372 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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375 /* Next we just leave a space. When a context is saved the stack pointer
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376 is incremented before it is used so as not to corrupt whatever the stack
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377 pointer is actually pointing to. This is especially necessary during
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378 function epilogue code generated by the compiler. */
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379 *pxTopOfStack = 0x44;
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382 /* Next are all the registers that form part of the task context. */
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384 *pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
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387 *pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
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390 /* INTCON is saved with interrupts enabled. */
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391 *pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
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394 *pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
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397 *pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
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400 *pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
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403 *pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
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406 *pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
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409 *pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
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412 *pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
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415 *pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
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418 *pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
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421 *pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
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424 *pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
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427 *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
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430 *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
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433 /* Next the .tmpdata and MATH_DATA sections. */
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434 for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
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436 *pxTopOfStack = ( StackType_t ) ucBlock;
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440 /* Store the top of the global data section. */
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441 *pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
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444 *pxTopOfStack = ( StackType_t ) 0x00; /* High. */
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447 /* The only function return address so far is the address of the
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449 ulAddress = ( uint32_t ) pxCode;
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452 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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457 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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461 /* TOS even higher. */
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462 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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465 /* Store the number of return addresses on the hardware stack - so far only
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466 the address of the task entry point. */
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467 *pxTopOfStack = ( StackType_t ) 1;
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470 return pxTopOfStack;
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472 /*-----------------------------------------------------------*/
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474 BaseType_t xPortStartScheduler( void )
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476 /* Setup a timer for the tick ISR is using the preemptive scheduler. */
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477 prvSetupTimerInterrupt();
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479 /* Restore the context of the first task to run. */
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480 portRESTORE_CONTEXT();
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482 /* Should not get here. Use the function name to stop compiler warnings. */
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483 ( void ) prvLowInterrupt;
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484 ( void ) prvTickISR;
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488 /*-----------------------------------------------------------*/
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490 void vPortEndScheduler( void )
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492 /* It is unlikely that the scheduler for the PIC port will get stopped
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493 once running. If required disable the tick interrupt here, then return
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494 to xPortStartScheduler(). */
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496 /*-----------------------------------------------------------*/
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499 * Manual context switch. This is similar to the tick context switch,
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500 * but does not increment the tick count. It must be identical to the
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501 * tick context switch in how it stores the stack of a task.
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503 void vPortYield( void )
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505 /* This can get called with interrupts either enabled or disabled. We
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506 will save the INTCON register with the interrupt enable bits unmodified. */
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507 portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
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509 /* Switch to the highest priority task that is ready to run. */
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510 vTaskSwitchContext();
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512 /* Start executing the task we have just switched to. */
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513 portRESTORE_CONTEXT();
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515 /*-----------------------------------------------------------*/
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518 * Vector for ISR. Nothing here must alter any registers!
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520 #pragma code high_vector=0x08
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521 static void prvLowInterrupt( void )
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523 /* Was the interrupt the tick? */
\r
524 if( PIR1bits.CCP1IF )
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531 /* Was the interrupt a byte being received? */
\r
532 if( PIR1bits.RCIF )
\r
539 /* Was the interrupt the Tx register becoming empty? */
\r
540 if( PIR1bits.TXIF )
\r
542 if( PIE1bits.TXIE )
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552 /*-----------------------------------------------------------*/
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555 * ISR for the tick.
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556 * This increments the tick count and, if using the preemptive scheduler,
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557 * performs a context switch. This must be identical to the manual
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558 * context switch in how it stores the context of a task.
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560 static void prvTickISR( void )
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562 /* Interrupts must have been enabled for the ISR to fire, so we have to
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563 save the context with interrupts enabled. */
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564 portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
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565 PIR1bits.CCP1IF = 0;
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567 /* Maintain the tick count. */
\r
568 if( xTaskIncrementTick() != pdFALSE )
\r
570 /* Switch to the highest priority task that is ready to run. */
\r
571 vTaskSwitchContext();
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574 portRESTORE_CONTEXT();
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576 /*-----------------------------------------------------------*/
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579 * Setup a timer for a regular tick.
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581 static void prvSetupTimerInterrupt( void )
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583 const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
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584 uint32_t ulCompareValue;
\r
587 /* Interrupts are disabled when this function is called.
\r
589 Setup CCP1 to provide the tick interrupt using a compare match on timer
\r
592 Clear the time count then setup timer. */
\r
593 TMR1H = ( uint8_t ) 0x00;
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594 TMR1L = ( uint8_t ) 0x00;
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596 /* Set the compare match value. */
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597 ulCompareValue = ulConstCompareValue;
\r
598 CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
\r
599 ulCompareValue >>= ( uint32_t ) 8;
\r
600 CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
\r
602 CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
\r
603 CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
\r
604 CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
\r
605 CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
\r
606 PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
\r
608 /* We are only going to use the global interrupt bit, so set the peripheral
\r
610 INTCONbits.GIEL = portBIT_SET;
\r
612 /* Provided library function for setting up the timer that will produce the
\r
614 OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
\r