2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 >>! NOTE: The modification to the GPL is included to allow you to !<<
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14 >>! distribute a combined work that includes FreeRTOS without being !<<
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15 >>! obliged to provide the source code for proprietary components !<<
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16 >>! outside of the FreeRTOS kernel. !<<
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18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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21 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * Having a problem? Start by reading the FAQ "My application does *
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28 * not run, what could be wrong?". Have you defined configASSERT()? *
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30 * http://www.FreeRTOS.org/FAQHelp.html *
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32 ***************************************************************************
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34 ***************************************************************************
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36 * FreeRTOS provides completely free yet professionally developed, *
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37 * robust, strictly quality controlled, supported, and cross *
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38 * platform software that is more than just the market leader, it *
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39 * is the industry's de facto standard. *
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41 * Help yourself get started quickly while simultaneously helping *
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42 * to support the FreeRTOS project by purchasing a FreeRTOS *
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43 * tutorial book, reference manual, or both: *
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44 * http://www.FreeRTOS.org/Documentation *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * Investing in training allows your team to be as productive as *
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51 * possible as early as possible, lowering your overall development *
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52 * cost, and enabling you to bring a more robust product to market *
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53 * earlier than would otherwise be possible. Richard Barry is both *
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54 * the architect and key author of FreeRTOS, and so also the world's *
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55 * leading authority on what is the world's most popular real time *
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56 * kernel for deeply embedded MCU designs. Obtaining your training *
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57 * from Richard ensures your team will gain directly from his in-depth *
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58 * product knowledge and years of usage experience. Contact Real Time *
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59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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60 * by Richard Barry: http://www.FreeRTOS.org/contact
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62 ***************************************************************************
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64 ***************************************************************************
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66 * You are receiving this top quality software for free. Please play *
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67 * fair and reciprocate by reporting any suspected issues and *
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68 * participating in the community forum: *
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69 * http://www.FreeRTOS.org/support *
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73 ***************************************************************************
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75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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76 license and Real Time Engineers Ltd. contact details.
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78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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87 licenses offer ticketed support, indemnification and commercial middleware.
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89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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90 engineered and independently SIL3 certified version for use in safety and
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91 mission critical applications that require provable dependability.
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97 Changes between V1.2.4 and V1.2.5
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99 + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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100 interrupt flag setting. Using the two bits defined within
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101 portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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102 before the test was performed.
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104 Changes from V1.2.5
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106 + Set the interrupt vector address to 0x08. Previously it was at the
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107 incorrect address for compatibility mode of 0x18.
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109 Changes from V2.1.1
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111 + PCLATU and PCLATH are now saved as part of the context. This allows
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112 function pointers to be used within tasks. Thanks to Javier Espeche
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113 for the enhancement.
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115 Changes from V2.3.1
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117 + TABLAT is now saved as part of the task context.
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119 Changes from V3.2.0
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121 + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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122 value and does not write to the register.
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125 /* Scheduler include files. */
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126 #include "FreeRTOS.h"
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129 /* MPLAB library include file. */
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130 #include "timers.h"
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132 /*-----------------------------------------------------------
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133 * Implementation of functions defined in portable.h for the PIC port.
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134 *----------------------------------------------------------*/
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136 /* Hardware setup for tick. */
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137 #define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
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139 /* Initial interrupt enable state for newly created tasks. This value is
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140 copied into INTCON when a task switches in for the first time. */
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141 #define portINITAL_INTERRUPT_STATE 0xc0
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143 /* Just the bit within INTCON for the global interrupt flag. */
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144 #define portGLOBAL_INTERRUPT_FLAG 0x80
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146 /* Constant used for context switch macro when we require the interrupt
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147 enable state to be unchanged when the interrupted task is switched back in. */
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148 #define portINTERRUPTS_UNCHANGED 0x00
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150 /* Some memory areas get saved as part of the task context. These memory
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151 area's get used by the compiler for temporary storage, especially when
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152 performing mathematical operations, or when using 32bit data types. This
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153 constant defines the size of memory area which must be saved. */
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154 #define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
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156 /* We require the address of the pxCurrentTCB variable, but don't want to know
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157 any details of its type. */
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158 typedef void TCB_t;
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159 extern volatile TCB_t * volatile pxCurrentTCB;
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161 /* IO port constants. */
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162 #define portBIT_SET ( ( uint8_t ) 1 )
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163 #define portBIT_CLEAR ( ( uint8_t ) 0 )
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166 * The serial port ISR's are defined in serial.c, but are called from portable
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167 * as they use the same vector as the tick ISR.
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169 void vSerialTxISR( void );
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170 void vSerialRxISR( void );
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173 * Perform hardware setup to enable ticks.
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175 static void prvSetupTimerInterrupt( void );
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178 * ISR to maintain the tick, and perform tick context switches if the
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179 * preemptive scheduler is being used.
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181 static void prvTickISR( void );
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184 * ISR placed on the low priority vector. This calls the appropriate ISR for
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185 * the actual interrupt.
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187 static void prvLowInterrupt( void );
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190 * Macro that pushes all the registers that make up the context of a task onto
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191 * the stack, then saves the new top of stack into the TCB.
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193 * If this is called from an ISR then the interrupt enable bits must have been
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194 * set for the ISR to ever get called. Therefore we want to save the INTCON
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195 * register with the enable bits forced to be set - and ucForcedInterruptFlags
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196 * must contain these bit settings. This means the interrupts will again be
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197 * enabled when the interrupted task is switched back in.
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199 * If this is called from a manual context switch (i.e. from a call to yield),
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200 * then we want to save the INTCON so it is restored with its current state,
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201 * and ucForcedInterruptFlags must be 0. This allows a yield from within
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202 * a critical section.
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204 * The compiler uses some locations at the bottom of the memory for temporary
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205 * storage during math and other computations. This is especially true if
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206 * 32bit data types are utilised (as they are by the scheduler). The .tmpdata
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207 * and MATH_DATA sections have to be stored in there entirety as part of a task
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208 * context. This macro stores from data address 0x00 to
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209 * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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210 * applications but you should check the map file for your project to ensure
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211 * this is sufficient for your needs. It is not clear whether this size is
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212 * fixed for all compilations or has the potential to be program specific.
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214 #define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
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217 /* Save the status and WREG registers first, as these will get modified \
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218 by the operations below. */ \
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219 MOVFF WREG, PREINC1 \
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220 MOVFF STATUS, PREINC1 \
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221 /* Save the INTCON register with the appropriate bits forced if \
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222 necessary - as described above. */ \
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223 MOVFF INTCON, WREG \
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224 IORLW ucForcedInterruptFlags \
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225 MOVFF WREG, PREINC1 \
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228 portDISABLE_INTERRUPTS(); \
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231 /* Store the necessary registers to the stack. */ \
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232 MOVFF BSR, PREINC1 \
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233 MOVFF FSR2L, PREINC1 \
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234 MOVFF FSR2H, PREINC1 \
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235 MOVFF FSR0L, PREINC1 \
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236 MOVFF FSR0H, PREINC1 \
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237 MOVFF TABLAT, PREINC1 \
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238 MOVFF TBLPTRU, PREINC1 \
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239 MOVFF TBLPTRH, PREINC1 \
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240 MOVFF TBLPTRL, PREINC1 \
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241 MOVFF PRODH, PREINC1 \
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242 MOVFF PRODL, PREINC1 \
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243 MOVFF PCLATU, PREINC1 \
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244 MOVFF PCLATH, PREINC1 \
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245 /* Store the .tempdata and MATH_DATA areas as described above. */ \
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248 MOVFF POSTINC0, PREINC1 \
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249 MOVFF POSTINC0, PREINC1 \
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250 MOVFF POSTINC0, PREINC1 \
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251 MOVFF POSTINC0, PREINC1 \
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252 MOVFF POSTINC0, PREINC1 \
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253 MOVFF POSTINC0, PREINC1 \
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254 MOVFF POSTINC0, PREINC1 \
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255 MOVFF POSTINC0, PREINC1 \
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256 MOVFF POSTINC0, PREINC1 \
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257 MOVFF POSTINC0, PREINC1 \
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258 MOVFF POSTINC0, PREINC1 \
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259 MOVFF POSTINC0, PREINC1 \
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260 MOVFF POSTINC0, PREINC1 \
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261 MOVFF POSTINC0, PREINC1 \
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262 MOVFF POSTINC0, PREINC1 \
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263 MOVFF POSTINC0, PREINC1 \
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264 MOVFF POSTINC0, PREINC1 \
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265 MOVFF POSTINC0, PREINC1 \
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266 MOVFF POSTINC0, PREINC1 \
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267 MOVFF INDF0, PREINC1 \
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268 MOVFF FSR0L, PREINC1 \
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269 MOVFF FSR0H, PREINC1 \
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270 /* Store the hardware stack pointer in a temp register before we \
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272 MOVFF STKPTR, FSR0L \
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275 /* Store each address from the hardware stack. */ \
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276 while( STKPTR > ( uint8_t ) 0 ) \
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279 MOVFF TOSL, PREINC1 \
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280 MOVFF TOSH, PREINC1 \
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281 MOVFF TOSU, PREINC1 \
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287 /* Store the number of addresses on the hardware stack (from the \
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288 temporary register). */ \
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289 MOVFF FSR0L, PREINC1 \
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290 MOVF PREINC1, 1, 0 \
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293 /* Save the new top of the software stack in the TCB. */ \
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295 MOVFF pxCurrentTCB, FSR0L \
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296 MOVFF pxCurrentTCB + 1, FSR0H \
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297 MOVFF FSR1L, POSTINC0 \
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298 MOVFF FSR1H, POSTINC0 \
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301 /*-----------------------------------------------------------*/
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304 * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
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307 #define portRESTORE_CONTEXT() \
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310 /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
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311 MOVFF pxCurrentTCB, FSR0L \
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312 MOVFF pxCurrentTCB + 1, FSR0H \
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314 /* De-reference FSR0 to set the address it holds into FSR1. \
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315 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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316 MOVFF POSTINC0, FSR1L \
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317 MOVFF POSTINC0, FSR1H \
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319 /* How many return addresses are there on the hardware stack? Discard \
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320 the first byte as we are pointing to the next free space. */ \
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321 MOVFF POSTDEC1, FSR0L \
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322 MOVFF POSTDEC1, FSR0L \
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325 /* Fill the hardware stack from our software stack. */ \
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328 while( STKPTR < FSR0L ) \
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332 MOVF POSTDEC1, 0, 0 \
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334 MOVF POSTDEC1, 0, 0 \
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336 MOVF POSTDEC1, 0, 0 \
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342 /* Restore the .tmpdata and MATH_DATA memory. */ \
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343 MOVFF POSTDEC1, FSR0H \
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344 MOVFF POSTDEC1, FSR0L \
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345 MOVFF POSTDEC1, POSTDEC0 \
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346 MOVFF POSTDEC1, POSTDEC0 \
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347 MOVFF POSTDEC1, POSTDEC0 \
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348 MOVFF POSTDEC1, POSTDEC0 \
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349 MOVFF POSTDEC1, POSTDEC0 \
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350 MOVFF POSTDEC1, POSTDEC0 \
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351 MOVFF POSTDEC1, POSTDEC0 \
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352 MOVFF POSTDEC1, POSTDEC0 \
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353 MOVFF POSTDEC1, POSTDEC0 \
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354 MOVFF POSTDEC1, POSTDEC0 \
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355 MOVFF POSTDEC1, POSTDEC0 \
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356 MOVFF POSTDEC1, POSTDEC0 \
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357 MOVFF POSTDEC1, POSTDEC0 \
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358 MOVFF POSTDEC1, POSTDEC0 \
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359 MOVFF POSTDEC1, POSTDEC0 \
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360 MOVFF POSTDEC1, POSTDEC0 \
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361 MOVFF POSTDEC1, POSTDEC0 \
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362 MOVFF POSTDEC1, POSTDEC0 \
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363 MOVFF POSTDEC1, POSTDEC0 \
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364 MOVFF POSTDEC1, INDF0 \
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365 /* Restore the other registers forming the tasks context. */ \
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366 MOVFF POSTDEC1, PCLATH \
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367 MOVFF POSTDEC1, PCLATU \
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368 MOVFF POSTDEC1, PRODL \
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369 MOVFF POSTDEC1, PRODH \
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370 MOVFF POSTDEC1, TBLPTRL \
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371 MOVFF POSTDEC1, TBLPTRH \
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372 MOVFF POSTDEC1, TBLPTRU \
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373 MOVFF POSTDEC1, TABLAT \
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374 MOVFF POSTDEC1, FSR0H \
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375 MOVFF POSTDEC1, FSR0L \
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376 MOVFF POSTDEC1, FSR2H \
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377 MOVFF POSTDEC1, FSR2L \
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378 MOVFF POSTDEC1, BSR \
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379 /* The next byte is the INTCON register. Read this into WREG as some \
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380 manipulation is required. */ \
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381 MOVFF POSTDEC1, WREG \
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384 /* From the INTCON register, only the interrupt enable bits form part \
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385 of the tasks context. It is perfectly legitimate for another task to \
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386 have modified any other bits. We therefore only restore the top two bits. \
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388 if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
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391 MOVFF POSTDEC1, STATUS \
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392 MOVFF POSTDEC1, WREG \
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393 /* Return enabling interrupts. */ \
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400 MOVFF POSTDEC1, STATUS \
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401 MOVFF POSTDEC1, WREG \
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402 /* Return without effecting interrupts. The context may have \
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403 been saved from a critical region. */ \
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408 /*-----------------------------------------------------------*/
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411 * See header file for description.
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413 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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415 uint32_t ulAddress;
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418 /* Place a few bytes of known values on the bottom of the stack.
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419 This is just useful for debugging. */
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421 *pxTopOfStack = 0x11;
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423 *pxTopOfStack = 0x22;
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425 *pxTopOfStack = 0x33;
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429 /* Simulate how the stack would look after a call to vPortYield() generated
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432 First store the function parameters. This is where the task will expect to
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433 find them when it starts running. */
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434 ulAddress = ( uint32_t ) pvParameters;
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435 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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439 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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442 /* Next we just leave a space. When a context is saved the stack pointer
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443 is incremented before it is used so as not to corrupt whatever the stack
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444 pointer is actually pointing to. This is especially necessary during
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445 function epilogue code generated by the compiler. */
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446 *pxTopOfStack = 0x44;
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449 /* Next are all the registers that form part of the task context. */
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451 *pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
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454 *pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
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457 /* INTCON is saved with interrupts enabled. */
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458 *pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
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461 *pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
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464 *pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
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467 *pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
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470 *pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
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473 *pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
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476 *pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
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479 *pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
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482 *pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
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485 *pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
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488 *pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
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491 *pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
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494 *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
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497 *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
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500 /* Next the .tmpdata and MATH_DATA sections. */
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501 for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
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503 *pxTopOfStack = ( StackType_t ) ucBlock;
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507 /* Store the top of the global data section. */
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508 *pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
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511 *pxTopOfStack = ( StackType_t ) 0x00; /* High. */
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514 /* The only function return address so far is the address of the
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516 ulAddress = ( uint32_t ) pxCode;
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519 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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524 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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528 /* TOS even higher. */
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529 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
\r
532 /* Store the number of return addresses on the hardware stack - so far only
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533 the address of the task entry point. */
\r
534 *pxTopOfStack = ( StackType_t ) 1;
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537 return pxTopOfStack;
\r
539 /*-----------------------------------------------------------*/
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541 BaseType_t xPortStartScheduler( void )
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543 /* Setup a timer for the tick ISR is using the preemptive scheduler. */
\r
544 prvSetupTimerInterrupt();
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546 /* Restore the context of the first task to run. */
\r
547 portRESTORE_CONTEXT();
\r
549 /* Should not get here. Use the function name to stop compiler warnings. */
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550 ( void ) prvLowInterrupt;
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551 ( void ) prvTickISR;
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555 /*-----------------------------------------------------------*/
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557 void vPortEndScheduler( void )
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559 /* It is unlikely that the scheduler for the PIC port will get stopped
\r
560 once running. If required disable the tick interrupt here, then return
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561 to xPortStartScheduler(). */
\r
563 /*-----------------------------------------------------------*/
\r
566 * Manual context switch. This is similar to the tick context switch,
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567 * but does not increment the tick count. It must be identical to the
\r
568 * tick context switch in how it stores the stack of a task.
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570 void vPortYield( void )
\r
572 /* This can get called with interrupts either enabled or disabled. We
\r
573 will save the INTCON register with the interrupt enable bits unmodified. */
\r
574 portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
\r
576 /* Switch to the highest priority task that is ready to run. */
\r
577 vTaskSwitchContext();
\r
579 /* Start executing the task we have just switched to. */
\r
580 portRESTORE_CONTEXT();
\r
582 /*-----------------------------------------------------------*/
\r
585 * Vector for ISR. Nothing here must alter any registers!
\r
587 #pragma code high_vector=0x08
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588 static void prvLowInterrupt( void )
\r
590 /* Was the interrupt the tick? */
\r
591 if( PIR1bits.CCP1IF )
\r
598 /* Was the interrupt a byte being received? */
\r
599 if( PIR1bits.RCIF )
\r
606 /* Was the interrupt the Tx register becoming empty? */
\r
607 if( PIR1bits.TXIF )
\r
609 if( PIE1bits.TXIE )
\r
619 /*-----------------------------------------------------------*/
\r
622 * ISR for the tick.
\r
623 * This increments the tick count and, if using the preemptive scheduler,
\r
624 * performs a context switch. This must be identical to the manual
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625 * context switch in how it stores the context of a task.
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627 static void prvTickISR( void )
\r
629 /* Interrupts must have been enabled for the ISR to fire, so we have to
\r
630 save the context with interrupts enabled. */
\r
631 portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
\r
632 PIR1bits.CCP1IF = 0;
\r
634 /* Maintain the tick count. */
\r
635 if( xTaskIncrementTick() != pdFALSE )
\r
637 /* Switch to the highest priority task that is ready to run. */
\r
638 vTaskSwitchContext();
\r
641 portRESTORE_CONTEXT();
\r
643 /*-----------------------------------------------------------*/
\r
646 * Setup a timer for a regular tick.
\r
648 static void prvSetupTimerInterrupt( void )
\r
650 const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
\r
651 uint32_t ulCompareValue;
\r
654 /* Interrupts are disabled when this function is called.
\r
656 Setup CCP1 to provide the tick interrupt using a compare match on timer
\r
659 Clear the time count then setup timer. */
\r
660 TMR1H = ( uint8_t ) 0x00;
\r
661 TMR1L = ( uint8_t ) 0x00;
\r
663 /* Set the compare match value. */
\r
664 ulCompareValue = ulConstCompareValue;
\r
665 CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
\r
666 ulCompareValue >>= ( uint32_t ) 8;
\r
667 CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
\r
669 CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
\r
670 CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
\r
671 CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
\r
672 CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
\r
673 PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
\r
675 /* We are only going to use the global interrupt bit, so set the peripheral
\r
677 INTCONbits.GIEL = portBIT_SET;
\r
679 /* Provided library function for setting up the timer that will produce the
\r
681 OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
\r
projects / freertos / blob