2 FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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71 Changes between V1.2.4 and V1.2.5
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73 + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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74 interrupt flag setting. Using the two bits defined within
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75 portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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76 before the test was performed.
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80 + Set the interrupt vector address to 0x08. Previously it was at the
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81 incorrect address for compatibility mode of 0x18.
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85 + PCLATU and PCLATH are now saved as part of the context. This allows
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86 function pointers to be used within tasks. Thanks to Javier Espeche
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87 for the enhancement.
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91 + TABLAT is now saved as part of the task context.
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95 + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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96 value and does not write to the register.
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99 /* Scheduler include files. */
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100 #include "FreeRTOS.h"
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103 /* MPLAB library include file. */
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104 #include "timers.h"
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106 /*-----------------------------------------------------------
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107 * Implementation of functions defined in portable.h for the PIC port.
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108 *----------------------------------------------------------*/
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110 /* Hardware setup for tick. */
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111 #define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
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113 /* Initial interrupt enable state for newly created tasks. This value is
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114 copied into INTCON when a task switches in for the first time. */
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115 #define portINITAL_INTERRUPT_STATE 0xc0
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117 /* Just the bit within INTCON for the global interrupt flag. */
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118 #define portGLOBAL_INTERRUPT_FLAG 0x80
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120 /* Constant used for context switch macro when we require the interrupt
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121 enable state to be unchanged when the interrupted task is switched back in. */
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122 #define portINTERRUPTS_UNCHANGED 0x00
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124 /* Some memory areas get saved as part of the task context. These memory
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125 area's get used by the compiler for temporary storage, especially when
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126 performing mathematical operations, or when using 32bit data types. This
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127 constant defines the size of memory area which must be saved. */
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128 #define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
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130 /* We require the address of the pxCurrentTCB variable, but don't want to know
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131 any details of its type. */
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132 typedef void TCB_t;
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133 extern volatile TCB_t * volatile pxCurrentTCB;
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135 /* IO port constants. */
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136 #define portBIT_SET ( ( uint8_t ) 1 )
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137 #define portBIT_CLEAR ( ( uint8_t ) 0 )
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140 * The serial port ISR's are defined in serial.c, but are called from portable
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141 * as they use the same vector as the tick ISR.
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143 void vSerialTxISR( void );
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144 void vSerialRxISR( void );
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147 * Perform hardware setup to enable ticks.
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149 static void prvSetupTimerInterrupt( void );
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152 * ISR to maintain the tick, and perform tick context switches if the
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153 * preemptive scheduler is being used.
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155 static void prvTickISR( void );
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158 * ISR placed on the low priority vector. This calls the appropriate ISR for
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159 * the actual interrupt.
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161 static void prvLowInterrupt( void );
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164 * Macro that pushes all the registers that make up the context of a task onto
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165 * the stack, then saves the new top of stack into the TCB.
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167 * If this is called from an ISR then the interrupt enable bits must have been
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168 * set for the ISR to ever get called. Therefore we want to save the INTCON
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169 * register with the enable bits forced to be set - and ucForcedInterruptFlags
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170 * must contain these bit settings. This means the interrupts will again be
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171 * enabled when the interrupted task is switched back in.
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173 * If this is called from a manual context switch (i.e. from a call to yield),
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174 * then we want to save the INTCON so it is restored with its current state,
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175 * and ucForcedInterruptFlags must be 0. This allows a yield from within
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176 * a critical section.
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178 * The compiler uses some locations at the bottom of the memory for temporary
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179 * storage during math and other computations. This is especially true if
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180 * 32bit data types are utilised (as they are by the scheduler). The .tmpdata
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181 * and MATH_DATA sections have to be stored in there entirety as part of a task
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182 * context. This macro stores from data address 0x00 to
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183 * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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184 * applications but you should check the map file for your project to ensure
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185 * this is sufficient for your needs. It is not clear whether this size is
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186 * fixed for all compilations or has the potential to be program specific.
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188 #define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
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191 /* Save the status and WREG registers first, as these will get modified \
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192 by the operations below. */ \
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193 MOVFF WREG, PREINC1 \
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194 MOVFF STATUS, PREINC1 \
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195 /* Save the INTCON register with the appropriate bits forced if \
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196 necessary - as described above. */ \
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197 MOVFF INTCON, WREG \
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198 IORLW ucForcedInterruptFlags \
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199 MOVFF WREG, PREINC1 \
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202 portDISABLE_INTERRUPTS(); \
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205 /* Store the necessary registers to the stack. */ \
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206 MOVFF BSR, PREINC1 \
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207 MOVFF FSR2L, PREINC1 \
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208 MOVFF FSR2H, PREINC1 \
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209 MOVFF FSR0L, PREINC1 \
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210 MOVFF FSR0H, PREINC1 \
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211 MOVFF TABLAT, PREINC1 \
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212 MOVFF TBLPTRU, PREINC1 \
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213 MOVFF TBLPTRH, PREINC1 \
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214 MOVFF TBLPTRL, PREINC1 \
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215 MOVFF PRODH, PREINC1 \
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216 MOVFF PRODL, PREINC1 \
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217 MOVFF PCLATU, PREINC1 \
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218 MOVFF PCLATH, PREINC1 \
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219 /* Store the .tempdata and MATH_DATA areas as described above. */ \
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222 MOVFF POSTINC0, PREINC1 \
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223 MOVFF POSTINC0, PREINC1 \
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224 MOVFF POSTINC0, PREINC1 \
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225 MOVFF POSTINC0, PREINC1 \
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226 MOVFF POSTINC0, PREINC1 \
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227 MOVFF POSTINC0, PREINC1 \
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228 MOVFF POSTINC0, PREINC1 \
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229 MOVFF POSTINC0, PREINC1 \
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230 MOVFF POSTINC0, PREINC1 \
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231 MOVFF POSTINC0, PREINC1 \
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232 MOVFF POSTINC0, PREINC1 \
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233 MOVFF POSTINC0, PREINC1 \
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234 MOVFF POSTINC0, PREINC1 \
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235 MOVFF POSTINC0, PREINC1 \
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236 MOVFF POSTINC0, PREINC1 \
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237 MOVFF POSTINC0, PREINC1 \
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238 MOVFF POSTINC0, PREINC1 \
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239 MOVFF POSTINC0, PREINC1 \
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240 MOVFF POSTINC0, PREINC1 \
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241 MOVFF INDF0, PREINC1 \
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242 MOVFF FSR0L, PREINC1 \
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243 MOVFF FSR0H, PREINC1 \
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244 /* Store the hardware stack pointer in a temp register before we \
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246 MOVFF STKPTR, FSR0L \
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249 /* Store each address from the hardware stack. */ \
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250 while( STKPTR > ( uint8_t ) 0 ) \
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253 MOVFF TOSL, PREINC1 \
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254 MOVFF TOSH, PREINC1 \
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255 MOVFF TOSU, PREINC1 \
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261 /* Store the number of addresses on the hardware stack (from the \
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262 temporary register). */ \
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263 MOVFF FSR0L, PREINC1 \
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264 MOVF PREINC1, 1, 0 \
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267 /* Save the new top of the software stack in the TCB. */ \
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269 MOVFF pxCurrentTCB, FSR0L \
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270 MOVFF pxCurrentTCB + 1, FSR0H \
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271 MOVFF FSR1L, POSTINC0 \
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272 MOVFF FSR1H, POSTINC0 \
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275 /*-----------------------------------------------------------*/
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278 * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
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281 #define portRESTORE_CONTEXT() \
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284 /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
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285 MOVFF pxCurrentTCB, FSR0L \
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286 MOVFF pxCurrentTCB + 1, FSR0H \
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288 /* De-reference FSR0 to set the address it holds into FSR1. \
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289 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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290 MOVFF POSTINC0, FSR1L \
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291 MOVFF POSTINC0, FSR1H \
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293 /* How many return addresses are there on the hardware stack? Discard \
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294 the first byte as we are pointing to the next free space. */ \
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295 MOVFF POSTDEC1, FSR0L \
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296 MOVFF POSTDEC1, FSR0L \
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299 /* Fill the hardware stack from our software stack. */ \
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302 while( STKPTR < FSR0L ) \
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306 MOVF POSTDEC1, 0, 0 \
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308 MOVF POSTDEC1, 0, 0 \
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310 MOVF POSTDEC1, 0, 0 \
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316 /* Restore the .tmpdata and MATH_DATA memory. */ \
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317 MOVFF POSTDEC1, FSR0H \
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318 MOVFF POSTDEC1, FSR0L \
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319 MOVFF POSTDEC1, POSTDEC0 \
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320 MOVFF POSTDEC1, POSTDEC0 \
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321 MOVFF POSTDEC1, POSTDEC0 \
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322 MOVFF POSTDEC1, POSTDEC0 \
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323 MOVFF POSTDEC1, POSTDEC0 \
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324 MOVFF POSTDEC1, POSTDEC0 \
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325 MOVFF POSTDEC1, POSTDEC0 \
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326 MOVFF POSTDEC1, POSTDEC0 \
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327 MOVFF POSTDEC1, POSTDEC0 \
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328 MOVFF POSTDEC1, POSTDEC0 \
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329 MOVFF POSTDEC1, POSTDEC0 \
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330 MOVFF POSTDEC1, POSTDEC0 \
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331 MOVFF POSTDEC1, POSTDEC0 \
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332 MOVFF POSTDEC1, POSTDEC0 \
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333 MOVFF POSTDEC1, POSTDEC0 \
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334 MOVFF POSTDEC1, POSTDEC0 \
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335 MOVFF POSTDEC1, POSTDEC0 \
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336 MOVFF POSTDEC1, POSTDEC0 \
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337 MOVFF POSTDEC1, POSTDEC0 \
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338 MOVFF POSTDEC1, INDF0 \
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339 /* Restore the other registers forming the tasks context. */ \
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340 MOVFF POSTDEC1, PCLATH \
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341 MOVFF POSTDEC1, PCLATU \
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342 MOVFF POSTDEC1, PRODL \
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343 MOVFF POSTDEC1, PRODH \
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344 MOVFF POSTDEC1, TBLPTRL \
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345 MOVFF POSTDEC1, TBLPTRH \
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346 MOVFF POSTDEC1, TBLPTRU \
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347 MOVFF POSTDEC1, TABLAT \
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348 MOVFF POSTDEC1, FSR0H \
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349 MOVFF POSTDEC1, FSR0L \
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350 MOVFF POSTDEC1, FSR2H \
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351 MOVFF POSTDEC1, FSR2L \
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352 MOVFF POSTDEC1, BSR \
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353 /* The next byte is the INTCON register. Read this into WREG as some \
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354 manipulation is required. */ \
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355 MOVFF POSTDEC1, WREG \
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358 /* From the INTCON register, only the interrupt enable bits form part \
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359 of the tasks context. It is perfectly legitimate for another task to \
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360 have modified any other bits. We therefore only restore the top two bits. \
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362 if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
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365 MOVFF POSTDEC1, STATUS \
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366 MOVFF POSTDEC1, WREG \
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367 /* Return enabling interrupts. */ \
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374 MOVFF POSTDEC1, STATUS \
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375 MOVFF POSTDEC1, WREG \
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376 /* Return without effecting interrupts. The context may have \
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377 been saved from a critical region. */ \
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382 /*-----------------------------------------------------------*/
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385 * See header file for description.
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387 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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389 uint32_t ulAddress;
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392 /* Place a few bytes of known values on the bottom of the stack.
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393 This is just useful for debugging. */
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395 *pxTopOfStack = 0x11;
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397 *pxTopOfStack = 0x22;
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399 *pxTopOfStack = 0x33;
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403 /* Simulate how the stack would look after a call to vPortYield() generated
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406 First store the function parameters. This is where the task will expect to
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407 find them when it starts running. */
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408 ulAddress = ( uint32_t ) pvParameters;
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409 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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413 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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416 /* Next we just leave a space. When a context is saved the stack pointer
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417 is incremented before it is used so as not to corrupt whatever the stack
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418 pointer is actually pointing to. This is especially necessary during
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419 function epilogue code generated by the compiler. */
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420 *pxTopOfStack = 0x44;
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423 /* Next are all the registers that form part of the task context. */
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425 *pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
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428 *pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
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431 /* INTCON is saved with interrupts enabled. */
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432 *pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
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435 *pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
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438 *pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
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441 *pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
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444 *pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
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447 *pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
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450 *pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
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453 *pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
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456 *pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
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459 *pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
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462 *pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
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465 *pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
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468 *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
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471 *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
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474 /* Next the .tmpdata and MATH_DATA sections. */
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475 for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
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477 *pxTopOfStack = ( StackType_t ) ucBlock;
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481 /* Store the top of the global data section. */
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482 *pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
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485 *pxTopOfStack = ( StackType_t ) 0x00; /* High. */
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488 /* The only function return address so far is the address of the
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490 ulAddress = ( uint32_t ) pxCode;
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493 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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498 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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502 /* TOS even higher. */
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503 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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506 /* Store the number of return addresses on the hardware stack - so far only
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507 the address of the task entry point. */
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508 *pxTopOfStack = ( StackType_t ) 1;
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511 return pxTopOfStack;
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513 /*-----------------------------------------------------------*/
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515 BaseType_t xPortStartScheduler( void )
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517 /* Setup a timer for the tick ISR is using the preemptive scheduler. */
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518 prvSetupTimerInterrupt();
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520 /* Restore the context of the first task to run. */
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521 portRESTORE_CONTEXT();
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523 /* Should not get here. Use the function name to stop compiler warnings. */
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524 ( void ) prvLowInterrupt;
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525 ( void ) prvTickISR;
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529 /*-----------------------------------------------------------*/
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531 void vPortEndScheduler( void )
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533 /* It is unlikely that the scheduler for the PIC port will get stopped
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534 once running. If required disable the tick interrupt here, then return
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535 to xPortStartScheduler(). */
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537 /*-----------------------------------------------------------*/
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540 * Manual context switch. This is similar to the tick context switch,
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541 * but does not increment the tick count. It must be identical to the
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542 * tick context switch in how it stores the stack of a task.
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544 void vPortYield( void )
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546 /* This can get called with interrupts either enabled or disabled. We
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547 will save the INTCON register with the interrupt enable bits unmodified. */
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548 portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
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550 /* Switch to the highest priority task that is ready to run. */
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551 vTaskSwitchContext();
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553 /* Start executing the task we have just switched to. */
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554 portRESTORE_CONTEXT();
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556 /*-----------------------------------------------------------*/
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559 * Vector for ISR. Nothing here must alter any registers!
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561 #pragma code high_vector=0x08
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562 static void prvLowInterrupt( void )
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564 /* Was the interrupt the tick? */
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565 if( PIR1bits.CCP1IF )
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572 /* Was the interrupt a byte being received? */
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573 if( PIR1bits.RCIF )
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580 /* Was the interrupt the Tx register becoming empty? */
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581 if( PIR1bits.TXIF )
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583 if( PIE1bits.TXIE )
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593 /*-----------------------------------------------------------*/
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596 * ISR for the tick.
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597 * This increments the tick count and, if using the preemptive scheduler,
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598 * performs a context switch. This must be identical to the manual
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599 * context switch in how it stores the context of a task.
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601 static void prvTickISR( void )
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603 /* Interrupts must have been enabled for the ISR to fire, so we have to
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604 save the context with interrupts enabled. */
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605 portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
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606 PIR1bits.CCP1IF = 0;
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608 /* Maintain the tick count. */
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609 if( xTaskIncrementTick() != pdFALSE )
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611 /* Switch to the highest priority task that is ready to run. */
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612 vTaskSwitchContext();
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615 portRESTORE_CONTEXT();
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617 /*-----------------------------------------------------------*/
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620 * Setup a timer for a regular tick.
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622 static void prvSetupTimerInterrupt( void )
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624 const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
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625 uint32_t ulCompareValue;
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628 /* Interrupts are disabled when this function is called.
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630 Setup CCP1 to provide the tick interrupt using a compare match on timer
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633 Clear the time count then setup timer. */
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634 TMR1H = ( uint8_t ) 0x00;
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635 TMR1L = ( uint8_t ) 0x00;
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637 /* Set the compare match value. */
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638 ulCompareValue = ulConstCompareValue;
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639 CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
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640 ulCompareValue >>= ( uint32_t ) 8;
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641 CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
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643 CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
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644 CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
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645 CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
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646 CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
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647 PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
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649 /* We are only going to use the global interrupt bit, so set the peripheral
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651 INTCONbits.GIEL = portBIT_SET;
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653 /* Provided library function for setting up the timer that will produce the
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655 OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
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projects / freertos / blob