2 * FreeRTOS Kernel V10.2.0
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 Changes between V1.2.4 and V1.2.5
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31 + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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32 interrupt flag setting. Using the two bits defined within
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33 portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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34 before the test was performed.
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38 + Set the interrupt vector address to 0x08. Previously it was at the
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39 incorrect address for compatibility mode of 0x18.
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43 + PCLATU and PCLATH are now saved as part of the context. This allows
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44 function pointers to be used within tasks. Thanks to Javier Espeche
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45 for the enhancement.
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49 + TABLAT is now saved as part of the task context.
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53 + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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54 value and does not write to the register.
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57 /* Scheduler include files. */
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58 #include "FreeRTOS.h"
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61 /* MPLAB library include file. */
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64 /*-----------------------------------------------------------
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65 * Implementation of functions defined in portable.h for the PIC port.
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66 *----------------------------------------------------------*/
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68 /* Hardware setup for tick. */
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69 #define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
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71 /* Initial interrupt enable state for newly created tasks. This value is
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72 copied into INTCON when a task switches in for the first time. */
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73 #define portINITAL_INTERRUPT_STATE 0xc0
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75 /* Just the bit within INTCON for the global interrupt flag. */
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76 #define portGLOBAL_INTERRUPT_FLAG 0x80
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78 /* Constant used for context switch macro when we require the interrupt
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79 enable state to be unchanged when the interrupted task is switched back in. */
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80 #define portINTERRUPTS_UNCHANGED 0x00
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82 /* Some memory areas get saved as part of the task context. These memory
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83 area's get used by the compiler for temporary storage, especially when
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84 performing mathematical operations, or when using 32bit data types. This
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85 constant defines the size of memory area which must be saved. */
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86 #define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
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88 /* We require the address of the pxCurrentTCB variable, but don't want to know
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89 any details of its type. */
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91 extern volatile TCB_t * volatile pxCurrentTCB;
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93 /* IO port constants. */
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94 #define portBIT_SET ( ( uint8_t ) 1 )
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95 #define portBIT_CLEAR ( ( uint8_t ) 0 )
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98 * The serial port ISR's are defined in serial.c, but are called from portable
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99 * as they use the same vector as the tick ISR.
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101 void vSerialTxISR( void );
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102 void vSerialRxISR( void );
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105 * Perform hardware setup to enable ticks.
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107 static void prvSetupTimerInterrupt( void );
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110 * ISR to maintain the tick, and perform tick context switches if the
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111 * preemptive scheduler is being used.
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113 static void prvTickISR( void );
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116 * ISR placed on the low priority vector. This calls the appropriate ISR for
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117 * the actual interrupt.
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119 static void prvLowInterrupt( void );
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122 * Macro that pushes all the registers that make up the context of a task onto
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123 * the stack, then saves the new top of stack into the TCB.
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125 * If this is called from an ISR then the interrupt enable bits must have been
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126 * set for the ISR to ever get called. Therefore we want to save the INTCON
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127 * register with the enable bits forced to be set - and ucForcedInterruptFlags
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128 * must contain these bit settings. This means the interrupts will again be
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129 * enabled when the interrupted task is switched back in.
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131 * If this is called from a manual context switch (i.e. from a call to yield),
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132 * then we want to save the INTCON so it is restored with its current state,
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133 * and ucForcedInterruptFlags must be 0. This allows a yield from within
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134 * a critical section.
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136 * The compiler uses some locations at the bottom of the memory for temporary
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137 * storage during math and other computations. This is especially true if
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138 * 32bit data types are utilised (as they are by the scheduler). The .tmpdata
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139 * and MATH_DATA sections have to be stored in there entirety as part of a task
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140 * context. This macro stores from data address 0x00 to
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141 * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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142 * applications but you should check the map file for your project to ensure
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143 * this is sufficient for your needs. It is not clear whether this size is
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144 * fixed for all compilations or has the potential to be program specific.
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146 #define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
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149 /* Save the status and WREG registers first, as these will get modified \
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150 by the operations below. */ \
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151 MOVFF WREG, PREINC1 \
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152 MOVFF STATUS, PREINC1 \
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153 /* Save the INTCON register with the appropriate bits forced if \
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154 necessary - as described above. */ \
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155 MOVFF INTCON, WREG \
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156 IORLW ucForcedInterruptFlags \
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157 MOVFF WREG, PREINC1 \
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160 portDISABLE_INTERRUPTS(); \
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163 /* Store the necessary registers to the stack. */ \
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164 MOVFF BSR, PREINC1 \
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165 MOVFF FSR2L, PREINC1 \
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166 MOVFF FSR2H, PREINC1 \
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167 MOVFF FSR0L, PREINC1 \
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168 MOVFF FSR0H, PREINC1 \
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169 MOVFF TABLAT, PREINC1 \
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170 MOVFF TBLPTRU, PREINC1 \
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171 MOVFF TBLPTRH, PREINC1 \
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172 MOVFF TBLPTRL, PREINC1 \
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173 MOVFF PRODH, PREINC1 \
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174 MOVFF PRODL, PREINC1 \
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175 MOVFF PCLATU, PREINC1 \
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176 MOVFF PCLATH, PREINC1 \
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177 /* Store the .tempdata and MATH_DATA areas as described above. */ \
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180 MOVFF POSTINC0, PREINC1 \
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181 MOVFF POSTINC0, PREINC1 \
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182 MOVFF POSTINC0, PREINC1 \
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183 MOVFF POSTINC0, PREINC1 \
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184 MOVFF POSTINC0, PREINC1 \
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185 MOVFF POSTINC0, PREINC1 \
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186 MOVFF POSTINC0, PREINC1 \
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187 MOVFF POSTINC0, PREINC1 \
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188 MOVFF POSTINC0, PREINC1 \
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189 MOVFF POSTINC0, PREINC1 \
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190 MOVFF POSTINC0, PREINC1 \
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191 MOVFF POSTINC0, PREINC1 \
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192 MOVFF POSTINC0, PREINC1 \
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193 MOVFF POSTINC0, PREINC1 \
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194 MOVFF POSTINC0, PREINC1 \
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195 MOVFF POSTINC0, PREINC1 \
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196 MOVFF POSTINC0, PREINC1 \
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197 MOVFF POSTINC0, PREINC1 \
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198 MOVFF POSTINC0, PREINC1 \
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199 MOVFF INDF0, PREINC1 \
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200 MOVFF FSR0L, PREINC1 \
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201 MOVFF FSR0H, PREINC1 \
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202 /* Store the hardware stack pointer in a temp register before we \
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204 MOVFF STKPTR, FSR0L \
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207 /* Store each address from the hardware stack. */ \
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208 while( STKPTR > ( uint8_t ) 0 ) \
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211 MOVFF TOSL, PREINC1 \
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212 MOVFF TOSH, PREINC1 \
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213 MOVFF TOSU, PREINC1 \
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219 /* Store the number of addresses on the hardware stack (from the \
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220 temporary register). */ \
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221 MOVFF FSR0L, PREINC1 \
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222 MOVF PREINC1, 1, 0 \
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225 /* Save the new top of the software stack in the TCB. */ \
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227 MOVFF pxCurrentTCB, FSR0L \
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228 MOVFF pxCurrentTCB + 1, FSR0H \
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229 MOVFF FSR1L, POSTINC0 \
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230 MOVFF FSR1H, POSTINC0 \
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233 /*-----------------------------------------------------------*/
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236 * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
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239 #define portRESTORE_CONTEXT() \
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242 /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
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243 MOVFF pxCurrentTCB, FSR0L \
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244 MOVFF pxCurrentTCB + 1, FSR0H \
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246 /* De-reference FSR0 to set the address it holds into FSR1. \
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247 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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248 MOVFF POSTINC0, FSR1L \
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249 MOVFF POSTINC0, FSR1H \
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251 /* How many return addresses are there on the hardware stack? Discard \
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252 the first byte as we are pointing to the next free space. */ \
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253 MOVFF POSTDEC1, FSR0L \
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254 MOVFF POSTDEC1, FSR0L \
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257 /* Fill the hardware stack from our software stack. */ \
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260 while( STKPTR < FSR0L ) \
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264 MOVF POSTDEC1, 0, 0 \
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266 MOVF POSTDEC1, 0, 0 \
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268 MOVF POSTDEC1, 0, 0 \
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274 /* Restore the .tmpdata and MATH_DATA memory. */ \
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275 MOVFF POSTDEC1, FSR0H \
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276 MOVFF POSTDEC1, FSR0L \
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277 MOVFF POSTDEC1, POSTDEC0 \
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278 MOVFF POSTDEC1, POSTDEC0 \
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279 MOVFF POSTDEC1, POSTDEC0 \
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280 MOVFF POSTDEC1, POSTDEC0 \
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281 MOVFF POSTDEC1, POSTDEC0 \
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282 MOVFF POSTDEC1, POSTDEC0 \
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283 MOVFF POSTDEC1, POSTDEC0 \
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284 MOVFF POSTDEC1, POSTDEC0 \
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285 MOVFF POSTDEC1, POSTDEC0 \
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286 MOVFF POSTDEC1, POSTDEC0 \
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287 MOVFF POSTDEC1, POSTDEC0 \
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288 MOVFF POSTDEC1, POSTDEC0 \
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289 MOVFF POSTDEC1, POSTDEC0 \
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290 MOVFF POSTDEC1, POSTDEC0 \
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291 MOVFF POSTDEC1, POSTDEC0 \
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292 MOVFF POSTDEC1, POSTDEC0 \
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293 MOVFF POSTDEC1, POSTDEC0 \
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294 MOVFF POSTDEC1, POSTDEC0 \
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295 MOVFF POSTDEC1, POSTDEC0 \
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296 MOVFF POSTDEC1, INDF0 \
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297 /* Restore the other registers forming the tasks context. */ \
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298 MOVFF POSTDEC1, PCLATH \
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299 MOVFF POSTDEC1, PCLATU \
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300 MOVFF POSTDEC1, PRODL \
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301 MOVFF POSTDEC1, PRODH \
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302 MOVFF POSTDEC1, TBLPTRL \
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303 MOVFF POSTDEC1, TBLPTRH \
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304 MOVFF POSTDEC1, TBLPTRU \
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305 MOVFF POSTDEC1, TABLAT \
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306 MOVFF POSTDEC1, FSR0H \
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307 MOVFF POSTDEC1, FSR0L \
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308 MOVFF POSTDEC1, FSR2H \
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309 MOVFF POSTDEC1, FSR2L \
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310 MOVFF POSTDEC1, BSR \
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311 /* The next byte is the INTCON register. Read this into WREG as some \
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312 manipulation is required. */ \
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313 MOVFF POSTDEC1, WREG \
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316 /* From the INTCON register, only the interrupt enable bits form part \
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317 of the tasks context. It is perfectly legitimate for another task to \
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318 have modified any other bits. We therefore only restore the top two bits. \
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320 if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
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323 MOVFF POSTDEC1, STATUS \
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324 MOVFF POSTDEC1, WREG \
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325 /* Return enabling interrupts. */ \
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332 MOVFF POSTDEC1, STATUS \
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333 MOVFF POSTDEC1, WREG \
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334 /* Return without effecting interrupts. The context may have \
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335 been saved from a critical region. */ \
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340 /*-----------------------------------------------------------*/
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343 * See header file for description.
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345 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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347 uint32_t ulAddress;
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350 /* Place a few bytes of known values on the bottom of the stack.
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351 This is just useful for debugging. */
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353 *pxTopOfStack = 0x11;
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355 *pxTopOfStack = 0x22;
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357 *pxTopOfStack = 0x33;
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361 /* Simulate how the stack would look after a call to vPortYield() generated
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364 First store the function parameters. This is where the task will expect to
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365 find them when it starts running. */
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366 ulAddress = ( uint32_t ) pvParameters;
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367 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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371 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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374 /* Next we just leave a space. When a context is saved the stack pointer
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375 is incremented before it is used so as not to corrupt whatever the stack
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376 pointer is actually pointing to. This is especially necessary during
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377 function epilogue code generated by the compiler. */
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378 *pxTopOfStack = 0x44;
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381 /* Next are all the registers that form part of the task context. */
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383 *pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
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386 *pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
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389 /* INTCON is saved with interrupts enabled. */
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390 *pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
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393 *pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
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396 *pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
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399 *pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
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402 *pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
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405 *pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
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408 *pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
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411 *pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
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414 *pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
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417 *pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
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420 *pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
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423 *pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
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426 *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
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429 *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
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432 /* Next the .tmpdata and MATH_DATA sections. */
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433 for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
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435 *pxTopOfStack = ( StackType_t ) ucBlock;
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439 /* Store the top of the global data section. */
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440 *pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
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443 *pxTopOfStack = ( StackType_t ) 0x00; /* High. */
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446 /* The only function return address so far is the address of the
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448 ulAddress = ( uint32_t ) pxCode;
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451 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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456 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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460 /* TOS even higher. */
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461 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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464 /* Store the number of return addresses on the hardware stack - so far only
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465 the address of the task entry point. */
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466 *pxTopOfStack = ( StackType_t ) 1;
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469 return pxTopOfStack;
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471 /*-----------------------------------------------------------*/
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473 BaseType_t xPortStartScheduler( void )
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475 /* Setup a timer for the tick ISR is using the preemptive scheduler. */
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476 prvSetupTimerInterrupt();
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478 /* Restore the context of the first task to run. */
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479 portRESTORE_CONTEXT();
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481 /* Should not get here. Use the function name to stop compiler warnings. */
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482 ( void ) prvLowInterrupt;
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483 ( void ) prvTickISR;
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487 /*-----------------------------------------------------------*/
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489 void vPortEndScheduler( void )
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491 /* It is unlikely that the scheduler for the PIC port will get stopped
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492 once running. If required disable the tick interrupt here, then return
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493 to xPortStartScheduler(). */
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495 /*-----------------------------------------------------------*/
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498 * Manual context switch. This is similar to the tick context switch,
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499 * but does not increment the tick count. It must be identical to the
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500 * tick context switch in how it stores the stack of a task.
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502 void vPortYield( void )
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504 /* This can get called with interrupts either enabled or disabled. We
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505 will save the INTCON register with the interrupt enable bits unmodified. */
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506 portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
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508 /* Switch to the highest priority task that is ready to run. */
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509 vTaskSwitchContext();
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511 /* Start executing the task we have just switched to. */
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512 portRESTORE_CONTEXT();
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514 /*-----------------------------------------------------------*/
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517 * Vector for ISR. Nothing here must alter any registers!
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519 #pragma code high_vector=0x08
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520 static void prvLowInterrupt( void )
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522 /* Was the interrupt the tick? */
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523 if( PIR1bits.CCP1IF )
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530 /* Was the interrupt a byte being received? */
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531 if( PIR1bits.RCIF )
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538 /* Was the interrupt the Tx register becoming empty? */
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539 if( PIR1bits.TXIF )
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541 if( PIE1bits.TXIE )
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551 /*-----------------------------------------------------------*/
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554 * ISR for the tick.
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555 * This increments the tick count and, if using the preemptive scheduler,
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556 * performs a context switch. This must be identical to the manual
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557 * context switch in how it stores the context of a task.
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559 static void prvTickISR( void )
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561 /* Interrupts must have been enabled for the ISR to fire, so we have to
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562 save the context with interrupts enabled. */
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563 portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
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564 PIR1bits.CCP1IF = 0;
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566 /* Maintain the tick count. */
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567 if( xTaskIncrementTick() != pdFALSE )
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569 /* Switch to the highest priority task that is ready to run. */
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570 vTaskSwitchContext();
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573 portRESTORE_CONTEXT();
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575 /*-----------------------------------------------------------*/
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578 * Setup a timer for a regular tick.
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580 static void prvSetupTimerInterrupt( void )
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582 const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
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583 uint32_t ulCompareValue;
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586 /* Interrupts are disabled when this function is called.
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588 Setup CCP1 to provide the tick interrupt using a compare match on timer
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591 Clear the time count then setup timer. */
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592 TMR1H = ( uint8_t ) 0x00;
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593 TMR1L = ( uint8_t ) 0x00;
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595 /* Set the compare match value. */
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596 ulCompareValue = ulConstCompareValue;
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597 CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
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598 ulCompareValue >>= ( uint32_t ) 8;
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599 CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
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601 CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
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602 CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
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603 CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
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604 CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
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605 PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
\r
607 /* We are only going to use the global interrupt bit, so set the peripheral
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609 INTCONbits.GIEL = portBIT_SET;
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611 /* Provided library function for setting up the timer that will produce the
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613 OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
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projects / freertos / blob