2 FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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32 >>>NOTE<<< The modification to the GPL is included to allow you to
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33 distribute a combined work that includes FreeRTOS without being obliged to
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34 provide the source code for proprietary components outside of the FreeRTOS
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35 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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36 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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37 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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38 more details. You should have received a copy of the GNU General Public
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39 License and the FreeRTOS license exception along with FreeRTOS; if not it
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40 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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41 by writing to Richard Barry, contact details for whom are available on the
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46 ***************************************************************************
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48 * Having a problem? Start by reading the FAQ "My application does *
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49 * not run, what could be wrong?" *
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51 * http://www.FreeRTOS.org/FAQHelp.html *
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53 ***************************************************************************
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56 http://www.FreeRTOS.org - Documentation, training, latest versions, license
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57 and contact details.
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59 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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60 including FreeRTOS+Trace - an indispensable productivity tool.
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62 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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63 the code with commercial support, indemnification, and middleware, under
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64 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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65 provide a safety engineered and independently SIL3 certified version under
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66 the SafeRTOS brand: http://www.SafeRTOS.com.
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70 Changes between V1.2.4 and V1.2.5
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72 + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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73 interrupt flag setting. Using the two bits defined within
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74 portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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75 before the test was performed.
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79 + Set the interrupt vector address to 0x08. Previously it was at the
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80 incorrect address for compatibility mode of 0x18.
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84 + PCLATU and PCLATH are now saved as part of the context. This allows
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85 function pointers to be used within tasks. Thanks to Javier Espeche
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86 for the enhancement.
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90 + TABLAT is now saved as part of the task context.
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94 + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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95 value and does not write to the register.
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98 /* Scheduler include files. */
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99 #include "FreeRTOS.h"
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102 /* MPLAB library include file. */
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103 #include "timers.h"
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105 /*-----------------------------------------------------------
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106 * Implementation of functions defined in portable.h for the PIC port.
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107 *----------------------------------------------------------*/
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109 /* Hardware setup for tick. */
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110 #define portTIMER_FOSC_SCALE ( ( unsigned long ) 4 )
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112 /* Initial interrupt enable state for newly created tasks. This value is
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113 copied into INTCON when a task switches in for the first time. */
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114 #define portINITAL_INTERRUPT_STATE 0xc0
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116 /* Just the bit within INTCON for the global interrupt flag. */
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117 #define portGLOBAL_INTERRUPT_FLAG 0x80
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119 /* Constant used for context switch macro when we require the interrupt
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120 enable state to be unchanged when the interrupted task is switched back in. */
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121 #define portINTERRUPTS_UNCHANGED 0x00
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123 /* Some memory areas get saved as part of the task context. These memory
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124 area's get used by the compiler for temporary storage, especially when
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125 performing mathematical operations, or when using 32bit data types. This
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126 constant defines the size of memory area which must be saved. */
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127 #define portCOMPILER_MANAGED_MEMORY_SIZE ( ( unsigned char ) 0x13 )
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129 /* We require the address of the pxCurrentTCB variable, but don't want to know
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130 any details of its type. */
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131 typedef void tskTCB;
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132 extern volatile tskTCB * volatile pxCurrentTCB;
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134 /* IO port constants. */
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135 #define portBIT_SET ( ( unsigned char ) 1 )
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136 #define portBIT_CLEAR ( ( unsigned char ) 0 )
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139 * The serial port ISR's are defined in serial.c, but are called from portable
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140 * as they use the same vector as the tick ISR.
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142 void vSerialTxISR( void );
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143 void vSerialRxISR( void );
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146 * Perform hardware setup to enable ticks.
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148 static void prvSetupTimerInterrupt( void );
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151 * ISR to maintain the tick, and perform tick context switches if the
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152 * preemptive scheduler is being used.
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154 static void prvTickISR( void );
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157 * ISR placed on the low priority vector. This calls the appropriate ISR for
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158 * the actual interrupt.
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160 static void prvLowInterrupt( void );
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163 * Macro that pushes all the registers that make up the context of a task onto
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164 * the stack, then saves the new top of stack into the TCB.
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166 * If this is called from an ISR then the interrupt enable bits must have been
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167 * set for the ISR to ever get called. Therefore we want to save the INTCON
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168 * register with the enable bits forced to be set - and ucForcedInterruptFlags
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169 * must contain these bit settings. This means the interrupts will again be
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170 * enabled when the interrupted task is switched back in.
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172 * If this is called from a manual context switch (i.e. from a call to yield),
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173 * then we want to save the INTCON so it is restored with its current state,
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174 * and ucForcedInterruptFlags must be 0. This allows a yield from within
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175 * a critical section.
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177 * The compiler uses some locations at the bottom of the memory for temporary
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178 * storage during math and other computations. This is especially true if
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179 * 32bit data types are utilised (as they are by the scheduler). The .tmpdata
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180 * and MATH_DATA sections have to be stored in there entirety as part of a task
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181 * context. This macro stores from data address 0x00 to
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182 * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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183 * applications but you should check the map file for your project to ensure
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184 * this is sufficient for your needs. It is not clear whether this size is
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185 * fixed for all compilations or has the potential to be program specific.
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187 #define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
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190 /* Save the status and WREG registers first, as these will get modified \
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191 by the operations below. */ \
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192 MOVFF WREG, PREINC1 \
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193 MOVFF STATUS, PREINC1 \
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194 /* Save the INTCON register with the appropriate bits forced if \
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195 necessary - as described above. */ \
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196 MOVFF INTCON, WREG \
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197 IORLW ucForcedInterruptFlags \
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198 MOVFF WREG, PREINC1 \
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201 portDISABLE_INTERRUPTS(); \
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204 /* Store the necessary registers to the stack. */ \
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205 MOVFF BSR, PREINC1 \
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206 MOVFF FSR2L, PREINC1 \
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207 MOVFF FSR2H, PREINC1 \
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208 MOVFF FSR0L, PREINC1 \
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209 MOVFF FSR0H, PREINC1 \
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210 MOVFF TABLAT, PREINC1 \
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211 MOVFF TBLPTRU, PREINC1 \
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212 MOVFF TBLPTRH, PREINC1 \
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213 MOVFF TBLPTRL, PREINC1 \
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214 MOVFF PRODH, PREINC1 \
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215 MOVFF PRODL, PREINC1 \
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216 MOVFF PCLATU, PREINC1 \
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217 MOVFF PCLATH, PREINC1 \
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218 /* Store the .tempdata and MATH_DATA areas as described above. */ \
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221 MOVFF POSTINC0, PREINC1 \
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222 MOVFF POSTINC0, PREINC1 \
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223 MOVFF POSTINC0, PREINC1 \
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224 MOVFF POSTINC0, PREINC1 \
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225 MOVFF POSTINC0, PREINC1 \
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226 MOVFF POSTINC0, PREINC1 \
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227 MOVFF POSTINC0, PREINC1 \
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228 MOVFF POSTINC0, PREINC1 \
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229 MOVFF POSTINC0, PREINC1 \
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230 MOVFF POSTINC0, PREINC1 \
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231 MOVFF POSTINC0, PREINC1 \
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232 MOVFF POSTINC0, PREINC1 \
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233 MOVFF POSTINC0, PREINC1 \
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234 MOVFF POSTINC0, PREINC1 \
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235 MOVFF POSTINC0, PREINC1 \
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236 MOVFF POSTINC0, PREINC1 \
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237 MOVFF POSTINC0, PREINC1 \
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238 MOVFF POSTINC0, PREINC1 \
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239 MOVFF POSTINC0, PREINC1 \
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240 MOVFF INDF0, PREINC1 \
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241 MOVFF FSR0L, PREINC1 \
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242 MOVFF FSR0H, PREINC1 \
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243 /* Store the hardware stack pointer in a temp register before we \
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245 MOVFF STKPTR, FSR0L \
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248 /* Store each address from the hardware stack. */ \
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249 while( STKPTR > ( unsigned char ) 0 ) \
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252 MOVFF TOSL, PREINC1 \
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253 MOVFF TOSH, PREINC1 \
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254 MOVFF TOSU, PREINC1 \
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260 /* Store the number of addresses on the hardware stack (from the \
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261 temporary register). */ \
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262 MOVFF FSR0L, PREINC1 \
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263 MOVF PREINC1, 1, 0 \
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266 /* Save the new top of the software stack in the TCB. */ \
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268 MOVFF pxCurrentTCB, FSR0L \
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269 MOVFF pxCurrentTCB + 1, FSR0H \
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270 MOVFF FSR1L, POSTINC0 \
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271 MOVFF FSR1H, POSTINC0 \
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274 /*-----------------------------------------------------------*/
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277 * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
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280 #define portRESTORE_CONTEXT() \
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283 /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
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284 MOVFF pxCurrentTCB, FSR0L \
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285 MOVFF pxCurrentTCB + 1, FSR0H \
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287 /* De-reference FSR0 to set the address it holds into FSR1. \
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288 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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289 MOVFF POSTINC0, FSR1L \
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290 MOVFF POSTINC0, FSR1H \
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292 /* How many return addresses are there on the hardware stack? Discard \
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293 the first byte as we are pointing to the next free space. */ \
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294 MOVFF POSTDEC1, FSR0L \
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295 MOVFF POSTDEC1, FSR0L \
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298 /* Fill the hardware stack from our software stack. */ \
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301 while( STKPTR < FSR0L ) \
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305 MOVF POSTDEC1, 0, 0 \
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307 MOVF POSTDEC1, 0, 0 \
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309 MOVF POSTDEC1, 0, 0 \
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315 /* Restore the .tmpdata and MATH_DATA memory. */ \
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316 MOVFF POSTDEC1, FSR0H \
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317 MOVFF POSTDEC1, FSR0L \
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318 MOVFF POSTDEC1, POSTDEC0 \
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319 MOVFF POSTDEC1, POSTDEC0 \
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320 MOVFF POSTDEC1, POSTDEC0 \
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321 MOVFF POSTDEC1, POSTDEC0 \
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322 MOVFF POSTDEC1, POSTDEC0 \
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323 MOVFF POSTDEC1, POSTDEC0 \
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324 MOVFF POSTDEC1, POSTDEC0 \
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325 MOVFF POSTDEC1, POSTDEC0 \
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326 MOVFF POSTDEC1, POSTDEC0 \
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327 MOVFF POSTDEC1, POSTDEC0 \
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328 MOVFF POSTDEC1, POSTDEC0 \
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329 MOVFF POSTDEC1, POSTDEC0 \
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330 MOVFF POSTDEC1, POSTDEC0 \
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331 MOVFF POSTDEC1, POSTDEC0 \
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332 MOVFF POSTDEC1, POSTDEC0 \
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333 MOVFF POSTDEC1, POSTDEC0 \
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334 MOVFF POSTDEC1, POSTDEC0 \
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335 MOVFF POSTDEC1, POSTDEC0 \
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336 MOVFF POSTDEC1, POSTDEC0 \
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337 MOVFF POSTDEC1, INDF0 \
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338 /* Restore the other registers forming the tasks context. */ \
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339 MOVFF POSTDEC1, PCLATH \
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340 MOVFF POSTDEC1, PCLATU \
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341 MOVFF POSTDEC1, PRODL \
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342 MOVFF POSTDEC1, PRODH \
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343 MOVFF POSTDEC1, TBLPTRL \
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344 MOVFF POSTDEC1, TBLPTRH \
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345 MOVFF POSTDEC1, TBLPTRU \
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346 MOVFF POSTDEC1, TABLAT \
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347 MOVFF POSTDEC1, FSR0H \
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348 MOVFF POSTDEC1, FSR0L \
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349 MOVFF POSTDEC1, FSR2H \
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350 MOVFF POSTDEC1, FSR2L \
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351 MOVFF POSTDEC1, BSR \
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352 /* The next byte is the INTCON register. Read this into WREG as some \
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353 manipulation is required. */ \
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354 MOVFF POSTDEC1, WREG \
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357 /* From the INTCON register, only the interrupt enable bits form part \
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358 of the tasks context. It is perfectly legitimate for another task to \
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359 have modified any other bits. We therefore only restore the top two bits. \
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361 if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
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364 MOVFF POSTDEC1, STATUS \
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365 MOVFF POSTDEC1, WREG \
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366 /* Return enabling interrupts. */ \
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373 MOVFF POSTDEC1, STATUS \
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374 MOVFF POSTDEC1, WREG \
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375 /* Return without effecting interrupts. The context may have \
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376 been saved from a critical region. */ \
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381 /*-----------------------------------------------------------*/
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384 * See header file for description.
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386 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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388 unsigned long ulAddress;
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389 unsigned char ucBlock;
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391 /* Place a few bytes of known values on the bottom of the stack.
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392 This is just useful for debugging. */
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394 *pxTopOfStack = 0x11;
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396 *pxTopOfStack = 0x22;
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398 *pxTopOfStack = 0x33;
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402 /* Simulate how the stack would look after a call to vPortYield() generated
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405 First store the function parameters. This is where the task will expect to
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406 find them when it starts running. */
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407 ulAddress = ( unsigned long ) pvParameters;
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408 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
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412 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
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415 /* Next we just leave a space. When a context is saved the stack pointer
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416 is incremented before it is used so as not to corrupt whatever the stack
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417 pointer is actually pointing to. This is especially necessary during
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418 function epilogue code generated by the compiler. */
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419 *pxTopOfStack = 0x44;
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422 /* Next are all the registers that form part of the task context. */
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424 *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* WREG. */
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427 *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; /* Status. */
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430 /* INTCON is saved with interrupts enabled. */
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431 *pxTopOfStack = ( portSTACK_TYPE ) portINITAL_INTERRUPT_STATE; /* INTCON */
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434 *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* BSR. */
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437 *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* FSR2L. */
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440 *pxTopOfStack = ( portSTACK_TYPE ) 0x33; /* FSR2H. */
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443 *pxTopOfStack = ( portSTACK_TYPE ) 0x44; /* FSR0L. */
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446 *pxTopOfStack = ( portSTACK_TYPE ) 0x55; /* FSR0H. */
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449 *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* TABLAT. */
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452 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */
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455 *pxTopOfStack = ( portSTACK_TYPE ) 0x88; /* TBLPTRUH. */
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458 *pxTopOfStack = ( portSTACK_TYPE ) 0x99; /* TBLPTRUL. */
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461 *pxTopOfStack = ( portSTACK_TYPE ) 0xaa; /* PRODH. */
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464 *pxTopOfStack = ( portSTACK_TYPE ) 0xbb; /* PRODL. */
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467 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATU. */
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470 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATH. */
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473 /* Next the .tmpdata and MATH_DATA sections. */
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474 for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
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476 *pxTopOfStack = ( portSTACK_TYPE ) ucBlock;
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480 /* Store the top of the global data section. */
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481 *pxTopOfStack = ( portSTACK_TYPE ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
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484 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* High. */
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487 /* The only function return address so far is the address of the
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489 ulAddress = ( unsigned long ) pxCode;
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492 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
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497 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
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501 /* TOS even higher. */
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502 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
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505 /* Store the number of return addresses on the hardware stack - so far only
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506 the address of the task entry point. */
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507 *pxTopOfStack = ( portSTACK_TYPE ) 1;
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510 return pxTopOfStack;
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512 /*-----------------------------------------------------------*/
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514 portBASE_TYPE xPortStartScheduler( void )
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516 /* Setup a timer for the tick ISR is using the preemptive scheduler. */
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517 prvSetupTimerInterrupt();
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519 /* Restore the context of the first task to run. */
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520 portRESTORE_CONTEXT();
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522 /* Should not get here. Use the function name to stop compiler warnings. */
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523 ( void ) prvLowInterrupt;
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524 ( void ) prvTickISR;
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528 /*-----------------------------------------------------------*/
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530 void vPortEndScheduler( void )
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532 /* It is unlikely that the scheduler for the PIC port will get stopped
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533 once running. If required disable the tick interrupt here, then return
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534 to xPortStartScheduler(). */
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536 /*-----------------------------------------------------------*/
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539 * Manual context switch. This is similar to the tick context switch,
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540 * but does not increment the tick count. It must be identical to the
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541 * tick context switch in how it stores the stack of a task.
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543 void vPortYield( void )
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545 /* This can get called with interrupts either enabled or disabled. We
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546 will save the INTCON register with the interrupt enable bits unmodified. */
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547 portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
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549 /* Switch to the highest priority task that is ready to run. */
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550 vTaskSwitchContext();
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552 /* Start executing the task we have just switched to. */
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553 portRESTORE_CONTEXT();
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555 /*-----------------------------------------------------------*/
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558 * Vector for ISR. Nothing here must alter any registers!
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560 #pragma code high_vector=0x08
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561 static void prvLowInterrupt( void )
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563 /* Was the interrupt the tick? */
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564 if( PIR1bits.CCP1IF )
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571 /* Was the interrupt a byte being received? */
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572 if( PIR1bits.RCIF )
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579 /* Was the interrupt the Tx register becoming empty? */
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580 if( PIR1bits.TXIF )
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582 if( PIE1bits.TXIE )
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592 /*-----------------------------------------------------------*/
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595 * ISR for the tick.
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596 * This increments the tick count and, if using the preemptive scheduler,
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597 * performs a context switch. This must be identical to the manual
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598 * context switch in how it stores the context of a task.
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600 static void prvTickISR( void )
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602 /* Interrupts must have been enabled for the ISR to fire, so we have to
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603 save the context with interrupts enabled. */
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604 portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
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605 PIR1bits.CCP1IF = 0;
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607 /* Maintain the tick count. */
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608 vTaskIncrementTick();
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610 #if configUSE_PREEMPTION == 1
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612 /* Switch to the highest priority task that is ready to run. */
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613 vTaskSwitchContext();
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617 portRESTORE_CONTEXT();
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619 /*-----------------------------------------------------------*/
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622 * Setup a timer for a regular tick.
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624 static void prvSetupTimerInterrupt( void )
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626 const unsigned long ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
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627 unsigned long ulCompareValue;
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628 unsigned char ucByte;
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630 /* Interrupts are disabled when this function is called.
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632 Setup CCP1 to provide the tick interrupt using a compare match on timer
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635 Clear the time count then setup timer. */
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636 TMR1H = ( unsigned char ) 0x00;
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637 TMR1L = ( unsigned char ) 0x00;
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639 /* Set the compare match value. */
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640 ulCompareValue = ulConstCompareValue;
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641 CCPR1L = ( unsigned char ) ( ulCompareValue & ( unsigned long ) 0xff );
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642 ulCompareValue >>= ( unsigned long ) 8;
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643 CCPR1H = ( unsigned char ) ( ulCompareValue & ( unsigned long ) 0xff );
\r
645 CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
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646 CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
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647 CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
\r
648 CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
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649 PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
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651 /* We are only going to use the global interrupt bit, so set the peripheral
\r
653 INTCONbits.GIEL = portBIT_SET;
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655 /* Provided library function for setting up the timer that will produce the
\r
657 OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
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projects / freertos / blob