2 * FreeRTOS Kernel V10.0.1
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 #include "FreeRTOSConfig.h"
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30 #define portCONTEXT_SIZE 160
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31 #define portEPC_STACK_LOCATION 152
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32 #define portSTATUS_STACK_LOCATION 156
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33 #define portFPCSR_STACK_LOCATION 0
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34 #define portTASK_HAS_FPU_STACK_LOCATION 0
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35 #define portFPU_CONTEXT_SIZE 264
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37 /******************************************************************/
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38 .macro portSAVE_FPU_REGS offset, base
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39 /* Macro to assist with saving just the FPU registers to the
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40 * specified address and base offset,
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41 * offset is a constant, base is the base pointer register */
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43 sdc1 $f31, \offset + 248(\base)
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44 sdc1 $f30, \offset + 240(\base)
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45 sdc1 $f29, \offset + 232(\base)
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46 sdc1 $f28, \offset + 224(\base)
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47 sdc1 $f27, \offset + 216(\base)
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48 sdc1 $f26, \offset + 208(\base)
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49 sdc1 $f25, \offset + 200(\base)
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50 sdc1 $f24, \offset + 192(\base)
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51 sdc1 $f23, \offset + 184(\base)
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52 sdc1 $f22, \offset + 176(\base)
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53 sdc1 $f21, \offset + 168(\base)
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54 sdc1 $f20, \offset + 160(\base)
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55 sdc1 $f19, \offset + 152(\base)
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56 sdc1 $f18, \offset + 144(\base)
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57 sdc1 $f17, \offset + 136(\base)
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58 sdc1 $f16, \offset + 128(\base)
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59 sdc1 $f15, \offset + 120(\base)
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60 sdc1 $f14, \offset + 112(\base)
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61 sdc1 $f13, \offset + 104(\base)
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62 sdc1 $f12, \offset + 96(\base)
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63 sdc1 $f11, \offset + 88(\base)
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64 sdc1 $f10, \offset + 80(\base)
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65 sdc1 $f9, \offset + 72(\base)
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66 sdc1 $f8, \offset + 64(\base)
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67 sdc1 $f7, \offset + 56(\base)
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68 sdc1 $f6, \offset + 48(\base)
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69 sdc1 $f5, \offset + 40(\base)
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70 sdc1 $f4, \offset + 32(\base)
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71 sdc1 $f3, \offset + 24(\base)
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72 sdc1 $f2, \offset + 16(\base)
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73 sdc1 $f1, \offset + 8(\base)
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74 sdc1 $f0, \offset + 0(\base)
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78 /******************************************************************/
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79 .macro portLOAD_FPU_REGS offset, base
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80 /* Macro to assist with loading just the FPU registers from the
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81 * specified address and base offset, offset is a constant,
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82 * base is the base pointer register */
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84 ldc1 $f0, \offset + 0(\base)
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85 ldc1 $f1, \offset + 8(\base)
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86 ldc1 $f2, \offset + 16(\base)
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87 ldc1 $f3, \offset + 24(\base)
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88 ldc1 $f4, \offset + 32(\base)
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89 ldc1 $f5, \offset + 40(\base)
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90 ldc1 $f6, \offset + 48(\base)
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91 ldc1 $f7, \offset + 56(\base)
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92 ldc1 $f8, \offset + 64(\base)
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93 ldc1 $f9, \offset + 72(\base)
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94 ldc1 $f10, \offset + 80(\base)
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95 ldc1 $f11, \offset + 88(\base)
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96 ldc1 $f12, \offset + 96(\base)
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97 ldc1 $f13, \offset + 104(\base)
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98 ldc1 $f14, \offset + 112(\base)
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99 ldc1 $f15, \offset + 120(\base)
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100 ldc1 $f16, \offset + 128(\base)
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101 ldc1 $f17, \offset + 136(\base)
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102 ldc1 $f18, \offset + 144(\base)
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103 ldc1 $f19, \offset + 152(\base)
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104 ldc1 $f20, \offset + 160(\base)
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105 ldc1 $f21, \offset + 168(\base)
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106 ldc1 $f22, \offset + 176(\base)
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107 ldc1 $f23, \offset + 184(\base)
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108 ldc1 $f24, \offset + 192(\base)
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109 ldc1 $f25, \offset + 200(\base)
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110 ldc1 $f26, \offset + 208(\base)
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111 ldc1 $f27, \offset + 216(\base)
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112 ldc1 $f28, \offset + 224(\base)
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113 ldc1 $f29, \offset + 232(\base)
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114 ldc1 $f30, \offset + 240(\base)
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115 ldc1 $f31, \offset + 248(\base)
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119 /******************************************************************/
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120 .macro portSAVE_CONTEXT
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122 /* Make room for the context. First save the current status so it can be
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123 manipulated, and the cause and EPC registers so their original values are
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125 mfc0 k0, _CP0_CAUSE
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126 addiu sp, sp, -portCONTEXT_SIZE
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128 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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129 /* Test if we are already using the system stack. Only tasks may use the
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130 FPU so if we are already in a nested interrupt then the FPU context does
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131 not require saving. */
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132 la k1, uxInterruptNesting
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137 /* Test if the current task needs the FPU context saving. */
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138 la k1, ulTaskHasFPUContext
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143 /* Adjust the stack to account for the additional FPU context.*/
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144 addiu sp, sp, -portFPU_CONTEXT_SIZE
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147 /* Save the ulTaskHasFPUContext flag. */
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148 sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
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153 mfc0 k1, _CP0_STATUS
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155 /* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
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156 should maintain the values of these registers across the ISR. */
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160 sw k1, portSTATUS_STACK_LOCATION(sp)
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162 /* Prepare to enable interrupts above the current priority. */
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165 srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
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169 /* s5 is used as the frame pointer. */
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172 /* Check the nesting count value. */
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173 la k0, uxInterruptNesting
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176 /* If the nesting count is 0 then swap to the the system stack, otherwise
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177 the system stack is already being used. */
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181 /* Swap to the system stack. */
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182 la sp, xISRStackTop
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185 /* Increment and save the nesting count. */
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189 /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
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192 /* Re-enable interrupts. */
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193 mtc0 k1, _CP0_STATUS
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195 /* Save the context into the space just created. s6 is saved again
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196 here as it now contains the EPC value. No other s registers need be
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216 sw s6, portEPC_STACK_LOCATION(s5)
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219 /* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a
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220 scratch register. */
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236 /* Save the DSP Control register */
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240 /* ac0 is done separately to match the MX port. */
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246 /* Save the FPU context if the nesting count was zero. */
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247 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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248 la s6, uxInterruptNesting
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254 /* Test if the current task needs the FPU context saving. */
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255 lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
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259 /* Save the FPU registers. */
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260 portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
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262 /* Save the FPU status register */
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264 sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
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269 /* Update the task stack pointer value if nesting is zero. */
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270 la s6, uxInterruptNesting
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276 /* Save the stack pointer. */
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277 la s6, uxSavedTaskStackPointer
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282 /******************************************************************/
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283 .macro portRESTORE_CONTEXT
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285 /* Restore the stack pointer from the TCB. This is only done if the
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286 nesting count is 1. */
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287 la s6, uxInterruptNesting
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292 la s6, uxSavedTaskStackPointer
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295 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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296 /* Restore the FPU context if required. */
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297 lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
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301 /* Restore the FPU registers. */
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302 portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
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304 /* Restore the FPU status register. */
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305 lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
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311 /* Restore the context. */
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327 /* Restore DSPControl. */
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337 /* s6 is loaded as it was used as a scratch register and therefore saved
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338 as part of the interrupt context. */
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360 /* Protect access to the k registers, and others. */
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364 /* Decrement the nesting count. */
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365 la k0, uxInterruptNesting
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370 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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371 /* If the nesting count is now zero then the FPU context may be restored. */
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375 /* Restore the value of ulTaskHasFPUContext */
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376 la k0, ulTaskHasFPUContext
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380 /* If the task does not have an FPU context then adjust the stack normally. */
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384 /* Restore the STATUS and EPC registers */
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385 lw k0, portSTATUS_STACK_LOCATION(s5)
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386 lw k1, portEPC_STACK_LOCATION(s5)
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388 /* Leave the stack in its original state. First load sp from s5, then
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389 restore s5 from the stack. */
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393 /* Adjust the stack pointer to remove the FPU context */
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394 addiu sp, sp, portFPU_CONTEXT_SIZE
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398 1: /* Restore the STATUS and EPC registers */
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399 lw k0, portSTATUS_STACK_LOCATION(s5)
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400 lw k1, portEPC_STACK_LOCATION(s5)
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402 /* Leave the stack in its original state. First load sp from s5, then
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403 restore s5 from the stack. */
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407 2: /* Adjust the stack pointer */
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408 addiu sp, sp, portCONTEXT_SIZE
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412 /* Restore the frame when there is no hardware FP support. */
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413 lw k0, portSTATUS_STACK_LOCATION(s5)
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414 lw k1, portEPC_STACK_LOCATION(s5)
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416 /* Leave the stack in its original state. First load sp from s5, then
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417 restore s5 from the stack. */
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421 addiu sp, sp, portCONTEXT_SIZE
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423 #endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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425 mtc0 k0, _CP0_STATUS
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