2 FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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71 #include <sys/asm.h>
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72 #include "FreeRTOSConfig.h"
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73 #include "ISR_Support.h"
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76 .extern pxCurrentTCB
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77 .extern vTaskSwitchContext
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78 .extern vPortIncrementTick
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79 .extern xISRStackTop
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80 .extern ulTaskHasFPUContext
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82 .global vPortStartFirstTask
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83 .global vPortYieldISR
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84 .global vPortTickInterruptHandler
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85 .global vPortInitialiseFPSCR
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88 /******************************************************************/
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95 /***************************************************************
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96 * The following is needed to locate the
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97 * vPortTickInterruptHandler function into the correct vector
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98 ***************************************************************/
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99 #ifdef configTICK_INTERRUPT_VECTOR
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100 #if (configTICK_INTERRUPT_VECTOR == _CORE_TIMER_VECTOR)
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101 .equ __vector_dispatch_0, vPortTickInterruptHandler
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102 .global __vector_dispatch_0
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103 .section .vector_0, code, keep
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104 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_1_VECTOR)
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105 .equ __vector_dispatch_4, vPortTickInterruptHandler
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106 .global __vector_dispatch_4
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107 .section .vector_4, code, keep
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108 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_2_VECTOR)
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109 .equ __vector_dispatch_9, vPortTickInterruptHandler
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110 .global __vector_dispatch_9
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111 .section .vector_9, code, keep
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112 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_3_VECTOR)
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113 .equ __vector_dispatch_14, vPortTickInterruptHandler
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114 .global __vector_dispatch_14
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115 .section .vector_14, code, keep
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116 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_4_VECTOR)
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117 .equ __vector_dispatch_19, vPortTickInterruptHandler
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118 .global __vector_dispatch_19
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119 .section .vector_19, code, keep
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120 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_5_VECTOR)
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121 .equ __vector_dispatch_24, vPortTickInterruptHandler
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122 .global __vector_dispatch_24
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123 .section .vector_24, code, keep
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124 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_6_VECTOR)
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125 .equ __vector_dispatch_28, vPortTickInterruptHandler
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126 .global __vector_dispatch_28
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127 .section .vector_28, code, keep
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128 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_7_VECTOR)
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129 .equ __vector_dispatch_32, vPortTickInterruptHandler
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130 .global __vector_dispatch_32
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131 .section .vector_32, code, keep
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132 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_8_VECTOR)
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133 .equ __vector_dispatch_36, vPortTickInterruptHandler
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134 .global __vector_dispatch_36
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135 .section .vector_36, code, keep
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136 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_9_VECTOR)
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137 .equ __vector_dispatch_40, vPortTickInterruptHandler
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138 .global __vector_dispatch_40
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139 .section .vector_40, code, keep
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142 .equ __vector_dispatch_4, vPortTickInterruptHandler
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143 .global __vector_dispatch_4
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144 .section .vector_4, code, keep
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147 .ent vPortTickInterruptHandler
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149 vPortTickInterruptHandler:
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153 jal vPortIncrementTick
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156 portRESTORE_CONTEXT
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158 .end vPortTickInterruptHandler
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160 /******************************************************************/
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164 .section .text, code
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165 .ent vPortStartFirstTask
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167 vPortStartFirstTask:
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169 /* Simply restore the context of the highest priority task that has been
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171 portRESTORE_CONTEXT
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173 .end vPortStartFirstTask
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177 /*******************************************************************/
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183 /***************************************************************
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184 * The following is needed to locate the vPortYieldISR function
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185 * into the correct vector
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186 ***************************************************************/
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187 .equ __vector_dispatch_1, vPortYieldISR
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188 .global __vector_dispatch_1
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189 .section .vector_1, code
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194 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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195 /* Code sequence for FPU support, the context save requires advance
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196 knowledge of the stack frame size and if the current task actually uses the
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199 /* Make room for the context. First save the current status so it can be
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200 manipulated, and the cause and EPC registers so their original values are
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202 la k0, ulTaskHasFPUContext
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205 addiu sp, sp, -portCONTEXT_SIZE /* always reserve space for the context. */
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206 addiu sp, sp, -portFPU_CONTEXT_SIZE /* reserve additional space for the FPU context. */
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208 mfc0 k1, _CP0_STATUS
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210 /* Also save s6 and s5 so they can be used. Any nesting interrupts should
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211 maintain the values of these registers across the ISR. */
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214 sw k1, portSTATUS_STACK_LOCATION(sp)
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215 sw k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
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217 /* Prepare to re-enabled interrupts above the kernel priority. */
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218 ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
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219 ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */
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220 ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
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221 ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
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223 /* s5 is used as the frame pointer. */
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226 /* Swap to the system stack. This is not conditional on the nesting
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227 count as this interrupt is always the lowest priority and therefore
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228 the nesting is always 0. */
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229 la sp, xISRStackTop
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232 /* Set the nesting count. */
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233 la k0, uxInterruptNesting
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237 /* s6 holds the EPC value, this is saved with the rest of the context
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238 after interrupts are enabled. */
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241 /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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242 mtc0 k1, _CP0_STATUS
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244 /* Save the context into the space just created. s6 is saved again
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245 here as it now contains the EPC value. */
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265 sw s6, portEPC_STACK_LOCATION(s5)
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266 /* s5 and s6 has already been saved. */
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274 /* s7 is used as a scratch register as this should always be saved across
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275 nesting interrupts. */
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277 /* Save the AC0, AC1, AC2 and AC3. */
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301 /* Test if FPU context save is required. */
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302 lw s7, portTASK_HAS_FPU_STACK_LOCATION(s5)
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306 /* Save the FPU registers above the normal context. */
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307 portSAVE_FPU_REGS (portCONTEXT_SIZE + 8), s5
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309 /* Save the FPU status register */
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311 sw s7, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
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314 /* Save the stack pointer to the task. */
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315 la s7, pxCurrentTCB
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319 /* Set the interrupt mask to the max priority that can use the API. The
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320 yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
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321 is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
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322 raise the IPL value and never lower it. */
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325 mfc0 s7, _CP0_STATUS
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326 ins s7, zero, 10, 7
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327 ins s7, zero, 18, 1
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328 ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
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330 /* This mtc0 re-enables interrupts, but only above
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331 configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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332 mtc0 s6, _CP0_STATUS
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335 /* Clear the software interrupt in the core. */
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336 mfc0 s6, _CP0_CAUSE
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338 mtc0 s6, _CP0_CAUSE
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341 /* Clear the interrupt in the interrupt controller. */
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346 jal vTaskSwitchContext
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349 /* Clear the interrupt mask again. The saved status value is still in s7. */
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350 mtc0 s7, _CP0_STATUS
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353 /* Restore the stack pointer from the TCB. */
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354 la s0, pxCurrentTCB
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358 /* Test if the FPU context needs restoring. */
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359 lw s0, portTASK_HAS_FPU_STACK_LOCATION(s5)
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363 /* Restore the FPU status register. */
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364 lw s0, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
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367 /* Restore the FPU registers. */
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368 portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
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371 /* Restore the rest of the context. */
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402 /* s5 is loaded later. */
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424 /* Protect access to the k registers, and others. */
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428 /* Set nesting back to zero. As the lowest priority interrupt this
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429 interrupt cannot have nested. */
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430 la k0, uxInterruptNesting
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433 /* Switch back to use the real stack pointer. */
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436 /* Restore the real s5 value. */
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439 /* Pop the FPU context value from the stack */
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440 lw k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
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441 la k1, ulTaskHasFPUContext
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446 /* task has FPU context so adjust the stack frame after popping the
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447 status and epc values. */
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448 lw k1, portSTATUS_STACK_LOCATION(sp)
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449 lw k0, portEPC_STACK_LOCATION(sp)
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450 addiu sp, sp, portFPU_CONTEXT_SIZE
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455 /* Pop the status and epc values. */
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456 lw k1, portSTATUS_STACK_LOCATION(sp)
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457 lw k0, portEPC_STACK_LOCATION(sp)
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460 /* Remove stack frame. */
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461 addiu sp, sp, portCONTEXT_SIZE
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464 /* Code sequence for no FPU support, the context save requires advance
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465 knowledge of the stack frame size when no FPU is being used */
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467 /* Make room for the context. First save the current status so it can be
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468 manipulated, and the cause and EPC registers so thier original values are
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470 addiu sp, sp, -portCONTEXT_SIZE
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471 mfc0 k1, _CP0_STATUS
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473 /* Also save s6 and s5 so they can be used. Any nesting interrupts should
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474 maintain the values of these registers across the ISR. */
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477 sw k1, portSTATUS_STACK_LOCATION(sp)
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479 /* Prepare to re-enabled interrupts above the kernel priority. */
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480 ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
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481 ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */
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482 ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
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483 ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
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485 /* s5 is used as the frame pointer. */
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488 /* Swap to the system stack. This is not conditional on the nesting
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489 count as this interrupt is always the lowest priority and therefore
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490 the nesting is always 0. */
\r
491 la sp, xISRStackTop
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494 /* Set the nesting count. */
\r
495 la k0, uxInterruptNesting
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499 /* s6 holds the EPC value, this is saved with the rest of the context
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500 after interrupts are enabled. */
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503 /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
\r
504 mtc0 k1, _CP0_STATUS
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506 /* Save the context into the space just created. s6 is saved again
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507 here as it now contains the EPC value. */
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527 sw s6, portEPC_STACK_LOCATION(s5)
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528 /* s5 and s6 has already been saved. */
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536 /* s7 is used as a scratch register as this should always be saved across
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537 nesting interrupts. */
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539 /* Save the AC0, AC1, AC2 and AC3. */
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563 /* Save the stack pointer to the task. */
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564 la s7, pxCurrentTCB
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568 /* Set the interrupt mask to the max priority that can use the API. The
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569 yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
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570 is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
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571 raise the IPL value and never lower it. */
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574 mfc0 s7, _CP0_STATUS
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575 ins s7, zero, 10, 7
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576 ins s7, zero, 18, 1
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577 ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
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579 /* This mtc0 re-enables interrupts, but only above
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580 configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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581 mtc0 s6, _CP0_STATUS
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584 /* Clear the software interrupt in the core. */
\r
585 mfc0 s6, _CP0_CAUSE
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587 mtc0 s6, _CP0_CAUSE
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590 /* Clear the interrupt in the interrupt controller. */
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595 jal vTaskSwitchContext
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598 /* Clear the interrupt mask again. The saved status value is still in s7. */
\r
599 mtc0 s7, _CP0_STATUS
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602 /* Restore the stack pointer from the TCB. */
\r
603 la s0, pxCurrentTCB
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607 /* Restore the rest of the context. */
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638 /* s5 is loaded later. */
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660 /* Protect access to the k registers, and others. */
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664 /* Set nesting back to zero. As the lowest priority interrupt this
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665 interrupt cannot have nested. */
\r
666 la k0, uxInterruptNesting
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669 /* Switch back to use the real stack pointer. */
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672 /* Restore the real s5 value. */
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675 /* Pop the status and epc values. */
\r
676 lw k1, portSTATUS_STACK_LOCATION(sp)
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677 lw k0, portEPC_STACK_LOCATION(sp)
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679 /* Remove stack frame. */
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680 addiu sp, sp, portCONTEXT_SIZE
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682 #endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
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684 /* Restore the status and EPC registers and return */
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685 mtc0 k1, _CP0_STATUS
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693 /******************************************************************/
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695 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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697 .macro portFPUSetAndInc reg, dest
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699 cvt.d.w \dest, \dest
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700 addiu \reg, \reg, 1
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705 .section .text, code
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706 .ent vPortInitialiseFPSCR
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708 vPortInitialiseFPSCR:
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710 /* Initialize the floating point status register in CP1. The initial
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711 value is passed in a0. */
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714 /* Clear the FPU registers */
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715 addiu a0, zero, 0x0000
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716 portFPUSetAndInc a0, $f0
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717 portFPUSetAndInc a0, $f1
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718 portFPUSetAndInc a0, $f2
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719 portFPUSetAndInc a0, $f3
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720 portFPUSetAndInc a0, $f4
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721 portFPUSetAndInc a0, $f5
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722 portFPUSetAndInc a0, $f6
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723 portFPUSetAndInc a0, $f7
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724 portFPUSetAndInc a0, $f8
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725 portFPUSetAndInc a0, $f9
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726 portFPUSetAndInc a0, $f10
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727 portFPUSetAndInc a0, $f11
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728 portFPUSetAndInc a0, $f12
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729 portFPUSetAndInc a0, $f13
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730 portFPUSetAndInc a0, $f14
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731 portFPUSetAndInc a0, $f15
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732 portFPUSetAndInc a0, $f16
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733 portFPUSetAndInc a0, $f17
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734 portFPUSetAndInc a0, $f18
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735 portFPUSetAndInc a0, $f19
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736 portFPUSetAndInc a0, $f20
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737 portFPUSetAndInc a0, $f21
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738 portFPUSetAndInc a0, $f22
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739 portFPUSetAndInc a0, $f23
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740 portFPUSetAndInc a0, $f24
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741 portFPUSetAndInc a0, $f25
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742 portFPUSetAndInc a0, $f26
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743 portFPUSetAndInc a0, $f27
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744 portFPUSetAndInc a0, $f28
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745 portFPUSetAndInc a0, $f29
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746 portFPUSetAndInc a0, $f30
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747 portFPUSetAndInc a0, $f31
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752 .end vPortInitialiseFPSCR
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754 #endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
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756 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
\r
758 /**********************************************************************/
\r
759 /* Test read back */
\r
760 /* a0 = address to store registers */
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764 .section .text, code
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765 .ent vPortFPUReadback
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766 .global vPortFPUReadback
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805 .end vPortFPUReadback
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807 #endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
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