git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S

   1 /*\r
   2     FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  12 \r
  13     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  14     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  15     >>!   obliged to provide the source code for proprietary components     !<<\r
  16     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  17 \r
  18     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  19     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  20     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  21     link: http://www.freertos.org/a00114.html\r
  22 \r
  23     1 tab == 4 spaces!\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
  27      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  28      *    not run, what could be wrong?".  Have you defined configASSERT()?  *\r
  29      *                                                                       *\r
  30      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  31      *                                                                       *\r
  32     ***************************************************************************\r
  33 \r
  34     ***************************************************************************\r
  35      *                                                                       *\r
  36      *    FreeRTOS provides completely free yet professionally developed,    *\r
  37      *    robust, strictly quality controlled, supported, and cross          *\r
  38      *    platform software that is more than just the market leader, it     *\r
  39      *    is the industry's de facto standard.                               *\r
  40      *                                                                       *\r
  41      *    Help yourself get started quickly while simultaneously helping     *\r
  42      *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
  43      *    tutorial book, reference manual, or both:                          *\r
  44      *    http://www.FreeRTOS.org/Documentation                              *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     ***************************************************************************\r
  49      *                                                                       *\r
  50      *   Investing in training allows your team to be as productive as       *\r
  51      *   possible as early as possible, lowering your overall development    *\r
  52      *   cost, and enabling you to bring a more robust product to market     *\r
  53      *   earlier than would otherwise be possible.  Richard Barry is both    *\r
  54      *   the architect and key author of FreeRTOS, and so also the world's   *\r
  55      *   leading authority on what is the world's most popular real time     *\r
  56      *   kernel for deeply embedded MCU designs.  Obtaining your training    *\r
  57      *   from Richard ensures your team will gain directly from his in-depth *\r
  58      *   product knowledge and years of usage experience.  Contact Real Time *\r
  59      *   Engineers Ltd to enquire about the FreeRTOS Masterclass, presented  *\r
  60      *   by Richard Barry:  http://www.FreeRTOS.org/contact\r
  61      *                                                                       *\r
  62     ***************************************************************************\r
  63 \r
  64     ***************************************************************************\r
  65      *                                                                       *\r
  66      *    You are receiving this top quality software for free.  Please play *\r
  67      *    fair and reciprocate by reporting any suspected issues and         *\r
  68      *    participating in the community forum:                              *\r
  69      *    http://www.FreeRTOS.org/support                                    *\r
  70      *                                                                       *\r
  71      *    Thank you!                                                         *\r
  72      *                                                                       *\r
  73     ***************************************************************************\r
  74 \r
  75     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  76     license and Real Time Engineers Ltd. contact details.\r
  77 \r
  78     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  79     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  80     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  81 \r
  82     http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
  83     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
  84 \r
  85     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  86     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  87     licenses offer ticketed support, indemnification and commercial middleware.\r
  88 \r
  89     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  90     engineered and independently SIL3 certified version for use in safety and\r
  91     mission critical applications that require provable dependability.\r
  92 \r
  93     1 tab == 4 spaces!\r
  94 */\r
  95 \r
  96 #include <xc.h>\r
  97 #include <sys/asm.h>\r
  98 #include "FreeRTOSConfig.h"\r
  99 #include "ISR_Support.h"\r
 100 \r
 101 \r
 102         .extern pxCurrentTCB\r
 103         .extern vTaskSwitchContext\r
 104         .extern vPortIncrementTick\r
 105         .extern xISRStackTop\r
 106 \r
 107         .global vPortStartFirstTask\r
 108         .global vPortYieldISR\r
 109         .global vPortTickInterruptHandler\r
 110 \r
 111 \r
 112 /******************************************************************/\r
 113 \r
 114         .set  nomips16\r
 115         .set  nomicromips\r
 116         .set  noreorder\r
 117         .set  noat\r
 118 \r
 119         /***************************************************************\r
 120         *  The following is needed to locate the\r
 121         *  vPortTickInterruptHandler function into the correct vector\r
 122         ***************************************************************/\r
 123         #ifdef configTICK_INTERRUPT_VECTOR\r
 124                 #if (configTICK_INTERRUPT_VECTOR == _CORE_TIMER_VECTOR)\r
 125                         .equ     __vector_dispatch_0, vPortTickInterruptHandler\r
 126                         .global  __vector_dispatch_0\r
 127                         .section .vector_0, code, keep\r
 128                 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_1_VECTOR)\r
 129                         .equ     __vector_dispatch_4, vPortTickInterruptHandler\r
 130                         .global  __vector_dispatch_4\r
 131                         .section .vector_4, code, keep\r
 132                 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_2_VECTOR)\r
 133                         .equ     __vector_dispatch_9, vPortTickInterruptHandler\r
 134                         .global  __vector_dispatch_9\r
 135                         .section .vector_9, code, keep\r
 136                 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_3_VECTOR)\r
 137                         .equ     __vector_dispatch_14, vPortTickInterruptHandler\r
 138                         .global  __vector_dispatch_14\r
 139                         .section .vector_14, code, keep\r
 140                 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_4_VECTOR)\r
 141                         .equ     __vector_dispatch_19, vPortTickInterruptHandler\r
 142                         .global  __vector_dispatch_19\r
 143                         .section .vector_19, code, keep\r
 144                 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_5_VECTOR)\r
 145                         .equ     __vector_dispatch_24, vPortTickInterruptHandler\r
 146                         .global  __vector_dispatch_24\r
 147                         .section .vector_24, code, keep\r
 148                 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_6_VECTOR)\r
 149                         .equ     __vector_dispatch_28, vPortTickInterruptHandler\r
 150                         .global  __vector_dispatch_28\r
 151                         .section .vector_28, code, keep\r
 152                 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_7_VECTOR)\r
 153                         .equ     __vector_dispatch_32, vPortTickInterruptHandler\r
 154                         .global  __vector_dispatch_32\r
 155                         .section .vector_32, code, keep\r
 156                 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_8_VECTOR)\r
 157                         .equ     __vector_dispatch_36, vPortTickInterruptHandler\r
 158                         .global  __vector_dispatch_36\r
 159                         .section .vector_36, code, keep\r
 160                 #elif (configTICK_INTERRUPT_VECTOR == _TIMER_9_VECTOR)\r
 161                         .equ     __vector_dispatch_40, vPortTickInterruptHandler\r
 162                         .global  __vector_dispatch_40\r
 163                         .section .vector_40, code, keep\r
 164                 #endif\r
 165         #else\r
 166                 .equ     __vector_dispatch_4, vPortTickInterruptHandler\r
 167                 .global  __vector_dispatch_4\r
 168                 .section .vector_4, code, keep\r
 169         #endif\r
 170 \r
 171         .ent            vPortTickInterruptHandler\r
 172 \r
 173 vPortTickInterruptHandler:\r
 174 \r
 175         portSAVE_CONTEXT\r
 176 \r
 177         jal             vPortIncrementTick\r
 178         nop\r
 179 \r
 180         portRESTORE_CONTEXT\r
 181 \r
 182         .end vPortTickInterruptHandler\r
 183 \r
 184 /******************************************************************/\r
 185 \r
 186         .set            noreorder\r
 187         .set            noat\r
 188         .section .text, code\r
 189         .ent            vPortStartFirstTask\r
 190 \r
 191 vPortStartFirstTask:\r
 192 \r
 193         /* Simply restore the context of the highest priority task that has been\r
 194         created so far. */\r
 195         portRESTORE_CONTEXT\r
 196 \r
 197         .end vPortStartFirstTask\r
 198 \r
 199 \r
 200 \r
 201 /*******************************************************************/\r
 202 \r
 203         .set  nomips16\r
 204         .set  nomicromips\r
 205         .set  noreorder\r
 206         .set  noat\r
 207         /***************************************************************\r
 208         *  The following is needed to locate the vPortYieldISR function\r
 209         *  into the correct vector\r
 210         ***************************************************************/\r
 211         .equ     __vector_dispatch_1, vPortYieldISR\r
 212         .global  __vector_dispatch_1\r
 213         .section .vector_1, code\r
 214 \r
 215         .ent  vPortYieldISR\r
 216 vPortYieldISR:\r
 217 \r
 218         /* Make room for the context. First save the current status so it can be\r
 219         manipulated, and the cause and EPC registers so thier original values are\r
 220         captured. */\r
 221         addiu           sp, sp, -portCONTEXT_SIZE\r
 222         mfc0            k1, _CP0_STATUS\r
 223 \r
 224         /* Also save s6 and s5 so they can be used.  Any nesting interrupts should\r
 225         maintain the values of these registers across the ISR. */\r
 226         sw                      s6, 44(sp)\r
 227         sw                      s5, 40(sp)\r
 228         sw                      k1, portSTATUS_STACK_LOCATION(sp)\r
 229 \r
 230         /* Prepare to re-enabled interrupts above the kernel priority. */\r
 231         ins             k1, zero, 10, 7         /* Clear IPL bits 0:6. */\r
 232     ins                 k1, zero, 18, 1         /* Clear IPL bit 7.  It would be an error here if this bit were set anyway. */\r
 233         ori                     k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )\r
 234     ins                 k1, zero, 1, 4          /* Clear EXL, ERL and UM. */\r
 235 \r
 236         /* s5 is used as the frame pointer. */\r
 237         add                     s5, zero, sp\r
 238 \r
 239         /* Swap to the system stack.  This is not conditional on the nesting\r
 240         count as this interrupt is always the lowest priority and therefore\r
 241         the nesting is always 0. */\r
 242         la                      sp, xISRStackTop\r
 243         lw                      sp, (sp)\r
 244 \r
 245         /* Set the nesting count. */\r
 246         la                      k0, uxInterruptNesting\r
 247         addiu           s6, zero, 1\r
 248         sw                      s6, 0(k0)\r
 249 \r
 250         /* s6 holds the EPC value, this is saved with the rest of the context\r
 251         after interrupts are enabled. */\r
 252         mfc0            s6, _CP0_EPC\r
 253 \r
 254         /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 255         mtc0            k1, _CP0_STATUS\r
 256 \r
 257         /* Save the context into the space just created.  s6 is saved again\r
 258         here as it now contains the EPC value. */\r
 259         sw                      ra, 120(s5)\r
 260         sw                      s8, 116(s5)\r
 261         sw                      t9, 112(s5)\r
 262         sw                      t8, 108(s5)\r
 263         sw                      t7, 104(s5)\r
 264         sw                      t6, 100(s5)\r
 265         sw                      t5, 96(s5)\r
 266         sw                      t4, 92(s5)\r
 267         sw                      t3, 88(s5)\r
 268         sw                      t2, 84(s5)\r
 269         sw                      t1, 80(s5)\r
 270         sw                      t0, 76(s5)\r
 271         sw                      a3, 72(s5)\r
 272         sw                      a2, 68(s5)\r
 273         sw                      a1, 64(s5)\r
 274         sw                      a0, 60(s5)\r
 275         sw                      v1, 56(s5)\r
 276         sw                      v0, 52(s5)\r
 277         sw                      s7, 48(s5)\r
 278         sw                      s6, portEPC_STACK_LOCATION(s5)\r
 279         /* s5 and s6 has already been saved. */\r
 280         sw                      s4,     36(s5)\r
 281         sw                      s3, 32(s5)\r
 282         sw                      s2, 28(s5)\r
 283         sw                      s1, 24(s5)\r
 284         sw                      s0, 20(s5)\r
 285         sw                      $1, 16(s5)\r
 286 \r
 287         /* s7 is used as a scratch register as this should always be saved across\r
 288         nesting interrupts. */\r
 289 \r
 290         /* Save the AC0, AC1, AC2 and AC3. */\r
 291         mfhi            s7, $ac1\r
 292         sw                      s7, 128(s5)\r
 293         mflo            s7, $ac1\r
 294         sw                      s7, 124(s5)\r
 295 \r
 296         mfhi            s7, $ac2\r
 297         sw                      s7, 136(s5)\r
 298         mflo            s7, $ac2\r
 299         sw                      s7, 132(s5)\r
 300 \r
 301         mfhi            s7, $ac3\r
 302         sw                      s7, 144(s5)\r
 303         mflo            s7, $ac3\r
 304         sw                      s7, 140(s5)\r
 305 \r
 306         rddsp           s7\r
 307         sw                      s7, 148(s5)\r
 308 \r
 309         mfhi            s7, $ac0\r
 310         sw                      s7, 12(s5)\r
 311         mflo            s7, $ac0\r
 312         sw                      s7, 8(s5)\r
 313 \r
 314         /* Save the stack pointer to the task. */\r
 315         la                      s7, pxCurrentTCB\r
 316         lw                      s7, (s7)\r
 317         sw                      s5, (s7)\r
 318 \r
 319         /* Set the interrupt mask to the max priority that can use the API.  The\r
 320         yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which\r
 321         is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever\r
 322         raise the IPL value and never lower it. */\r
 323         di\r
 324         ehb\r
 325         mfc0            s7, _CP0_STATUS\r
 326         ins             s7, zero, 10, 7\r
 327     ins                 s7, zero, 18, 1\r
 328         ori                     s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1\r
 329 \r
 330         /* This mtc0 re-enables interrupts, but only above\r
 331         configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 332         mtc0            s6, _CP0_STATUS\r
 333         ehb\r
 334 \r
 335         /* Clear the software interrupt in the core. */\r
 336         mfc0            s6, _CP0_CAUSE\r
 337         ins                     s6, zero, 8, 1\r
 338         mtc0            s6, _CP0_CAUSE\r
 339         ehb\r
 340 \r
 341         /* Clear the interrupt in the interrupt controller. */\r
 342         la                      s6, IFS0CLR\r
 343         addiu           s4, zero, 2\r
 344         sw                      s4, (s6)\r
 345 \r
 346         jal                     vTaskSwitchContext\r
 347         nop\r
 348 \r
 349         /* Clear the interrupt mask again.  The saved status value is still in s7. */\r
 350         mtc0            s7, _CP0_STATUS\r
 351         ehb\r
 352 \r
 353         /* Restore the stack pointer from the TCB. */\r
 354         la                      s0, pxCurrentTCB\r
 355         lw                      s0, (s0)\r
 356         lw                      s5, (s0)\r
 357 \r
 358         /* Restore the rest of the context. */\r
 359         lw                      s0, 128(s5)\r
 360         mthi            s0, $ac1\r
 361         lw                      s0, 124(s5)\r
 362         mtlo            s0, $ac1\r
 363 \r
 364         lw                      s0, 136(s5)\r
 365         mthi            s0, $ac2\r
 366         lw                      s0, 132(s5)\r
 367         mtlo            s0, $ac2\r
 368 \r
 369         lw                      s0, 144(s5)\r
 370         mthi            s0, $ac3\r
 371         lw                      s0, 140(s5)\r
 372         mtlo            s0, $ac3\r
 373 \r
 374         lw                      s0, 148(s5)\r
 375         wrdsp           s0\r
 376 \r
 377         lw                      s0, 8(s5)\r
 378         mtlo            s0, $ac0\r
 379         lw                      s0, 12(s5)\r
 380         mthi            s0, $ac0\r
 381 \r
 382         lw                      $1, 16(s5)\r
 383         lw                      s0, 20(s5)\r
 384         lw                      s1, 24(s5)\r
 385         lw                      s2, 28(s5)\r
 386         lw                      s3, 32(s5)\r
 387         lw                      s4, 36(s5)\r
 388 \r
 389         /* s5 is loaded later. */\r
 390         lw                      s6, 44(s5)\r
 391         lw                      s7, 48(s5)\r
 392         lw                      v0, 52(s5)\r
 393         lw                      v1, 56(s5)\r
 394         lw                      a0, 60(s5)\r
 395         lw                      a1, 64(s5)\r
 396         lw                      a2, 68(s5)\r
 397         lw                      a3, 72(s5)\r
 398         lw                      t0, 76(s5)\r
 399         lw                      t1, 80(s5)\r
 400         lw                      t2, 84(s5)\r
 401         lw                      t3, 88(s5)\r
 402         lw                      t4, 92(s5)\r
 403         lw                      t5, 96(s5)\r
 404         lw                      t6, 100(s5)\r
 405         lw                      t7, 104(s5)\r
 406         lw                      t8, 108(s5)\r
 407         lw                      t9, 112(s5)\r
 408         lw                      s8, 116(s5)\r
 409         lw                      ra, 120(s5)\r
 410 \r
 411         /* Protect access to the k registers, and others. */\r
 412         di\r
 413         ehb\r
 414 \r
 415         /* Set nesting back to zero.  As the lowest priority interrupt this\r
 416         interrupt cannot have nested. */\r
 417         la                      k0, uxInterruptNesting\r
 418         sw                      zero, 0(k0)\r
 419 \r
 420         /* Switch back to use the real stack pointer. */\r
 421         add                     sp, zero, s5\r
 422 \r
 423         /* Restore the real s5 value. */\r
 424         lw                      s5, 40(sp)\r
 425 \r
 426         /* Pop the status and epc values. */\r
 427         lw                      k1, portSTATUS_STACK_LOCATION(sp)\r
 428         lw                      k0, portEPC_STACK_LOCATION(sp)\r
 429 \r
 430         /* Remove stack frame. */\r
 431         addiu           sp, sp, portCONTEXT_SIZE\r
 432 \r
 433         mtc0            k1, _CP0_STATUS\r
 434         mtc0            k0, _CP0_EPC\r
 435         ehb\r
 436         eret\r
 437         nop\r
 438 \r
 439         .end            vPortYieldISR\r
 440 \r
 441 \r
 442 \r