2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the ARM CM4F port.
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30 *----------------------------------------------------------*/
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32 /* Scheduler includes. */
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33 #include "FreeRTOS.h"
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36 #ifndef __TARGET_FPU_VFP
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37 #error This port can only be used when the project options are configured to enable hardware floating point support.
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40 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
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41 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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44 #ifndef configSYSTICK_CLOCK_HZ
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45 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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46 /* Ensure the SysTick is clocked at the same frequency as the core. */
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47 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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49 /* The way the SysTick is clocked is not modified in case it is not the same
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51 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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54 /* Legacy macro for backward compatibility only. This macro used to be used to
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55 replace the function that configures the clock used to generate the tick
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56 interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
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57 the application writer can override it by simply defining a function of the
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58 same name (vApplicationSetupTickInterrupt()). */
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59 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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60 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
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63 /* Constants required to manipulate the core. Registers first... */
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64 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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65 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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66 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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67 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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68 /* ...then bits in the registers. */
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69 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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70 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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71 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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72 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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73 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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75 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
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77 #define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
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78 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
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79 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
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81 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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82 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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84 /* Constants required to check the validity of an interrupt priority. */
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85 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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86 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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87 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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88 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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89 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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90 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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91 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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92 #define portPRIGROUP_SHIFT ( 8UL )
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94 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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95 #define portVECTACTIVE_MASK ( 0xFFUL )
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97 /* Constants required to manipulate the VFP. */
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98 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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99 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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101 /* Constants required to set up the initial stack. */
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102 #define portINITIAL_XPSR ( 0x01000000 )
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103 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
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105 /* The systick is a 24-bit counter. */
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106 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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108 /* A fiddle factor to estimate the number of SysTick counts that would have
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109 occurred while the SysTick counter is stopped during tickless idle
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111 #define portMISSED_COUNTS_FACTOR ( 45UL )
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113 /* For strict compliance with the Cortex-M spec the task start address should
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114 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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115 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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118 * Setup the timer to generate the tick interrupts. The implementation in this
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119 * file is weak to allow application writers to change the timer used to
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120 * generate the tick interrupt.
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122 void vPortSetupTimerInterrupt( void );
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125 * Exception handlers.
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127 void xPortPendSVHandler( void );
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128 void xPortSysTickHandler( void );
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129 void vPortSVCHandler( void );
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132 * Start first task is a separate function so it can be tested in isolation.
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134 static void prvStartFirstTask( void );
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137 * Functions defined in portasm.s to enable the VFP.
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139 static void prvEnableVFP( void );
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142 * Used to catch tasks that attempt to return from their implementing function.
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144 static void prvTaskExitError( void );
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146 /*-----------------------------------------------------------*/
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148 /* Each task maintains its own interrupt status in the critical nesting
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150 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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153 * The number of SysTick increments that make up one tick period.
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155 #if( configUSE_TICKLESS_IDLE == 1 )
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156 static uint32_t ulTimerCountsForOneTick = 0;
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157 #endif /* configUSE_TICKLESS_IDLE */
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160 * The maximum number of tick periods that can be suppressed is limited by the
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161 * 24 bit resolution of the SysTick timer.
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163 #if( configUSE_TICKLESS_IDLE == 1 )
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164 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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165 #endif /* configUSE_TICKLESS_IDLE */
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168 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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169 * power functionality only.
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171 #if( configUSE_TICKLESS_IDLE == 1 )
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172 static uint32_t ulStoppedTimerCompensation = 0;
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173 #endif /* configUSE_TICKLESS_IDLE */
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176 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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177 * FreeRTOS API functions are not called from interrupts that have been assigned
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178 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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180 #if ( configASSERT_DEFINED == 1 )
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181 static uint8_t ucMaxSysCallPriority = 0;
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182 static uint32_t ulMaxPRIGROUPValue = 0;
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183 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
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184 #endif /* configASSERT_DEFINED */
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186 /*-----------------------------------------------------------*/
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189 * See header file for description.
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191 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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193 /* Simulate the stack frame as it would be created by a context switch
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196 /* Offset added to account for the way the MCU uses the stack on entry/exit
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197 of interrupts, and to ensure alignment. */
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200 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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202 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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204 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
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206 /* Save code space by skipping register initialisation. */
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207 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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208 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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210 /* A save method is being used that requires each task to maintain its
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211 own exec return value. */
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213 *pxTopOfStack = portINITIAL_EXC_RETURN;
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215 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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217 return pxTopOfStack;
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219 /*-----------------------------------------------------------*/
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221 static void prvTaskExitError( void )
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223 /* A function that implements a task must not exit or attempt to return to
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224 its caller as there is nothing to return to. If a task wants to exit it
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225 should instead call vTaskDelete( NULL ).
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227 Artificially force an assert() to be triggered if configASSERT() is
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228 defined, then stop here so application writers can catch the error. */
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229 configASSERT( uxCriticalNesting == ~0UL );
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230 portDISABLE_INTERRUPTS();
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233 /*-----------------------------------------------------------*/
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235 __asm void vPortSVCHandler( void )
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239 /* Get the location of the current TCB. */
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240 ldr r3, =pxCurrentTCB
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243 /* Pop the core registers. */
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244 ldmia r0!, {r4-r11, r14}
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251 /*-----------------------------------------------------------*/
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253 __asm void prvStartFirstTask( void )
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257 /* Use the NVIC offset register to locate the stack. */
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258 ldr r0, =0xE000ED08
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261 /* Set the msp back to the start of the stack. */
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263 /* Clear the bit that indicates the FPU is in use in case the FPU was used
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264 before the scheduler was started - which would otherwise result in the
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265 unnecessary leaving of space in the SVC stack for lazy saving of FPU
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269 /* Globally enable interrupts. */
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274 /* Call SVC to start the first task. */
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279 /*-----------------------------------------------------------*/
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281 __asm void prvEnableVFP( void )
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285 /* The FPU enable bits are in the CPACR. */
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286 ldr.w r0, =0xE000ED88
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289 /* Enable CP10 and CP11 coprocessors, then save back. */
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290 orr r1, r1, #( 0xf << 20 )
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295 /*-----------------------------------------------------------*/
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298 * See header file for description.
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300 BaseType_t xPortStartScheduler( void )
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302 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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303 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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304 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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306 /* This port can be used on all revisions of the Cortex-M7 core other than
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307 the r0p1 parts. r0p1 parts should use the port from the
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308 /source/portable/GCC/ARM_CM7/r0p1 directory. */
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309 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
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310 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
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312 #if( configASSERT_DEFINED == 1 )
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314 volatile uint32_t ulOriginalPriority;
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315 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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316 volatile uint8_t ucMaxPriorityValue;
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318 /* Determine the maximum priority from which ISR safe FreeRTOS API
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319 functions can be called. ISR safe functions are those that end in
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320 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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321 ensure interrupt entry is as fast and simple as possible.
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323 Save the interrupt priority value that is about to be clobbered. */
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324 ulOriginalPriority = *pucFirstUserPriorityRegister;
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326 /* Determine the number of priority bits available. First write to all
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328 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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330 /* Read the value back to see how many bits stuck. */
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331 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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333 /* The kernel interrupt priority should be set to the lowest
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335 configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
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337 /* Use the same mask on the maximum system call priority. */
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338 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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340 /* Calculate the maximum acceptable priority group value for the number
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341 of bits read back. */
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342 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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343 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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345 ulMaxPRIGROUPValue--;
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346 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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349 #ifdef __NVIC_PRIO_BITS
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351 /* Check the CMSIS configuration that defines the number of
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352 priority bits matches the number of priority bits actually queried
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353 from the hardware. */
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354 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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358 #ifdef configPRIO_BITS
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360 /* Check the FreeRTOS configuration that defines the number of
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361 priority bits matches the number of priority bits actually queried
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362 from the hardware. */
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363 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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367 /* Shift the priority group value back to its position within the AIRCR
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369 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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370 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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372 /* Restore the clobbered interrupt priority register to its original
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374 *pucFirstUserPriorityRegister = ulOriginalPriority;
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376 #endif /* conifgASSERT_DEFINED */
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378 /* Make PendSV and SysTick the lowest priority interrupts. */
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379 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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380 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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382 /* Start the timer that generates the tick ISR. Interrupts are disabled
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384 vPortSetupTimerInterrupt();
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386 /* Initialise the critical nesting count ready for the first task. */
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387 uxCriticalNesting = 0;
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389 /* Ensure the VFP is enabled - it should be anyway. */
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392 /* Lazy save always. */
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393 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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395 /* Start the first task. */
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396 prvStartFirstTask();
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398 /* Should not get here! */
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401 /*-----------------------------------------------------------*/
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403 void vPortEndScheduler( void )
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405 /* Not implemented in ports where there is nothing to return to.
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406 Artificially force an assert. */
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407 configASSERT( uxCriticalNesting == 1000UL );
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409 /*-----------------------------------------------------------*/
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411 void vPortEnterCritical( void )
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413 portDISABLE_INTERRUPTS();
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414 uxCriticalNesting++;
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416 /* This is not the interrupt safe version of the enter critical function so
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417 assert() if it is being called from an interrupt context. Only API
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418 functions that end in "FromISR" can be used in an interrupt. Only assert if
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419 the critical nesting count is 1 to protect against recursive calls if the
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420 assert function also uses a critical section. */
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421 if( uxCriticalNesting == 1 )
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423 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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426 /*-----------------------------------------------------------*/
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428 void vPortExitCritical( void )
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430 configASSERT( uxCriticalNesting );
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431 uxCriticalNesting--;
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432 if( uxCriticalNesting == 0 )
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434 portENABLE_INTERRUPTS();
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437 /*-----------------------------------------------------------*/
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439 __asm void xPortPendSVHandler( void )
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441 extern uxCriticalNesting;
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442 extern pxCurrentTCB;
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443 extern vTaskSwitchContext;
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449 /* Get the location of the current TCB. */
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450 ldr r3, =pxCurrentTCB
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453 /* Is the task using the FPU context? If so, push high vfp registers. */
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456 vstmdbeq r0!, {s16-s31}
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458 /* Save the core registers. */
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459 stmdb r0!, {r4-r11, r14}
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461 /* Save the new top of stack into the first member of the TCB. */
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464 stmdb sp!, {r0, r3}
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465 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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469 bl vTaskSwitchContext
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472 ldmia sp!, {r0, r3}
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474 /* The first item in pxCurrentTCB is the task top of stack. */
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478 /* Pop the core registers. */
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479 ldmia r0!, {r4-r11, r14}
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481 /* Is the task using the FPU context? If so, pop the high vfp registers
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485 vldmiaeq r0!, {s16-s31}
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489 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
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490 #if WORKAROUND_PMU_CM001 == 1
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499 /*-----------------------------------------------------------*/
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501 void xPortSysTickHandler( void )
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503 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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504 executes all interrupts must be unmasked. There is therefore no need to
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505 save and then restore the interrupt mask value as its value is already
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506 known - therefore the slightly faster vPortRaiseBASEPRI() function is used
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507 in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
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508 vPortRaiseBASEPRI();
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510 /* Increment the RTOS tick. */
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511 if( xTaskIncrementTick() != pdFALSE )
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513 /* A context switch is required. Context switching is performed in
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514 the PendSV interrupt. Pend the PendSV interrupt. */
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515 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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518 vPortClearBASEPRIFromISR();
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520 /*-----------------------------------------------------------*/
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522 #if( configUSE_TICKLESS_IDLE == 1 )
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524 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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526 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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527 TickType_t xModifiableIdleTime;
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529 /* Make sure the SysTick reload value does not overflow the counter. */
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530 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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532 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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535 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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536 is accounted for as best it can be, but using the tickless mode will
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537 inevitably result in some tiny drift of the time maintained by the
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538 kernel with respect to calendar time. */
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539 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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541 /* Calculate the reload value required to wait xExpectedIdleTime
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542 tick periods. -1 is used because this code will execute part way
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543 through one of the tick periods. */
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544 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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545 if( ulReloadValue > ulStoppedTimerCompensation )
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547 ulReloadValue -= ulStoppedTimerCompensation;
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550 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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551 method as that will mask interrupts that should exit sleep mode. */
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553 __dsb( portSY_FULL_READ_WRITE );
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554 __isb( portSY_FULL_READ_WRITE );
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556 /* If a context switch is pending or a task is waiting for the scheduler
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557 to be unsuspended then abandon the low power entry. */
\r
558 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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560 /* Restart from whatever is left in the count register to complete
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561 this tick period. */
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562 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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564 /* Restart SysTick. */
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565 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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567 /* Reset the reload register to the value required for normal tick
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569 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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571 /* Re-enable interrupts - see comments above __disable_irq() call
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577 /* Set the new reload value. */
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578 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
580 /* Clear the SysTick count flag and set the count value back to
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582 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
584 /* Restart SysTick. */
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585 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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587 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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588 set its parameter to 0 to indicate that its implementation contains
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589 its own wait for interrupt or wait for event instruction, and so wfi
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590 should not be executed again. However, the original expected idle
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591 time variable must remain unmodified, so a copy is taken. */
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592 xModifiableIdleTime = xExpectedIdleTime;
\r
593 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
594 if( xModifiableIdleTime > 0 )
\r
596 __dsb( portSY_FULL_READ_WRITE );
\r
598 __isb( portSY_FULL_READ_WRITE );
\r
600 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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602 /* Re-enable interrupts to allow the interrupt that brought the MCU
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603 out of sleep mode to execute immediately. see comments above
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604 __disable_interrupt() call above. */
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606 __dsb( portSY_FULL_READ_WRITE );
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607 __isb( portSY_FULL_READ_WRITE );
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609 /* Disable interrupts again because the clock is about to be stopped
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610 and interrupts that execute while the clock is stopped will increase
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611 any slippage between the time maintained by the RTOS and calendar
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614 __dsb( portSY_FULL_READ_WRITE );
\r
615 __isb( portSY_FULL_READ_WRITE );
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617 /* Disable the SysTick clock without reading the
\r
618 portNVIC_SYSTICK_CTRL_REG register to ensure the
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619 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
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620 the time the SysTick is stopped for is accounted for as best it can
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621 be, but using the tickless mode will inevitably result in some tiny
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622 drift of the time maintained by the kernel with respect to calendar
\r
624 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
\r
626 /* Determine if the SysTick clock has already counted to zero and
\r
627 been set back to the current reload value (the reload back being
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628 correct for the entire expected idle time) or if the SysTick is yet
\r
629 to count to zero (in which case an interrupt other than the SysTick
\r
630 must have brought the system out of sleep mode). */
\r
631 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
633 uint32_t ulCalculatedLoadValue;
\r
635 /* The tick interrupt is already pending, and the SysTick count
\r
636 reloaded with ulReloadValue. Reset the
\r
637 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
639 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
641 /* Don't allow a tiny value, or values that have somehow
\r
642 underflowed because the post sleep hook did something
\r
643 that took too long. */
\r
644 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
646 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
649 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
651 /* As the pending tick will be processed as soon as this
\r
652 function exits, the tick value maintained by the tick is stepped
\r
653 forward by one less than the time spent waiting. */
\r
654 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
658 /* Something other than the tick interrupt ended the sleep.
\r
659 Work out how long the sleep lasted rounded to complete tick
\r
660 periods (not the ulReload value which accounted for part
\r
662 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
664 /* How many complete tick periods passed while the processor
\r
666 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
668 /* The reload value is set to whatever fraction of a single tick
\r
670 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
673 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
674 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
676 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
677 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
678 vTaskStepTick( ulCompleteTickPeriods );
\r
679 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
681 /* Exit with interrupts enabled. */
\r
686 #endif /* #if configUSE_TICKLESS_IDLE */
\r
688 /*-----------------------------------------------------------*/
\r
691 * Setup the SysTick timer to generate the tick interrupts at the required
\r
694 #if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
\r
696 __weak void vPortSetupTimerInterrupt( void )
\r
698 /* Calculate the constants required to configure the tick interrupt. */
\r
699 #if( configUSE_TICKLESS_IDLE == 1 )
\r
701 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
702 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
703 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
705 #endif /* configUSE_TICKLESS_IDLE */
\r
707 /* Stop and clear the SysTick. */
\r
708 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
709 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
711 /* Configure SysTick to interrupt at the requested rate. */
\r
712 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
713 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
716 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
\r
717 /*-----------------------------------------------------------*/
\r
719 __asm uint32_t vPortGetIPSR( void )
\r
726 /*-----------------------------------------------------------*/
\r
728 #if( configASSERT_DEFINED == 1 )
\r
730 void vPortValidateInterruptPriority( void )
\r
732 uint32_t ulCurrentInterrupt;
\r
733 uint8_t ucCurrentPriority;
\r
735 /* Obtain the number of the currently executing interrupt. */
\r
736 ulCurrentInterrupt = vPortGetIPSR();
\r
738 /* Is the interrupt number a user defined interrupt? */
\r
739 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
741 /* Look up the interrupt's priority. */
\r
742 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
744 /* The following assertion will fail if a service routine (ISR) for
\r
745 an interrupt that has been assigned a priority above
\r
746 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
747 function. ISR safe FreeRTOS API functions must *only* be called
\r
748 from interrupts that have been assigned a priority at or below
\r
749 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
751 Numerically low interrupt priority numbers represent logically high
\r
752 interrupt priorities, therefore the priority of the interrupt must
\r
753 be set to a value equal to or numerically *higher* than
\r
754 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
756 Interrupts that use the FreeRTOS API must not be left at their
\r
757 default priority of zero as that is the highest possible priority,
\r
758 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
759 and therefore also guaranteed to be invalid.
\r
761 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
762 interrupt entry is as fast and simple as possible.
\r
764 The following links provide detailed information:
\r
765 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
766 http://www.freertos.org/FAQHelp.html */
\r
767 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
770 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
771 that define each interrupt's priority to be split between bits that
\r
772 define the interrupt's pre-emption priority bits and bits that define
\r
773 the interrupt's sub-priority. For simplicity all bits must be defined
\r
774 to be pre-emption priority bits. The following assertion will fail if
\r
775 this is not the case (if some bits represent a sub-priority).
\r
777 If the application only uses CMSIS libraries for interrupt
\r
778 configuration then the correct setting can be achieved on all Cortex-M
\r
779 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
780 scheduler. Note however that some vendor specific peripheral libraries
\r
781 assume a non-zero priority group setting, in which cases using a value
\r
782 of zero will result in unpredictable behaviour. */
\r
783 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
786 #endif /* configASSERT_DEFINED */
\r