2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 >>! NOTE: The modification to the GPL is included to allow you to !<<
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14 >>! distribute a combined work that includes FreeRTOS without being !<<
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15 >>! obliged to provide the source code for proprietary components !<<
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16 >>! outside of the FreeRTOS kernel. !<<
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18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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21 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * Having a problem? Start by reading the FAQ "My application does *
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28 * not run, what could be wrong?". Have you defined configASSERT()? *
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30 * http://www.FreeRTOS.org/FAQHelp.html *
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32 ***************************************************************************
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34 ***************************************************************************
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36 * FreeRTOS provides completely free yet professionally developed, *
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37 * robust, strictly quality controlled, supported, and cross *
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38 * platform software that is more than just the market leader, it *
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39 * is the industry's de facto standard. *
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41 * Help yourself get started quickly while simultaneously helping *
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42 * to support the FreeRTOS project by purchasing a FreeRTOS *
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43 * tutorial book, reference manual, or both: *
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44 * http://www.FreeRTOS.org/Documentation *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * Investing in training allows your team to be as productive as *
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51 * possible as early as possible, lowering your overall development *
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52 * cost, and enabling you to bring a more robust product to market *
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53 * earlier than would otherwise be possible. Richard Barry is both *
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54 * the architect and key author of FreeRTOS, and so also the world's *
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55 * leading authority on what is the world's most popular real time *
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56 * kernel for deeply embedded MCU designs. Obtaining your training *
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57 * from Richard ensures your team will gain directly from his in-depth *
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58 * product knowledge and years of usage experience. Contact Real Time *
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59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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60 * by Richard Barry: http://www.FreeRTOS.org/contact
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62 ***************************************************************************
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64 ***************************************************************************
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66 * You are receiving this top quality software for free. Please play *
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67 * fair and reciprocate by reporting any suspected issues and *
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68 * participating in the community forum: *
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69 * http://www.FreeRTOS.org/support *
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73 ***************************************************************************
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75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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76 license and Real Time Engineers Ltd. contact details.
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78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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87 licenses offer ticketed support, indemnification and commercial middleware.
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89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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90 engineered and independently SIL3 certified version for use in safety and
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91 mission critical applications that require provable dependability.
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96 /*-----------------------------------------------------------
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97 * Implementation of functions defined in portable.h for the ARM CM4F port.
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98 *----------------------------------------------------------*/
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100 /* Scheduler includes. */
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101 #include "FreeRTOS.h"
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104 #ifndef __TARGET_FPU_VFP
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105 #error This port can only be used when the project options are configured to enable hardware floating point support.
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108 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
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109 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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112 #ifndef configSYSTICK_CLOCK_HZ
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113 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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114 /* Ensure the SysTick is clocked at the same frequency as the core. */
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115 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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117 /* The way the SysTick is clocked is not modified in case it is not the same
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119 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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122 /* The __weak attribute does not work as you might expect with the Keil tools
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123 so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
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124 the application writer wants to provide their own implementation of
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125 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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127 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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128 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
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131 /* Constants required to manipulate the core. Registers first... */
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132 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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133 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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134 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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135 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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136 /* ...then bits in the registers. */
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137 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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138 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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139 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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140 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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141 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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143 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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144 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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146 /* Constants required to check the validity of an interrupt priority. */
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147 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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148 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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149 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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150 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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151 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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152 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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153 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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154 #define portPRIGROUP_SHIFT ( 8UL )
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156 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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157 #define portVECTACTIVE_MASK ( 0xFFUL )
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159 /* Constants required to manipulate the VFP. */
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160 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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161 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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163 /* Constants required to set up the initial stack. */
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164 #define portINITIAL_XPSR ( 0x01000000 )
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165 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
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167 /* The systick is a 24-bit counter. */
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168 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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170 /* A fiddle factor to estimate the number of SysTick counts that would have
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171 occurred while the SysTick counter is stopped during tickless idle
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173 #define portMISSED_COUNTS_FACTOR ( 45UL )
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175 /* Each task maintains its own interrupt status in the critical nesting
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177 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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180 * Setup the timer to generate the tick interrupts. The implementation in this
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181 * file is weak to allow application writers to change the timer used to
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182 * generate the tick interrupt.
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184 void vPortSetupTimerInterrupt( void );
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187 * Exception handlers.
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189 void xPortPendSVHandler( void );
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190 void xPortSysTickHandler( void );
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191 void vPortSVCHandler( void );
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194 * Start first task is a separate function so it can be tested in isolation.
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196 static void prvStartFirstTask( void );
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199 * Functions defined in portasm.s to enable the VFP.
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201 static void prvEnableVFP( void );
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204 * Used to catch tasks that attempt to return from their implementing function.
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206 static void prvTaskExitError( void );
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208 /*-----------------------------------------------------------*/
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211 * The number of SysTick increments that make up one tick period.
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213 #if configUSE_TICKLESS_IDLE == 1
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214 static uint32_t ulTimerCountsForOneTick = 0;
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215 #endif /* configUSE_TICKLESS_IDLE */
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218 * The maximum number of tick periods that can be suppressed is limited by the
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219 * 24 bit resolution of the SysTick timer.
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221 #if configUSE_TICKLESS_IDLE == 1
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222 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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223 #endif /* configUSE_TICKLESS_IDLE */
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226 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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227 * power functionality only.
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229 #if configUSE_TICKLESS_IDLE == 1
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230 static uint32_t ulStoppedTimerCompensation = 0;
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231 #endif /* configUSE_TICKLESS_IDLE */
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234 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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235 * FreeRTOS API functions are not called from interrupts that have been assigned
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236 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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238 #if ( configASSERT_DEFINED == 1 )
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239 static uint8_t ucMaxSysCallPriority = 0;
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240 static uint32_t ulMaxPRIGROUPValue = 0;
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241 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
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242 #endif /* configASSERT_DEFINED */
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244 /*-----------------------------------------------------------*/
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247 * See header file for description.
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249 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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251 /* Simulate the stack frame as it would be created by a context switch
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254 /* Offset added to account for the way the MCU uses the stack on entry/exit
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255 of interrupts, and to ensure alignment. */
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258 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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260 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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262 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
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264 /* Save code space by skipping register initialisation. */
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265 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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266 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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268 /* A save method is being used that requires each task to maintain its
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269 own exec return value. */
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271 *pxTopOfStack = portINITIAL_EXEC_RETURN;
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273 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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275 return pxTopOfStack;
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277 /*-----------------------------------------------------------*/
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279 static void prvTaskExitError( void )
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281 /* A function that implements a task must not exit or attempt to return to
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282 its caller as there is nothing to return to. If a task wants to exit it
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283 should instead call vTaskDelete( NULL ).
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285 Artificially force an assert() to be triggered if configASSERT() is
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286 defined, then stop here so application writers can catch the error. */
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287 configASSERT( uxCriticalNesting == ~0UL );
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288 portDISABLE_INTERRUPTS();
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291 /*-----------------------------------------------------------*/
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293 __asm void vPortSVCHandler( void )
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297 /* Get the location of the current TCB. */
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298 ldr r3, =pxCurrentTCB
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301 /* Pop the core registers. */
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302 ldmia r0!, {r4-r11, r14}
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309 /*-----------------------------------------------------------*/
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311 __asm void prvStartFirstTask( void )
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315 /* Use the NVIC offset register to locate the stack. */
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316 ldr r0, =0xE000ED08
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319 /* Set the msp back to the start of the stack. */
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321 /* Globally enable interrupts. */
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326 /* Call SVC to start the first task. */
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331 /*-----------------------------------------------------------*/
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333 __asm void prvEnableVFP( void )
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337 /* The FPU enable bits are in the CPACR. */
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338 ldr.w r0, =0xE000ED88
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341 /* Enable CP10 and CP11 coprocessors, then save back. */
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342 orr r1, r1, #( 0xf << 20 )
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347 /*-----------------------------------------------------------*/
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350 * See header file for description.
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352 BaseType_t xPortStartScheduler( void )
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354 #if( configASSERT_DEFINED == 1 )
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356 volatile uint32_t ulOriginalPriority;
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357 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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358 volatile uint8_t ucMaxPriorityValue;
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360 /* Determine the maximum priority from which ISR safe FreeRTOS API
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361 functions can be called. ISR safe functions are those that end in
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362 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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363 ensure interrupt entry is as fast and simple as possible.
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365 Save the interrupt priority value that is about to be clobbered. */
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366 ulOriginalPriority = *pucFirstUserPriorityRegister;
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368 /* Determine the number of priority bits available. First write to all
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370 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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372 /* Read the value back to see how many bits stuck. */
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373 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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375 /* Use the same mask on the maximum system call priority. */
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376 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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378 /* Calculate the maximum acceptable priority group value for the number
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379 of bits read back. */
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380 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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381 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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383 ulMaxPRIGROUPValue--;
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384 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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387 /* Shift the priority group value back to its position within the AIRCR
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389 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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390 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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392 /* Restore the clobbered interrupt priority register to its original
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394 *pucFirstUserPriorityRegister = ulOriginalPriority;
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396 #endif /* conifgASSERT_DEFINED */
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398 /* Make PendSV and SysTick the lowest priority interrupts. */
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399 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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400 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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402 /* Start the timer that generates the tick ISR. Interrupts are disabled
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404 vPortSetupTimerInterrupt();
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406 /* Initialise the critical nesting count ready for the first task. */
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407 uxCriticalNesting = 0;
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409 /* Ensure the VFP is enabled - it should be anyway. */
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412 /* Lazy save always. */
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413 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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415 /* Start the first task. */
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416 prvStartFirstTask();
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418 /* Should not get here! */
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421 /*-----------------------------------------------------------*/
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423 void vPortEndScheduler( void )
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425 /* Not implemented in ports where there is nothing to return to.
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426 Artificially force an assert. */
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427 configASSERT( uxCriticalNesting == 1000UL );
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429 /*-----------------------------------------------------------*/
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431 void vPortEnterCritical( void )
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433 portDISABLE_INTERRUPTS();
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434 uxCriticalNesting++;
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436 /* This is not the interrupt safe version of the enter critical function so
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437 assert() if it is being called from an interrupt context. Only API
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438 functions that end in "FromISR" can be used in an interrupt. Only assert if
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439 the critical nesting count is 1 to protect against recursive calls if the
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440 assert function also uses a critical section. */
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441 if( uxCriticalNesting == 1 )
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443 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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446 /*-----------------------------------------------------------*/
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448 void vPortExitCritical( void )
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450 configASSERT( uxCriticalNesting );
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451 uxCriticalNesting--;
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452 if( uxCriticalNesting == 0 )
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454 portENABLE_INTERRUPTS();
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457 /*-----------------------------------------------------------*/
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459 __asm void xPortPendSVHandler( void )
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461 extern uxCriticalNesting;
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462 extern pxCurrentTCB;
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463 extern vTaskSwitchContext;
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469 /* Get the location of the current TCB. */
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470 ldr r3, =pxCurrentTCB
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473 /* Is the task using the FPU context? If so, push high vfp registers. */
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476 vstmdbeq r0!, {s16-s31}
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478 /* Save the core registers. */
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479 stmdb r0!, {r4-r11, r14}
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481 /* Save the new top of stack into the first member of the TCB. */
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485 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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489 bl vTaskSwitchContext
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494 /* The first item in pxCurrentTCB is the task top of stack. */
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498 /* Pop the core registers. */
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499 ldmia r0!, {r4-r11, r14}
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501 /* Is the task using the FPU context? If so, pop the high vfp registers
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505 vldmiaeq r0!, {s16-s31}
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509 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
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510 #if WORKAROUND_PMU_CM001 == 1
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520 /*-----------------------------------------------------------*/
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522 void xPortSysTickHandler( void )
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524 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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525 executes all interrupts must be unmasked. There is therefore no need to
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526 save and then restore the interrupt mask value as its value is already
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528 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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530 /* Increment the RTOS tick. */
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531 if( xTaskIncrementTick() != pdFALSE )
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533 /* A context switch is required. Context switching is performed in
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534 the PendSV interrupt. Pend the PendSV interrupt. */
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535 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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538 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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540 /*-----------------------------------------------------------*/
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542 #if configUSE_TICKLESS_IDLE == 1
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544 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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546 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
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547 TickType_t xModifiableIdleTime;
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549 /* Make sure the SysTick reload value does not overflow the counter. */
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550 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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552 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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555 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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556 is accounted for as best it can be, but using the tickless mode will
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557 inevitably result in some tiny drift of the time maintained by the
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558 kernel with respect to calendar time. */
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559 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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561 /* Calculate the reload value required to wait xExpectedIdleTime
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562 tick periods. -1 is used because this code will execute part way
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563 through one of the tick periods. */
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564 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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565 if( ulReloadValue > ulStoppedTimerCompensation )
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567 ulReloadValue -= ulStoppedTimerCompensation;
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570 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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571 method as that will mask interrupts that should exit sleep mode. */
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574 /* If a context switch is pending or a task is waiting for the scheduler
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575 to be unsuspended then abandon the low power entry. */
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576 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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578 /* Restart from whatever is left in the count register to complete
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579 this tick period. */
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580 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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582 /* Restart SysTick. */
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583 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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585 /* Reset the reload register to the value required for normal tick
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587 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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589 /* Re-enable interrupts - see comments above __disable_irq() call
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595 /* Set the new reload value. */
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596 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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598 /* Clear the SysTick count flag and set the count value back to
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600 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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602 /* Restart SysTick. */
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603 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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605 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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606 set its parameter to 0 to indicate that its implementation contains
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607 its own wait for interrupt or wait for event instruction, and so wfi
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608 should not be executed again. However, the original expected idle
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609 time variable must remain unmodified, so a copy is taken. */
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610 xModifiableIdleTime = xExpectedIdleTime;
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611 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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612 if( xModifiableIdleTime > 0 )
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614 __dsb( portSY_FULL_READ_WRITE );
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616 __isb( portSY_FULL_READ_WRITE );
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618 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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620 /* Stop SysTick. Again, the time the SysTick is stopped for is
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621 accounted for as best it can be, but using the tickless mode will
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622 inevitably result in some tiny drift of the time maintained by the
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623 kernel with respect to calendar time. */
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624 ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
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625 portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
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627 /* Re-enable interrupts - see comments above __disable_irq() call
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631 if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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633 uint32_t ulCalculatedLoadValue;
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635 /* The tick interrupt has already executed, and the SysTick
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636 count reloaded with ulReloadValue. Reset the
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637 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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639 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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641 /* Don't allow a tiny value, or values that have somehow
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642 underflowed because the post sleep hook did something
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643 that took too long. */
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644 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
646 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
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649 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
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651 /* The tick interrupt handler will already have pended the tick
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652 processing in the kernel. As the pending tick will be
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653 processed as soon as this function exits, the tick value
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654 maintained by the tick is stepped forward by one less than the
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655 time spent waiting. */
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656 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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660 /* Something other than the tick interrupt ended the sleep.
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661 Work out how long the sleep lasted rounded to complete tick
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662 periods (not the ulReload value which accounted for part
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664 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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666 /* How many complete tick periods passed while the processor
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668 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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670 /* The reload value is set to whatever fraction of a single tick
\r
672 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
675 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
676 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
677 value. The critical section is used to ensure the tick interrupt
\r
678 can only execute once in the case that the reload register is near
\r
680 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
681 portENTER_CRITICAL();
\r
683 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
684 vTaskStepTick( ulCompleteTickPeriods );
\r
685 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
687 portEXIT_CRITICAL();
\r
691 #endif /* #if configUSE_TICKLESS_IDLE */
\r
693 /*-----------------------------------------------------------*/
\r
696 * Setup the SysTick timer to generate the tick interrupts at the required
\r
699 #if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0
\r
701 void vPortSetupTimerInterrupt( void )
\r
703 /* Calculate the constants required to configure the tick interrupt. */
\r
704 #if configUSE_TICKLESS_IDLE == 1
\r
706 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
707 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
708 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
710 #endif /* configUSE_TICKLESS_IDLE */
\r
712 /* Configure SysTick to interrupt at the requested rate. */
\r
713 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
714 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
717 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
\r
718 /*-----------------------------------------------------------*/
\r
720 __asm uint32_t vPortGetIPSR( void )
\r
727 /*-----------------------------------------------------------*/
\r
729 #if( configASSERT_DEFINED == 1 )
\r
731 void vPortValidateInterruptPriority( void )
\r
733 uint32_t ulCurrentInterrupt;
\r
734 uint8_t ucCurrentPriority;
\r
736 /* Obtain the number of the currently executing interrupt. */
\r
737 ulCurrentInterrupt = vPortGetIPSR();
\r
739 /* Is the interrupt number a user defined interrupt? */
\r
740 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
742 /* Look up the interrupt's priority. */
\r
743 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
745 /* The following assertion will fail if a service routine (ISR) for
\r
746 an interrupt that has been assigned a priority above
\r
747 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
748 function. ISR safe FreeRTOS API functions must *only* be called
\r
749 from interrupts that have been assigned a priority at or below
\r
750 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
752 Numerically low interrupt priority numbers represent logically high
\r
753 interrupt priorities, therefore the priority of the interrupt must
\r
754 be set to a value equal to or numerically *higher* than
\r
755 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
757 Interrupts that use the FreeRTOS API must not be left at their
\r
758 default priority of zero as that is the highest possible priority,
\r
759 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
760 and therefore also guaranteed to be invalid.
\r
762 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
763 interrupt entry is as fast and simple as possible.
\r
765 The following links provide detailed information:
\r
766 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
767 http://www.freertos.org/FAQHelp.html */
\r
768 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
771 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
772 that define each interrupt's priority to be split between bits that
\r
773 define the interrupt's pre-emption priority bits and bits that define
\r
774 the interrupt's sub-priority. For simplicity all bits must be defined
\r
775 to be pre-emption priority bits. The following assertion will fail if
\r
776 this is not the case (if some bits represent a sub-priority).
\r
778 If the application only uses CMSIS libraries for interrupt
\r
779 configuration then the correct setting can be achieved on all Cortex-M
\r
780 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
781 scheduler. Note however that some vendor specific peripheral libraries
\r
782 assume a non-zero priority group setting, in which cases using a value
\r
783 of zero will result in unpredicable behaviour. */
\r
784 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
787 #endif /* configASSERT_DEFINED */
\r