2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Implementation of functions defined in portable.h for the ARM CM4F port.
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31 *----------------------------------------------------------*/
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33 /* Scheduler includes. */
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34 #include "FreeRTOS.h"
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37 #ifndef __TARGET_FPU_VFP
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38 #error This port can only be used when the project options are configured to enable hardware floating point support.
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41 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
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42 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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45 #ifndef configSYSTICK_CLOCK_HZ
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46 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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47 /* Ensure the SysTick is clocked at the same frequency as the core. */
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48 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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50 /* The way the SysTick is clocked is not modified in case it is not the same
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52 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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55 /* The __weak attribute does not work as you might expect with the Keil tools
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56 so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
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57 the application writer wants to provide their own implementation of
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58 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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60 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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61 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
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64 /* Constants required to manipulate the core. Registers first... */
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65 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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66 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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67 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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68 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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69 /* ...then bits in the registers. */
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70 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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71 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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72 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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73 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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74 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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76 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
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78 #define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
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79 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
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80 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
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82 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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83 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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85 /* Constants required to check the validity of an interrupt priority. */
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86 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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87 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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88 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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89 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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90 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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91 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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92 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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93 #define portPRIGROUP_SHIFT ( 8UL )
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95 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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96 #define portVECTACTIVE_MASK ( 0xFFUL )
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98 /* Constants required to manipulate the VFP. */
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99 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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100 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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102 /* Constants required to set up the initial stack. */
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103 #define portINITIAL_XPSR ( 0x01000000 )
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104 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
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106 /* The systick is a 24-bit counter. */
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107 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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109 /* A fiddle factor to estimate the number of SysTick counts that would have
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110 occurred while the SysTick counter is stopped during tickless idle
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112 #define portMISSED_COUNTS_FACTOR ( 45UL )
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114 /* For strict compliance with the Cortex-M spec the task start address should
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115 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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116 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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119 * Setup the timer to generate the tick interrupts. The implementation in this
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120 * file is weak to allow application writers to change the timer used to
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121 * generate the tick interrupt.
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123 void vPortSetupTimerInterrupt( void );
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126 * Exception handlers.
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128 void xPortPendSVHandler( void );
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129 void xPortSysTickHandler( void );
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130 void vPortSVCHandler( void );
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133 * Start first task is a separate function so it can be tested in isolation.
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135 static void prvStartFirstTask( void );
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138 * Functions defined in portasm.s to enable the VFP.
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140 static void prvEnableVFP( void );
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143 * Used to catch tasks that attempt to return from their implementing function.
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145 static void prvTaskExitError( void );
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147 /*-----------------------------------------------------------*/
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149 /* Each task maintains its own interrupt status in the critical nesting
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151 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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154 * The number of SysTick increments that make up one tick period.
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156 #if( configUSE_TICKLESS_IDLE == 1 )
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157 static uint32_t ulTimerCountsForOneTick = 0;
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158 #endif /* configUSE_TICKLESS_IDLE */
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161 * The maximum number of tick periods that can be suppressed is limited by the
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162 * 24 bit resolution of the SysTick timer.
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164 #if( configUSE_TICKLESS_IDLE == 1 )
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165 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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166 #endif /* configUSE_TICKLESS_IDLE */
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169 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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170 * power functionality only.
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172 #if( configUSE_TICKLESS_IDLE == 1 )
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173 static uint32_t ulStoppedTimerCompensation = 0;
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174 #endif /* configUSE_TICKLESS_IDLE */
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177 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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178 * FreeRTOS API functions are not called from interrupts that have been assigned
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179 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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181 #if ( configASSERT_DEFINED == 1 )
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182 static uint8_t ucMaxSysCallPriority = 0;
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183 static uint32_t ulMaxPRIGROUPValue = 0;
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184 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
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185 #endif /* configASSERT_DEFINED */
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187 /*-----------------------------------------------------------*/
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190 * See header file for description.
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192 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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194 /* Simulate the stack frame as it would be created by a context switch
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197 /* Offset added to account for the way the MCU uses the stack on entry/exit
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198 of interrupts, and to ensure alignment. */
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201 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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203 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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205 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
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207 /* Save code space by skipping register initialisation. */
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208 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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209 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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211 /* A save method is being used that requires each task to maintain its
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212 own exec return value. */
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214 *pxTopOfStack = portINITIAL_EXC_RETURN;
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216 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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218 return pxTopOfStack;
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220 /*-----------------------------------------------------------*/
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222 static void prvTaskExitError( void )
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224 /* A function that implements a task must not exit or attempt to return to
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225 its caller as there is nothing to return to. If a task wants to exit it
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226 should instead call vTaskDelete( NULL ).
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228 Artificially force an assert() to be triggered if configASSERT() is
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229 defined, then stop here so application writers can catch the error. */
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230 configASSERT( uxCriticalNesting == ~0UL );
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231 portDISABLE_INTERRUPTS();
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234 /*-----------------------------------------------------------*/
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236 __asm void vPortSVCHandler( void )
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240 /* Get the location of the current TCB. */
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241 ldr r3, =pxCurrentTCB
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244 /* Pop the core registers. */
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245 ldmia r0!, {r4-r11, r14}
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252 /*-----------------------------------------------------------*/
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254 __asm void prvStartFirstTask( void )
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258 /* Use the NVIC offset register to locate the stack. */
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259 ldr r0, =0xE000ED08
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262 /* Set the msp back to the start of the stack. */
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264 /* Clear the bit that indicates the FPU is in use in case the FPU was used
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265 before the scheduler was started - which would otherwise result in the
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266 unnecessary leaving of space in the SVC stack for lazy saving of FPU
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270 /* Globally enable interrupts. */
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275 /* Call SVC to start the first task. */
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280 /*-----------------------------------------------------------*/
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282 __asm void prvEnableVFP( void )
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286 /* The FPU enable bits are in the CPACR. */
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287 ldr.w r0, =0xE000ED88
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290 /* Enable CP10 and CP11 coprocessors, then save back. */
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291 orr r1, r1, #( 0xf << 20 )
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296 /*-----------------------------------------------------------*/
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299 * See header file for description.
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301 BaseType_t xPortStartScheduler( void )
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303 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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304 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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305 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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307 /* This port can be used on all revisions of the Cortex-M7 core other than
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308 the r0p1 parts. r0p1 parts should use the port from the
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309 /source/portable/GCC/ARM_CM7/r0p1 directory. */
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310 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
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311 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
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313 #if( configASSERT_DEFINED == 1 )
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315 volatile uint32_t ulOriginalPriority;
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316 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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317 volatile uint8_t ucMaxPriorityValue;
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319 /* Determine the maximum priority from which ISR safe FreeRTOS API
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320 functions can be called. ISR safe functions are those that end in
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321 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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322 ensure interrupt entry is as fast and simple as possible.
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324 Save the interrupt priority value that is about to be clobbered. */
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325 ulOriginalPriority = *pucFirstUserPriorityRegister;
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327 /* Determine the number of priority bits available. First write to all
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329 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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331 /* Read the value back to see how many bits stuck. */
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332 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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334 /* The kernel interrupt priority should be set to the lowest
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336 configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
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338 /* Use the same mask on the maximum system call priority. */
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339 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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341 /* Calculate the maximum acceptable priority group value for the number
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342 of bits read back. */
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343 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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344 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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346 ulMaxPRIGROUPValue--;
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347 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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350 #ifdef __NVIC_PRIO_BITS
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352 /* Check the CMSIS configuration that defines the number of
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353 priority bits matches the number of priority bits actually queried
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354 from the hardware. */
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355 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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359 #ifdef configPRIO_BITS
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361 /* Check the FreeRTOS configuration that defines the number of
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362 priority bits matches the number of priority bits actually queried
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363 from the hardware. */
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364 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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368 /* Shift the priority group value back to its position within the AIRCR
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370 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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371 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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373 /* Restore the clobbered interrupt priority register to its original
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375 *pucFirstUserPriorityRegister = ulOriginalPriority;
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377 #endif /* conifgASSERT_DEFINED */
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379 /* Make PendSV and SysTick the lowest priority interrupts. */
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380 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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381 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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383 /* Start the timer that generates the tick ISR. Interrupts are disabled
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385 vPortSetupTimerInterrupt();
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387 /* Initialise the critical nesting count ready for the first task. */
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388 uxCriticalNesting = 0;
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390 /* Ensure the VFP is enabled - it should be anyway. */
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393 /* Lazy save always. */
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394 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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396 /* Start the first task. */
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397 prvStartFirstTask();
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399 /* Should not get here! */
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402 /*-----------------------------------------------------------*/
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404 void vPortEndScheduler( void )
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406 /* Not implemented in ports where there is nothing to return to.
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407 Artificially force an assert. */
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408 configASSERT( uxCriticalNesting == 1000UL );
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410 /*-----------------------------------------------------------*/
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412 void vPortEnterCritical( void )
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414 portDISABLE_INTERRUPTS();
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415 uxCriticalNesting++;
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417 /* This is not the interrupt safe version of the enter critical function so
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418 assert() if it is being called from an interrupt context. Only API
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419 functions that end in "FromISR" can be used in an interrupt. Only assert if
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420 the critical nesting count is 1 to protect against recursive calls if the
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421 assert function also uses a critical section. */
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422 if( uxCriticalNesting == 1 )
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424 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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427 /*-----------------------------------------------------------*/
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429 void vPortExitCritical( void )
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431 configASSERT( uxCriticalNesting );
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432 uxCriticalNesting--;
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433 if( uxCriticalNesting == 0 )
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435 portENABLE_INTERRUPTS();
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438 /*-----------------------------------------------------------*/
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440 __asm void xPortPendSVHandler( void )
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442 extern uxCriticalNesting;
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443 extern pxCurrentTCB;
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444 extern vTaskSwitchContext;
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450 /* Get the location of the current TCB. */
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451 ldr r3, =pxCurrentTCB
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454 /* Is the task using the FPU context? If so, push high vfp registers. */
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457 vstmdbeq r0!, {s16-s31}
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459 /* Save the core registers. */
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460 stmdb r0!, {r4-r11, r14}
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462 /* Save the new top of stack into the first member of the TCB. */
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465 stmdb sp!, {r0, r3}
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466 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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470 bl vTaskSwitchContext
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473 ldmia sp!, {r0, r3}
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475 /* The first item in pxCurrentTCB is the task top of stack. */
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479 /* Pop the core registers. */
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480 ldmia r0!, {r4-r11, r14}
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482 /* Is the task using the FPU context? If so, pop the high vfp registers
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486 vldmiaeq r0!, {s16-s31}
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490 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
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491 #if WORKAROUND_PMU_CM001 == 1
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500 /*-----------------------------------------------------------*/
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502 void xPortSysTickHandler( void )
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504 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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505 executes all interrupts must be unmasked. There is therefore no need to
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506 save and then restore the interrupt mask value as its value is already
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507 known - therefore the slightly faster vPortRaiseBASEPRI() function is used
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508 in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
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509 vPortRaiseBASEPRI();
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511 /* Increment the RTOS tick. */
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512 if( xTaskIncrementTick() != pdFALSE )
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514 /* A context switch is required. Context switching is performed in
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515 the PendSV interrupt. Pend the PendSV interrupt. */
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516 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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519 vPortClearBASEPRIFromISR();
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521 /*-----------------------------------------------------------*/
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523 #if( configUSE_TICKLESS_IDLE == 1 )
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525 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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527 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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528 TickType_t xModifiableIdleTime;
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530 /* Make sure the SysTick reload value does not overflow the counter. */
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531 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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533 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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536 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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537 is accounted for as best it can be, but using the tickless mode will
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538 inevitably result in some tiny drift of the time maintained by the
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539 kernel with respect to calendar time. */
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540 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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542 /* Calculate the reload value required to wait xExpectedIdleTime
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543 tick periods. -1 is used because this code will execute part way
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544 through one of the tick periods. */
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545 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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546 if( ulReloadValue > ulStoppedTimerCompensation )
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548 ulReloadValue -= ulStoppedTimerCompensation;
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551 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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552 method as that will mask interrupts that should exit sleep mode. */
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554 __dsb( portSY_FULL_READ_WRITE );
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555 __isb( portSY_FULL_READ_WRITE );
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557 /* If a context switch is pending or a task is waiting for the scheduler
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558 to be unsuspended then abandon the low power entry. */
\r
559 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
561 /* Restart from whatever is left in the count register to complete
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562 this tick period. */
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563 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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565 /* Restart SysTick. */
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566 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
568 /* Reset the reload register to the value required for normal tick
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570 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
572 /* Re-enable interrupts - see comments above __disable_irq() call
\r
578 /* Set the new reload value. */
\r
579 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
581 /* Clear the SysTick count flag and set the count value back to
\r
583 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
585 /* Restart SysTick. */
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586 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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588 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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589 set its parameter to 0 to indicate that its implementation contains
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590 its own wait for interrupt or wait for event instruction, and so wfi
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591 should not be executed again. However, the original expected idle
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592 time variable must remain unmodified, so a copy is taken. */
\r
593 xModifiableIdleTime = xExpectedIdleTime;
\r
594 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
595 if( xModifiableIdleTime > 0 )
\r
597 __dsb( portSY_FULL_READ_WRITE );
\r
599 __isb( portSY_FULL_READ_WRITE );
\r
601 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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603 /* Re-enable interrupts to allow the interrupt that brought the MCU
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604 out of sleep mode to execute immediately. see comments above
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605 __disable_interrupt() call above. */
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607 __dsb( portSY_FULL_READ_WRITE );
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608 __isb( portSY_FULL_READ_WRITE );
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610 /* Disable interrupts again because the clock is about to be stopped
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611 and interrupts that execute while the clock is stopped will increase
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612 any slippage between the time maintained by the RTOS and calendar
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615 __dsb( portSY_FULL_READ_WRITE );
\r
616 __isb( portSY_FULL_READ_WRITE );
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618 /* Disable the SysTick clock without reading the
\r
619 portNVIC_SYSTICK_CTRL_REG register to ensure the
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620 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
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621 the time the SysTick is stopped for is accounted for as best it can
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622 be, but using the tickless mode will inevitably result in some tiny
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623 drift of the time maintained by the kernel with respect to calendar
\r
625 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
\r
627 /* Determine if the SysTick clock has already counted to zero and
\r
628 been set back to the current reload value (the reload back being
\r
629 correct for the entire expected idle time) or if the SysTick is yet
\r
630 to count to zero (in which case an interrupt other than the SysTick
\r
631 must have brought the system out of sleep mode). */
\r
632 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
634 uint32_t ulCalculatedLoadValue;
\r
636 /* The tick interrupt is already pending, and the SysTick count
\r
637 reloaded with ulReloadValue. Reset the
\r
638 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
640 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
642 /* Don't allow a tiny value, or values that have somehow
\r
643 underflowed because the post sleep hook did something
\r
644 that took too long. */
\r
645 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
647 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
650 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
652 /* As the pending tick will be processed as soon as this
\r
653 function exits, the tick value maintained by the tick is stepped
\r
654 forward by one less than the time spent waiting. */
\r
655 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
659 /* Something other than the tick interrupt ended the sleep.
\r
660 Work out how long the sleep lasted rounded to complete tick
\r
661 periods (not the ulReload value which accounted for part
\r
663 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
665 /* How many complete tick periods passed while the processor
\r
667 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
669 /* The reload value is set to whatever fraction of a single tick
\r
671 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
674 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
675 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
677 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
678 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
679 vTaskStepTick( ulCompleteTickPeriods );
\r
680 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
682 /* Exit with interrpts enabled. */
\r
687 #endif /* #if configUSE_TICKLESS_IDLE */
\r
689 /*-----------------------------------------------------------*/
\r
692 * Setup the SysTick timer to generate the tick interrupts at the required
\r
695 #if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
\r
697 void vPortSetupTimerInterrupt( void )
\r
699 /* Calculate the constants required to configure the tick interrupt. */
\r
700 #if( configUSE_TICKLESS_IDLE == 1 )
\r
702 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
703 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
704 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
706 #endif /* configUSE_TICKLESS_IDLE */
\r
708 /* Stop and clear the SysTick. */
\r
709 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
710 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
712 /* Configure SysTick to interrupt at the requested rate. */
\r
713 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
714 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
717 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
\r
718 /*-----------------------------------------------------------*/
\r
720 __asm uint32_t vPortGetIPSR( void )
\r
727 /*-----------------------------------------------------------*/
\r
729 #if( configASSERT_DEFINED == 1 )
\r
731 void vPortValidateInterruptPriority( void )
\r
733 uint32_t ulCurrentInterrupt;
\r
734 uint8_t ucCurrentPriority;
\r
736 /* Obtain the number of the currently executing interrupt. */
\r
737 ulCurrentInterrupt = vPortGetIPSR();
\r
739 /* Is the interrupt number a user defined interrupt? */
\r
740 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
742 /* Look up the interrupt's priority. */
\r
743 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
745 /* The following assertion will fail if a service routine (ISR) for
\r
746 an interrupt that has been assigned a priority above
\r
747 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
748 function. ISR safe FreeRTOS API functions must *only* be called
\r
749 from interrupts that have been assigned a priority at or below
\r
750 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
752 Numerically low interrupt priority numbers represent logically high
\r
753 interrupt priorities, therefore the priority of the interrupt must
\r
754 be set to a value equal to or numerically *higher* than
\r
755 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
757 Interrupts that use the FreeRTOS API must not be left at their
\r
758 default priority of zero as that is the highest possible priority,
\r
759 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
760 and therefore also guaranteed to be invalid.
\r
762 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
763 interrupt entry is as fast and simple as possible.
\r
765 The following links provide detailed information:
\r
766 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
767 http://www.freertos.org/FAQHelp.html */
\r
768 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
771 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
772 that define each interrupt's priority to be split between bits that
\r
773 define the interrupt's pre-emption priority bits and bits that define
\r
774 the interrupt's sub-priority. For simplicity all bits must be defined
\r
775 to be pre-emption priority bits. The following assertion will fail if
\r
776 this is not the case (if some bits represent a sub-priority).
\r
778 If the application only uses CMSIS libraries for interrupt
\r
779 configuration then the correct setting can be achieved on all Cortex-M
\r
780 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
781 scheduler. Note however that some vendor specific peripheral libraries
\r
782 assume a non-zero priority group setting, in which cases using a value
\r
783 of zero will result in unpredictable behaviour. */
\r
784 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
787 #endif /* configASSERT_DEFINED */
\r