2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Implementation of functions defined in portable.h for the RX100 port.
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31 *----------------------------------------------------------*/
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33 /* Standard C includes. */
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36 /* Scheduler includes. */
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37 #include "FreeRTOS.h"
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40 /* Library includes. */
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43 /* Hardware specifics. */
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44 #include "iodefine.h"
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46 /*-----------------------------------------------------------*/
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48 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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49 PSW is set with U and I set, and PM and IPL clear. */
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50 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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52 /* The peripheral clock is divided by this value before being supplying the
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54 #if ( configUSE_TICKLESS_IDLE == 0 )
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55 /* If tickless idle is not used then the divisor can be fixed. */
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56 #define portCLOCK_DIVISOR 8UL
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57 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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58 #define portCLOCK_DIVISOR 512UL
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59 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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60 #define portCLOCK_DIVISOR 128UL
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61 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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62 #define portCLOCK_DIVISOR 32UL
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64 #define portCLOCK_DIVISOR 8UL
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68 /* Keys required to lock and unlock access to certain system registers
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70 #define portUNLOCK_KEY 0xA50B
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71 #define portLOCK_KEY 0xA500
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73 /*-----------------------------------------------------------*/
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75 /* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
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76 and therefore installed in the vector table, when the FreeRTOS code is built
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78 extern BaseType_t vSoftwareInterruptEntry;
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79 const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
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81 /*-----------------------------------------------------------*/
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84 * Function to start the first task executing - written in asm code as direct
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85 * access to registers is required.
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87 static void prvStartFirstTask( void );
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90 * Software interrupt handler. Performs the actual context switch (saving and
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91 * restoring of registers). Written in asm code as direct register access is
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94 static void prvYieldHandler( void );
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97 * The entry point for the software interrupt handler. This is the function
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98 * that calls the inline asm function prvYieldHandler(). It is installed in
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99 * the vector table, but the code that installs it is in prvYieldHandler rather
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100 * than using a #pragma.
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102 void vSoftwareInterruptISR( void );
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105 * Sets up the periodic ISR used for the RTOS tick using the CMT.
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106 * The application writer can define configSETUP_TICK_INTERRUPT() (in
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107 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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108 * in place of prvSetupTimerInterrupt().
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110 static void prvSetupTimerInterrupt( void );
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111 #ifndef configSETUP_TICK_INTERRUPT
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112 /* The user has not provided their own tick interrupt configuration so use
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113 the definition in this file (which uses the interval timer). */
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114 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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115 #endif /* configSETUP_TICK_INTERRUPT */
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118 * Called after the sleep mode registers have been configured, prvSleep()
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119 * executes the pre and post sleep macros, and actually calls the wait
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122 #if configUSE_TICKLESS_IDLE == 1
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123 static void prvSleep( TickType_t xExpectedIdleTime );
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124 #endif /* configUSE_TICKLESS_IDLE */
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126 /*-----------------------------------------------------------*/
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128 /* These is accessed by the inline assembler functions. */
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129 extern void *pxCurrentTCB;
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130 extern void vTaskSwitchContext( void );
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132 /*-----------------------------------------------------------*/
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134 /* Calculate how many clock increments make up a single tick period. */
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135 static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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137 #if configUSE_TICKLESS_IDLE == 1
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139 /* Holds the maximum number of ticks that can be suppressed - which is
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140 basically how far into the future an interrupt can be generated. Set
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141 during initialisation. This is the maximum possible value that the
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142 compare match register can hold divided by ulMatchValueForOneTick. */
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143 static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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145 /* Flag set from the tick interrupt to allow the sleep processing to know if
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146 sleep mode was exited because of a tick interrupt, or an interrupt
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147 generated by something else. */
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148 static volatile uint32_t ulTickFlag = pdFALSE;
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150 /* The CMT counter is stopped temporarily each time it is re-programmed.
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151 The following constant offsets the CMT counter match value by the number of
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152 CMT counts that would typically be missed while the counter was stopped to
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153 compensate for the lost time. The large difference between the divided CMT
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154 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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155 equal zero - and be optimised away. */
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156 static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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160 /*-----------------------------------------------------------*/
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163 * See header file for description.
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165 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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167 /* Offset to end up on 8 byte boundary. */
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170 /* R0 is not included as it is the stack pointer. */
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171 *pxTopOfStack = 0x00;
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173 *pxTopOfStack = 0x00;
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175 *pxTopOfStack = portINITIAL_PSW;
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177 *pxTopOfStack = ( StackType_t ) pxCode;
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179 /* When debugging it can be useful if every register is set to a known
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180 value. Otherwise code space can be saved by just setting the registers
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181 that need to be set. */
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182 #ifdef USE_FULL_REGISTER_INITIALISATION
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185 *pxTopOfStack = 0x12345678; /* r15. */
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187 *pxTopOfStack = 0xaaaabbbb;
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189 *pxTopOfStack = 0xdddddddd;
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191 *pxTopOfStack = 0xcccccccc;
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193 *pxTopOfStack = 0xbbbbbbbb;
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195 *pxTopOfStack = 0xaaaaaaaa;
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197 *pxTopOfStack = 0x99999999;
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199 *pxTopOfStack = 0x88888888;
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201 *pxTopOfStack = 0x77777777;
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203 *pxTopOfStack = 0x66666666;
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205 *pxTopOfStack = 0x55555555;
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207 *pxTopOfStack = 0x44444444;
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209 *pxTopOfStack = 0x33333333;
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211 *pxTopOfStack = 0x22222222;
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216 /* Leave space for the registers that will get popped from the stack
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217 when the task first starts executing. */
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218 pxTopOfStack -= 15;
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222 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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224 *pxTopOfStack = 0x12345678; /* Accumulator. */
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226 *pxTopOfStack = 0x87654321; /* Accumulator. */
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228 return pxTopOfStack;
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230 /*-----------------------------------------------------------*/
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232 BaseType_t xPortStartScheduler( void )
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234 /* Use pxCurrentTCB just so it does not get optimised away. */
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235 if( pxCurrentTCB != NULL )
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237 /* Call an application function to set up the timer that will generate
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238 the tick interrupt. This way the application can decide which
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239 peripheral to use. If tickless mode is used then the default
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240 implementation defined in this file (which uses CMT0) should not be
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242 configSETUP_TICK_INTERRUPT();
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244 /* Enable the software interrupt. */
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245 _IEN( _ICU_SWINT ) = 1;
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247 /* Ensure the software interrupt is clear. */
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248 _IR( _ICU_SWINT ) = 0;
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250 /* Ensure the software interrupt is set to the kernel priority. */
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251 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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253 /* Start the first task. */
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254 prvStartFirstTask();
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257 /* Execution should not reach here as the tasks are now running!
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258 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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259 a warning about a statically declared function not being referenced in the
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260 case that the application writer has provided their own tick interrupt
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261 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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262 their own routine will be called in place of prvSetupTimerInterrupt()). */
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263 prvSetupTimerInterrupt();
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265 /* Just to make sure the function is not optimised away. */
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266 ( void ) vSoftwareInterruptISR();
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268 /* Should not get here. */
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271 /*-----------------------------------------------------------*/
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273 #pragma inline_asm prvStartFirstTask
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274 static void prvStartFirstTask( void )
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276 /* When starting the scheduler there is nothing that needs moving to the
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277 interrupt stack because the function is not called from an interrupt.
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278 Just ensure the current stack is the user stack. */
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281 /* Obtain the location of the stack associated with which ever task
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282 pxCurrentTCB is currently pointing to. */
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283 MOV.L #_pxCurrentTCB, R15
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287 /* Restore the registers from the stack of the task pointed to by
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290 MVTACLO R15 /* Accumulator low 32 bits. */
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292 MVTACHI R15 /* Accumulator high 32 bits. */
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293 POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */
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294 RTE /* This pops the remaining registers. */
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298 /*-----------------------------------------------------------*/
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300 #pragma interrupt ( prvTickISR( vect = configTICK_VECTOR, enable ) )
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301 void prvTickISR( void )
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303 /* Increment the tick, and perform any processing the new tick value
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305 set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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307 if( xTaskIncrementTick() != pdFALSE )
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312 set_ipl( configKERNEL_INTERRUPT_PRIORITY );
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314 #if configUSE_TICKLESS_IDLE == 1
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316 /* The CPU woke because of a tick. */
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317 ulTickFlag = pdTRUE;
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319 /* If this is the first tick since exiting tickless mode then the CMT
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320 compare match value needs resetting. */
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321 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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325 /*-----------------------------------------------------------*/
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327 void vSoftwareInterruptISR( void )
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331 /*-----------------------------------------------------------*/
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333 #pragma inline_asm prvYieldHandler
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334 static void prvYieldHandler( void )
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336 /* Re-enable interrupts. */
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339 /* Move the data that was automatically pushed onto the interrupt stack
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340 when the interrupt occurred from the interrupt stack to the user stack.
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342 R15 is saved before it is clobbered. */
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345 /* Read the user stack pointer. */
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348 /* Move the address down to the data being moved. */
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352 /* Copy the data across. */
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353 MOV.L [ R0 ], [ R15 ] ; R15
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354 MOV.L 4[ R0 ], 4[ R15 ] ; PC
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355 MOV.L 8[ R0 ], 8[ R15 ] ; PSW
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357 /* Move the interrupt stack pointer to its new correct position. */
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360 /* All the rest of the registers are saved directly to the user stack. */
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363 /* Save the rest of the general registers (R15 has been saved already). */
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366 /* Save the accumulator. */
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369 MVFACMI R15 ; Middle order word.
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370 SHLL #16, R15 ; Shifted left as it is restored to the low order word.
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373 /* Save the stack pointer to the TCB. */
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374 MOV.L #_pxCurrentTCB, R15
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378 /* Ensure the interrupt mask is set to the syscall priority while the
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379 kernel structures are being accessed. */
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380 MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
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382 /* Select the next task to run. */
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383 BSR.A _vTaskSwitchContext
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385 /* Reset the interrupt mask as no more data structure access is
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387 MVTIPL #configKERNEL_INTERRUPT_PRIORITY
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389 /* Load the stack pointer of the task that is now selected as the Running
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390 state task from its TCB. */
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391 MOV.L #_pxCurrentTCB,R15
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395 /* Restore the context of the new task. The PSW (Program Status Word) and
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396 PC will be popped by the RTE instruction. */
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406 /*-----------------------------------------------------------*/
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408 void vPortEndScheduler( void )
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410 /* Not implemented in ports where there is nothing to return to.
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411 Artificially force an assert. */
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412 configASSERT( pxCurrentTCB == NULL );
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414 /* The following line is just to prevent the symbol getting optimised away. */
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415 ( void ) vTaskSwitchContext();
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417 /*-----------------------------------------------------------*/
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419 static void prvSetupTimerInterrupt( void )
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422 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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428 SYSTEM.PRCR.WORD = portLOCK_KEY;
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430 /* Interrupt on compare match. */
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431 CMT0.CMCR.BIT.CMIE = 1;
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433 /* Set the compare match value. */
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434 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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436 /* Divide the PCLK. */
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437 #if portCLOCK_DIVISOR == 512
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439 CMT0.CMCR.BIT.CKS = 3;
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441 #elif portCLOCK_DIVISOR == 128
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443 CMT0.CMCR.BIT.CKS = 2;
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445 #elif portCLOCK_DIVISOR == 32
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447 CMT0.CMCR.BIT.CKS = 1;
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449 #elif portCLOCK_DIVISOR == 8
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451 CMT0.CMCR.BIT.CKS = 0;
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455 #error Invalid portCLOCK_DIVISOR setting
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460 /* Enable the interrupt... */
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461 _IEN( _CMT0_CMI0 ) = 1;
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463 /* ...and set its priority to the application defined kernel priority. */
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464 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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466 /* Start the timer. */
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467 CMT.CMSTR0.BIT.STR0 = 1;
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469 /*-----------------------------------------------------------*/
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471 #if configUSE_TICKLESS_IDLE == 1
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473 static void prvSleep( TickType_t xExpectedIdleTime )
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475 /* Allow the application to define some pre-sleep processing. */
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476 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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478 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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479 means the application defined code has already executed the WAIT
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481 if( xExpectedIdleTime > 0 )
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486 /* Allow the application to define some post sleep processing. */
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487 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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490 #endif /* configUSE_TICKLESS_IDLE */
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491 /*-----------------------------------------------------------*/
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493 #if configUSE_TICKLESS_IDLE == 1
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495 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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497 uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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498 eSleepModeStatus eSleepAction;
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500 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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502 /* Make sure the CMT reload value does not overflow the counter. */
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503 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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505 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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508 /* Calculate the reload value required to wait xExpectedIdleTime tick
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510 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
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511 if( ulMatchValue > ulStoppedTimerCompensation )
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513 /* Compensate for the fact that the CMT is going to be stopped
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515 ulMatchValue -= ulStoppedTimerCompensation;
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518 /* Stop the CMT momentarily. The time the CMT is stopped for is
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519 accounted for as best it can be, but using the tickless mode will
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520 inevitably result in some tiny drift of the time maintained by the
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521 kernel with respect to calendar time. */
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522 CMT.CMSTR0.BIT.STR0 = 0;
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523 while( CMT.CMSTR0.BIT.STR0 == 1 )
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525 /* Nothing to do here. */
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528 /* Critical section using the global interrupt bit as the i bit is
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529 automatically reset by the WAIT instruction. */
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532 /* The tick flag is set to false before sleeping. If it is true when
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533 sleep mode is exited then sleep mode was probably exited because the
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534 tick was suppressed for the entire xExpectedIdleTime period. */
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535 ulTickFlag = pdFALSE;
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537 /* If a context switch is pending then abandon the low power entry as
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538 the context switch might have been pended by an external interrupt that
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539 requires processing. */
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540 eSleepAction = eTaskConfirmSleepModeStatus();
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541 if( eSleepAction == eAbortSleep )
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543 /* Restart tick. */
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544 CMT.CMSTR0.BIT.STR0 = 1;
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547 else if( eSleepAction == eNoTasksWaitingTimeout )
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549 /* Protection off. */
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550 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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552 /* Ready for software standby with all clocks stopped. */
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553 SYSTEM.SBYCR.BIT.SSBY = 1;
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555 /* Protection on. */
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556 SYSTEM.PRCR.WORD = portLOCK_KEY;
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558 /* Sleep until something happens. Calling prvSleep() will
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559 automatically reset the i bit in the PSW. */
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560 prvSleep( xExpectedIdleTime );
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562 /* Restart the CMT. */
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563 CMT.CMSTR0.BIT.STR0 = 1;
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567 /* Protection off. */
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568 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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570 /* Ready for deep sleep mode. */
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571 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
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572 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
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573 SYSTEM.SBYCR.BIT.SSBY = 0;
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575 /* Protection on. */
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576 SYSTEM.PRCR.WORD = portLOCK_KEY;
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578 /* Adjust the match value to take into account that the current
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579 time slice is already partially complete. */
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580 ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
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581 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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583 /* Restart the CMT to count up to the new match value. */
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585 CMT.CMSTR0.BIT.STR0 = 1;
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587 /* Sleep until something happens. Calling prvSleep() will
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588 automatically reset the i bit in the PSW. */
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589 prvSleep( xExpectedIdleTime );
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591 /* Stop CMT. Again, the time the SysTick is stopped for is
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592 accounted for as best it can be, but using the tickless mode will
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593 inevitably result in some tiny drift of the time maintained by the
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594 kernel with respect to calendar time. */
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595 CMT.CMSTR0.BIT.STR0 = 0;
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596 while( CMT.CMSTR0.BIT.STR0 == 1 )
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598 /* Nothing to do here. */
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601 ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
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603 if( ulTickFlag != pdFALSE )
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605 /* The tick interrupt has already executed, although because
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606 this function is called with the scheduler suspended the actual
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607 tick processing will not occur until after this function has
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608 exited. Reset the match value with whatever remains of this
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610 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
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611 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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613 /* The tick interrupt handler will already have pended the tick
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614 processing in the kernel. As the pending tick will be
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615 processed as soon as this function exits, the tick value
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616 maintained by the tick is stepped forward by one less than the
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617 time spent sleeping. The actual stepping of the tick appears
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618 later in this function. */
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619 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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623 /* Something other than the tick interrupt ended the sleep.
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624 How many complete tick periods passed while the processor was
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626 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
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628 /* The match value is set to whatever fraction of a single tick
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630 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
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631 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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634 /* Restart the CMT so it runs up to the match value. The match value
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635 will get set to the value required to generate exactly one tick period
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636 the next time the CMT interrupt executes. */
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638 CMT.CMSTR0.BIT.STR0 = 1;
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640 /* Wind the tick forward by the number of tick periods that the CPU
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641 remained in a low power state. */
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642 vTaskStepTick( ulCompleteTickPeriods );
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646 #endif /* configUSE_TICKLESS_IDLE */
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