2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 >>! NOTE: The modification to the GPL is included to allow you to !<<
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14 >>! distribute a combined work that includes FreeRTOS without being !<<
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15 >>! obliged to provide the source code for proprietary components !<<
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16 >>! outside of the FreeRTOS kernel. !<<
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18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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21 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * Having a problem? Start by reading the FAQ "My application does *
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28 * not run, what could be wrong?". Have you defined configASSERT()? *
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30 * http://www.FreeRTOS.org/FAQHelp.html *
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32 ***************************************************************************
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34 ***************************************************************************
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36 * FreeRTOS provides completely free yet professionally developed, *
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37 * robust, strictly quality controlled, supported, and cross *
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38 * platform software that is more than just the market leader, it *
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39 * is the industry's de facto standard. *
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41 * Help yourself get started quickly while simultaneously helping *
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42 * to support the FreeRTOS project by purchasing a FreeRTOS *
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43 * tutorial book, reference manual, or both: *
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44 * http://www.FreeRTOS.org/Documentation *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * Investing in training allows your team to be as productive as *
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51 * possible as early as possible, lowering your overall development *
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52 * cost, and enabling you to bring a more robust product to market *
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53 * earlier than would otherwise be possible. Richard Barry is both *
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54 * the architect and key author of FreeRTOS, and so also the world's *
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55 * leading authority on what is the world's most popular real time *
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56 * kernel for deeply embedded MCU designs. Obtaining your training *
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57 * from Richard ensures your team will gain directly from his in-depth *
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58 * product knowledge and years of usage experience. Contact Real Time *
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59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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60 * by Richard Barry: http://www.FreeRTOS.org/contact
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62 ***************************************************************************
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64 ***************************************************************************
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66 * You are receiving this top quality software for free. Please play *
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67 * fair and reciprocate by reporting any suspected issues and *
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68 * participating in the community forum: *
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69 * http://www.FreeRTOS.org/support *
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73 ***************************************************************************
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75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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76 license and Real Time Engineers Ltd. contact details.
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78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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87 licenses offer ticketed support, indemnification and commercial middleware.
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89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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90 engineered and independently SIL3 certified version for use in safety and
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91 mission critical applications that require provable dependability.
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96 /*-----------------------------------------------------------
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97 * Implementation of functions defined in portable.h for the Cygnal port.
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98 *----------------------------------------------------------*/
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100 /* Standard includes. */
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101 #include <string.h>
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103 /* Scheduler includes. */
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104 #include "FreeRTOS.h"
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107 /* Constants required to setup timer 2 to produce the RTOS tick. */
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108 #define portCLOCK_DIVISOR ( ( uint32_t ) 12 )
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109 #define portMAX_TIMER_VALUE ( ( uint32_t ) 0xffff )
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110 #define portENABLE_TIMER ( ( uint8_t ) 0x04 )
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111 #define portTIMER_2_INTERRUPT_ENABLE ( ( uint8_t ) 0x20 )
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113 /* The value used in the IE register when a task first starts. */
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114 #define portGLOBAL_INTERRUPT_BIT ( ( StackType_t ) 0x80 )
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116 /* The value used in the PSW register when a task first starts. */
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117 #define portINITIAL_PSW ( ( StackType_t ) 0x00 )
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119 /* Macro to clear the timer 2 interrupt flag. */
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120 #define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80;
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122 /* Used during a context switch to store the size of the stack being copied
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123 to or from XRAM. */
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124 data static uint8_t ucStackBytes;
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126 /* Used during a context switch to point to the next byte in XRAM from/to which
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127 a RAM byte is to be copied. */
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128 xdata static StackType_t * data pxXRAMStack;
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130 /* Used during a context switch to point to the next byte in RAM from/to which
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131 an XRAM byte is to be copied. */
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132 data static StackType_t * data pxRAMStack;
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134 /* We require the address of the pxCurrentTCB variable, but don't want to know
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135 any details of its type. */
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136 typedef void TCB_t;
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137 extern volatile TCB_t * volatile pxCurrentTCB;
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140 * Setup the hardware to generate an interrupt off timer 2 at the required
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143 static void prvSetupTimerInterrupt( void );
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145 /*-----------------------------------------------------------*/
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147 * Macro that copies the current stack from internal RAM to XRAM. This is
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148 * required as the 8051 only contains enough internal RAM for a single stack,
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149 * but we have a stack for every task.
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151 #define portCOPY_STACK_TO_XRAM() \
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153 /* pxCurrentTCB points to a TCB which itself points to the location into \
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154 which the first stack byte should be copied. Set pxXRAMStack to point \
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155 to the location into which the first stack byte is to be copied. */ \
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156 pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
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158 /* Set pxRAMStack to point to the first byte to be coped from the stack. */ \
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159 pxRAMStack = ( data StackType_t * data ) configSTACK_START; \
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161 /* Calculate the size of the stack we are about to copy from the current \
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162 stack pointer value. */ \
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163 ucStackBytes = SP - ( configSTACK_START - 1 ); \
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165 /* Before starting to copy the stack, store the calculated stack size so \
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166 the stack can be restored when the task is resumed. */ \
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167 *pxXRAMStack = ucStackBytes; \
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169 /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \
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170 have already stored the stack size into XRAM. */ \
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171 while( ucStackBytes ) \
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174 *pxXRAMStack = *pxRAMStack; \
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179 /*-----------------------------------------------------------*/
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182 * Macro that copies the stack of the task being resumed from XRAM into
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185 #define portCOPY_XRAM_TO_STACK() \
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187 /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \
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188 copy the data back out of XRAM and into the stack. */ \
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189 pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
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190 pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 ); \
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192 /* The first value stored in XRAM was the size of the stack - i.e. the \
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193 number of bytes we need to copy back. */ \
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194 ucStackBytes = pxXRAMStack[ 0 ]; \
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196 /* Copy the required number of bytes back into the stack. */ \
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201 *pxRAMStack = *pxXRAMStack; \
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203 } while( ucStackBytes ); \
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205 /* Restore the stack pointer ready to use the restored stack. */ \
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206 SP = ( uint8_t ) pxRAMStack; \
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208 /*-----------------------------------------------------------*/
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211 * Macro to push the current execution context onto the stack, before the stack
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212 * is moved to XRAM.
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214 #define portSAVE_CONTEXT() \
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217 /* Push ACC first, as when restoring the context it must be restored \
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218 last (it is used to set the IE register). */ \
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220 /* Store the IE register then disable interrupts. */ \
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241 /*-----------------------------------------------------------*/
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244 * Macro that restores the execution context from the stack. The execution
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245 * context was saved into the stack before the stack was copied into XRAM.
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247 #define portRESTORE_CONTEXT() \
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263 /* The next byte of the stack is the IE register. Only the global \
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264 enable bit forms part of the task context. Pop off the IE then set \
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265 the global enable bit to match that of the stored IE register. */ \
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273 /* Finally pop off the ACC, which was the first register saved. */ \
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278 /*-----------------------------------------------------------*/
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281 * See header file for description.
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283 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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285 uint32_t ulAddress;
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286 StackType_t *pxStartOfStack;
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288 /* Leave space to write the size of the stack as the first byte. */
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289 pxStartOfStack = pxTopOfStack;
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292 /* Place a few bytes of known values on the bottom of the stack.
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293 This is just useful for debugging and can be uncommented if required.
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294 *pxTopOfStack = 0x11;
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296 *pxTopOfStack = 0x22;
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298 *pxTopOfStack = 0x33;
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302 /* Simulate how the stack would look after a call to the scheduler tick
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305 The return address that would have been pushed by the MCU. */
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306 ulAddress = ( uint32_t ) pxCode;
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307 *pxTopOfStack = ( StackType_t ) ulAddress;
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310 *pxTopOfStack = ( StackType_t ) ( ulAddress );
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313 /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
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314 *pxTopOfStack = 0xaa; /* acc */
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317 /* We want tasks to start with interrupts enabled. */
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318 *pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
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321 /* The function parameters will be passed in the DPTR and B register as
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322 a three byte generic pointer is used. */
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323 ulAddress = ( uint32_t ) pvParameters;
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324 *pxTopOfStack = ( StackType_t ) ulAddress; /* DPL */
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327 *pxTopOfStack = ( StackType_t ) ulAddress; /* DPH */
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330 *pxTopOfStack = ( StackType_t ) ulAddress; /* b */
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333 /* The remaining registers are straight forward. */
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334 *pxTopOfStack = 0x02; /* R2 */
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336 *pxTopOfStack = 0x03; /* R3 */
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338 *pxTopOfStack = 0x04; /* R4 */
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340 *pxTopOfStack = 0x05; /* R5 */
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342 *pxTopOfStack = 0x06; /* R6 */
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344 *pxTopOfStack = 0x07; /* R7 */
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346 *pxTopOfStack = 0x00; /* R0 */
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348 *pxTopOfStack = 0x01; /* R1 */
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350 *pxTopOfStack = 0x00; /* PSW */
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352 *pxTopOfStack = 0xbb; /* BP */
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354 /* Dont increment the stack size here as we don't want to include
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355 the stack size byte as part of the stack size count.
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357 Finally we place the stack size at the beginning. */
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358 *pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
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360 /* Unlike most ports, we return the start of the stack as this is where the
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361 size of the stack is stored. */
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362 return pxStartOfStack;
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364 /*-----------------------------------------------------------*/
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367 * See header file for description.
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369 BaseType_t xPortStartScheduler( void )
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371 /* Setup timer 2 to generate the RTOS tick. */
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372 prvSetupTimerInterrupt();
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374 /* Make sure we start with the expected SFR page. This line should not
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375 really be required. */
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378 /* Copy the stack for the first task to execute from XRAM into the stack,
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379 restore the task context from the new stack, then start running the task. */
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380 portCOPY_XRAM_TO_STACK();
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381 portRESTORE_CONTEXT();
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383 /* Should never get here! */
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386 /*-----------------------------------------------------------*/
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388 void vPortEndScheduler( void )
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390 /* Not implemented for this port. */
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392 /*-----------------------------------------------------------*/
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395 * Manual context switch. The first thing we do is save the registers so we
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396 * can use a naked attribute.
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398 void vPortYield( void ) _naked
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400 /* Save the execution context onto the stack, then copy the entire stack
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401 to XRAM. This is necessary as the internal RAM is only large enough to
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402 hold one stack, and we want one per task.
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404 PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
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406 portSAVE_CONTEXT();
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407 portCOPY_STACK_TO_XRAM();
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409 /* Call the standard scheduler context switch function. */
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410 vTaskSwitchContext();
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412 /* Copy the stack of the task about to execute from XRAM into RAM and
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413 restore it's context ready to run on exiting. */
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414 portCOPY_XRAM_TO_STACK();
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415 portRESTORE_CONTEXT();
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417 /*-----------------------------------------------------------*/
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419 #if configUSE_PREEMPTION == 1
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420 void vTimer2ISR( void ) interrupt 5 _naked
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422 /* Preemptive context switch function triggered by the timer 2 ISR.
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423 This does the same as vPortYield() (see above) with the addition
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424 of incrementing the RTOS tick count. */
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426 portSAVE_CONTEXT();
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427 portCOPY_STACK_TO_XRAM();
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429 if( xTaskIncrementTick() != pdFALSE )
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431 vTaskSwitchContext();
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434 portCLEAR_INTERRUPT_FLAG();
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435 portCOPY_XRAM_TO_STACK();
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436 portRESTORE_CONTEXT();
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439 void vTimer2ISR( void ) interrupt 5
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441 /* When using the cooperative scheduler the timer 2 ISR is only
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442 required to increment the RTOS tick count. */
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444 xTaskIncrementTick();
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445 portCLEAR_INTERRUPT_FLAG();
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448 /*-----------------------------------------------------------*/
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450 static void prvSetupTimerInterrupt( void )
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452 uint8_t ucOriginalSFRPage;
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454 /* Constants calculated to give the required timer capture values. */
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455 const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
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456 const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
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457 const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
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458 const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
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459 const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
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461 /* NOTE: This uses a timer only present on 8052 architecture. */
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463 /* Remember the current SFR page so we can restore it at the end of the
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465 ucOriginalSFRPage = SFRPAGE;
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468 /* TMR2CF can be left in its default state. */
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469 TMR2CF = ( uint8_t ) 0;
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471 /* Setup the overflow reload value. */
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472 RCAP2L = ucLowCaptureByte;
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473 RCAP2H = ucHighCaptureByte;
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475 /* The initial load is performed manually. */
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476 TMR2L = ucLowCaptureByte;
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477 TMR2H = ucHighCaptureByte;
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479 /* Enable the timer 2 interrupts. */
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480 IE |= portTIMER_2_INTERRUPT_ENABLE;
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482 /* Interrupts are disabled when this is called so the timer can be started
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484 TMR2CN = portENABLE_TIMER;
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486 /* Restore the original SFR page. */
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487 SFRPAGE = ucOriginalSFRPage;
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