1 /*******************************************************************************
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2 Copyright (c) 2006-2015 Cadence Design Systems Inc.
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4 Permission is hereby granted, free of charge, to any person obtaining
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5 a copy of this software and associated documentation files (the
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6 "Software"), to deal in the Software without restriction, including
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7 without limitation the rights to use, copy, modify, merge, publish,
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8 distribute, sublicense, and/or sell copies of the Software, and to
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9 permit persons to whom the Software is furnished to do so, subject to
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10 the following conditions:
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12 The above copyright notice and this permission notice shall be included
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13 in all copies or substantial portions of the Software.
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15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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16 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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17 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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18 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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19 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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20 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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21 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 --------------------------------------------------------------------------------
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24 XTENSA CONTEXT SAVE AND RESTORE ROUTINES
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26 Low-level Call0 functions for handling generic context save and restore of
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27 registers not specifically addressed by the interrupt vectors and handlers.
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28 Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
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29 Except for the calls to RTOS functions, this code is generic to Xtensa.
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31 Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
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32 save regs (A12-A15), which is always the case if the handlers are coded in C.
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33 However A12, A13 are made available as scratch registers for interrupt dispatch
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34 code, so are presumed saved anyway, and are always restored even in Call0 ABI.
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35 Only A14, A15 are truly handled as callee-save regs.
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37 Because Xtensa is a configurable architecture, this port supports all user
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38 generated configurations (except restrictions stated in the release notes).
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39 This is accomplished by conditional compilation using macros and functions
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40 defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
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41 Only the processor state included in your configuration is saved and restored,
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42 including any processor state added by user configuration options or TIE.
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44 *******************************************************************************/
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46 /* Warn nicely if this file gets named with a lowercase .s instead of .S: */
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48 NOERROR: .error "C preprocessor needed for this file: make sure its filename\
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49 ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
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52 #include "xtensa_rtos.h"
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55 #include <xtensa/overlay_os_asm.h>
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60 /*******************************************************************************
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64 !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
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66 Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
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67 interrupt stack frame defined in xtensa_rtos.h.
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68 Its counterpart is _xt_context_restore (which also restores A12, A13).
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70 Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
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71 This function preserves A12 & A13 in order to provide the caller with 2 scratch
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72 regs that need not be saved over the call to this function. The choice of which
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73 2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
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74 to avoid moving data more than necessary. Caller can assign regs accordingly.
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77 A0 = Return address in caller.
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78 A1 = Stack pointer of interrupted thread or handler ("interruptee").
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79 Original A12, A13 have already been saved in the interrupt stack frame.
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80 Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
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81 point of interruption.
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82 If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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85 A0 = Return address in caller.
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86 A1 = Stack pointer of interrupted thread or handler ("interruptee").
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87 A12, A13 as at entry (preserved).
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88 If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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90 *******************************************************************************/
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92 .global _xt_context_save
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93 .type _xt_context_save,@function
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97 s32i a2, sp, XT_STK_A2
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98 s32i a3, sp, XT_STK_A3
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99 s32i a4, sp, XT_STK_A4
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100 s32i a5, sp, XT_STK_A5
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101 s32i a6, sp, XT_STK_A6
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102 s32i a7, sp, XT_STK_A7
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103 s32i a8, sp, XT_STK_A8
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104 s32i a9, sp, XT_STK_A9
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105 s32i a10, sp, XT_STK_A10
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106 s32i a11, sp, XT_STK_A11
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109 Call0 ABI callee-saved regs a12-15 do not need to be saved here.
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110 a12-13 are the caller's responsibility so it can use them as scratch.
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111 So only need to save a14-a15 here for Windowed ABI (not Call0).
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113 #ifndef __XTENSA_CALL0_ABI__
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114 s32i a14, sp, XT_STK_A14
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115 s32i a15, sp, XT_STK_A15
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119 s32i a3, sp, XT_STK_SAR
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121 #if XCHAL_HAVE_LOOPS
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123 s32i a3, sp, XT_STK_LBEG
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125 s32i a3, sp, XT_STK_LEND
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127 s32i a3, sp, XT_STK_LCOUNT
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131 /* Save virtual priority mask */
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132 movi a3, _xt_vpri_mask
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134 s32i a3, sp, XT_STK_VPRI
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137 #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
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138 mov a9, a0 /* preserve ret addr */
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141 #ifndef __XTENSA_CALL0_ABI__
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143 To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
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144 Need to save a9,12,13 temporarily (in frame temps) and recover originals.
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145 Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
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146 and underflow exceptions disabled (assured by PS.EXCM == 1).
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148 s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */
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149 s32i a13, sp, XT_STK_TMP1
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150 s32i a9, sp, XT_STK_TMP2
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153 Save the overlay state if we are supporting overlays. Since we just saved
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154 three registers, we can conveniently use them here. Note that as of now,
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155 overlays only work for windowed calling ABI.
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158 l32i a9, sp, XT_STK_PC /* recover saved PC */
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159 _xt_overlay_get_state a9, a12, a13
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160 s32i a9, sp, XT_STK_OVLY /* save overlay state */
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163 l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */
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164 l32i a13, sp, XT_STK_A13
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165 l32i a9, sp, XT_STK_A9
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166 addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */
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167 call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */
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168 addi sp, sp, -XT_STK_FRMSZ
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169 l32i a12, sp, XT_STK_TMP0 /* recover stuff from stack frame */
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170 l32i a13, sp, XT_STK_TMP1
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171 l32i a9, sp, XT_STK_TMP2
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174 #if XCHAL_EXTRA_SA_SIZE > 0
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176 NOTE: Normally the xthal_save_extra_nw macro only affects address
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177 registers a2-a5. It is theoretically possible for Xtensa processor
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178 designers to write TIE that causes more address registers to be
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179 affected, but it is generally unlikely. If that ever happens,
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180 more registers need to be saved/restored around this macro invocation.
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181 Here we assume a9,12,13 are preserved.
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182 Future Xtensa tools releases might limit the regs that can be affected.
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184 addi a2, sp, XT_STK_EXTRA /* where to save it */
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185 # if XCHAL_EXTRA_SA_ALIGN > 16
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186 movi a3, -XCHAL_EXTRA_SA_ALIGN
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187 and a2, a2, a3 /* align dynamically >16 bytes */
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189 call0 xthal_save_extra_nw /* destroys a0,2,3,4,5 */
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192 #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
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193 mov a0, a9 /* retrieve ret addr */
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198 /*******************************************************************************
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200 _xt_context_restore
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202 !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
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204 Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
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205 ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt
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206 stack frame defined in xtensa_rtos.h .
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207 Its counterpart is _xt_context_save (whose caller saved A12, A13).
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209 Caller is responsible to restore PC, PS, A0, A1 (SP).
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212 A0 = Return address in caller.
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213 A1 = Stack pointer of interrupted thread or handler ("interruptee").
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216 A0 = Return address in caller.
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217 A1 = Stack pointer of interrupted thread or handler ("interruptee").
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218 Other processor state except PC, PS, A0, A1 (SP), is as at the point
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221 *******************************************************************************/
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223 .global _xt_context_restore
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224 .type _xt_context_restore,@function
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226 _xt_context_restore:
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228 #if XCHAL_EXTRA_SA_SIZE > 0
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230 NOTE: Normally the xthal_restore_extra_nw macro only affects address
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231 registers a2-a5. It is theoretically possible for Xtensa processor
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232 designers to write TIE that causes more address registers to be
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233 affected, but it is generally unlikely. If that ever happens,
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234 more registers need to be saved/restored around this macro invocation.
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235 Here we only assume a13 is preserved.
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236 Future Xtensa tools releases might limit the regs that can be affected.
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238 mov a13, a0 /* preserve ret addr */
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239 addi a2, sp, XT_STK_EXTRA /* where to find it */
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240 # if XCHAL_EXTRA_SA_ALIGN > 16
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241 movi a3, -XCHAL_EXTRA_SA_ALIGN
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242 and a2, a2, a3 /* align dynamically >16 bytes */
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244 call0 xthal_restore_extra_nw /* destroys a0,2,3,4,5 */
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245 mov a0, a13 /* retrieve ret addr */
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248 #if XCHAL_HAVE_LOOPS
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249 l32i a2, sp, XT_STK_LBEG
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250 l32i a3, sp, XT_STK_LEND
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252 l32i a2, sp, XT_STK_LCOUNT
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259 If we are using overlays, this is a good spot to check if we need
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260 to restore an overlay for the incoming task. Here we have a bunch
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261 of registers to spare. Note that this step is going to use a few
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262 bytes of storage below SP (SP-20 to SP-32) if an overlay is going
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265 l32i a2, sp, XT_STK_PC /* retrieve PC */
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266 l32i a3, sp, XT_STK_PS /* retrieve PS */
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267 l32i a4, sp, XT_STK_OVLY /* retrieve overlay state */
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268 l32i a5, sp, XT_STK_A1 /* retrieve stack ptr */
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269 _xt_overlay_check_map a2, a3, a4, a5, a6
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270 s32i a2, sp, XT_STK_PC /* save updated PC */
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271 s32i a3, sp, XT_STK_PS /* save updated PS */
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274 #ifdef XT_USE_SWPRI
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275 /* Restore virtual interrupt priority and interrupt enable */
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276 movi a3, _xt_intdata
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277 l32i a4, a3, 0 /* a4 = _xt_intenable */
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278 l32i a5, sp, XT_STK_VPRI /* a5 = saved _xt_vpri_mask */
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280 wsr a4, INTENABLE /* update INTENABLE */
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281 s32i a5, a3, 4 /* restore _xt_vpri_mask */
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284 l32i a3, sp, XT_STK_SAR
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285 l32i a2, sp, XT_STK_A2
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287 l32i a3, sp, XT_STK_A3
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288 l32i a4, sp, XT_STK_A4
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289 l32i a5, sp, XT_STK_A5
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290 l32i a6, sp, XT_STK_A6
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291 l32i a7, sp, XT_STK_A7
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292 l32i a8, sp, XT_STK_A8
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293 l32i a9, sp, XT_STK_A9
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294 l32i a10, sp, XT_STK_A10
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295 l32i a11, sp, XT_STK_A11
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298 Call0 ABI callee-saved regs a12-15 do not need to be restored here.
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299 However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
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300 so need to be restored anyway, despite being callee-saved in Call0.
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302 l32i a12, sp, XT_STK_A12
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303 l32i a13, sp, XT_STK_A13
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304 #ifndef __XTENSA_CALL0_ABI__
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305 l32i a14, sp, XT_STK_A14
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306 l32i a15, sp, XT_STK_A15
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312 /*******************************************************************************
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316 Initializes global co-processor management data, setting all co-processors
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317 to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
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319 Called during initialization of the RTOS, before any threads run.
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321 This may be called from normal Xtensa single-threaded application code which
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322 might use co-processors. The Xtensa run-time initialization enables all
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323 co-processors. They must remain enabled here, else a co-processor exception
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324 might occur outside of a thread, which the exception handler doesn't expect.
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327 Xtensa single-threaded run-time environment is in effect.
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328 No thread is yet running.
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333 Obeys ABI conventions per prototype:
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334 void _xt_coproc_init(void)
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336 *******************************************************************************/
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338 #if XCHAL_CP_NUM > 0
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340 .global _xt_coproc_init
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341 .type _xt_coproc_init,@function
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346 /* Initialize thread co-processor ownerships to 0 (unowned). */
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347 movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */
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348 addi a3, a2, XCHAL_CP_MAX << 2 /* a3 = top+1 of owner array */
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349 movi a4, 0 /* a4 = 0 (unowned) */
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359 /*******************************************************************************
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363 Releases any and all co-processors owned by a given thread. The thread is
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364 identified by it's co-processor state save area defined in xtensa_context.h .
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366 Must be called before a thread's co-proc save area is deleted to avoid
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367 memory corruption when the exception handler tries to save the state.
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368 May be called when a thread terminates or completes but does not delete
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369 the co-proc save area, to avoid the exception handler having to save the
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370 thread's co-proc state before another thread can use it (optimization).
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373 A2 = Pointer to base of co-processor state save area.
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378 Obeys ABI conventions per prototype:
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379 void _xt_coproc_release(void * coproc_sa_base)
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381 *******************************************************************************/
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383 #if XCHAL_CP_NUM > 0
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385 .global _xt_coproc_release
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386 .type _xt_coproc_release,@function
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388 _xt_coproc_release:
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389 ENTRY0 /* a2 = base of save area */
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391 movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
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392 addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */
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393 movi a5, 0 /* a5 = 0 (unowned) */
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395 rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */
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397 1: l32i a7, a3, 0 /* a7 = owner at a3 */
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398 bne a2, a7, 2f /* if (coproc_sa_base == owner) */
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399 s32i a5, a3, 0 /* owner = unowned */
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400 2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */
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401 bltu a3, a4, 1b /* repeat until end of array */
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403 3: wsr a6, PS /* restore interrupts */
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410 /*******************************************************************************
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413 If there is a current thread and it has a coprocessor state save area, then
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414 save all callee-saved state into this area. This function is called from the
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415 solicited context switch handler. It calls a system-specific function to get
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416 the coprocessor save area base address.
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419 - The thread being switched out is still the current thread.
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420 - CPENABLE state reflects which coprocessors are active.
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421 - Registers have been saved/spilled already.
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424 - All necessary CP callee-saved state has been saved.
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425 - Registers a2-a7, a13-a15 have been trashed.
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427 Must be called from assembly code only, using CALL0.
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428 *******************************************************************************/
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429 #if XCHAL_CP_NUM > 0
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431 .extern _xt_coproc_sa_offset /* external reference */
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433 .global _xt_coproc_savecs
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434 .type _xt_coproc_savecs,@function
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438 /* At entry, CPENABLE should be showing which CPs are enabled. */
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440 rsr a2, CPENABLE /* a2 = which CPs are enabled */
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441 beqz a2, .Ldone /* quick exit if none */
\r
442 mov a14, a0 /* save return address */
\r
443 call0 XT_RTOS_CP_STATE /* get address of CP save area */
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444 mov a0, a14 /* restore return address */
\r
445 beqz a15, .Ldone /* if none then nothing to do */
\r
446 s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */
\r
447 movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
\r
448 l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
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450 #if XCHAL_CP0_SA_SIZE
\r
451 bbci.l a2, 0, 2f /* CP 0 not enabled */
\r
452 l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
\r
453 add a3, a14, a15 /* a3 = save area for CP 0 */
\r
454 xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
458 #if XCHAL_CP1_SA_SIZE
\r
459 bbci.l a2, 1, 2f /* CP 1 not enabled */
\r
460 l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
\r
461 add a3, a14, a15 /* a3 = save area for CP 1 */
\r
462 xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
466 #if XCHAL_CP2_SA_SIZE
\r
470 xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
474 #if XCHAL_CP3_SA_SIZE
\r
478 xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
482 #if XCHAL_CP4_SA_SIZE
\r
486 xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
490 #if XCHAL_CP5_SA_SIZE
\r
494 xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
498 #if XCHAL_CP6_SA_SIZE
\r
502 xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
506 #if XCHAL_CP7_SA_SIZE
\r
510 xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
519 /*******************************************************************************
\r
520 _xt_coproc_restorecs
\r
522 Restore any callee-saved coprocessor state for the incoming thread.
\r
523 This function is called from coprocessor exception handling, when giving
\r
524 ownership to a thread that solicited a context switch earlier. It calls a
\r
525 system-specific function to get the coprocessor save area base address.
\r
528 - The incoming thread is set as the current thread.
\r
529 - CPENABLE is set up correctly for all required coprocessors.
\r
530 - a2 = mask of coprocessors to be restored.
\r
533 - All necessary CP callee-saved state has been restored.
\r
534 - CPENABLE - unchanged.
\r
535 - Registers a2-a7, a13-a15 have been trashed.
\r
537 Must be called from assembly code only, using CALL0.
\r
538 *******************************************************************************/
\r
539 #if XCHAL_CP_NUM > 0
\r
541 .global _xt_coproc_restorecs
\r
542 .type _xt_coproc_restorecs,@function
\r
544 _xt_coproc_restorecs:
\r
546 mov a14, a0 /* save return address */
\r
547 call0 XT_RTOS_CP_STATE /* get address of CP save area */
\r
548 mov a0, a14 /* restore return address */
\r
549 beqz a15, .Ldone2 /* if none then nothing to do */
\r
550 l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */
\r
551 xor a3, a3, a2 /* clear the ones being restored */
\r
552 s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */
\r
553 movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
\r
554 l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
\r
556 #if XCHAL_CP0_SA_SIZE
\r
557 bbci.l a2, 0, 2f /* CP 0 not enabled */
\r
558 l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
\r
559 add a3, a14, a15 /* a3 = save area for CP 0 */
\r
560 xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
564 #if XCHAL_CP1_SA_SIZE
\r
565 bbci.l a2, 1, 2f /* CP 1 not enabled */
\r
566 l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
\r
567 add a3, a14, a15 /* a3 = save area for CP 1 */
\r
568 xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
572 #if XCHAL_CP2_SA_SIZE
\r
576 xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
580 #if XCHAL_CP3_SA_SIZE
\r
584 xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
588 #if XCHAL_CP4_SA_SIZE
\r
592 xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
596 #if XCHAL_CP5_SA_SIZE
\r
600 xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
604 #if XCHAL_CP6_SA_SIZE
\r
608 xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r
612 #if XCHAL_CP7_SA_SIZE
\r
616 xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
\r