2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
5 ***************************************************************************
\r
7 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
8 * Complete, revised, and edited pdf reference manuals are also *
\r
11 * Purchasing FreeRTOS documentation will not only help you, by *
\r
12 * ensuring you get running as quickly as possible and with an *
\r
13 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
14 * the FreeRTOS project to continue with its mission of providing *
\r
15 * professional grade, cross platform, de facto standard solutions *
\r
16 * for microcontrollers - completely free of charge! *
\r
18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
20 * Thank you for using FreeRTOS, and thank you for your support! *
\r
22 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
31 distribute a combined work that includes FreeRTOS without being obliged to
\r
32 provide the source code for proprietary components outside of the FreeRTOS
\r
33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 ***************************************************************************
\r
46 * Having a problem? Start by reading the FAQ "My application does *
\r
47 * not run, what could be wrong? *
\r
49 * http://www.FreeRTOS.org/FAQHelp.html *
\r
51 ***************************************************************************
\r
54 http://www.FreeRTOS.org - Documentation, training, latest information,
\r
55 license and contact details.
\r
57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
58 including FreeRTOS+Trace - an indispensable productivity tool.
\r
60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
61 the code with commercial support, indemnification, and middleware, under
\r
62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
63 provide a safety engineered and independently SIL3 certified version under
\r
64 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
70 + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
\r
74 + Removed the use of the %0 parameter within the assembler macros and
\r
75 replaced them with hard coded registers. This will ensure the
\r
76 assembler does not select the link register as the temp register as
\r
77 was occasionally happening previously.
\r
79 + The assembler statements are now included in a single asm block rather
\r
80 than each line having its own asm block.
\r
84 + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
\r
85 and replaced them with portYIELD_FROM_ISR() macro. Application code
\r
86 should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
\r
87 macros as per the V4.5.1 demo code.
\r
97 /*-----------------------------------------------------------
\r
98 * Port specific definitions.
\r
100 * The settings in this file configure FreeRTOS correctly for the
\r
101 * given hardware and compiler.
\r
103 * These settings should not be altered.
\r
104 *-----------------------------------------------------------
\r
107 /* Type definitions. */
\r
108 #define portCHAR char
\r
109 #define portFLOAT float
\r
110 #define portDOUBLE double
\r
111 #define portLONG long
\r
112 #define portSHORT short
\r
113 #define portSTACK_TYPE unsigned portLONG
\r
114 #define portBASE_TYPE portLONG
\r
116 #if( configUSE_16_BIT_TICKS == 1 )
\r
117 typedef unsigned portSHORT portTickType;
\r
118 #define portMAX_DELAY ( portTickType ) 0xffff
\r
120 typedef unsigned portLONG portTickType;
\r
121 #define portMAX_DELAY ( portTickType ) 0xffffffff
\r
123 /*-----------------------------------------------------------*/
\r
125 /* Architecture specifics. */
\r
126 #define portSTACK_GROWTH ( -1 )
\r
127 #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
\r
128 #define portBYTE_ALIGNMENT 8
\r
129 #define portNOP() __asm volatile ( "NOP" );
\r
130 /*-----------------------------------------------------------*/
\r
133 /* Scheduler utilities. */
\r
136 * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
\r
137 * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
\r
138 * are included here for efficiency. An attempt to call one from
\r
139 * THUMB mode code will result in a compile time error.
\r
142 #define portRESTORE_CONTEXT() \
\r
144 extern volatile void * volatile pxCurrentTCB; \
\r
145 extern volatile unsigned portLONG ulCriticalNesting; \
\r
147 /* Set the LR to the task stack. */ \
\r
149 "LDR R0, =pxCurrentTCB \n\t" \
\r
150 "LDR R0, [R0] \n\t" \
\r
151 "LDR LR, [R0] \n\t" \
\r
153 /* The critical nesting depth is the first item on the stack. */ \
\r
154 /* Load it into the ulCriticalNesting variable. */ \
\r
155 "LDR R0, =ulCriticalNesting \n\t" \
\r
156 "LDMFD LR!, {R1} \n\t" \
\r
157 "STR R1, [R0] \n\t" \
\r
159 /* Get the SPSR from the stack. */ \
\r
160 "LDMFD LR!, {R0} \n\t" \
\r
161 "MSR SPSR, R0 \n\t" \
\r
163 /* Restore all system mode registers for the task. */ \
\r
164 "LDMFD LR, {R0-R14}^ \n\t" \
\r
167 /* Restore the return address. */ \
\r
168 "LDR LR, [LR, #+60] \n\t" \
\r
170 /* And return - correcting the offset in the LR to obtain the */ \
\r
171 /* correct address. */ \
\r
172 "SUBS PC, LR, #4 \n\t" \
\r
174 ( void ) ulCriticalNesting; \
\r
175 ( void ) pxCurrentTCB; \
\r
177 /*-----------------------------------------------------------*/
\r
179 #define portSAVE_CONTEXT() \
\r
181 extern volatile void * volatile pxCurrentTCB; \
\r
182 extern volatile unsigned portLONG ulCriticalNesting; \
\r
184 /* Push R0 as we are going to use the register. */ \
\r
186 "STMDB SP!, {R0} \n\t" \
\r
188 /* Set R0 to point to the task stack pointer. */ \
\r
189 "STMDB SP,{SP}^ \n\t" \
\r
191 "SUB SP, SP, #4 \n\t" \
\r
192 "LDMIA SP!,{R0} \n\t" \
\r
194 /* Push the return address onto the stack. */ \
\r
195 "STMDB R0!, {LR} \n\t" \
\r
197 /* Now we have saved LR we can use it instead of R0. */ \
\r
198 "MOV LR, R0 \n\t" \
\r
200 /* Pop R0 so we can save it onto the system mode stack. */ \
\r
201 "LDMIA SP!, {R0} \n\t" \
\r
203 /* Push all the system mode registers onto the task stack. */ \
\r
204 "STMDB LR,{R0-LR}^ \n\t" \
\r
206 "SUB LR, LR, #60 \n\t" \
\r
208 /* Push the SPSR onto the task stack. */ \
\r
209 "MRS R0, SPSR \n\t" \
\r
210 "STMDB LR!, {R0} \n\t" \
\r
212 "LDR R0, =ulCriticalNesting \n\t" \
\r
213 "LDR R0, [R0] \n\t" \
\r
214 "STMDB LR!, {R0} \n\t" \
\r
216 /* Store the new top of stack for the task. */ \
\r
217 "LDR R0, =pxCurrentTCB \n\t" \
\r
218 "LDR R0, [R0] \n\t" \
\r
219 "STR LR, [R0] \n\t" \
\r
221 ( void ) ulCriticalNesting; \
\r
222 ( void ) pxCurrentTCB; \
\r
226 #define portYIELD_FROM_ISR() vTaskSwitchContext()
\r
227 #define portYIELD() __asm volatile ( "SWI 0" )
\r
228 /*-----------------------------------------------------------*/
\r
231 /* Critical section management. */
\r
234 * The interrupt management utilities can only be called from ARM mode. When
\r
235 * THUMB_INTERWORK is defined the utilities are defined as functions in
\r
236 * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
\r
237 * defined then the utilities are defined as macros here - as per other ports.
\r
240 #ifdef THUMB_INTERWORK
\r
242 extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
\r
243 extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
\r
245 #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
\r
246 #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
\r
250 #define portDISABLE_INTERRUPTS() \
\r
252 "STMDB SP!, {R0} \n\t" /* Push R0. */ \
\r
253 "MRS R0, CPSR \n\t" /* Get CPSR. */ \
\r
254 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
\r
255 "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
\r
256 "LDMIA SP!, {R0} " ) /* Pop R0. */
\r
258 #define portENABLE_INTERRUPTS() \
\r
260 "STMDB SP!, {R0} \n\t" /* Push R0. */ \
\r
261 "MRS R0, CPSR \n\t" /* Get CPSR. */ \
\r
262 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
\r
263 "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
\r
264 "LDMIA SP!, {R0} " ) /* Pop R0. */
\r
266 #endif /* THUMB_INTERWORK */
\r
268 extern void vPortEnterCritical( void );
\r
269 extern void vPortExitCritical( void );
\r
271 #define portENTER_CRITICAL() vPortEnterCritical();
\r
272 #define portEXIT_CRITICAL() vPortExitCritical();
\r
273 /*-----------------------------------------------------------*/
\r
275 /* Task function macros as described on the FreeRTOS.org WEB site. */
\r
276 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
277 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
283 #endif /* PORTMACRO_H */
\r
projects / freertos / blob