2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
5 ***************************************************************************
\r
7 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
8 * Complete, revised, and edited pdf reference manuals are also *
\r
11 * Purchasing FreeRTOS documentation will not only help you, by *
\r
12 * ensuring you get running as quickly as possible and with an *
\r
13 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
14 * the FreeRTOS project to continue with its mission of providing *
\r
15 * professional grade, cross platform, de facto standard solutions *
\r
16 * for microcontrollers - completely free of charge! *
\r
18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
20 * Thank you for using FreeRTOS, and thank you for your support! *
\r
22 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
31 distribute a combined work that includes FreeRTOS without being obliged to
\r
32 provide the source code for proprietary components outside of the FreeRTOS
\r
33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 ***************************************************************************
\r
46 * Having a problem? Start by reading the FAQ "My application does *
\r
47 * not run, what could be wrong? *
\r
49 * http://www.FreeRTOS.org/FAQHelp.html *
\r
51 ***************************************************************************
\r
54 http://www.FreeRTOS.org - Documentation, training, latest information,
\r
55 license and contact details.
\r
57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
58 including FreeRTOS+Trace - an indispensable productivity tool.
\r
60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
61 the code with commercial support, indemnification, and middleware, under
\r
62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
63 provide a safety engineered and independently SIL3 certified version under
\r
64 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
68 Changes between V1.2.4 and V1.2.5
\r
70 + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
\r
71 interrupt flag setting. Using the two bits defined within
\r
72 portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
\r
73 before the test was performed.
\r
77 + Set the interrupt vector address to 0x08. Previously it was at the
\r
78 incorrect address for compatibility mode of 0x18.
\r
82 + PCLATU and PCLATH are now saved as part of the context. This allows
\r
83 function pointers to be used within tasks. Thanks to Javier Espeche
\r
84 for the enhancement.
\r
88 + TABLAT is now saved as part of the task context.
\r
92 + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
\r
93 value and does not write to the register.
\r
96 /* Scheduler include files. */
\r
97 #include "FreeRTOS.h"
\r
100 /* MPLAB library include file. */
\r
101 #include "timers.h"
\r
103 /*-----------------------------------------------------------
\r
104 * Implementation of functions defined in portable.h for the PIC port.
\r
105 *----------------------------------------------------------*/
\r
107 /* Hardware setup for tick. */
\r
108 #define portTIMER_FOSC_SCALE ( ( unsigned long ) 4 )
\r
110 /* Initial interrupt enable state for newly created tasks. This value is
\r
111 copied into INTCON when a task switches in for the first time. */
\r
112 #define portINITAL_INTERRUPT_STATE 0xc0
\r
114 /* Just the bit within INTCON for the global interrupt flag. */
\r
115 #define portGLOBAL_INTERRUPT_FLAG 0x80
\r
117 /* Constant used for context switch macro when we require the interrupt
\r
118 enable state to be unchanged when the interrupted task is switched back in. */
\r
119 #define portINTERRUPTS_UNCHANGED 0x00
\r
121 /* Some memory areas get saved as part of the task context. These memory
\r
122 area's get used by the compiler for temporary storage, especially when
\r
123 performing mathematical operations, or when using 32bit data types. This
\r
124 constant defines the size of memory area which must be saved. */
\r
125 #define portCOMPILER_MANAGED_MEMORY_SIZE ( ( unsigned char ) 0x13 )
\r
127 /* We require the address of the pxCurrentTCB variable, but don't want to know
\r
128 any details of its type. */
\r
129 typedef void tskTCB;
\r
130 extern volatile tskTCB * volatile pxCurrentTCB;
\r
132 /* IO port constants. */
\r
133 #define portBIT_SET ( ( unsigned char ) 1 )
\r
134 #define portBIT_CLEAR ( ( unsigned char ) 0 )
\r
137 * The serial port ISR's are defined in serial.c, but are called from portable
\r
138 * as they use the same vector as the tick ISR.
\r
140 void vSerialTxISR( void );
\r
141 void vSerialRxISR( void );
\r
144 * Perform hardware setup to enable ticks.
\r
146 static void prvSetupTimerInterrupt( void );
\r
149 * ISR to maintain the tick, and perform tick context switches if the
\r
150 * preemptive scheduler is being used.
\r
152 static void prvTickISR( void );
\r
155 * ISR placed on the low priority vector. This calls the appropriate ISR for
\r
156 * the actual interrupt.
\r
158 static void prvLowInterrupt( void );
\r
161 * Macro that pushes all the registers that make up the context of a task onto
\r
162 * the stack, then saves the new top of stack into the TCB.
\r
164 * If this is called from an ISR then the interrupt enable bits must have been
\r
165 * set for the ISR to ever get called. Therefore we want to save the INTCON
\r
166 * register with the enable bits forced to be set - and ucForcedInterruptFlags
\r
167 * must contain these bit settings. This means the interrupts will again be
\r
168 * enabled when the interrupted task is switched back in.
\r
170 * If this is called from a manual context switch (i.e. from a call to yield),
\r
171 * then we want to save the INTCON so it is restored with its current state,
\r
172 * and ucForcedInterruptFlags must be 0. This allows a yield from within
\r
173 * a critical section.
\r
175 * The compiler uses some locations at the bottom of the memory for temporary
\r
176 * storage during math and other computations. This is especially true if
\r
177 * 32bit data types are utilised (as they are by the scheduler). The .tmpdata
\r
178 * and MATH_DATA sections have to be stored in there entirety as part of a task
\r
179 * context. This macro stores from data address 0x00 to
\r
180 * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
\r
181 * applications but you should check the map file for your project to ensure
\r
182 * this is sufficient for your needs. It is not clear whether this size is
\r
183 * fixed for all compilations or has the potential to be program specific.
\r
185 #define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
\r
188 /* Save the status and WREG registers first, as these will get modified \
\r
189 by the operations below. */ \
\r
190 MOVFF WREG, PREINC1 \
\r
191 MOVFF STATUS, PREINC1 \
\r
192 /* Save the INTCON register with the appropriate bits forced if \
\r
193 necessary - as described above. */ \
\r
194 MOVFF INTCON, WREG \
\r
195 IORLW ucForcedInterruptFlags \
\r
196 MOVFF WREG, PREINC1 \
\r
199 portDISABLE_INTERRUPTS(); \
\r
202 /* Store the necessary registers to the stack. */ \
\r
203 MOVFF BSR, PREINC1 \
\r
204 MOVFF FSR2L, PREINC1 \
\r
205 MOVFF FSR2H, PREINC1 \
\r
206 MOVFF FSR0L, PREINC1 \
\r
207 MOVFF FSR0H, PREINC1 \
\r
208 MOVFF TABLAT, PREINC1 \
\r
209 MOVFF TBLPTRU, PREINC1 \
\r
210 MOVFF TBLPTRH, PREINC1 \
\r
211 MOVFF TBLPTRL, PREINC1 \
\r
212 MOVFF PRODH, PREINC1 \
\r
213 MOVFF PRODL, PREINC1 \
\r
214 MOVFF PCLATU, PREINC1 \
\r
215 MOVFF PCLATH, PREINC1 \
\r
216 /* Store the .tempdata and MATH_DATA areas as described above. */ \
\r
219 MOVFF POSTINC0, PREINC1 \
\r
220 MOVFF POSTINC0, PREINC1 \
\r
221 MOVFF POSTINC0, PREINC1 \
\r
222 MOVFF POSTINC0, PREINC1 \
\r
223 MOVFF POSTINC0, PREINC1 \
\r
224 MOVFF POSTINC0, PREINC1 \
\r
225 MOVFF POSTINC0, PREINC1 \
\r
226 MOVFF POSTINC0, PREINC1 \
\r
227 MOVFF POSTINC0, PREINC1 \
\r
228 MOVFF POSTINC0, PREINC1 \
\r
229 MOVFF POSTINC0, PREINC1 \
\r
230 MOVFF POSTINC0, PREINC1 \
\r
231 MOVFF POSTINC0, PREINC1 \
\r
232 MOVFF POSTINC0, PREINC1 \
\r
233 MOVFF POSTINC0, PREINC1 \
\r
234 MOVFF POSTINC0, PREINC1 \
\r
235 MOVFF POSTINC0, PREINC1 \
\r
236 MOVFF POSTINC0, PREINC1 \
\r
237 MOVFF POSTINC0, PREINC1 \
\r
238 MOVFF INDF0, PREINC1 \
\r
239 MOVFF FSR0L, PREINC1 \
\r
240 MOVFF FSR0H, PREINC1 \
\r
241 /* Store the hardware stack pointer in a temp register before we \
\r
243 MOVFF STKPTR, FSR0L \
\r
246 /* Store each address from the hardware stack. */ \
\r
247 while( STKPTR > ( unsigned char ) 0 ) \
\r
250 MOVFF TOSL, PREINC1 \
\r
251 MOVFF TOSH, PREINC1 \
\r
252 MOVFF TOSU, PREINC1 \
\r
258 /* Store the number of addresses on the hardware stack (from the \
\r
259 temporary register). */ \
\r
260 MOVFF FSR0L, PREINC1 \
\r
261 MOVF PREINC1, 1, 0 \
\r
264 /* Save the new top of the software stack in the TCB. */ \
\r
266 MOVFF pxCurrentTCB, FSR0L \
\r
267 MOVFF pxCurrentTCB + 1, FSR0H \
\r
268 MOVFF FSR1L, POSTINC0 \
\r
269 MOVFF FSR1H, POSTINC0 \
\r
272 /*-----------------------------------------------------------*/
\r
275 * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
\r
278 #define portRESTORE_CONTEXT() \
\r
281 /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
\r
282 MOVFF pxCurrentTCB, FSR0L \
\r
283 MOVFF pxCurrentTCB + 1, FSR0H \
\r
285 /* De-reference FSR0 to set the address it holds into FSR1. \
\r
286 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
\r
287 MOVFF POSTINC0, FSR1L \
\r
288 MOVFF POSTINC0, FSR1H \
\r
290 /* How many return addresses are there on the hardware stack? Discard \
\r
291 the first byte as we are pointing to the next free space. */ \
\r
292 MOVFF POSTDEC1, FSR0L \
\r
293 MOVFF POSTDEC1, FSR0L \
\r
296 /* Fill the hardware stack from our software stack. */ \
\r
299 while( STKPTR < FSR0L ) \
\r
303 MOVF POSTDEC1, 0, 0 \
\r
305 MOVF POSTDEC1, 0, 0 \
\r
307 MOVF POSTDEC1, 0, 0 \
\r
313 /* Restore the .tmpdata and MATH_DATA memory. */ \
\r
314 MOVFF POSTDEC1, FSR0H \
\r
315 MOVFF POSTDEC1, FSR0L \
\r
316 MOVFF POSTDEC1, POSTDEC0 \
\r
317 MOVFF POSTDEC1, POSTDEC0 \
\r
318 MOVFF POSTDEC1, POSTDEC0 \
\r
319 MOVFF POSTDEC1, POSTDEC0 \
\r
320 MOVFF POSTDEC1, POSTDEC0 \
\r
321 MOVFF POSTDEC1, POSTDEC0 \
\r
322 MOVFF POSTDEC1, POSTDEC0 \
\r
323 MOVFF POSTDEC1, POSTDEC0 \
\r
324 MOVFF POSTDEC1, POSTDEC0 \
\r
325 MOVFF POSTDEC1, POSTDEC0 \
\r
326 MOVFF POSTDEC1, POSTDEC0 \
\r
327 MOVFF POSTDEC1, POSTDEC0 \
\r
328 MOVFF POSTDEC1, POSTDEC0 \
\r
329 MOVFF POSTDEC1, POSTDEC0 \
\r
330 MOVFF POSTDEC1, POSTDEC0 \
\r
331 MOVFF POSTDEC1, POSTDEC0 \
\r
332 MOVFF POSTDEC1, POSTDEC0 \
\r
333 MOVFF POSTDEC1, POSTDEC0 \
\r
334 MOVFF POSTDEC1, POSTDEC0 \
\r
335 MOVFF POSTDEC1, INDF0 \
\r
336 /* Restore the other registers forming the tasks context. */ \
\r
337 MOVFF POSTDEC1, PCLATH \
\r
338 MOVFF POSTDEC1, PCLATU \
\r
339 MOVFF POSTDEC1, PRODL \
\r
340 MOVFF POSTDEC1, PRODH \
\r
341 MOVFF POSTDEC1, TBLPTRL \
\r
342 MOVFF POSTDEC1, TBLPTRH \
\r
343 MOVFF POSTDEC1, TBLPTRU \
\r
344 MOVFF POSTDEC1, TABLAT \
\r
345 MOVFF POSTDEC1, FSR0H \
\r
346 MOVFF POSTDEC1, FSR0L \
\r
347 MOVFF POSTDEC1, FSR2H \
\r
348 MOVFF POSTDEC1, FSR2L \
\r
349 MOVFF POSTDEC1, BSR \
\r
350 /* The next byte is the INTCON register. Read this into WREG as some \
\r
351 manipulation is required. */ \
\r
352 MOVFF POSTDEC1, WREG \
\r
355 /* From the INTCON register, only the interrupt enable bits form part \
\r
356 of the tasks context. It is perfectly legitimate for another task to \
\r
357 have modified any other bits. We therefore only restore the top two bits. \
\r
359 if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
\r
362 MOVFF POSTDEC1, STATUS \
\r
363 MOVFF POSTDEC1, WREG \
\r
364 /* Return enabling interrupts. */ \
\r
371 MOVFF POSTDEC1, STATUS \
\r
372 MOVFF POSTDEC1, WREG \
\r
373 /* Return without effecting interrupts. The context may have \
\r
374 been saved from a critical region. */ \
\r
379 /*-----------------------------------------------------------*/
\r
382 * See header file for description.
\r
384 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
386 unsigned long ulAddress;
\r
387 unsigned char ucBlock;
\r
389 /* Place a few bytes of known values on the bottom of the stack.
\r
390 This is just useful for debugging. */
\r
392 *pxTopOfStack = 0x11;
\r
394 *pxTopOfStack = 0x22;
\r
396 *pxTopOfStack = 0x33;
\r
400 /* Simulate how the stack would look after a call to vPortYield() generated
\r
403 First store the function parameters. This is where the task will expect to
\r
404 find them when it starts running. */
\r
405 ulAddress = ( unsigned long ) pvParameters;
\r
406 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
\r
410 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
\r
413 /* Next we just leave a space. When a context is saved the stack pointer
\r
414 is incremented before it is used so as not to corrupt whatever the stack
\r
415 pointer is actually pointing to. This is especially necessary during
\r
416 function epilogue code generated by the compiler. */
\r
417 *pxTopOfStack = 0x44;
\r
420 /* Next are all the registers that form part of the task context. */
\r
422 *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* WREG. */
\r
425 *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; /* Status. */
\r
428 /* INTCON is saved with interrupts enabled. */
\r
429 *pxTopOfStack = ( portSTACK_TYPE ) portINITAL_INTERRUPT_STATE; /* INTCON */
\r
432 *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* BSR. */
\r
435 *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* FSR2L. */
\r
438 *pxTopOfStack = ( portSTACK_TYPE ) 0x33; /* FSR2H. */
\r
441 *pxTopOfStack = ( portSTACK_TYPE ) 0x44; /* FSR0L. */
\r
444 *pxTopOfStack = ( portSTACK_TYPE ) 0x55; /* FSR0H. */
\r
447 *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* TABLAT. */
\r
450 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */
\r
453 *pxTopOfStack = ( portSTACK_TYPE ) 0x88; /* TBLPTRUH. */
\r
456 *pxTopOfStack = ( portSTACK_TYPE ) 0x99; /* TBLPTRUL. */
\r
459 *pxTopOfStack = ( portSTACK_TYPE ) 0xaa; /* PRODH. */
\r
462 *pxTopOfStack = ( portSTACK_TYPE ) 0xbb; /* PRODL. */
\r
465 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATU. */
\r
468 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATH. */
\r
471 /* Next the .tmpdata and MATH_DATA sections. */
\r
472 for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
\r
474 *pxTopOfStack = ( portSTACK_TYPE ) ucBlock;
\r
478 /* Store the top of the global data section. */
\r
479 *pxTopOfStack = ( portSTACK_TYPE ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
\r
482 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* High. */
\r
485 /* The only function return address so far is the address of the
\r
487 ulAddress = ( unsigned long ) pxCode;
\r
490 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
\r
495 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
\r
499 /* TOS even higher. */
\r
500 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
\r
503 /* Store the number of return addresses on the hardware stack - so far only
\r
504 the address of the task entry point. */
\r
505 *pxTopOfStack = ( portSTACK_TYPE ) 1;
\r
508 return pxTopOfStack;
\r
510 /*-----------------------------------------------------------*/
\r
512 portBASE_TYPE xPortStartScheduler( void )
\r
514 /* Setup a timer for the tick ISR is using the preemptive scheduler. */
\r
515 prvSetupTimerInterrupt();
\r
517 /* Restore the context of the first task to run. */
\r
518 portRESTORE_CONTEXT();
\r
520 /* Should not get here. Use the function name to stop compiler warnings. */
\r
521 ( void ) prvLowInterrupt;
\r
522 ( void ) prvTickISR;
\r
526 /*-----------------------------------------------------------*/
\r
528 void vPortEndScheduler( void )
\r
530 /* It is unlikely that the scheduler for the PIC port will get stopped
\r
531 once running. If required disable the tick interrupt here, then return
\r
532 to xPortStartScheduler(). */
\r
534 /*-----------------------------------------------------------*/
\r
537 * Manual context switch. This is similar to the tick context switch,
\r
538 * but does not increment the tick count. It must be identical to the
\r
539 * tick context switch in how it stores the stack of a task.
\r
541 void vPortYield( void )
\r
543 /* This can get called with interrupts either enabled or disabled. We
\r
544 will save the INTCON register with the interrupt enable bits unmodified. */
\r
545 portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
\r
547 /* Switch to the highest priority task that is ready to run. */
\r
548 vTaskSwitchContext();
\r
550 /* Start executing the task we have just switched to. */
\r
551 portRESTORE_CONTEXT();
\r
553 /*-----------------------------------------------------------*/
\r
556 * Vector for ISR. Nothing here must alter any registers!
\r
558 #pragma code high_vector=0x08
\r
559 static void prvLowInterrupt( void )
\r
561 /* Was the interrupt the tick? */
\r
562 if( PIR1bits.CCP1IF )
\r
569 /* Was the interrupt a byte being received? */
\r
570 if( PIR1bits.RCIF )
\r
577 /* Was the interrupt the Tx register becoming empty? */
\r
578 if( PIR1bits.TXIF )
\r
580 if( PIE1bits.TXIE )
\r
590 /*-----------------------------------------------------------*/
\r
593 * ISR for the tick.
\r
594 * This increments the tick count and, if using the preemptive scheduler,
\r
595 * performs a context switch. This must be identical to the manual
\r
596 * context switch in how it stores the context of a task.
\r
598 static void prvTickISR( void )
\r
600 /* Interrupts must have been enabled for the ISR to fire, so we have to
\r
601 save the context with interrupts enabled. */
\r
602 portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
\r
603 PIR1bits.CCP1IF = 0;
\r
605 /* Maintain the tick count. */
\r
606 vTaskIncrementTick();
\r
608 #if configUSE_PREEMPTION == 1
\r
610 /* Switch to the highest priority task that is ready to run. */
\r
611 vTaskSwitchContext();
\r
615 portRESTORE_CONTEXT();
\r
617 /*-----------------------------------------------------------*/
\r
620 * Setup a timer for a regular tick.
\r
622 static void prvSetupTimerInterrupt( void )
\r
624 const unsigned long ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
\r
625 unsigned long ulCompareValue;
\r
626 unsigned char ucByte;
\r
628 /* Interrupts are disabled when this function is called.
\r
630 Setup CCP1 to provide the tick interrupt using a compare match on timer
\r
633 Clear the time count then setup timer. */
\r
634 TMR1H = ( unsigned char ) 0x00;
\r
635 TMR1L = ( unsigned char ) 0x00;
\r
637 /* Set the compare match value. */
\r
638 ulCompareValue = ulConstCompareValue;
\r
639 CCPR1L = ( unsigned char ) ( ulCompareValue & ( unsigned long ) 0xff );
\r
640 ulCompareValue >>= ( unsigned long ) 8;
\r
641 CCPR1H = ( unsigned char ) ( ulCompareValue & ( unsigned long ) 0xff );
\r
643 CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
\r
644 CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
\r
645 CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
\r
646 CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
\r
647 PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
\r
649 /* We are only going to use the global interrupt bit, so set the peripheral
\r
651 INTCONbits.GIEL = portBIT_SET;
\r
653 /* Provided library function for setting up the timer that will produce the
\r
655 OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
\r
projects / freertos / blob