*/\r
\r
/* Includes ------------------------------------------------------------------*/\r
-#define __STM32_HAL_LEGACY 1\r
\r
#if defined(STM32F7xx)\r
#include "stm32f7xx_hal.h"\r
- #include "stm32f7xx_hal_def.h"\r
#define stm_is_F7 1\r
#elif defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\r
#include "stm32f4xx_hal.h"\r
- #include "stm32f4xx_hal_def.h"\r
#define stm_is_F4 1\r
#elif defined(STM32F2xx)\r
#include "stm32f2xx_hal.h"\r
- #include "stm32f2xx_hal_def.h"\r
#define stm_is_F2 1\r
#else\r
#error For what part should this be compiled?\r
*/\r
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)\r
{\r
- uint32_t tmpreg = 0;\r
- uint32_t hclk = 60000000;\r
+ uint32_t tmpreg = 0uL;\r
+ uint32_t hclk = 60000000uL;\r
uint32_t err = ETH_SUCCESS;\r
\r
/* Check the ETH peripheral state */\r
/* Clear CSR Clock Range CR[2:0] bits */\r
tmpreg &= ETH_MACMIIAR_CR_MASK;\r
\r
- /* Get hclk frequency value (168,000,000) */\r
+ /* Get hclk frequency value (e.g. 168,000,000) */\r
hclk = HAL_RCC_GetHCLKFreq();\r
\r
/* Set CR bits depending on hclk value */\r
- if( ( hclk >= 20000000 ) && ( hclk < 35000000 ) )\r
+ if(( hclk >= 20000000uL ) && ( hclk < 35000000uL ) )\r
{\r
/* CSR Clock Range between 20-35 MHz */\r
- tmpreg |= (uint32_t) ETH_MACMIIAR_CR_Div16;\r
+ tmpreg |= ( uint32_t) ETH_MACMIIAR_CR_Div16;\r
}\r
- else if( ( hclk >= 35000000 ) && ( hclk < 60000000 ) )\r
+ else if( ( hclk >= 35000000uL ) && ( hclk < 60000000uL ) )\r
{\r
/* CSR Clock Range between 35-60 MHz */\r
tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26;\r
}\r
- else if((hclk >= 60000000 ) && ( hclk < 100000000 ) )\r
+ else if( ( hclk >= 60000000uL ) && ( hclk < 100000000uL ) )\r
{\r
/* CSR Clock Range between 60-100 MHz */\r
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;\r
}\r
- else if((hclk >= 100000000 ) && ( hclk < 150000000))\r
+ else if( ( hclk >= 100000000uL ) && ( hclk < 150000000uL ) )\r
{\r
/* CSR Clock Range between 100-150 MHz */\r
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;\r
}\r
- else /* ((hclk >= 150000000 ) && ( hclk <= 168000000)) */\r
+ else /* ( ( hclk >= 150000000uL ) && ( hclk <= 183000000uL ) ) */\r
{\r
- /* CSR Clock Range between 150-168 MHz */\r
+ /* CSR Clock Range between 150-183 MHz */\r
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;\r
}\r
\r
return HAL_OK;\r
}\r
\r
-/**\r
- * @brief Initializes the DMA Tx descriptors in chain mode.\r
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
- * the configuration information for ETHERNET module\r
- * @param DMATxDescTab: Pointer to the first Tx desc list\r
- * @param TxBuff: Pointer to the first TxBuffer list\r
- * @param TxBuffCount: Number of the used Tx desc in the list\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)\r
-{\r
- uint32_t i = 0;\r
- ETH_DMADescTypeDef *pxDMADescriptor;\r
-\r
- /* Process Locked */\r
- __HAL_LOCK( heth );\r
-\r
- /* Set the ETH peripheral state to BUSY */\r
- heth->State = HAL_ETH_STATE_BUSY;\r
-\r
- /* Set the TxDesc pointer with the first one of the pxDMATable list */\r
- heth->TxDesc = pxDMATable;\r
-\r
- /* Fill each DMA descriptor with the right values */\r
- for( i=0; i < ulBufferCount; i++ )\r
- {\r
- /* Get the pointer on the ith member of the descriptor list */\r
- pxDMADescriptor = pxDMATable + i;\r
-\r
- /* Set Second Address Chained bit */\r
- pxDMADescriptor->Status = ETH_DMATXDESC_TCH;\r
-\r
- pxDMADescriptor->ControlBufferSize = 0;\r
-\r
- /* Set Buffer1 address pointer */\r
- if( ucDataBuffer != NULL )\r
- {\r
- pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_TX_BUF_SIZE ] );\r
- }\r
- else\r
- {\r
- /* Buffer space is not provided because it uses zero-copy transmissions. */\r
- pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;\r
- }\r
-\r
- if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
- {\r
- /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */\r
- pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;\r
- }\r
-\r
- /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
- if(i < ( ulBufferCount - 1 ) )\r
- {\r
- /* Set next descriptor address register with next descriptor base address */\r
- pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMATable + i + 1 );\r
- }\r
- else\r
- {\r
- /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
- pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;\r
- }\r
- }\r
-\r
- /* Set Transmit Descriptor List Address Register */\r
- heth->Instance->DMATDLAR = ( uint32_t ) pxDMATable;\r
-\r
- /* Set ETH HAL State to Ready */\r
- heth->State= HAL_ETH_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK( heth );\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the DMA Rx descriptors in chain mode.\r
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
- * the configuration information for ETHERNET module\r
- * @param DMARxDescTab: Pointer to the first Rx desc list\r
- * @param RxBuff: Pointer to the first RxBuffer list\r
- * @param RxBuffCount: Number of the used Rx desc in the list\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)\r
-{\r
- uint32_t i = 0;\r
- ETH_DMADescTypeDef *pxDMADescriptor;\r
-\r
- /* Process Locked */\r
- __HAL_LOCK( heth );\r
-\r
- /* Set the ETH peripheral state to BUSY */\r
- heth->State = HAL_ETH_STATE_BUSY;\r
-\r
- /* Set the RxDesc pointer with the first one of the pxDMATable list */\r
- heth->RxDesc = pxDMATable;\r
-\r
- /* Fill each DMA descriptor with the right values */\r
- for(i=0; i < ulBufferCount; i++)\r
- {\r
- /* Get the pointer on the ith member of the descriptor list */\r
- pxDMADescriptor = pxDMATable+i;\r
-\r
- /* Set Own bit of the Rx descriptor Status */\r
- pxDMADescriptor->Status = ETH_DMARXDESC_OWN;\r
-\r
- /* Set Buffer1 size and Second Address Chained bit */\r
- pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;\r
-\r
- /* Set Buffer1 address pointer */\r
- if( ucDataBuffer != NULL )\r
- {\r
- pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_RX_BUF_SIZE ] );\r
- }\r
- else\r
- {\r
- /* Buffer space is not provided because it uses zero-copy reception. */\r
- pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;\r
- }\r
-\r
- if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE )\r
- {\r
- /* Enable Ethernet DMA Rx Descriptor interrupt */\r
- pxDMADescriptor->ControlBufferSize &= ~ETH_DMARXDESC_DIC;\r
- }\r
-\r
- /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
- if(i < (ulBufferCount-1))\r
- {\r
- /* Set next descriptor address register with next descriptor base address */\r
- pxDMADescriptor->Buffer2NextDescAddr = (uint32_t)(pxDMATable+i+1);\r
- }\r
- else\r
- {\r
- /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
- pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;\r
- }\r
- }\r
-\r
- /* Set Receive Descriptor List Address Register */\r
- heth->Instance->DMARDLAR = ( uint32_t ) pxDMATable;\r
-\r
- /* Set ETH HAL State to Ready */\r
- heth->State= HAL_ETH_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK( heth );\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
/**\r
* @brief Initializes the ETH MSP.\r
* @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
/* NOTE : This function Should not be modified, when the callback is needed,\r
the HAL_ETH_MspInit could be implemented in the user file\r
*/\r
+ ( void ) heth;\r
}\r
\r
/**\r
/* NOTE : This function Should not be modified, when the callback is needed,\r
the HAL_ETH_MspDeInit could be implemented in the user file\r
*/\r
+ ( void ) heth;\r
}\r
\r
/**\r
* @{\r
*/\r
\r
-/**\r
- * @brief Sends an Ethernet frame.\r
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
- * the configuration information for ETHERNET module\r
- * @param FrameLength: Amount of data to be sent\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)\r
-{\r
- uint32_t bufcount = 0, size = 0, i = 0;\r
- __IO ETH_DMADescTypeDef *pxDmaTxDesc = heth->TxDesc;\r
- /* Process Locked */\r
- __HAL_LOCK( heth );\r
-\r
- /* Set the ETH peripheral state to BUSY */\r
- heth->State = HAL_ETH_STATE_BUSY;\r
-\r
- if( FrameLength == 0 )\r
- {\r
- /* Set ETH HAL state to READY */\r
- heth->State = HAL_ETH_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK( heth );\r
-\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
- if( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) != ( uint32_t ) RESET )\r
- {\r
- /* OWN bit set */\r
- heth->State = HAL_ETH_STATE_BUSY_TX;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK( heth );\r
-\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Get the number of needed Tx buffers for the current frame, rounding up. */\r
- bufcount = ( FrameLength + ETH_TX_BUF_SIZE - 1 ) / ETH_TX_BUF_SIZE;\r
-\r
- if (bufcount == 1)\r
- {\r
- /* Set LAST and FIRST segment */\r
- pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;\r
- /* Set frame size */\r
- pxDmaTxDesc->ControlBufferSize = ( FrameLength & ETH_DMATXDESC_TBS1 );\r
- /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
- pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;\r
- /* Point to next descriptor */\r
- heth->TxDesc = ( ETH_DMADescTypeDef * ) ( heth->TxDesc->Buffer2NextDescAddr );\r
- }\r
- else\r
- {\r
- for( i = 0; i < bufcount; i++ )\r
- {\r
- /* Clear FIRST and LAST segment bits */\r
- uint32_t ulStatus = heth->TxDesc->Status & ~( ETH_DMATXDESC_FS | ETH_DMATXDESC_LS );\r
-\r
- if( i == 0 )\r
- {\r
- /* Setting the first segment bit */\r
- heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_FS;\r
- }\r
-\r
- /* Program size */\r
- if (i < (bufcount-1))\r
- {\r
- heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);\r
- }\r
- else\r
- {\r
- /* Setting the last segment bit */\r
- heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_LS;\r
- size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;\r
- heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);\r
- }\r
-\r
- /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
- heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r
- /* point to next descriptor */\r
- heth->TxDesc = (ETH_DMADescTypeDef *)( heth->TxDesc->Buffer2NextDescAddr );\r
- }\r
- }\r
-\r
- __DSB();\r
-\r
- /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
- if( ( heth->Instance->DMASR & ETH_DMASR_TBUS ) != ( uint32_t )RESET )\r
- {\r
- heth->Instance->DMACHTDR = ( uint32_t )pxDmaTxDesc;\r
-\r
- /* Clear TBUS ETHERNET DMA flag */\r
- heth->Instance->DMASR = ETH_DMASR_TBUS;\r
- /* Resume DMA transmission*/\r
- heth->Instance->DMATPDR = 0;\r
- }\r
-\r
- /* Set ETH HAL State to Ready */\r
- heth->State = HAL_ETH_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK( heth );\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Checks for received frames.\r
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
- * the configuration information for ETHERNET module\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef *heth )\r
-{\r
- return HAL_ETH_GetReceivedFrame( heth );\r
-}\r
-\r
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef *heth )\r
-{\r
-uint32_t ulCounter = 0;\r
-ETH_DMADescTypeDef *pxDescriptor = heth->RxDesc;\r
-HAL_StatusTypeDef xResult = HAL_ERROR;\r
-\r
- /* Process Locked */\r
- __HAL_LOCK( heth );\r
-\r
- /* Check the ETH state to BUSY */\r
- heth->State = HAL_ETH_STATE_BUSY;\r
-\r
- /* Scan descriptors owned by CPU */\r
- while( ( ( pxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0ul ) && ( ulCounter < ETH_RXBUFNB ) )\r
- {\r
- uint32_t ulStatus = pxDescriptor->Status;\r
-\r
- /* Just for security. */\r
- ulCounter++;\r
-\r
- if( ( ulStatus & ( ETH_DMARXDESC_FS | ETH_DMARXDESC_LS ) ) == ( uint32_t )ETH_DMARXDESC_FS )\r
- {\r
- /* First segment in frame, but not the last. */\r
- heth->RxFrameInfos.FSRxDesc = pxDescriptor;\r
- heth->RxFrameInfos.LSRxDesc = ( ETH_DMADescTypeDef *)NULL;\r
- heth->RxFrameInfos.SegCount = 1;\r
- /* Point to next descriptor. */\r
- pxDescriptor = (ETH_DMADescTypeDef*) (pxDescriptor->Buffer2NextDescAddr);\r
- heth->RxDesc = pxDescriptor;\r
- }\r
- else if( ( ulStatus & ( ETH_DMARXDESC_LS | ETH_DMARXDESC_FS ) ) == 0ul )\r
- {\r
- /* This is an intermediate segment, not first, not last. */\r
- /* Increment segment count. */\r
- heth->RxFrameInfos.SegCount++;\r
- /* Move to the next descriptor. */\r
- pxDescriptor = ( ETH_DMADescTypeDef * ) ( pxDescriptor->Buffer2NextDescAddr );\r
- heth->RxDesc = pxDescriptor;\r
- }\r
- /* Must be a last segment */\r
- else\r
- {\r
- /* This is the last segment. */\r
- /* Check if last segment is first segment: one segment contains the frame */\r
- if( heth->RxFrameInfos.SegCount == 0 )\r
- {\r
- /* Remember the first segment. */\r
- heth->RxFrameInfos.FSRxDesc = pxDescriptor;\r
- }\r
-\r
- /* Increment segment count */\r
- heth->RxFrameInfos.SegCount++;\r
-\r
- /* Remember the last segment. */\r
- heth->RxFrameInfos.LSRxDesc = pxDescriptor;\r
-\r
- /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
- heth->RxFrameInfos.length =\r
- ( ( ulStatus & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;\r
-\r
- /* Get the address of the buffer start address */\r
- heth->RxFrameInfos.buffer = heth->RxFrameInfos.FSRxDesc->Buffer1Addr;\r
-\r
- /* Point to next descriptor */\r
- heth->RxDesc = ( ETH_DMADescTypeDef * ) pxDescriptor->Buffer2NextDescAddr;\r
-\r
- /* Return OK status: a packet was received. */\r
- xResult = HAL_OK;\r
- break;\r
- }\r
- }\r
-\r
- /* Set ETH HAL State to Ready */\r
- heth->State = HAL_ETH_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK( heth );\r
-\r
- /* Return function status */\r
- return xResult;\r
-}\r
-\r
#define ETH_DMA_ALL_INTS \\r
( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \\r
ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \\r
/* NOTE : This function Should not be modified, when the callback is needed,\r
the HAL_ETH_TxCpltCallback could be implemented in the user file\r
*/\r
+ ( void ) heth;\r
}\r
\r
/**\r
/* NOTE : This function Should not be modified, when the callback is needed,\r
the HAL_ETH_TxCpltCallback could be implemented in the user file\r
*/\r
+ ( void ) heth;\r
}\r
\r
/**\r
/* NOTE : This function Should not be modified, when the callback is needed,\r
the HAL_ETH_TxCpltCallback could be implemented in the user file\r
*/\r
+ ( void ) heth;\r
}\r
\r
/**\r
*/\r
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)\r
{\r
-uint32_t tmpreg = 0;\r
-uint32_t tickstart = 0;\r
+uint32_t tmpreg = 0uL;\r
+uint32_t tickstart = 0uL;\r
HAL_StatusTypeDef xResult;\r
\r
/* Check parameters */\r
{\r
tmpreg = heth->Instance->MACMIIAR;\r
\r
- if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )\r
+ if( ( tmpreg & ETH_MACMIIAR_MB ) == 0uL )\r
{\r
/* Get MACMIIDR value */\r
*RegValue = ( uint32_t ) heth->Instance->MACMIIDR;\r
return HAL_OK;\r
}\r
\r
+static void vRegisterDelay()\r
+{\r
+uint32_t uxCount;\r
+ /*\r
+ * Regarding the HAL delay functions, I noticed that HAL delay is being used to workaround the\r
+ * "Successive write operations to the same register might not be fully taken into account" errata.\r
+ * The workaround requires a delay of four TX_CLK/RX_CLK clock cycles. For a 10 Mbit connection,\r
+ * these clocks are running at 2.5 MHz, so this delay would be at most 1.6 microseconds.\r
+ * 180 Mhz = 288 loops\r
+ * 168 Mhz = 269 loops\r
+ * 100 Mhz = 160 loops\r
+ * 84 Mhz = 134 loops\r
+ */\r
+ #define WAIT_TIME_NS 1600uL /* 1.6 microseconds */\r
+ #define CPU_MAX_FREQ SystemCoreClock /* 84, 100, 168 or 180 MHz */\r
+ uint32_t NOP_COUNT = ( WAIT_TIME_NS * ( CPU_MAX_FREQ / 1000uL ) ) / 1000000uL;\r
+ for( uxCount = NOP_COUNT; uxCount > 0uL; uxCount-- )\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
static void prvWriteMACFCR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
{\r
/* Enable the MAC transmission */\r
Read it back, wait a ms and */\r
( void ) heth->Instance->MACFCR;\r
\r
- HAL_Delay( ETH_REG_WRITE_DELAY );\r
+ vRegisterDelay();\r
\r
heth->Instance->MACFCR = ulValue;\r
}\r
Read it back, wait a ms and */\r
( void ) heth->Instance->DMAOMR;\r
\r
- HAL_Delay( ETH_REG_WRITE_DELAY );\r
+ vRegisterDelay();\r
\r
heth->Instance->DMAOMR = ulValue;\r
}\r
Read it back, wait a ms and */\r
( void ) heth->Instance->MACCR;\r
\r
- HAL_Delay( ETH_REG_WRITE_DELAY );\r
+ vRegisterDelay();\r
\r
heth->Instance->MACCR = ulValue;\r
}\r
*/\r
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)\r
{\r
- uint32_t tmpreg = 0;\r
+ uint32_t tmpreg = 0uL;\r
\r
/* Process Locked */\r
__HAL_LOCK( heth );\r
/* Wait until the write operation will be taken into account :\r
at least four TX_CLK/RX_CLK clock cycles */\r
tmpreg = heth->Instance->MACFFR;\r
- HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ vRegisterDelay();\r
heth->Instance->MACFFR = tmpreg;\r
\r
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/\r
/* Wait until the write operation will be taken into account :\r
at least four TX_CLK/RX_CLK clock cycles */\r
tmpreg = heth->Instance->MACVLANTR;\r
- HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ vRegisterDelay();\r
heth->Instance->MACVLANTR = tmpreg;\r
}\r
else /* macconf == NULL : here we just configure Speed and Duplex mode */\r
tmpreg = heth->Instance->MACCR;\r
\r
/* Clear FES and DM bits */\r
- tmpreg &= ~((uint32_t)0x00004800);\r
+ tmpreg &= ~( ( uint32_t ) 0x00004800uL );\r
\r
tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);\r
\r
*/\r
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)\r
{\r
- uint32_t tmpreg = 0;\r
+ uint32_t tmpreg = 0uL;\r
\r
/* Process Locked */\r
__HAL_LOCK( heth );\r
/* Wait until the write operation will be taken into account:\r
at least four TX_CLK/RX_CLK clock cycles */\r
tmpreg = heth->Instance->DMABMR;\r
- HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ vRegisterDelay();\r
heth->Instance->DMABMR = tmpreg;\r
\r
/* Set the ETH state to Ready */\r
{\r
ETH_MACInitTypeDef macinit;\r
ETH_DMAInitTypeDef dmainit;\r
- uint32_t tmpreg = 0;\r
+ uint32_t tmpreg = 0uL;\r
\r
if (err != ETH_SUCCESS) /* Auto-negotiation failed */\r
{\r
macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;\r
macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;\r
macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;\r
- macinit.HashTableHigh = 0x0;\r
- macinit.HashTableLow = 0x0;\r
- macinit.PauseTime = 0x0;\r
+ macinit.HashTableHigh = 0x0uL;\r
+ macinit.HashTableLow = 0x0uL;\r
+ macinit.PauseTime = 0x0uL;\r
macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;\r
macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;\r
macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;\r
macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;\r
macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;\r
macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;\r
- macinit.VLANTagIdentifier = 0x0;\r
+ macinit.VLANTagIdentifier = 0x0uL;\r
\r
/*------------------------ ETHERNET MACCR Configuration --------------------*/\r
/* Get the ETHERNET MACCR value */\r
/* Wait until the write operation will be taken into account:\r
at least four TX_CLK/RX_CLK clock cycles */\r
tmpreg = heth->Instance->MACFFR;\r
- HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ vRegisterDelay();\r
heth->Instance->MACFFR = tmpreg;\r
\r
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/\r
/* Wait until the write operation will be taken into account:\r
at least four TX_CLK/RX_CLK clock cycles */\r
tmpreg = heth->Instance->MACVLANTR;\r
- HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ vRegisterDelay();\r
heth->Instance->MACVLANTR = tmpreg;\r
\r
/* Ethernet DMA default initialization ************************************/\r
dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;\r
dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;\r
dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;\r
- dmainit.DescriptorSkipLength = 0x0;\r
+ dmainit.DescriptorSkipLength = 0x0uL;\r
dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;\r
\r
/* Get the ETHERNET DMAOMR value */\r
/* Wait until the write operation will be taken into account:\r
at least four TX_CLK/RX_CLK clock cycles */\r
tmpreg = heth->Instance->DMABMR;\r
- HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ vRegisterDelay();\r
heth->Instance->DMABMR = tmpreg;\r
\r
if(heth->Init.RxMode == ETH_RXINTERRUPT_MODE)\r
{\r
uint32_t tmpreg;\r
\r
+ ( void ) heth;\r
+\r
/* Check the parameters */\r
assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) );\r
\r
/* Calculate the selected MAC address high register */\r
- tmpreg = 0x80000000ul | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ];\r
+ /* Register ETH_MACA0HR: Bit 31 MO: Always 1. */\r
+ tmpreg = 0x80000000uL | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ];\r
/* Load the selected MAC address high register */\r
( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg;\r
/* Calculate the selected MAC address low register */\r
projects / freertos / blobdiff