--- /dev/null
+/**************************************************************************//**\r
+ * @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*****************************************************************************/\r
+#include "M480.h"\r
+#ifndef _M480_ETH_\r
+#define _M480_ETH_\r
+\r
+/* Generic MII registers. */\r
+\r
+#define MII_BMCR 0x00 /* Basic mode control register */\r
+#define MII_BMSR 0x01 /* Basic mode status register */\r
+#define MII_PHYSID1 0x02 /* PHYS ID 1 */\r
+#define MII_PHYSID2 0x03 /* PHYS ID 2 */\r
+#define MII_ADVERTISE 0x04 /* Advertisement control reg */\r
+#define MII_LPA 0x05 /* Link partner ability reg */\r
+#define MII_EXPANSION 0x06 /* Expansion register */\r
+#define MII_DCOUNTER 0x12 /* Disconnect counter */\r
+#define MII_FCSCOUNTER 0x13 /* False carrier counter */\r
+#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */\r
+#define MII_RERRCOUNTER 0x15 /* Receive error counter */\r
+#define MII_SREVISION 0x16 /* Silicon revision */\r
+#define MII_RESV1 0x17 /* Reserved... */\r
+#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */\r
+#define MII_PHYADDR 0x19 /* PHY address */\r
+#define MII_RESV2 0x1a /* Reserved... */\r
+#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */\r
+#define MII_NCONFIG 0x1c /* Network interface config */\r
+\r
+/* Basic mode control register. */\r
+#define BMCR_RESV 0x007f /* Unused... */\r
+#define BMCR_CTST 0x0080 /* Collision test */\r
+#define BMCR_FULLDPLX 0x0100 /* Full duplex */\r
+#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */\r
+#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */\r
+#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */\r
+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */\r
+#define BMCR_SPEED100 0x2000 /* Select 100Mbps */\r
+#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */\r
+#define BMCR_RESET 0x8000 /* Reset the DP83840 */\r
+\r
+/* Basic mode status register. */\r
+#define BMSR_ERCAP 0x0001 /* Ext-reg capability */\r
+#define BMSR_JCD 0x0002 /* Jabber detected */\r
+#define BMSR_LSTATUS 0x0004 /* Link status */\r
+#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */\r
+#define BMSR_RFAULT 0x0010 /* Remote fault detected */\r
+#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */\r
+#define BMSR_RESV 0x07c0 /* Unused... */\r
+#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */\r
+#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */\r
+#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */\r
+#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */\r
+#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */\r
+\r
+/* Advertisement control register. */\r
+#define ADVERTISE_SLCT 0x001f /* Selector bits */\r
+#define ADVERTISE_CSMA 0x0001 /* Only selector supported */\r
+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */\r
+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */\r
+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */\r
+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */\r
+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */\r
+#define ADVERTISE_RESV 0x1c00 /* Unused... */\r
+#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */\r
+#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */\r
+#define ADVERTISE_NPAGE 0x8000 /* Next page bit */\r
+\r
+#define RX_DESCRIPTOR_NUM 4 //8 // Max Number of Rx Frame Descriptors\r
+#define TX_DESCRIPTOR_NUM 2 //4 // Max number of Tx Frame Descriptors\r
+\r
+#define PACKET_BUFFER_SIZE 1520\r
+\r
+#define CONFIG_PHY_ADDR 1\r
+\r
+\r
+// Frame Descriptor's Owner bit\r
+#define OWNERSHIP_EMAC 0x80000000 // 1 = EMAC\r
+//#define OWNERSHIP_CPU 0x7fffffff // 0 = CPU\r
+\r
+\r
+\r
+// Rx Frame Descriptor Status\r
+#define RXFD_RXGD 0x00100000 // Receiving Good Packet Received\r
+#define RXFD_RTSAS 0x00800000 // RX Time Stamp Available \r
+\r
+\r
+// Tx Frame Descriptor's Control bits\r
+#define TXFD_TTSEN 0x08 // Tx Time Stamp Enable\r
+#define TXFD_INTEN 0x04 // Interrupt Enable\r
+#define TXFD_CRCAPP 0x02 // Append CRC\r
+#define TXFD_PADEN 0x01 // Padding Enable\r
+\r
+// Tx Frame Descriptor Status\r
+#define TXFD_TXCP 0x00080000 // Transmission Completion\r
+#define TXFD_TTSAS 0x08000000 // TX Time Stamp Available\r
+\r
+// Tx/Rx buffer descriptor structure\r
+struct eth_descriptor;\r
+struct eth_descriptor {\r
+ uint32_t status1;\r
+ uint8_t *buf;\r
+ uint32_t status2;\r
+ struct eth_descriptor *next;\r
+#ifdef TIME_STAMPING\r
+ uint32_t backup1;\r
+ uint32_t backup2;\r
+ uint32_t reserved1;\r
+ uint32_t reserved2;\r
+#endif\r
+};\r
+\r
+#ifdef TIME_STAMPING\r
+\r
+#define ETH_TS_ENABLE() do{EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;}while(0)\r
+#define ETH_TS_START() do{EMAC->TSCTL |= (EMAC_TSCTL_TSMODE_Msk | EMAC_TSCTL_TSIEN_Msk);}while(0)\r
+s32_t ETH_settime(u32_t sec, u32_t nsec);\r
+s32_t ETH_gettime(u32_t *sec, u32_t *nsec);\r
+s32_t ETH_updatetime(u32_t neg, u32_t sec, u32_t nsec);\r
+s32_t ETH_adjtimex(int ppm);\r
+void ETH_setinc(void);\r
+\r
+#endif\r
+\r
+#ifdef NU_TRACE\r
+#define NU_DEBUGF(x) { printf x; }\r
+#else\r
+#define NU_DEBUGF(x)\r
+#endif\r
+\r
+void numaker_set_mac_addr(uint8_t *addr);\r
+int numaker_eth_init(uint8_t *mac_addr);\r
+uint8_t *numaker_eth_get_tx_buf(void);\r
+void numaker_eth_trigger_tx(uint16_t length, void *p);\r
+int numaker_eth_get_rx_buf(uint16_t *len, uint8_t **buf);\r
+void numaker_eth_rx_next(void);\r
+void numaker_eth_trigger_rx(void);\r
+int numaker_eth_link_ok(void);\r
+void numaker_mac_address(uint8_t *mac);\r
+void numaker_eth_enable_interrupts(void);\r
+void numaker_eth_disable_interrupts(void);\r
+\r
+#endif /* _M480_ETH_ */\r
projects / freertos / blobdiff