-/**\r
- ******************************************************************************\r
- * @file stm32f4xx_hal_eth.h\r
- * @author MCD Application Team\r
- * @version V1.3.2\r
- * @date 26-June-2015\r
- * @brief Header file of ETH HAL module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F4xx_HAL_ETH_H\r
-#define __STM32F4xx_HAL_ETH_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F4xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup ETH\r
- * @{\r
- */\r
-\r
-/** @addtogroup ETH_Private_Macros\r
- * @{\r
- */\r
-#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r
-#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \\r
- ((CMD) == ETH_AUTONEGOTIATION_DISABLE))\r
-#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \\r
- ((SPEED) == ETH_SPEED_100M))\r
-#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
- ((MODE) == ETH_MODE_HALFDUPLEX))\r
-#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
- ((MODE) == ETH_MODE_HALFDUPLEX))\r
-#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
- ((MODE) == ETH_RXINTERRUPT_MODE))\r
-#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
- ((MODE) == ETH_RXINTERRUPT_MODE))\r
-#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
- ((MODE) == ETH_RXINTERRUPT_MODE))\r
-#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \\r
- ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))\r
-#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \\r
- ((MODE) == ETH_MEDIA_INTERFACE_RMII))\r
-#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \\r
- ((CMD) == ETH_WATCHDOG_DISABLE))\r
-#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \\r
- ((CMD) == ETH_JABBER_DISABLE))\r
-#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \\r
- ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \\r
- ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \\r
- ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \\r
- ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \\r
- ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \\r
- ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \\r
- ((GAP) == ETH_INTERFRAMEGAP_40BIT))\r
-#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \\r
- ((CMD) == ETH_CARRIERSENCE_DISABLE))\r
-#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \\r
- ((CMD) == ETH_RECEIVEOWN_DISABLE))\r
-#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \\r
- ((CMD) == ETH_LOOPBACKMODE_DISABLE))\r
-#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \\r
- ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))\r
-#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \\r
- ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))\r
-#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \\r
- ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))\r
-#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \\r
- ((LIMIT) == ETH_BACKOFFLIMIT_8) || \\r
- ((LIMIT) == ETH_BACKOFFLIMIT_4) || \\r
- ((LIMIT) == ETH_BACKOFFLIMIT_1))\r
-#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \\r
- ((CMD) == ETH_DEFFERRALCHECK_DISABLE))\r
-#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \\r
- ((CMD) == ETH_RECEIVEAll_DISABLE))\r
-#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \\r
- ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \\r
- ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))\r
-#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \\r
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \\r
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))\r
-#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \\r
- ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))\r
-#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \\r
- ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))\r
-#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \\r
- ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))\r
-#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \\r
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \\r
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))\r
-#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
- ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \\r
- ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))\r
-#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r
-#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \\r
- ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))\r
-#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \\r
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \\r
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \\r
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))\r
-#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \\r
- ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))\r
-#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \\r
- ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))\r
-#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \\r
- ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))\r
-#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \\r
- ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))\r
-#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r
-#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \\r
- ((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
- ((ADDRESS) == ETH_MAC_ADDRESS3))\r
-#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
- ((ADDRESS) == ETH_MAC_ADDRESS3))\r
-#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \\r
- ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))\r
-#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \\r
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \\r
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \\r
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \\r
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \\r
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))\r
-#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \\r
- ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))\r
-#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \\r
- ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))\r
-#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \\r
- ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))\r
-#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \\r
- ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))\r
-#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \\r
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \\r
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \\r
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \\r
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \\r
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \\r
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \\r
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))\r
-#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \\r
- ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))\r
-#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \\r
- ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))\r
-#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \\r
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \\r
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \\r
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))\r
-#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \\r
- ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))\r
-#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \\r
- ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))\r
-#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \\r
- ((CMD) == ETH_FIXEDBURST_DISABLE))\r
-#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))\r
-#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))\r
-#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r
-#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \\r
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \\r
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \\r
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \\r
- ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))\r
-#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \\r
- ((FLAG) == ETH_DMATXDESC_IC) || \\r
- ((FLAG) == ETH_DMATXDESC_LS) || \\r
- ((FLAG) == ETH_DMATXDESC_FS) || \\r
- ((FLAG) == ETH_DMATXDESC_DC) || \\r
- ((FLAG) == ETH_DMATXDESC_DP) || \\r
- ((FLAG) == ETH_DMATXDESC_TTSE) || \\r
- ((FLAG) == ETH_DMATXDESC_TER) || \\r
- ((FLAG) == ETH_DMATXDESC_TCH) || \\r
- ((FLAG) == ETH_DMATXDESC_TTSS) || \\r
- ((FLAG) == ETH_DMATXDESC_IHE) || \\r
- ((FLAG) == ETH_DMATXDESC_ES) || \\r
- ((FLAG) == ETH_DMATXDESC_JT) || \\r
- ((FLAG) == ETH_DMATXDESC_FF) || \\r
- ((FLAG) == ETH_DMATXDESC_PCE) || \\r
- ((FLAG) == ETH_DMATXDESC_LCA) || \\r
- ((FLAG) == ETH_DMATXDESC_NC) || \\r
- ((FLAG) == ETH_DMATXDESC_LCO) || \\r
- ((FLAG) == ETH_DMATXDESC_EC) || \\r
- ((FLAG) == ETH_DMATXDESC_VF) || \\r
- ((FLAG) == ETH_DMATXDESC_CC) || \\r
- ((FLAG) == ETH_DMATXDESC_ED) || \\r
- ((FLAG) == ETH_DMATXDESC_UF) || \\r
- ((FLAG) == ETH_DMATXDESC_DB))\r
-#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \\r
- ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))\r
-#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \\r
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \\r
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \\r
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))\r
-#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r
-#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \\r
- ((FLAG) == ETH_DMARXDESC_AFM) || \\r
- ((FLAG) == ETH_DMARXDESC_ES) || \\r
- ((FLAG) == ETH_DMARXDESC_DE) || \\r
- ((FLAG) == ETH_DMARXDESC_SAF) || \\r
- ((FLAG) == ETH_DMARXDESC_LE) || \\r
- ((FLAG) == ETH_DMARXDESC_OE) || \\r
- ((FLAG) == ETH_DMARXDESC_VLAN) || \\r
- ((FLAG) == ETH_DMARXDESC_FS) || \\r
- ((FLAG) == ETH_DMARXDESC_LS) || \\r
- ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \\r
- ((FLAG) == ETH_DMARXDESC_LC) || \\r
- ((FLAG) == ETH_DMARXDESC_FT) || \\r
- ((FLAG) == ETH_DMARXDESC_RWT) || \\r
- ((FLAG) == ETH_DMARXDESC_RE) || \\r
- ((FLAG) == ETH_DMARXDESC_DBE) || \\r
- ((FLAG) == ETH_DMARXDESC_CE) || \\r
- ((FLAG) == ETH_DMARXDESC_MAMPCE))\r
-#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \\r
- ((BUFFER) == ETH_DMARXDESC_BUFFER2))\r
-#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\r
- ((FLAG) == ETH_PMT_FLAG_MPR))\r
-#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))\r
-#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\r
- ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \\r
- ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \\r
- ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\r
- ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\r
- ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\r
- ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\r
- ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\r
- ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\r
- ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\r
- ((FLAG) == ETH_DMA_FLAG_T))\r
-#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))\r
-#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\r
- ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\r
- ((IT) == ETH_MAC_IT_PMT))\r
-#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\r
- ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\r
- ((FLAG) == ETH_MAC_FLAG_PMT))\r
-#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))\r
-#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\r
- ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\r
- ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\r
- ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\r
- ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\r
- ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\r
- ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\r
- ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\r
- ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r
-#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \\r
- ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))\r
-#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \\r
- ((IT) != 0x00))\r
-#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\r
- ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\r
- ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r
-#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \\r
- ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup ETH_Private_Defines\r
- * @{\r
- */\r
-/* Delay to wait when writing to some Ethernet registers */\r
-#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)\r
-\r
-/* ETHERNET Errors */\r
-#define ETH_SUCCESS ((uint32_t)0)\r
-#define ETH_ERROR ((uint32_t)1)\r
-\r
-/* ETHERNET DMA Tx descriptors Collision Count Shift */\r
-#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)\r
-\r
-/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */\r
-#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)\r
-\r
-/* ETHERNET DMA Rx descriptors Frame Length Shift */\r
-#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)\r
-\r
-/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */\r
-#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)\r
-\r
-/* ETHERNET DMA Rx descriptors Frame length Shift */\r
-#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)\r
-\r
-/* ETHERNET MAC address offsets */\r
-#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */\r
-#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */\r
-\r
-/* ETHERNET MACMIIAR register Mask */\r
-#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)\r
-\r
-/* ETHERNET MACCR register Mask */\r
-#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)\r
-\r
-/* ETHERNET MACFCR register Mask */\r
-#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)\r
-\r
-/* ETHERNET DMAOMR register Mask */\r
-#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)\r
-\r
-/* ETHERNET Remote Wake-up frame register length */\r
-#define ETH_WAKEUP_REGISTER_LENGTH 8\r
-\r
-/* ETHERNET Missed frames counter Shift */\r
-#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17\r
- /**\r
- * @}\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup ETH_Exported_Types ETH Exported Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief HAL State structures definition\r
- */\r
-typedef enum\r
-{\r
- HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */\r
- HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
- HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */\r
- HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */\r
- HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */\r
- HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */\r
- HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */\r
- HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */\r
- HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
- HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */\r
-}HAL_ETH_StateTypeDef;\r
-\r
-/**\r
- * @brief ETH Init Structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY\r
- The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)\r
- and the mode (half/full-duplex).\r
- This parameter can be a value of @ref ETH_AutoNegotiation */\r
-\r
- uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.\r
- This parameter can be a value of @ref ETH_Speed */\r
-\r
- uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode\r
- This parameter can be a value of @ref ETH_Duplex_Mode */\r
-\r
- uint16_t PhyAddress; /*!< Ethernet PHY address.\r
- This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r
-\r
- uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */\r
-\r
- uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.\r
- This parameter can be a value of @ref ETH_Rx_Mode */\r
-\r
- uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.\r
- This parameter can be a value of @ref ETH_Checksum_Mode */\r
-\r
- uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.\r
- This parameter can be a value of @ref ETH_Media_Interface */\r
-\r
-} ETH_InitTypeDef;\r
-\r
-\r
- /**\r
- * @brief ETH MAC Configuration Structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t Watchdog; /*!< Selects or not the Watchdog timer\r
- When enabled, the MAC allows no more then 2048 bytes to be received.\r
- When disabled, the MAC can receive up to 16384 bytes.\r
- This parameter can be a value of @ref ETH_Watchdog */\r
-\r
- uint32_t Jabber; /*!< Selects or not Jabber timer\r
- When enabled, the MAC allows no more then 2048 bytes to be sent.\r
- When disabled, the MAC can send up to 16384 bytes.\r
- This parameter can be a value of @ref ETH_Jabber */\r
-\r
- uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.\r
- This parameter can be a value of @ref ETH_Inter_Frame_Gap */\r
-\r
- uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.\r
- This parameter can be a value of @ref ETH_Carrier_Sense */\r
-\r
- uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,\r
- ReceiveOwn allows the reception of frames when the TX_EN signal is asserted\r
- in Half-Duplex mode.\r
- This parameter can be a value of @ref ETH_Receive_Own */\r
-\r
- uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.\r
- This parameter can be a value of @ref ETH_Loop_Back_Mode */\r
-\r
- uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.\r
- This parameter can be a value of @ref ETH_Checksum_Offload */\r
-\r
- uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,\r
- when a collision occurs (Half-Duplex mode).\r
- This parameter can be a value of @ref ETH_Retry_Transmission */\r
-\r
- uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.\r
- This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */\r
-\r
- uint32_t BackOffLimit; /*!< Selects the BackOff limit value.\r
- This parameter can be a value of @ref ETH_Back_Off_Limit */\r
-\r
- uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).\r
- This parameter can be a value of @ref ETH_Deferral_Check */\r
-\r
- uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).\r
- This parameter can be a value of @ref ETH_Receive_All */\r
-\r
- uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.\r
- This parameter can be a value of @ref ETH_Source_Addr_Filter */\r
-\r
- uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)\r
- This parameter can be a value of @ref ETH_Pass_Control_Frames */\r
-\r
- uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.\r
- This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */\r
-\r
- uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.\r
- This parameter can be a value of @ref ETH_Destination_Addr_Filter */\r
-\r
- uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode\r
- This parameter can be a value of @ref ETH_Promiscuous_Mode */\r
-\r
- uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
- This parameter can be a value of @ref ETH_Multicast_Frames_Filter */\r
-\r
- uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
- This parameter can be a value of @ref ETH_Unicast_Frames_Filter */\r
-\r
- uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.\r
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r
-\r
- uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.\r
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r
-\r
- uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.\r
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */\r
-\r
- uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.\r
- This parameter can be a value of @ref ETH_Zero_Quanta_Pause */\r
-\r
- uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for\r
- automatic retransmission of PAUSE Frame.\r
- This parameter can be a value of @ref ETH_Pause_Low_Threshold */\r
-\r
- uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0\r
- unicast address and unique multicast address).\r
- This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */\r
-\r
- uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and\r
- disable its transmitter for a specified time (Pause Time)\r
- This parameter can be a value of @ref ETH_Receive_Flow_Control */\r
-\r
- uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)\r
- or the MAC back-pressure operation (Half-Duplex mode)\r
- This parameter can be a value of @ref ETH_Transmit_Flow_Control */\r
-\r
- uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for\r
- comparison and filtering.\r
- This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */\r
-\r
- uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */\r
-\r
-} ETH_MACInitTypeDef;\r
-\r
-\r
-/**\r
- * @brief ETH DMA Configuration Structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.\r
- This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */\r
-\r
- uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.\r
- This parameter can be a value of @ref ETH_Receive_Store_Forward */\r
-\r
- uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.\r
- This parameter can be a value of @ref ETH_Flush_Received_Frame */\r
-\r
- uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.\r
- This parameter can be a value of @ref ETH_Transmit_Store_Forward */\r
-\r
- uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.\r
- This parameter can be a value of @ref ETH_Transmit_Threshold_Control */\r
-\r
- uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.\r
- This parameter can be a value of @ref ETH_Forward_Error_Frames */\r
-\r
- uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error\r
- and length less than 64 bytes) including pad-bytes and CRC)\r
- This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */\r
-\r
- uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.\r
- This parameter can be a value of @ref ETH_Receive_Threshold_Control */\r
-\r
- uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second\r
- frame of Transmit data even before obtaining the status for the first frame.\r
- This parameter can be a value of @ref ETH_Second_Frame_Operate */\r
-\r
- uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.\r
- This parameter can be a value of @ref ETH_Address_Aligned_Beats */\r
-\r
- uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.\r
- This parameter can be a value of @ref ETH_Fixed_Burst */\r
-\r
- uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.\r
- This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */\r
-\r
- uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.\r
- This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */\r
-\r
- uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.\r
- This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */\r
-\r
- uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)\r
- This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r
-\r
- uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.\r
- This parameter can be a value of @ref ETH_DMA_Arbitration */\r
-} ETH_DMAInitTypeDef;\r
-\r
-\r
-/**\r
- * @brief ETH DMA Descriptors data structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t Status; /*!< Status */\r
-\r
- uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */\r
-\r
- uint32_t Buffer1Addr; /*!< Buffer1 address pointer */\r
-\r
- uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */\r
-\r
- /*!< Enhanced ETHERNET DMA PTP Descriptors */\r
- uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */\r
-\r
- uint32_t Reserved1; /*!< Reserved */\r
-\r
- uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */\r
-\r
- uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */\r
-\r
-} ETH_DMADescTypeDef;\r
-\r
-\r
-/**\r
- * @brief Received Frame Informations structure definition\r
- */\r
-typedef struct\r
-{\r
- ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */\r
-\r
- ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */\r
-\r
- uint32_t SegCount; /*!< Segment count */\r
-\r
- uint32_t length; /*!< Frame length */\r
-\r
- uint32_t buffer; /*!< Frame buffer */\r
-\r
-} ETH_DMARxFrameInfos;\r
-\r
-\r
-/**\r
- * @brief ETH Handle Structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- ETH_TypeDef *Instance; /*!< Register base address */\r
-\r
- ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */\r
-\r
- uint32_t LinkStatus; /*!< Ethernet link status */\r
-\r
- ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */\r
-\r
- ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */\r
-\r
- ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */\r
-\r
- __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */\r
-\r
- HAL_LockTypeDef Lock; /*!< ETH Lock */\r
-\r
-} ETH_HandleTypeDef;\r
-\r
- /**\r
- * @}\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup ETH_Exported_Constants ETH Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup ETH_Buffers_setting ETH Buffers setting\r
- * @{\r
- */\r
-#define ETH_MAX_PACKET_SIZE (1536u) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */\r
-#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r
-#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */\r
-#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */\r
-#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */\r
-#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */\r
-#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */\r
-#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */\r
-\r
- /* Ethernet driver receive buffers are organized in a chained linked-list, when\r
- an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO\r
- to the driver receive buffers memory.\r
-\r
- Depending on the size of the received ethernet packet and the size of\r
- each ethernet driver receive buffer, the received packet can take one or more\r
- ethernet driver receive buffer.\r
-\r
- In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE\r
- and the total count of the driver receive buffers ETH_RXBUFNB.\r
-\r
- The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as\r
- example, they can be reconfigured in the application layer to fit the application\r
- needs */\r
-\r
-/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet\r
- packet */\r
-#ifndef ETH_RX_BUF_SIZE\r
- #error please define ETH_RX_BUF_SIZE\r
- #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE\r
-#endif\r
-\r
-/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/\r
-#ifndef ETH_RXBUFNB\r
- #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */\r
-#endif\r
-\r
-\r
- /* Ethernet driver transmit buffers are organized in a chained linked-list, when\r
- an ethernet packet is transmitted, Tx-DMA will transfer the packet from the\r
- driver transmit buffers memory to the TxFIFO.\r
-\r
- Depending on the size of the Ethernet packet to be transmitted and the size of\r
- each ethernet driver transmit buffer, the packet to be transmitted can take\r
- one or more ethernet driver transmit buffer.\r
-\r
- In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE\r
- and the total count of the driver transmit buffers ETH_TXBUFNB.\r
-\r
- The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as\r
- example, they can be reconfigured in the application layer to fit the application\r
- needs */\r
-\r
-/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet\r
- packet */\r
-#ifndef ETH_TX_BUF_SIZE\r
- #error please define ETH_TX_BUF_SIZE\r
- #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE\r
-#endif\r
-\r
-/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/\r
-#ifndef ETH_TXBUFNB\r
- #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */\r
-#endif\r
-\r
- /**\r
- * @}\r
- */\r
-\r
-/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor\r
- * @{\r
- */\r
-\r
-/*\r
- DMA Tx Descriptor\r
- -----------------------------------------------------------------------------------------------\r
- TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |\r
- -----------------------------------------------------------------------------------------------\r
- TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r
- -----------------------------------------------------------------------------------------------\r
- TDES2 | Buffer1 Address [31:0] |\r
- -----------------------------------------------------------------------------------------------\r
- TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
- -----------------------------------------------------------------------------------------------\r
-*/\r
-\r
-/**\r
- * @brief Bit definition of TDES0 register: DMA Tx descriptor status register\r
- */\r
-#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */\r
-#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */\r
-#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */\r
-#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */\r
-#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */\r
-#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */\r
-#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */\r
-#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */\r
-#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */\r
-#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */\r
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */\r
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */\r
-#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */\r
-#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */\r
-#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */\r
-#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */\r
-#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r
-#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */\r
-#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r
-#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */\r
-#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */\r
-#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */\r
-#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */\r
-#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */\r
-#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */\r
-#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */\r
-#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */\r
-#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */\r
-#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */\r
-\r
-/**\r
- * @brief Bit definition of TDES1 register\r
- */\r
-#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */\r
-#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */\r
-\r
-/**\r
- * @brief Bit definition of TDES2 register\r
- */\r
-#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */\r
-\r
-/**\r
- * @brief Bit definition of TDES3 register\r
- */\r
-#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */\r
-\r
- /*---------------------------------------------------------------------------------------------\r
- TDES6 | Transmit Time Stamp Low [31:0] |\r
- -----------------------------------------------------------------------------------------------\r
- TDES7 | Transmit Time Stamp High [31:0] |\r
- ----------------------------------------------------------------------------------------------*/\r
-\r
-/* Bit definition of TDES6 register */\r
- #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */\r
-\r
-/* Bit definition of TDES7 register */\r
- #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */\r
-\r
-/**\r
- * @}\r
- */\r
-/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor\r
- * @{\r
- */\r
-\r