--- /dev/null
+/**\r
+ *\r
+ * \file\r
+ *\r
+ * \brief KS8851SNL registers definitions.\r
+ *\r
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef KSZ8851SNL_REG_H_INCLUDED\r
+#define KSZ8851SNL_REG_H_INCLUDED\r
+\r
+#define REG_ADDR_MASK (0x3F0) /* Register address mask */\r
+#define OPCODE_MASK (3 << 14)\r
+#define CMD_READ (0 << 14)\r
+#define CMD_WRITE (1 << 14)\r
+#define FIFO_READ (0x80)\r
+#define FIFO_WRITE (0xC0)\r
+\r
+/*\r
+ * MAC Registers\r
+ * (Offset 0x00 - 0x25)\r
+ */\r
+#define REG_BUS_ERROR_STATUS (0x06) /* BESR */\r
+#define BUS_ERROR_IBEC (0x8000)\r
+#define BUS_ERROR_IBECV_MASK (0x7800) /* Default IPSec clock at 166Mhz */\r
+\r
+#define REG_CHIP_CFG_STATUS (0x08) /* CCFG */\r
+#define LITTLE_ENDIAN_BUS_MODE (0x0400) /* Bus in little endian mode */\r
+#define EEPROM_PRESENCE (0x0200) /* External EEPROM is used */\r
+#define SPI_BUS_MODE (0x0100) /* In SPI bus mode */\r
+#define DATA_BUS_8BIT (0x0080) /* In 8-bit bus mode operation */\r
+#define DATA_BUS_16BIT (0x0040) /* In 16-bit bus mode operation */\r
+#define DATA_BUS_32BIT (0x0020) /* In 32-bit bus mode operation */\r
+#define MULTIPLEX_MODE (0x0010) /* Data and address bus are shared */\r
+#define CHIP_PACKAGE_128PIN (0x0008) /* 128-pin package */\r
+#define CHIP_PACKAGE_80PIN (0x0004) /* 80-pin package */\r
+#define CHIP_PACKAGE_48PIN (0x0002) /* 48-pin package */\r
+#define CHIP_PACKAGE_32PIN (0x0001) /* 32-pin package for SPI host interface only */\r
+\r
+#define REG_MAC_ADDR_0 (0x10) /* MARL */\r
+#define REG_MAC_ADDR_1 (0x11) /* MARL */\r
+#define REG_MAC_ADDR_2 (0x12) /* MARM */\r
+#define REG_MAC_ADDR_3 (0x13) /* MARM */\r
+#define REG_MAC_ADDR_4 (0x14) /* MARH */\r
+#define REG_MAC_ADDR_5 (0x15) /* MARH */\r
+\r
+#define REG_BUS_CLOCK_CTRL (0x20) /* OBCR */\r
+#define BUS_CLOCK_166 (0x0004) /* 166 MHz on-chip bus clock (defaul is 125MHz) */\r
+#define BUS_CLOCK_DIVIDEDBY_5 (0x0003) /* Bus clock devided by 5 */\r
+#define BUS_CLOCK_DIVIDEDBY_3 (0x0002) /* Bus clock devided by 3 */\r
+#define BUS_CLOCK_DIVIDEDBY_2 (0x0001) /* Bus clock devided by 2 */\r
+#define BUS_CLOCK_DIVIDEDBY_1 (0x0000) /* Bus clock devided by 1 */\r
+#define BUS_CLOCK_DIVIDED_MASK (0x0003) /* Bus clock devider mask */\r
+\r
+#define BUS_SPEED_166_MHZ (0x0004) /* Set bus speed to 166 MHz */\r
+#define BUS_SPEED_125_MHZ (0x0000) /* Set bus speed to 125 MHz */\r
+#define BUS_SPEED_83_MHZ (0x0005) /* Set bus speed to 83 MHz (166/2)*/\r
+#define BUS_SPEED_62_5_MHZ (0x0001) /* Set bus speed to 62.5 MHz (125/2) */\r
+#define BUS_SPEED_53_3_MHZ (0x0006) /* Set bus speed to 53.3 MHz (166/3) */\r
+#define BUS_SPEED_41_7_MHZ (0x0002) /* Set bus speed to 41.67 MHz (125/3) */\r
+#define BUS_SPEED_33_2_MHZ (0x0007) /* Set bus speed to 33.2 MHz (166/5) */\r
+#define BUS_SPEED_25_MHZ (0x0003) /* Set bus speed to 25 MHz (125/5) */\r
+\r
+#define REG_EEPROM_CTRL (0x22) /* EEPCR */\r
+#define EEPROM_ACCESS_ENABLE (0x0010) /* Enable software to access EEPROM through bit 3 to bit 0 */\r
+#define EEPROM_DATA_IN (0x0008) /* Data receive from EEPROM (EEDI pin) */\r
+#define EEPROM_DATA_OUT (0x0004) /* Data transmit to EEPROM (EEDO pin) */\r
+#define EEPROM_SERIAL_CLOCK (0x0002) /* Serial clock (EESK pin) */\r
+#define EEPROM_CHIP_SELECT (0x0001) /* EEPROM chip select (EECS pin) */\r
+\r
+#define REG_MEM_BIST_INFO (0x24) /* MBIR */\r
+#define TX_MEM_TEST_FINISHED (0x1000) /* TX memeory BIST test finish */\r
+#define TX_MEM_TEST_FAILED (0x0800) /* TX memory BIST test fail */\r
+#define TX_MEM_TEST_FAILED_COUNT (0x0700) /* TX memory BIST test fail count */\r
+#define RX_MEM_TEST_FINISHED (0x0010) /* RX memory BIST test finish */\r
+#define RX_MEM_TEST_FAILED (0x0008) /* RX memory BIST test fail */\r
+#define RX_MEM_TEST_FAILED_COUNT (0x0003) /* RX memory BIST test fail count */\r
+\r
+#define REG_RESET_CTRL (0x26) /* GRR */\r
+#define QMU_SOFTWARE_RESET (0x0002) /* QMU soft reset (clear TxQ, RxQ) */\r
+#define GLOBAL_SOFTWARE_RESET (0x0001) /* Global soft reset (PHY, MAC, QMU) */\r
+\r
+/*\r
+ * Wake On Lan Control Registers\r
+ * (Offset 0x2A - 0x6B)\r
+ */\r
+#define REG_WOL_CTRL (0x2A) /* WFCR */\r
+#define WOL_MAGIC_ENABLE (0x0080) /* Enable the magic packet pattern detection */\r
+#define WOL_FRAME3_ENABLE (0x0008) /* Enable the wake up frame 3 pattern detection */\r
+#define WOL_FRAME2_ENABLE (0x0004) /* Enable the wake up frame 2 pattern detection */\r
+#define WOL_FRAME1_ENABLE (0x0002) /* Enable the wake up frame 1 pattern detection */\r
+#define WOL_FRAME0_ENABLE (0x0001) /* Enable the wake up frame 0 pattern detection */\r
+\r
+#define REG_WOL_FRAME0_CRC0 (0x30) /* WF0CRC0 */\r
+#define REG_WOL_FRAME0_CRC1 (0x32) /* WF0CRC1 */\r
+#define REG_WOL_FRAME0_BYTE_MASK0 (0x34) /* WF0BM0 */\r
+#define REG_WOL_FRAME0_BYTE_MASK1 (0x36) /* WF0BM1 */\r
+#define REG_WOL_FRAME0_BYTE_MASK2 (0x38) /* WF0BM2 */\r
+#define REG_WOL_FRAME0_BYTE_MASK3 (0x3A) /* WF0BM3 */\r
+\r
+#define REG_WOL_FRAME1_CRC0 (0x40) /* WF1CRC0 */\r
+#define REG_WOL_FRAME1_CRC1 (0x42) /* WF1CRC1 */\r
+#define REG_WOL_FRAME1_BYTE_MASK0 (0x44) /* WF1BM0 */\r
+#define REG_WOL_FRAME1_BYTE_MASK1 (0x46) /* WF1BM1 */\r
+#define REG_WOL_FRAME1_BYTE_MASK2 (0x48) /* WF1BM2 */\r
+#define REG_WOL_FRAME1_BYTE_MASK3 (0x4A) /* WF1BM3 */\r
+\r
+#define REG_WOL_FRAME2_CRC0 (0x50) /* WF2CRC0 */\r
+#define REG_WOL_FRAME2_CRC1 (0x52) /* WF2CRC1 */\r
+#define REG_WOL_FRAME2_BYTE_MASK0 (0x54) /* WF2BM0 */\r
+#define REG_WOL_FRAME2_BYTE_MASK1 (0x56) /* WF2BM1 */\r
+#define REG_WOL_FRAME2_BYTE_MASK2 (0x58) /* WF2BM2 */\r
+#define REG_WOL_FRAME2_BYTE_MASK3 (0x5A) /* WF2BM3 */\r
+\r
+#define REG_WOL_FRAME3_CRC0 (0x60) /* WF3CRC0 */\r
+#define REG_WOL_FRAME3_CRC1 (0x62) /* WF3CRC1 */\r
+#define REG_WOL_FRAME3_BYTE_MASK0 (0x64) /* WF3BM0 */\r
+#define REG_WOL_FRAME3_BYTE_MASK1 (0x66) /* WF3BM1 */\r
+#define REG_WOL_FRAME3_BYTE_MASK2 (0x68) /* WF3BM2 */\r
+#define REG_WOL_FRAME3_BYTE_MASK3 (0x6A) /* WF3BM3 */\r
+\r
+/*\r
+ * Transmit/Receive Control Registers\r
+ * (Offset 0x70 - 0x9F)\r
+ */\r
+\r
+/* Transmit Frame Header */\r
+#define REG_QDR_DUMMY (0x00) /* Dummy address to access QMU RxQ, TxQ */\r
+#define TX_CTRL_INTERRUPT_ON (0x8000) /* Transmit Interrupt on Completion */\r
+\r
+#define REG_TX_CTRL (0x70) /* TXCR */\r
+#define TX_CTRL_ICMP_CHECKSUM (0x0100) /* Enable ICMP frame checksum generation */\r
+#define TX_CTRL_UDP_CHECKSUM (0x0080) /* Enable UDP frame checksum generation */\r
+#define TX_CTRL_TCP_CHECKSUM (0x0040) /* Enable TCP frame checksum generation */\r
+#define TX_CTRL_IP_CHECKSUM (0x0020) /* Enable IP frame checksum generation */\r
+#define TX_CTRL_FLUSH_QUEUE (0x0010) /* Clear transmit queue, reset tx frame pointer */\r
+#define TX_CTRL_FLOW_ENABLE (0x0008) /* Enable transmit flow control */\r
+#define TX_CTRL_PAD_ENABLE (0x0004) /* Eanble adding a padding to a packet shorter than 64 bytes */\r
+#define TX_CTRL_CRC_ENABLE (0x0002) /* Enable adding a CRC to the end of transmit frame */\r
+#define TX_CTRL_ENABLE (0x0001) /* Enable tranmsit */\r
+\r
+#define REG_TX_STATUS (0x72) /* TXSR */\r
+#define TX_STAT_LATE_COL (0x2000) /* Tranmsit late collision occurs */\r
+#define TX_STAT_MAX_COL (0x1000) /* Tranmsit maximum collision is reached */\r
+#define TX_FRAME_ID_MASK (0x003F) /* Transmit frame ID mask */\r
+#define TX_STAT_ERRORS ( TX_STAT_MAX_COL | TX_STAT_LATE_COL )\r
+\r
+#define REG_RX_CTRL1 (0x74) /* RXCR1 */\r
+#define RX_CTRL_FLUSH_QUEUE (0x8000) /* Clear receive queue, reset rx frame pointer */\r
+#define RX_CTRL_UDP_CHECKSUM (0x4000) /* Enable UDP frame checksum verification */\r
+#define RX_CTRL_TCP_CHECKSUM (0x2000) /* Enable TCP frame checksum verification */\r
+#define RX_CTRL_IP_CHECKSUM (0x1000) /* Enable IP frame checksum verification */\r
+#define RX_CTRL_MAC_FILTER (0x0800) /* Receive with address that pass MAC address filtering */\r
+#define RX_CTRL_FLOW_ENABLE (0x0400) /* Enable receive flow control */\r
+#define RX_CTRL_BAD_PACKET (0x0200) /* Eanble receive CRC error frames */\r
+#define RX_CTRL_MULTICAST (0x0100) /* Receive multicast frames that pass the CRC hash filtering */\r
+#define RX_CTRL_BROADCAST (0x0080) /* Receive all the broadcast frames */\r
+#define RX_CTRL_ALL_MULTICAST (0x0040) /* Receive all the multicast frames (including broadcast frames) */\r
+#define RX_CTRL_UNICAST (0x0020) /* Receive unicast frames that match the device MAC address */\r
+#define RX_CTRL_PROMISCUOUS (0x0010) /* Receive all incoming frames, regardless of frame's DA */\r
+#define RX_CTRL_STRIP_CRC (0x0008) /* Enable strip CRC on the received frames */\r
+#define RX_CTRL_INVERSE_FILTER (0x0002) /* Receive with address check in inverse filtering mode */\r
+#define RX_CTRL_ENABLE (0x0001) /* Enable receive */\r
+\r
+/* Address filtering scheme mask */\r
+#define RX_CTRL_FILTER_MASK ( RX_CTRL_INVERSE_FILTER | RX_CTRL_PROMISCUOUS | RX_CTRL_MULTICAST | RX_CTRL_MAC_FILTER )\r
+\r
+#define REG_RX_CTRL2 (0x76) /* RXCR2 */\r
+#define RX_CTRL_IPV6_UDP_NOCHECKSUM (0x0010) /* No checksum generation and verification if IPv6 UDP is fragment */\r
+#define RX_CTRL_IPV6_UDP_CHECKSUM (0x0008) /* Receive pass IPv6 UDP frame with UDP checksum is zero */\r
+#define RX_CTRL_UDP_LITE_CHECKSUM (0x0004) /* Enable UDP Lite frame checksum generation and verification */\r
+#define RX_CTRL_ICMP_CHECKSUM (0x0002) /* Enable ICMP frame checksum verification */\r
+#define RX_CTRL_BLOCK_MAC (0x0001) /* Receive drop frame if the SA is same as device MAC address */\r
+#define RX_CTRL_BURST_LEN_MASK (0x00e0) /* SRDBL SPI Receive Data Burst Length */\r
+#define RX_CTRL_BURST_LEN_4 (0x0000)\r
+#define RX_CTRL_BURST_LEN_8 (0x0020)\r
+#define RX_CTRL_BURST_LEN_16 (0x0040)\r
+#define RX_CTRL_BURST_LEN_32 (0x0060)\r
+#define RX_CTRL_BURST_LEN_FRAME (0x0080)\r
+\r
+#define REG_TX_MEM_INFO (0x78) /* TXMIR */\r
+#define TX_MEM_AVAILABLE_MASK (0x1FFF) /* The amount of memory available in TXQ */\r
+\r
+#define REG_RX_FHR_STATUS (0x7C) /* RXFHSR */\r
+#define RX_VALID (0x8000) /* Frame in the receive packet memory is valid */\r
+#define RX_ICMP_ERROR (0x2000) /* ICMP checksum field doesn't match */\r
+#define RX_IP_ERROR (0x1000) /* IP checksum field doesn't match */\r
+#define RX_TCP_ERROR (0x0800) /* TCP checksum field doesn't match */\r
+#define RX_UDP_ERROR (0x0400) /* UDP checksum field doesn't match */\r
+#define RX_BROADCAST (0x0080) /* Received frame is a broadcast frame */\r
+#define RX_MULTICAST (0x0040) /* Received frame is a multicast frame */\r
+#define RX_UNICAST (0x0020) /* Received frame is a unicast frame */\r
+#define RX_PHY_ERROR (0x0010) /* Received frame has runt error */\r
+#define RX_FRAME_ETHER (0x0008) /* Received frame is an Ethernet-type frame */\r
+#define RX_TOO_LONG (0x0004) /* Received frame length exceeds max size 0f 2048 bytes */\r
+#define RX_RUNT_ERROR (0x0002) /* Received frame was demaged by a collision */\r
+#define RX_BAD_CRC (0x0001) /* Received frame has a CRC error */\r
+#define RX_ERRORS ( RX_BAD_CRC | RX_TOO_LONG | RX_RUNT_ERROR | RX_PHY_ERROR | \\r
+ RX_ICMP_ERROR | RX_IP_ERROR | RX_TCP_ERROR | RX_UDP_ERROR )\r
+\r
+#define REG_RX_FHR_BYTE_CNT (0x7E) /* RXFHBCR */\r
+#define RX_BYTE_CNT_MASK (0x0FFF) /* Received frame byte size mask */\r
+\r
+#define REG_TXQ_CMD (0x80) /* TXQCR */\r
+#define TXQ_AUTO_ENQUEUE (0x0004) /* Enable enqueue tx frames from tx buffer automatically */\r
+#define TXQ_MEM_AVAILABLE_INT (0x0002) /* Enable generate interrupt when tx memory is available */\r
+#define TXQ_ENQUEUE (0x0001) /* Enable enqueue tx frames one frame at a time */\r
+\r
+#define REG_RXQ_CMD (0x82) /* RXQCR */\r
+#define RXQ_STAT_TIME_INT (0x1000) /* RX interrupt is occured by timer duration */\r
+#define RXQ_STAT_BYTE_CNT_INT (0x0800) /* RX interrupt is occured by byte count threshold */\r
+#define RXQ_STAT_FRAME_CNT_INT (0x0400) /* RX interrupt is occured by frame count threshold */\r
+#define RXQ_TWOBYTE_OFFSET (0x0200) /* Enable adding 2-byte before frame header for IP aligned with DWORD */\r
+#define RXQ_TIME_INT (0x0080) /* Enable RX interrupt by timer duration */\r
+#define RXQ_BYTE_CNT_INT (0x0040) /* Enable RX interrupt by byte count threshold */\r
+#define RXQ_FRAME_CNT_INT (0x0020) /* Enable RX interrupt by frame count threshold */\r
+#define RXQ_AUTO_DEQUEUE (0x0010) /* Enable release rx frames from rx buffer automatically */\r
+#define RXQ_START (0x0008) /* Start QMU transfer operation */\r
+#define RXQ_CMD_FREE_PACKET (0x0001) /* Manual dequeue (release the current frame from RxQ) */\r
+\r
+#define RXQ_CMD_CNTL (RXQ_FRAME_CNT_INT|RXQ_AUTO_DEQUEUE)\r
+\r
+#define REG_TX_ADDR_PTR (0x84) /* TXFDPR */\r
+#define REG_RX_ADDR_PTR (0x86) /* RXFDPR */\r
+#define ADDR_PTR_AUTO_INC (0x4000) /* Enable Frame data pointer increments automatically */\r
+#define ADDR_PTR_MASK (0x03ff) /* Address pointer mask */\r
+\r
+#define REG_RX_TIME_THRES (0x8C) /* RXDTTR */\r
+#define RX_TIME_THRESHOLD_MASK (0xFFFF) /* Set receive timer duration threshold */\r
+\r
+#define REG_RX_BYTE_CNT_THRES (0x8E) /* RXDBCTR */\r
+#define RX_BYTE_THRESHOLD_MASK (0xFFFF) /* Set receive byte count threshold */\r
+\r
+#define REG_INT_MASK (0x90) /* IER */\r
+#define INT_PHY (0x8000) /* Enable link change interrupt */\r
+#define INT_TX (0x4000) /* Enable transmit done interrupt */\r
+#define INT_RX (0x2000) /* Enable receive interrupt */\r
+#define INT_RX_OVERRUN (0x0800) /* Enable receive overrun interrupt */\r
+#define INT_TX_STOPPED (0x0200) /* Enable transmit process stopped interrupt */\r
+#define INT_RX_STOPPED (0x0100) /* Enable receive process stopped interrupt */\r
+#define INT_TX_SPACE (0x0040) /* Enable transmit space available interrupt */\r
+#define INT_RX_WOL_FRAME (0x0020) /* Enable WOL on receive wake-up frame detect interrupt */\r
+#define INT_RX_WOL_MAGIC (0x0010) /* Enable WOL on receive magic packet detect interrupt */\r
+#define INT_RX_WOL_LINKUP (0x0008) /* Enable WOL on link up detect interrupt */\r
+#define INT_RX_WOL_ENERGY (0x0004) /* Enable WOL on energy detect interrupt */\r
+#define INT_RX_SPI_ERROR (0x0002) /* Enable receive SPI bus error interrupt */\r
+#define INT_RX_WOL_DELAY_ENERGY (0x0001) /* Enable WOL on delay energy detect interrupt */\r
+#define INT_MASK ( INT_RX | INT_TX | INT_PHY )\r
+\r
+#define REG_INT_STATUS (0x92) /* ISR */\r
+\r
+#define REG_RX_FRAME_CNT_THRES (0x9C) /* RXFCTFC */\r
+#define RX_FRAME_CNT_MASK (0xFF00) /* Received frame count mask */\r
+#define RX_FRAME_THRESHOLD_MASK (0x00FF) /* Set receive frame count threshold mask */\r
+\r
+#define REG_TX_TOTAL_FRAME_SIZE (0x9E) /* TXNTFSR */\r
+#define TX_TOTAL_FRAME_SIZE_MASK (0xFFFF) /* Set next total tx frame size mask */\r
+\r
+/*\r
+ * MAC Address Hash Table Control Registers\r
+ * (Offset 0xA0 - 0xA7)\r
+ */\r
+#define REG_MAC_HASH_0 (0xA0) /* MAHTR0 */\r
+#define REG_MAC_HASH_1 (0xA1)\r
+\r
+#define REG_MAC_HASH_2 (0xA2) /* MAHTR1 */\r
+#define REG_MAC_HASH_3 (0xA3)\r
+\r
+#define REG_MAC_HASH_4 (0xA4) /* MAHTR2 */\r
+#define REG_MAC_HASH_5 (0xA5)\r
+\r
+#define REG_MAC_HASH_6 (0xA6) /* MAHTR3 */\r
+#define REG_MAC_HASH_7 (0xA7)\r
+\r
+/*\r
+ * QMU Receive Queue Watermark Control Registers\r
+ * (Offset 0xB0 - 0xB5)\r
+ */\r
+#define REG_RX_LOW_WATERMARK (0xB0) /* FCLWR */\r
+#define RX_LOW_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ low watermark mask */\r
+\r
+#define REG_RX_HIGH_WATERMARK (0xB2) /* FCHWR */\r
+#define RX_HIGH_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ high watermark mask */\r
+\r
+#define REG_RX_OVERRUN_WATERMARK (0xB4) /* FCOWR */\r
+#define RX_OVERRUN_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ overrun watermark mask */\r
+\r
+/*\r
+ * Global Control Registers\r
+ * (Offset 0xC0 - 0xD3)\r
+ */\r
+#define REG_CHIP_ID (0xC0) /* CIDER */\r
+#define CHIP_ID_MASK (0xFFF0) /* Family ID and chip ID mask */\r
+#define REVISION_MASK (0x000E) /* Chip revision mask */\r
+#define CHIP_ID_SHIFT (4)\r
+#define REVISION_SHIFT (1)\r
+#define CHIP_ID_8851_16 (0x8870) /* KS8851-16/32MQL chip ID */\r
+\r
+#define REG_LED_CTRL (0xC6) /* CGCR */\r
+#define LED_CTRL_SEL1 (0x8000) /* Select LED3/LED2/LED1/LED0 indication */\r
+#define LED_CTRL_SEL0 (0x0200) /* Select LED3/LED2/LED1/LED0 indication */\r
+\r
+#define REG_IND_IACR (0xC8) /* IACR */\r
+#define TABLE_READ (0x1000) /* Indirect read */\r
+#define TABLE_MIB (0x0C00) /* Select MIB counter table */\r
+#define TABLE_ENTRY_MASK (0x001F) /* Set table entry to access */\r
+\r
+#define REG_IND_DATA_LOW (0xD0) /* IADLR */\r
+#define REG_IND_DATA_HIGH (0xD2) /* IADHR */\r
+\r
+/*\r
+ * Power Management Control Registers\r
+ * (Offset 0xD4 - 0xD7)\r
+ */\r
+#define REG_POWER_CNTL (0xD4) /* PMECR */\r
+#define PME_DELAY_ENABLE (0x4000) /* Enable the PME output pin assertion delay */\r
+#define PME_ACTIVE_HIGHT (0x1000) /* PME output pin is active high */\r
+#define PME_FROM_WKFRAME (0x0800) /* PME asserted when wake-up frame is detected */\r
+#define PME_FROM_MAGIC (0x0400) /* PME asserted when magic packet is detected */\r
+#define PME_FROM_LINKUP (0x0200) /* PME asserted when link up is detected */\r
+#define PME_FROM_ENERGY (0x0100) /* PME asserted when energy is detected */\r
+#define PME_EVENT_MASK (0x0F00) /* PME asserted event mask */\r
+#define WAKEUP_AUTO_ENABLE (0x0080) /* Enable auto wake-up in energy mode */\r
+#define WAKEUP_NORMAL_AUTO_ENABLE (0x0040) /* Enable auto goto normal mode from energy detecion mode */\r
+#define WAKEUP_FROM_WKFRAME (0x0020) /* Wake-up from wake-up frame event detected */\r
+#define WAKEUP_FROM_MAGIC (0x0010) /* Wake-up from magic packet event detected */\r
+#define WAKEUP_FROM_LINKUP (0x0008) /* Wake-up from link up event detected */\r
+#define WAKEUP_FROM_ENERGY (0x0004) /* Wake-up from energy event detected */\r
+#define WAKEUP_EVENT_MASK (0x003C) /* Wake-up event mask */\r
+#define POWER_STATE_D1 (0x0003) /* Power saving mode */\r
+#define POWER_STATE_D3 (0x0002) /* Power down mode */\r
+#define POWER_STATE_D2 (0x0001) /* Power detection mode */\r
+#define POWER_STATE_D0 (0x0000) /* Normal operation mode (default) */\r
+#define POWER_STATE_MASK (0x0003) /* Power management mode mask */\r
+\r
+#define REG_WAKEUP_TIME (0xD6) /* GSWUTR */\r
+#define WAKEUP_TIME (0xFF00) /* Min time (sec) wake-uo after detected energy */\r
+#define GOSLEEP_TIME (0x00FF) /* Min time (sec) before goto sleep when in energy mode */\r
+\r
+/*\r
+ * PHY Control Registers\r
+ * (Offset 0xD8 - 0xF9)\r
+ */\r
+#define REG_PHY_RESET (0xD8) /* PHYRR */\r
+#define PHY_RESET (0x0001) /* Reset PHY */\r
+\r
+#define REG_PHY_CNTL (0xE4) /* P1MBCR */\r
+#define PHY_SPEED_100MBIT (0x2000) /* Force PHY 100Mbps */\r
+#define PHY_AUTO_NEG_ENABLE (0x1000) /* Enable PHY auto-negotiation */\r
+#define PHY_POWER_DOWN (0x0800) /* Set PHY power-down */\r
+#define PHY_AUTO_NEG_RESTART (0x0200) /* Restart PHY auto-negotiation */\r
+#define PHY_FULL_DUPLEX (0x0100) /* Force PHY in full duplex mode */\r
+#define PHY_HP_MDIX (0x0020) /* Set PHY in HP auto MDI-X mode */\r
+#define PHY_FORCE_MDIX (0x0010) /* Force MDI-X */\r
+#define PHY_AUTO_MDIX_DISABLE (0x0008) /* Disable auto MDI-X */\r
+#define PHY_TRANSMIT_DISABLE (0x0002) /* Disable PHY transmit */\r
+#define PHY_LED_DISABLE (0x0001) /* Disable PHY LED */\r
+\r
+#define REG_PHY_STATUS (0xE6) /* P1MBSR */\r
+#define PHY_100BT4_CAPABLE (0x8000) /* 100 BASE-T4 capable */\r
+#define PHY_100BTX_FD_CAPABLE (0x4000) /* 100BASE-TX full duplex capable */\r
+#define PHY_100BTX_CAPABLE (0x2000) /* 100BASE-TX half duplex capable */\r
+#define PHY_10BT_FD_CAPABLE (0x1000) /* 10BASE-TX full duplex capable */\r
+#define PHY_10BT_CAPABLE (0x0800) /* 10BASE-TX half duplex capable */\r
+#define PHY_AUTO_NEG_ACKNOWLEDGE (0x0020) /* Auto-negotiation complete */\r
+#define PHY_AUTO_NEG_CAPABLE (0x0008) /* Auto-negotiation capable */\r
+#define PHY_LINK_UP (0x0004) /* PHY link is up */\r
+#define PHY_EXTENDED_CAPABILITY (0x0001) /* PHY extended register capable */\r
+\r
+#define REG_PHY_ID_LOW (0xE8) /* PHY1ILR */\r
+#define REG_PHY_ID_HIGH (0xEA) /* PHY1IHR */\r
+\r
+#define REG_PHY_AUTO_NEGOTIATION (0xEC) /* P1ANAR */\r
+#define PHY_AUTO_NEG_SYM_PAUSE (0x0400) /* Advertise pause capability */\r
+#define PHY_AUTO_NEG_100BTX_FD (0x0100) /* Advertise 100 full-duplex capability */\r
+#define PHY_AUTO_NEG_100BTX (0x0080) /* Advertise 100 half-duplex capability */\r
+#define PHY_AUTO_NEG_10BT_FD (0x0040) /* Advertise 10 full-duplex capability */\r
+#define PHY_AUTO_NEG_10BT (0x0020) /* Advertise 10 half-duplex capability */\r
+#define PHY_AUTO_NEG_SELECTOR (0x001F) /* Selector field mask */\r
+#define PHY_AUTO_NEG_802_3 (0x0001) /* 802.3 */\r
+\r
+#define REG_PHY_REMOTE_CAPABILITY (0xEE) /* P1ANLPR */\r
+#define PHY_REMOTE_SYM_PAUSE (0x0400) /* Link partner pause capability */\r
+#define PHY_REMOTE_100BTX_FD (0x0100) /* Link partner 100 full-duplex capability */\r
+#define PHY_REMOTE_100BTX (0x0080) /* Link partner 100 half-duplex capability */\r
+#define PHY_REMOTE_10BT_FD (0x0040) /* Link partner 10 full-duplex capability */\r
+#define PHY_REMOTE_10BT (0x0020) /* Link partner 10 half-duplex capability */\r
+\r
+#define REG_PORT_LINK_MD (0xF4) /* P1SCLMD */\r
+#define PORT_CABLE_10M_SHORT (0x8000) /* Cable length is less than 10m short */\r
+#define PORT_CABLE_STAT_FAILED (0x6000) /* Cable diagnostic test fail */\r
+#define PORT_CABLE_STAT_SHORT (0x4000) /* Short condition detected in the cable */\r
+#define PORT_CABLE_STAT_OPEN (0x2000) /* Open condition detected in the cable */\r
+#define PORT_CABLE_STAT_NORMAL (0x0000) /* Normal condition */\r
+#define PORT_CABLE_DIAG_RESULT (0x6000) /* Cable diagnostic test result mask */\r
+#define PORT_START_CABLE_DIAG (0x1000) /* Enable cable diagnostic test */\r
+#define PORT_FORCE_LINK (0x0800) /* Enable force link pass */\r
+#define PORT_POWER_SAVING (0x0400) /* Disable power saving */\r
+#define PORT_REMOTE_LOOPBACK (0x0200) /* Enable remote loopback at PHY */\r
+#define PORT_CABLE_FAULT_COUNTER (0x01FF) /* Cable length distance to the fault */\r
+\r
+#define REG_PORT_CTRL (0xF6) /* P1CR */\r
+#define PORT_LED_OFF (0x8000) /* Turn off all the port LEDs (LED3/LED2/LED1/LED0) */\r
+#define PORT_TX_DISABLE (0x4000) /* Disable port transmit */\r
+#define PORT_AUTO_NEG_RESTART (0x2000) /* Restart auto-negotiation */\r
+#define PORT_POWER_DOWN (0x0800) /* Set port power-down */\r
+#define PORT_AUTO_MDIX_DISABLE (0x0400) /* Disable auto MDI-X */\r
+#define PORT_FORCE_MDIX (0x0200) /* Force MDI-X */\r
+#define PORT_AUTO_NEG_ENABLE (0x0080) /* Enable auto-negotiation */\r
+#define PORT_FORCE_100_MBIT (0x0040) /* Force PHY 100Mbps */\r
+#define PORT_FORCE_FULL_DUPLEX (0x0020) /* Force PHY in full duplex mode */\r
+#define PORT_AUTO_NEG_SYM_PAUSE (0x0010) /* Advertise pause capability */\r
+#define PORT_AUTO_NEG_100BTX_FD (0x0008) /* Advertise 100 full-duplex capability */\r
+#define PORT_AUTO_NEG_100BTX (0x0004) /* Advertise 100 half-duplex capability */\r
+#define PORT_AUTO_NEG_10BT_FD (0x0002) /* Advertise 10 full-duplex capability */\r
+#define PORT_AUTO_NEG_10BT (0x0001) /* Advertise 10 half-duplex capability */\r
+\r
+#define REG_PORT_STATUS (0xF8) /* P1SR */\r
+#define PORT_HP_MDIX (0x8000) /* Set PHY in HP auto MDI-X mode */\r
+#define PORT_REVERSED_POLARITY (0x2000) /* Polarity is reversed */\r
+#define PORT_RX_FLOW_CTRL (0x1000) /* Reeive flow control feature is active */\r
+#define PORT_TX_FLOW_CTRL (0x0800) /* Transmit flow control feature is active */\r
+#define PORT_STAT_SPEED_100MBIT (0x0400) /* Link is 100Mbps */\r
+#define PORT_STAT_FULL_DUPLEX (0x0200) /* Link is full duplex mode */\r
+#define PORT_MDIX_STATUS (0x0080) /* Is MDI */\r
+#define PORT_AUTO_NEG_COMPLETE (0x0040) /* Auto-negotiation complete */\r
+#define PORT_STATUS_LINK_GOOD (0x0020) /* PHY link is up */\r
+#define PORT_REMOTE_SYM_PAUSE (0x0010) /* Link partner pause capability */\r
+#define PORT_REMOTE_100BTX_FD (0x0008) /* Link partner 100 full-duplex capability */\r
+#define PORT_REMOTE_100BTX (0x0004) /* Link partner 100 half-duplex capability */\r
+#define PORT_REMOTE_10BT_FD (0x0002) /* Link partner 10 full-duplex capability */\r
+#define PORT_REMOTE_10BT (0x0001) /* Link partner 10 half-duplex capability */\r
+\r
+#endif /* KSZ8851SNL_REG_H_INCLUDED */\r
projects / freertos / blobdiff