Update CEC1302 peripheral library version.

[freertos] / FreeRTOS / Demo / CORTEX_M4F_CEC1302_Keil_GCC / Keil_Specific / startup_CEC1302.s

diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s
index 17984f30e420527e5c50162e356656f0cd8b63ce..aa1fe659c2e4a090e6b1b074101cbc04dd4175e2 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s
@@ -19,10 +19,10 @@
 ;* OF THESE TERMS.\r
 ;******************************************************************************\r
 ; */\r
-;/** @file startup_MEC1322.s\r
-; *MEC1322 API Test: startup and vector table\r
+;/** @file startup_CEC1302.s\r
+; *CEC1302 API Test: startup and vector table\r
 ; */\r
-;/** @defgroup startup_MEC1322\r
+;/** @defgroup startup_CEC1302\r
 ; *  @{\r
 ; */\r
 \r
@@ -55,7 +55,7 @@ __initial_sp
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
 ; </h>\r
 \r
-Heap_Size       EQU     0x00000000 \r
+Heap_Size       EQU     0x00000000\r
 \r
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
 __heap_base\r
@@ -88,7 +88,7 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     PendSV_Handler            ; PendSV Handler\r
                 DCD     SysTick_Handler           ; SysTick Handler\r
 \r
-                ; MEC1322 External Interrupts\r
+                ; CEC1302 External Interrupts\r
                 DCD     NVIC_Handler_I2C0           ; 40h: 0, I2C/SMBus 0\r
                 DCD     NVIC_Handler_I2C1           ; 44h: 1, I2C/SMBus 1\r
                 DCD     NVIC_Handler_I2C2           ; 48h: 2, I2C/SMBus 2\r
@@ -152,7 +152,7 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     NVIC_Handler_GIRQ11         ; 130h: 60, GIRQ11\r
                 DCD     NVIC_Handler_GIRQ12        ; 134h: 61, GIRQ12\r
                 DCD     NVIC_Handler_GIRQ13         ; 138h: 62, GIRQ13\r
-                               DCD     NVIC_Handler_GIRQ14         ; 13Ch: 63, GIRQ14\r
+                DCD     NVIC_Handler_GIRQ14         ; 13Ch: 63, GIRQ14\r
                 DCD     NVIC_Handler_GIRQ15         ; 140h: 64, GIRQ15\r
                 DCD     NVIC_Handler_GIRQ16         ; 144h: 65, GIRQ16\r
                 DCD     NVIC_Handler_GIRQ17         ; 148h: 66, GIRQ17\r
@@ -178,9 +178,9 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     NVIC_Handler_PKE_ERR        ; 198h: 86, PKE Error\r
                 DCD     NVIC_Handler_PKE_END        ; 19Ch: 87, PKE End\r
                 DCD     NVIC_Handler_TRNG           ; 1A0h: 88, TRandom Num Gen\r
-                DCD     NVIC_Handler_AES            ; 1A4h: 89, AES \r
+                DCD     NVIC_Handler_AES            ; 1A4h: 89, AES\r
                 DCD     NVIC_Handler_HASH           ; 1A8h: 90, HASH\r
-                \r
+\r
 \r
                 AREA    ROMTABLE, CODE, READONLY\r
                 THUMB\r
@@ -198,16 +198,16 @@ Reset_Handler   PROC
                 EXPORT  Reset_Handler             [WEAK]\r
 \r
                 CPSID    i\r
-                \r
-                               ; support code is loaded from ROM loader\r
-                       LDR     SP, =__initial_sp\r
-                               ; configure CPU speed \r
+\r
+                ; support code is loaded from ROM loader\r
+                LDR     SP, =__initial_sp\r
+                ; configure CPU speed\r
                 LDR     R0, =system_set_ec_clock\r
                 BLX     R0\r
 \r
                 LDR     SP, =__initial_sp\r
 \r
-                               ; support FPU\r
+                ; support FPU\r
                 IF      {CPU} = "Cortex-M4.fp"\r
                 LDR     R0, =0xE000ED88           ; Enable CP10,CP11\r
                 LDR     R1,[R0]\r
@@ -275,7 +275,7 @@ SysTick_Handler PROC
 \r
 Default_Handler PROC\r
 \r
-        ; External MEC1322 NVIC Interrupt Inputs\r
+        ; External CEC1302 NVIC Interrupt Inputs\r
         EXPORT  NVIC_Handler_I2C0               [WEAK]\r
         EXPORT  NVIC_Handler_I2C1               [WEAK]\r
         EXPORT  NVIC_Handler_I2C2               [WEAK]\r
@@ -468,14 +468,14 @@ NVIC_Handler_HASH
 ; User Initial Stack & Heap\r
 \r
                 IF      :DEF:__MICROLIB\r
-                \r
+\r
                 EXPORT  __initial_sp\r
                 EXPORT  __heap_base\r
                 EXPORT  __heap_limit\r
                 EXPORT  __stack_bottom\r
 \r
                 ELSE\r
-                \r
+\r
                 IMPORT  __use_two_region_memory\r
                 EXPORT  __user_initial_stackheap\r
 __user_initial_stackheap\r