Update CEC1302 peripheral library version.

[freertos] / FreeRTOS / Demo / CORTEX_M4F_CEC1302_Keil_GCC / main_full / IntQueueTimer.c

diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c
index 6ff34e743afabfff1b656d8585e9c47766502831..50c9bff50ecf9b9221cd8cdee0f1d317b6a766c8 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c
@@ -117,8 +117,13 @@ timers must still be above the tick interrupt priority. */
 #define tmrMEDIUM_PRIORITY             ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 )\r
 #define tmrHIGHER_PRIORITY             ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )\r
 \r
-/* Hardware register locations. */\r
-#define tmrGIRQ23_ENABLE_SET                   ( * ( volatile uint32_t * ) 0x4000C130 )\r
+/* Hardware register locations and bit definitions to enable the btimer \r
+interrupts. */\r
+#define tmrGIRQ23_ENABLE_SET   ( * ( volatile uint32_t * ) 0x4000C130 )\r
+#define tmrGIRQ23_BIT_TIMER0   ( 1UL << 0UL )\r
+#define tmrGIRQ23_BIT_TIMER1   ( 1UL << 1UL )\r
+#define tmrGIRQ23_BIT_TIMER2   ( 1UL << 2UL )\r
+#define tmrGIRQ23_TIMER_BITS   ( tmrGIRQ23_BIT_TIMER0 | tmrGIRQ23_BIT_TIMER1 | tmrGIRQ23_BIT_TIMER2 )\r
 \r
 #define tmrRECORD_NESTING_DEPTH()                                              \\r
        ulNestingDepth++;                                                                       \\r
@@ -138,13 +143,12 @@ const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY;
 const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY;\r
 const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;\r
 \r
-       tmrGIRQ23_ENABLE_SET = 0x03;\r
+       tmrGIRQ23_ENABLE_SET = tmrGIRQ23_TIMER_BITS;\r
 \r
        /* Initialise the three timers as described at the top of this file, and\r
        enable their interrupts in the NVIC. */\r
        btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
        btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 );\r
-       enable_timer0_irq();\r
        NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY ); //0xc0 into 0xe000e431\r
        NVIC_ClearPendingIRQ( TIMER0_IRQn );\r
        NVIC_EnableIRQ( TIMER0_IRQn );\r
@@ -152,7 +156,6 @@ const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
 \r
        btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count );\r
        btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 );\r
-       enable_timer1_irq();\r
        NVIC_SetPriority( TIMER1_IRQn, tmrMEDIUM_PRIORITY ); //0xa0 into 0xe000e432\r
        NVIC_ClearPendingIRQ( TIMER1_IRQn );\r
        NVIC_EnableIRQ( TIMER1_IRQn );\r
@@ -160,7 +163,6 @@ const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
 \r
        btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count );\r
        btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 );\r
-       enable_timer2_irq();\r
        NVIC_SetPriority( TIMER2_IRQn, tmrHIGHER_PRIORITY );\r
        NVIC_ClearPendingIRQ( TIMER2_IRQn );\r
        NVIC_EnableIRQ( TIMER2_IRQn );\r