--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_iccarm.h\r
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file\r
+ * @version V5.0.7\r
+ * @date 19. June 2018\r
+ ******************************************************************************/\r
+\r
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2017-2018 IAR Systems\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License")\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+#ifndef __CMSIS_ICCARM_H__\r
+#define __CMSIS_ICCARM_H__\r
+\r
+#ifndef __ICCARM__\r
+ #error This file should only be compiled by ICCARM\r
+#endif\r
+\r
+#pragma system_include\r
+\r
+#define __IAR_FT _Pragma("inline=forced") __intrinsic\r
+\r
+#if (__VER__ >= 8000000)\r
+ #define __ICCARM_V8 1\r
+#else\r
+ #define __ICCARM_V8 0\r
+#endif\r
+\r
+#ifndef __ALIGNED\r
+ #if __ICCARM_V8\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #elif (__VER__ >= 7080000)\r
+ /* Needs IAR language extensions */\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #else\r
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+#endif\r
+\r
+\r
+/* Define compiler macros for CPU architecture, used in CMSIS 5.\r
+ */\r
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\r
+/* Macros already defined */\r
+#else\r
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #elif defined(__ARM8M_BASELINE__)\r
+ #define __ARM_ARCH_8M_BASE__ 1\r
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\r
+ #if __ARM_ARCH == 6\r
+ #define __ARM_ARCH_6M__ 1\r
+ #elif __ARM_ARCH == 7\r
+ #if __ARM_FEATURE_DSP\r
+ #define __ARM_ARCH_7EM__ 1\r
+ #else\r
+ #define __ARM_ARCH_7M__ 1\r
+ #endif\r
+ #endif /* __ARM_ARCH */\r
+ #endif /* __ARM_ARCH_PROFILE == 'M' */\r
+#endif\r
+\r
+/* Alternativ core deduction for older ICCARM's */\r
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\r
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\r
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\r
+ #define __ARM_ARCH_6M__ 1\r
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\r
+ #define __ARM_ARCH_7M__ 1\r
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\r
+ #define __ARM_ARCH_7EM__ 1\r
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\r
+ #define __ARM_ARCH_8M_BASE__ 1\r
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #else\r
+ #error "Unknown target."\r
+ #endif\r
+#endif\r
+\r
+\r
+\r
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\r
+ #define __IAR_M0_FAMILY 1\r
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\r
+ #define __IAR_M0_FAMILY 1\r
+#else\r
+ #define __IAR_M0_FAMILY 0\r
+#endif\r
+\r
+\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+\r
+#ifndef __INLINE\r
+ #define __INLINE inline\r
+#endif\r
+\r
+#ifndef __NO_RETURN\r
+ #if __ICCARM_V8\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+ #else\r
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED\r
+ #if __ICCARM_V8\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED __packed\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED_STRUCT\r
+ #if __ICCARM_V8\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED_STRUCT __packed struct\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED_UNION\r
+ #if __ICCARM_V8\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED_UNION __packed union\r
+ #endif\r
+#endif\r
+\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+#endif\r
+\r
+#ifndef __FORCEINLINE\r
+ #define __FORCEINLINE _Pragma("inline=forced")\r
+#endif\r
+\r
+#ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT16_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\r
+{\r
+ return *(__packed uint16_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\r
+#endif\r
+\r
+\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\r
+{\r
+ *(__packed uint16_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\r
+{\r
+ return *(__packed uint32_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\r
+{\r
+ *(__packed uint32_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+#pragma language=save\r
+#pragma language=extended\r
+__packed struct __iar_u32 { uint32_t v; };\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\r
+#endif\r
+\r
+#ifndef __USED\r
+ #if __ICCARM_V8\r
+ #define __USED __attribute__((used))\r
+ #else\r
+ #define __USED _Pragma("__root")\r
+ #endif\r
+#endif\r
+\r
+#ifndef __WEAK\r
+ #if __ICCARM_V8\r
+ #define __WEAK __attribute__((weak))\r
+ #else\r
+ #define __WEAK _Pragma("__weak")\r
+ #endif\r
+#endif\r
+\r
+\r
+#ifndef __ICCARM_INTRINSICS_VERSION__\r
+ #define __ICCARM_INTRINSICS_VERSION__ 0\r
+#endif\r
+\r
+#if __ICCARM_INTRINSICS_VERSION__ == 2\r
+\r
+ #if defined(__CLZ)\r
+ #undef __CLZ\r
+ #endif\r
+ #if defined(__REVSH)\r
+ #undef __REVSH\r
+ #endif\r
+ #if defined(__RBIT)\r
+ #undef __RBIT\r
+ #endif\r
+ #if defined(__SSAT)\r
+ #undef __SSAT\r
+ #endif\r
+ #if defined(__USAT)\r
+ #undef __USAT\r
+ #endif\r
+\r
+ #include "iccarm_builtin.h"\r
+\r
+ #define __disable_fault_irq __iar_builtin_disable_fiq\r
+ #define __disable_irq __iar_builtin_disable_interrupt\r
+ #define __enable_fault_irq __iar_builtin_enable_fiq\r
+ #define __enable_irq __iar_builtin_enable_interrupt\r
+ #define __arm_rsr __iar_builtin_rsr\r
+ #define __arm_wsr __iar_builtin_wsr\r
+\r
+\r
+ #define __get_APSR() (__arm_rsr("APSR"))\r
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))\r
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))\r
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))\r
+\r
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))\r
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))\r
+ #else\r
+ #define __get_FPSCR() ( 0 )\r
+ #define __set_FPSCR(VALUE) ((void)VALUE)\r
+ #endif\r
+\r
+ #define __get_IPSR() (__arm_rsr("IPSR"))\r
+ #define __get_MSP() (__arm_rsr("MSP"))\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ #define __get_MSPLIM() (0U)\r
+ #else\r
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))\r
+ #endif\r
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))\r
+ #define __get_PSP() (__arm_rsr("PSP"))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __get_PSPLIM() (0U)\r
+ #else\r
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))\r
+ #endif\r
+\r
+ #define __get_xPSR() (__arm_rsr("xPSR"))\r
+\r
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))\r
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))\r
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))\r
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))\r
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))\r
+ #endif\r
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))\r
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))\r
+ #endif\r
+\r
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))\r
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))\r
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))\r
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))\r
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))\r
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))\r
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))\r
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))\r
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))\r
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))\r
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))\r
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))\r
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))\r
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __TZ_get_PSPLIM_NS() (0U)\r
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))\r
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))\r
+ #endif\r
+\r
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))\r
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))\r
+\r
+ #define __NOP __iar_builtin_no_operation\r
+\r
+ #define __CLZ __iar_builtin_CLZ\r
+ #define __CLREX __iar_builtin_CLREX\r
+\r
+ #define __DMB __iar_builtin_DMB\r
+ #define __DSB __iar_builtin_DSB\r
+ #define __ISB __iar_builtin_ISB\r
+\r
+ #define __LDREXB __iar_builtin_LDREXB\r
+ #define __LDREXH __iar_builtin_LDREXH\r
+ #define __LDREXW __iar_builtin_LDREX\r
+\r
+ #define __RBIT __iar_builtin_RBIT\r
+ #define __REV __iar_builtin_REV\r
+ #define __REV16 __iar_builtin_REV16\r
+\r
+ __IAR_FT int16_t __REVSH(int16_t val)\r
+ {\r
+ return (int16_t) __iar_builtin_REVSH(val);\r
+ }\r
+\r
+ #define __ROR __iar_builtin_ROR\r
+ #define __RRX __iar_builtin_RRX\r
+\r
+ #define __SEV __iar_builtin_SEV\r
+\r
+ #if !__IAR_M0_FAMILY\r
+ #define __SSAT __iar_builtin_SSAT\r
+ #endif\r
+\r
+ #define __STREXB __iar_builtin_STREXB\r
+ #define __STREXH __iar_builtin_STREXH\r
+ #define __STREXW __iar_builtin_STREX\r
+\r
+ #if !__IAR_M0_FAMILY\r
+ #define __USAT __iar_builtin_USAT\r
+ #endif\r
+\r
+ #define __WFE __iar_builtin_WFE\r
+ #define __WFI __iar_builtin_WFI\r
+\r
+ #if __ARM_MEDIA__\r
+ #define __SADD8 __iar_builtin_SADD8\r
+ #define __QADD8 __iar_builtin_QADD8\r
+ #define __SHADD8 __iar_builtin_SHADD8\r
+ #define __UADD8 __iar_builtin_UADD8\r
+ #define __UQADD8 __iar_builtin_UQADD8\r
+ #define __UHADD8 __iar_builtin_UHADD8\r
+ #define __SSUB8 __iar_builtin_SSUB8\r
+ #define __QSUB8 __iar_builtin_QSUB8\r
+ #define __SHSUB8 __iar_builtin_SHSUB8\r
+ #define __USUB8 __iar_builtin_USUB8\r
+ #define __UQSUB8 __iar_builtin_UQSUB8\r
+ #define __UHSUB8 __iar_builtin_UHSUB8\r
+ #define __SADD16 __iar_builtin_SADD16\r
+ #define __QADD16 __iar_builtin_QADD16\r
+ #define __SHADD16 __iar_builtin_SHADD16\r
+ #define __UADD16 __iar_builtin_UADD16\r
+ #define __UQADD16 __iar_builtin_UQADD16\r
+ #define __UHADD16 __iar_builtin_UHADD16\r
+ #define __SSUB16 __iar_builtin_SSUB16\r
+ #define __QSUB16 __iar_builtin_QSUB16\r
+ #define __SHSUB16 __iar_builtin_SHSUB16\r
+ #define __USUB16 __iar_builtin_USUB16\r
+ #define __UQSUB16 __iar_builtin_UQSUB16\r
+ #define __UHSUB16 __iar_builtin_UHSUB16\r
+ #define __SASX __iar_builtin_SASX\r
+ #define __QASX __iar_builtin_QASX\r
+ #define __SHASX __iar_builtin_SHASX\r
+ #define __UASX __iar_builtin_UASX\r
+ #define __UQASX __iar_builtin_UQASX\r
+ #define __UHASX __iar_builtin_UHASX\r
+ #define __SSAX __iar_builtin_SSAX\r
+ #define __QSAX __iar_builtin_QSAX\r
+ #define __SHSAX __iar_builtin_SHSAX\r
+ #define __USAX __iar_builtin_USAX\r
+ #define __UQSAX __iar_builtin_UQSAX\r
+ #define __UHSAX __iar_builtin_UHSAX\r
+ #define __USAD8 __iar_builtin_USAD8\r
+ #define __USADA8 __iar_builtin_USADA8\r
+ #define __SSAT16 __iar_builtin_SSAT16\r
+ #define __USAT16 __iar_builtin_USAT16\r
+ #define __UXTB16 __iar_builtin_UXTB16\r
+ #define __UXTAB16 __iar_builtin_UXTAB16\r
+ #define __SXTB16 __iar_builtin_SXTB16\r
+ #define __SXTAB16 __iar_builtin_SXTAB16\r
+ #define __SMUAD __iar_builtin_SMUAD\r
+ #define __SMUADX __iar_builtin_SMUADX\r
+ #define __SMMLA __iar_builtin_SMMLA\r
+ #define __SMLAD __iar_builtin_SMLAD\r
+ #define __SMLADX __iar_builtin_SMLADX\r
+ #define __SMLALD __iar_builtin_SMLALD\r
+ #define __SMLALDX __iar_builtin_SMLALDX\r
+ #define __SMUSD __iar_builtin_SMUSD\r
+ #define __SMUSDX __iar_builtin_SMUSDX\r
+ #define __SMLSD __iar_builtin_SMLSD\r
+ #define __SMLSDX __iar_builtin_SMLSDX\r
+ #define __SMLSLD __iar_builtin_SMLSLD\r
+ #define __SMLSLDX __iar_builtin_SMLSLDX\r
+ #define __SEL __iar_builtin_SEL\r
+ #define __QADD __iar_builtin_QADD\r
+ #define __QSUB __iar_builtin_QSUB\r
+ #define __PKHBT __iar_builtin_PKHBT\r
+ #define __PKHTB __iar_builtin_PKHTB\r
+ #endif\r
+\r
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+ #if __IAR_M0_FAMILY\r
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+ #define __CLZ __cmsis_iar_clz_not_active\r
+ #define __SSAT __cmsis_iar_ssat_not_active\r
+ #define __USAT __cmsis_iar_usat_not_active\r
+ #define __RBIT __cmsis_iar_rbit_not_active\r
+ #define __get_APSR __cmsis_iar_get_APSR_not_active\r
+ #endif\r
+\r
+\r
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))\r
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\r
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\r
+ #endif\r
+\r
+ #ifdef __INTRINSICS_INCLUDED\r
+ #error intrinsics.h is already included previously!\r
+ #endif\r
+\r
+ #include <intrinsics.h>\r
+\r
+ #if __IAR_M0_FAMILY\r
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+ #undef __CLZ\r
+ #undef __SSAT\r
+ #undef __USAT\r
+ #undef __RBIT\r
+ #undef __get_APSR\r
+\r
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)\r
+ {\r
+ if (data == 0U) { return 32U; }\r
+\r
+ uint32_t count = 0U;\r
+ uint32_t mask = 0x80000000U;\r
+\r
+ while ((data & mask) == 0U)\r
+ {\r
+ count += 1U;\r
+ mask = mask >> 1U;\r
+ }\r
+ return count;\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)\r
+ {\r
+ uint8_t sc = 31U;\r
+ uint32_t r = v;\r
+ for (v >>= 1U; v; v >>= 1U)\r
+ {\r
+ r <<= 1U;\r
+ r |= v & 1U;\r
+ sc--;\r
+ }\r
+ return (r << sc);\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __get_APSR(void)\r
+ {\r
+ uint32_t res;\r
+ __asm("MRS %0,APSR" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ #endif\r
+\r
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))\r
+ #undef __get_FPSCR\r
+ #undef __set_FPSCR\r
+ #define __get_FPSCR() (0)\r
+ #define __set_FPSCR(VALUE) ((void)VALUE)\r
+ #endif\r
+\r
+ #pragma diag_suppress=Pe940\r
+ #pragma diag_suppress=Pe177\r
+\r
+ #define __enable_irq __enable_interrupt\r
+ #define __disable_irq __disable_interrupt\r
+ #define __NOP __no_operation\r
+\r
+ #define __get_xPSR __get_PSR\r
+\r
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\r
+\r
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\r
+ {\r
+ return __LDREX((unsigned long *)ptr);\r
+ }\r
+\r
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\r
+ {\r
+ return __STREX(value, (unsigned long *)ptr);\r
+ }\r
+ #endif\r
+\r
+\r
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+ #if (__CORTEX_M >= 0x03)\r
+\r
+ __IAR_FT uint32_t __RRX(uint32_t value)\r
+ {\r
+ uint32_t result;\r
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");\r
+ return(result);\r
+ }\r
+\r
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\r
+ {\r
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));\r
+ }\r
+\r
+\r
+ #define __enable_fault_irq __enable_fiq\r
+ #define __disable_fault_irq __disable_fiq\r
+\r
+\r
+ #endif /* (__CORTEX_M >= 0x03) */\r
+\r
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+ {\r
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\r
+ }\r
+\r
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+ __IAR_FT uint32_t __get_MSPLIM(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __set_MSPLIM(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __get_PSPLIM(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __set_PSPLIM(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))\r
+\r
+#if __IAR_M0_FAMILY\r
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+ {\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+ {\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+ }\r
+#endif\r
+\r
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+\r
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+ {\r
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+ {\r
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\r
+ {\r
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");\r
+ }\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+\r
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+ {\r
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+ {\r
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\r
+ {\r
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#undef __IAR_FT\r
+#undef __IAR_M0_FAMILY\r
+#undef __ICCARM_V8\r
+\r
+#pragma diag_default=Pe940\r
+#pragma diag_default=Pe177\r
+\r
+#endif /* __CMSIS_ICCARM_H__ */\r
projects / freertos / blobdiff