Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignmen...

[freertos] / FreeRTOS / Demo / RISC-V-Qemu-sifive_e-FreedomStudio / full_demo / RegTest.S

diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S
index 0a5e544b6dd8f817028c7d98f07c72e6bd8c2d76..8eef086e6e266336582269fcaaec7a8c5b904c4a 100644 (file)
--- a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S
@@ -38,6 +38,7 @@
  * main_full.c.\r
  */\r
 \r
+.align( 8 )\r
 vRegTest1Implementation:\r
 \r
        /* Fill the core registers with known values. */\r
@@ -144,13 +145,15 @@ reg1_loop:
 reg1_error_loop:\r
        /* Jump here if a register contains an uxpected value.  This stops the loop\r
        counter being incremented so the check task knows an error was found. */\r
-//     ebreak\r
+       ebreak\r
        jal reg1_error_loop\r
 \r
+.align( 16 )\r
 ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
+.align( 8 )\r
 vRegTest2Implementation:\r
 \r
        /* Fill the core registers with known values. */\r
@@ -254,9 +257,10 @@ Reg2_loop:
 reg2_error_loop:\r
        /* Jump here if a register contains an uxpected value.  This stops the loop\r
        counter being incremented so the check task knows an error was found. */\r
-//     ebreak\r
+       ebreak\r
        jal reg2_error_loop\r
 \r
+.align( 16 )\r
 ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter\r
 \r
 \r