Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignmen...

[freertos] / FreeRTOS / Demo / RISC-V_RV32M1_Vega_GCC_Eclipse / projects / RTOSDemo_ri5cy / full_demo / RegTest.S

diff --git a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
index b40c18dcf1a03bd196d294c9720e2ce74d296a5f..ca2c01b88f0b4242af588ce6c278d667057fb62d 100644 (file)
--- a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
@@ -47,6 +47,8 @@
  * The register check tasks are described in the comments at the top of\r
  * main_full.c.\r
  */\r
+\r
+.align( 8 )\r
 vRegTest1Implementation:\r
 \r
        /* Fill the additional registers with known values. */\r
@@ -191,10 +193,12 @@ reg1_error_loop:
        ebreak\r
        jal reg1_error_loop\r
 \r
+.align( 16 )\r
 ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
+.align( 8 )\r
 vRegTest2Implementation:\r
 \r
        /* Fill the additional registers with known values. */\r
@@ -336,6 +340,7 @@ reg2_error_loop:
        ebreak\r
        jal reg2_error_loop\r
 \r
+.align( 16 )\r
 ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter\r
 \r
 \r