Continue working on the GIC-less Cortex-A5 port for IAR:

[freertos] / FreeRTOS / Source / portable / IAR / ARM_CA5_No_GIC / portASM.h

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
index 3af3284d34532a6793069b35c8d63d92a775dade..fe6c74579e6a76fcccd10e7d46dcbc3512f04857 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -127,18 +127,12 @@ portRESTORE_CONTEXT macro
        POP             {R1}\r
        STR             R1, [R0]\r
 \r
-       ; Ensure the priority mask is correct for the critical nesting depth\r
-;_RB_  LDR             R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS\r
-       CMP             R1, #0\r
-       MOVEQ   R4, #255\r
-;_RB_  LDRNE   R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )\r
-       STR             R4, [r2]\r
-\r
        ; Restore all system mode registers other than the SP (which is already\r
        ; being used)\r
        POP             {R0-R12, R14}\r
 \r
-       ; Return to the task code, loading CPSR on the way.\r
+       ; Return to the task code, loading CPSR on the way.  CPSR has the interrupt\r
+       ; enable bit set appropriately for the task about to execute.\r
        RFEIA   sp!\r
 \r
        endm\r