Continue working on the GIC-less Cortex-A5 port for IAR:

- Add in the assert when a task attempts to exit its implementing function without deleting itself.
- Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register).
- Attempt to make code more generic by using definitions for additional register addresses.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2283 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
index b8c1b64148ca70aa09e4032e460a51f84a090133..965d304f55a0fd2cc9a5e59b4b230d6341919aa0 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
@@ -111,6 +111,11 @@ mode. */
  */\r
 extern void vPortRestoreTaskContext( void );\r
 \r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
 /*-----------------------------------------------------------*/\r
 \r
 /* A variable is used to keep track of the critical section nesting.  This\r
@@ -137,7 +142,6 @@ uint32_t ulPortInterruptNesting = 0UL;
 #warning What about branch distance in asm file.\r
 #warning Does not support flop use in ISRs.\r
 #warning Level interrupts must be cleared in their handling function.\r
-#warning Can this be made generic by defining the vector address register externally?\r
 \r
 /*\r
  * See header file for description.\r
@@ -165,13 +169,13 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
        }\r
 \r
        pxTopOfStack--;\r
-#warning What about task exit error function?\r
+\r
        /* Next the return address, which in this case is the start of the task. */\r
        *pxTopOfStack = ( StackType_t ) pxCode;\r
        pxTopOfStack--;\r
 \r
        /* Next all the registers other than the stack pointer. */\r
-       *pxTopOfStack = ( StackType_t ) 0x00000000;     /* R14 */\r
+       *pxTopOfStack = ( StackType_t ) prvTaskExitError;       /* R14 */\r
        pxTopOfStack--;\r
        *pxTopOfStack = ( StackType_t ) 0x12121212;     /* R12 */\r
        pxTopOfStack--;\r
@@ -214,6 +218,20 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 }\r
 /*-----------------------------------------------------------*/\r
 \r
+static void prvTaskExitError( void )\r
+{\r
+       /* A function that implements a task must not exit or attempt to return to\r
+       its caller as there is nothing to return to.  If a task wants to exit it\r
+       should instead call vTaskDelete( NULL ).\r
+\r
+       Artificially force an assert() to be triggered if configASSERT() is\r
+       defined, then stop here so application writers can catch the error. */\r
+       configASSERT( ulPortInterruptNesting == ~0UL );\r
+       portDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
 BaseType_t xPortStartScheduler( void )\r
 {\r
 uint32_t ulAPSR;\r
@@ -228,7 +246,6 @@ uint32_t ulAPSR;
        {\r
                /* Start the timer that generates the tick ISR. */\r
                configSETUP_TICK_INTERRUPT();\r
-#warning Install spurious handler\r
                __enable_irq();\r
                vPortRestoreTaskContext();\r
        }\r

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
index 3af3284d34532a6793069b35c8d63d92a775dade..fe6c74579e6a76fcccd10e7d46dcbc3512f04857 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -127,18 +127,12 @@ portRESTORE_CONTEXT macro
        POP             {R1}\r
        STR             R1, [R0]\r
 \r
-       ; Ensure the priority mask is correct for the critical nesting depth\r
-;_RB_  LDR             R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS\r
-       CMP             R1, #0\r
-       MOVEQ   R4, #255\r
-;_RB_  LDRNE   R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )\r
-       STR             R4, [r2]\r
-\r
        ; Restore all system mode registers other than the SP (which is already\r
        ; being used)\r
        POP             {R0-R12, R14}\r
 \r
-       ; Return to the task code, loading CPSR on the way.\r
+       ; Return to the task code, loading CPSR on the way.  CPSR has the interrupt\r
+       ; enable bit set appropriately for the task about to execute.\r
        RFEIA   sp!\r
 \r
        endm\r

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
index b9086d486fea060b1323e6e3c3bdb8461b5c0d8e..c66146964e3981eb5de7f63e48a2687a4b3ca5cd 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
@@ -67,10 +67,6 @@ SYS_MODE                     EQU             0x1f
 SVC_MODE                       EQU             0x13\r
 IRQ_MODE                       EQU             0x12\r
 \r
-; AIC register definitions.\r
-AIC_IVR                                EQU             0xFFFFF010UL\r
-AIC_EOICR                      EQU             0xFFFFF038UL\r
-\r
        SECTION .text:CODE:ROOT(2)\r
        ARM\r
 \r
@@ -93,7 +89,7 @@ vPortRestoreTaskContext
 \r
 \r
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-; AIC interrupt handler\r
+; IRQ interrupt handler used when individual priorities cannot be masked\r
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
 FreeRTOS_IRQ_Handler\r
 \r
@@ -127,7 +123,7 @@ FreeRTOS_IRQ_Handler
 \r
        ; Call the interrupt handler\r
        PUSH    {r0-r3, lr}\r
-       LDR             r1, =AIC_IVR\r
+       LDR             r1, =configINTERRUPT_VECTOR_ADDRESS\r
        LDR             r0, [r1]\r
        STR             r1, [r1] ; Write to IVR in case protect mode is being used.\r
        BLX             r0\r
@@ -137,7 +133,7 @@ FreeRTOS_IRQ_Handler
        CPSID   i\r
 \r
        ; Write to the EOI register\r
-       LDR     r4, =AIC_EOICR\r
+       LDR     r4, =configEOI_ADDRESS\r
        STR             r0, [r4]\r
 \r
        ; Restore the old nesting count\r