Added portASSERT_IF_IN_INTERRUPT() macro to the GCC Cortex A9 port layer.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2258 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c b/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
index 0c9d48c1badbb5e2a592e95427500f333f4a6a7f..b66a8c764415be4536ed0ef1eeeff55f4f0e5635 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
@@ -110,6 +110,10 @@
        #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\r
 #endif\r
 \r
+/* Used to check non ISR safe API functions are not called from inside an\r
+ISR. */\r
+#define portASSERT_IF_IN_INTERRUPT() configASSERT( ( portICCRPR_RUNNING_PRIORITY_REGISTER == 0xffUL ) || ( portICCRPR_RUNNING_PRIORITY_REGISTER == portLOWEST_INTERRUPT_PRIORITY ) )\r
+\r
 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in\r
 portmacro.h. */\r
 #ifndef configCLEAR_TICK_INTERRUPT\r
@@ -371,6 +375,10 @@ void vPortEndScheduler( void )
 \r
 void vPortEnterCritical( void )\r
 {\r
+       /* This is not the interrupt safe version of the enter critical function.\r
+       Only API functions that end in "FromISR" can be used in an interrupt. */\r
+       portASSERT_IF_IN_INTERRUPT();\r
+\r
        /* Mask interrupts up to the max syscall interrupt priority. */\r
        ulPortSetInterruptMask();\r
 \r
@@ -383,6 +391,10 @@ void vPortEnterCritical( void )
 \r
 void vPortExitCritical( void )\r
 {\r
+       /* This is not the interrupt safe version of the enter critical function.\r
+       Only API functions that end in "FromISR" can be used in an interrupt. */\r
+       portASSERT_IF_IN_INTERRUPT();\r
+\r
        if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
        {\r
                /* Decrement the nesting count as the critical section is being\r
@@ -490,11 +502,8 @@ uint32_t ulReturn;
                configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 \r
                FreeRTOS maintains separate thread and ISR API functions to ensure\r
-               interrupt entry is as fast and simple as possible.\r
+               interrupt entry is as fast and simple as possible. */\r
 \r
-               The following links provide detailed information:\r
-               http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
-               http://www.freertos.org/FAQHelp.html */\r
                configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\r
 \r
                /* Priority grouping:  The interrupt controller (GIC) allows the bits\r
@@ -513,3 +522,5 @@ uint32_t ulReturn;
 #endif /* configASSERT_DEFINED */\r
 /*-----------------------------------------------------------*/\r
 \r
+\r
+\r