\r
#define configUSE_PREEMPTION 1\r
#define configUSE_IDLE_HOOK 0\r
-#define configUSE_TICK_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6500 ) )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 3000 ) )\r
#define configMAX_TASK_NAME_LEN ( 5 )\r
#define configUSE_TRACE_FACILITY 1\r
#define configUSE_16_BIT_TICKS 0\r
#define configIDLE_SHOULD_YIELD 1\r
#define configUSE_MUTEXES 1\r
#define configQUEUE_REGISTRY_SIZE 8\r
-#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configCHECK_FOR_STACK_OVERFLOW 1\r
#define configUSE_RECURSIVE_MUTEXES 1\r
#define configUSE_MALLOC_FAILED_HOOK 1\r
#define configUSE_APPLICATION_TASK_TAG 0\r
+++ /dev/null
-/*\r
- FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*-----------------------------------------------------------\r
- * Simple GPIO (parallel port) IO routines.\r
- *-----------------------------------------------------------*/\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Hardware includes. */\r
-#include <XMC1300.h>\r
-\r
-/* Standard demo include. */\r
-#include "partest.h"\r
-\r
-/* The port bits on which LEDs are connected. */\r
-static const unsigned long ulLEDBits[] = \r
-{ \r
- 1UL << 0, /* P0.0 */\r
- 1UL << 2, /* P0.2 */\r
- 1UL << 5, /* P0.5 */\r
- 1UL << 6, /* P0.6 */\r
- 1UL << 7 /* P0.7 */\r
-};\r
-\r
-#define partstNUM_LEDS ( sizeof( ulLEDBits ) / sizeof( unsigned long ) )\r
-\r
-/* Shift the LED bit into the correct position within the POW register to\r
-perform the desired operation. */\r
-#define partstON_SHIFT ( 16UL )\r
-#define partstOFF_SHIFT ( 0UL )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestInitialise( void )\r
-{\r
- /* Configure relevant port P0 to push pull output to drive LEDs. */\r
- \r
- /* P0.0 */\r
- PORT0->IOCR0 &= ~( ( 0xFFUL << 0 ) );\r
- PORT0->IOCR0 |= ( 0x80UL << 0 );\r
-\r
- /* P0.2 */\r
- PORT0->IOCR0 &= ~( ( 0xFFUL << 16 ) );\r
- PORT0->IOCR0 |= ( 0x80UL << 16 );\r
-\r
- /* P0.5 */\r
- PORT0->IOCR4 &= ~( ( 0xFFUL << 8 ) );\r
- PORT0->IOCR4 |= ( 0x80UL << 8 );\r
-\r
- /* P0.6 */\r
- PORT0->IOCR4 &= ~( ( 0xFFUL << 16 ) );\r
- PORT0->IOCR4 |= ( 0x80UL << 16 );\r
-\r
- /* P0.7 */\r
- PORT0->IOCR4 &= ~( ( 0xFFUL << 24 ) );\r
- PORT0->IOCR4 |= ( 0x80UL << 24 );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue )\r
-{\r
- if( ulLED < partstNUM_LEDS )\r
- {\r
- if( xValue == pdTRUE )\r
- {\r
- /* Turn the LED on. */\r
- PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT );\r
- }\r
- else\r
- {\r
- /* Turn the LED off. */\r
- PORT0->OMR = ( ulLEDBits[ ulLED ] << partstOFF_SHIFT );\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestToggleLED( unsigned long ulLED )\r
-{\r
- if( ulLED < partstNUM_LEDS )\r
- {\r
- /* Setting both the ON and OFF bits simultaneously results in the bit\r
- being toggled. */\r
- PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ) | ( ulLEDBits[ ulLED ] << partstOFF_SHIFT );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple GPIO (parallel port) IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Hardware includes. */\r
+#include <XMC1200.h>\r
+\r
+/* Standard demo include. */\r
+#include "partest.h"\r
+\r
+/* The port bits on which LEDs are connected. */\r
+static const unsigned long ulLEDBits[] = \r
+{ \r
+ 1UL << 0, /* P0.0 */\r
+ 1UL << 2, /* P0.2 */\r
+ 1UL << 5, /* P0.5 */\r
+ 1UL << 6, /* P0.6 */\r
+ 1UL << 7 /* P0.7 */\r
+};\r
+\r
+#define partstNUM_LEDS ( sizeof( ulLEDBits ) / sizeof( unsigned long ) )\r
+\r
+/* Shift the LED bit into the correct position within the POW register to\r
+perform the desired operation. */\r
+#define partstON_SHIFT ( 16UL )\r
+#define partstOFF_SHIFT ( 0UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Configure relevant port P0 to push pull output to drive LEDs. */\r
+ \r
+ /* P0.0 */\r
+ PORT0->IOCR0 &= ~( ( 0xFFUL << 0 ) );\r
+ PORT0->IOCR0 |= ( 0x80UL << 0 );\r
+\r
+ /* P0.2 */\r
+ PORT0->IOCR0 &= ~( ( 0xFFUL << 16 ) );\r
+ PORT0->IOCR0 |= ( 0x80UL << 16 );\r
+\r
+ /* P0.5 */\r
+ PORT0->IOCR4 &= ~( ( 0xFFUL << 8 ) );\r
+ PORT0->IOCR4 |= ( 0x80UL << 8 );\r
+\r
+ /* P0.6 */\r
+ PORT0->IOCR4 &= ~( ( 0xFFUL << 16 ) );\r
+ PORT0->IOCR4 |= ( 0x80UL << 16 );\r
+\r
+ /* P0.7 */\r
+ PORT0->IOCR4 &= ~( ( 0xFFUL << 24 ) );\r
+ PORT0->IOCR4 |= ( 0x80UL << 24 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( ulLED < partstNUM_LEDS )\r
+ {\r
+ if( xValue == pdTRUE )\r
+ {\r
+ /* Turn the LED on. */\r
+ PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT );\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LED off. */\r
+ PORT0->OMR = ( ulLEDBits[ ulLED ] << partstOFF_SHIFT );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+ if( ulLED < partstNUM_LEDS )\r
+ {\r
+ /* Setting both the ON and OFF bits simultaneously results in the bit\r
+ being toggled. */\r
+ PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ) | ( ulLEDBits[ ulLED ] << partstOFF_SHIFT );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
- <IsCurrentTarget>1</IsCurrentTarget>
+ <IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<Books>
<Name>UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0XMC1300_200 -FL032000 -FS010001000</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
- <Breakpoint>
- <Bp>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>XMC1200</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <Books>
+ <Book>
+ <Number>0</Number>
+ <Title>Data Sheet</Title>
+ <Path>DATASHTS\Infineon\XMC1200\xmc1100_ds.pdf</Path>
+ </Book>
+ <Book>
+ <Number>1</Number>
+ <Title>User Manual</Title>
+ <Path>DATASHTS\Infineon\XMC1200\xmc1100_ds.pdf</Path>
+ </Book>
+ <Book>
+ <Number>2</Number>
+ <Title>Technical Reference Manual</Title>
+ <Path>datashts\arm\cortex_m0\r0p0\DDI0432C_CORTEX_M0_R0P0_TRM.PDF</Path>
+ </Book>
+ <Book>
+ <Number>3</Number>
+ <Title>Generic User Guide</Title>
+ <Path>datashts\arm\cortex_m0\r0p0\DUI0497A_CORTEX_M0_R0P0_GENERIC_UG.PDF</Path>
+ </Book>
+ </Books>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>0</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>1</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>7</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>Segger\JL2CM3.dll</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
<Number>0</Number>
- <Type>0</Type>
- <LineNumber>132</LineNumber>
- <EnabledFlag>1</EnabledFlag>
- <Address>0</Address>
- <ByteObject>0</ByteObject>
- <HtxType>0</HtxType>
- <ManyObjects>0</ManyObjects>
- <SizeOfObject>0</SizeOfObject>
- <BreakByAccess>0</BreakByAccess>
- <BreakIfRCount>0</BreakIfRCount>
- <Filename>C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil\startup_XMC1300.s</Filename>
- <ExecCommand></ExecCommand>
- <Expression></Expression>
- </Bp>
- </Breakpoint>
+ <Key>DLGTARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGUARM</Key>
+ <Name></Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>JL2CM3</Key>
+ <Name>-U591005602 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1200_200 -FS010001000 -FL032000</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1200_200 -FS010001000 -FL032000)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <WatchWindow1>
+ <Ww>
+ <count>0</count>
+ <WinNumber>1</WinNumber>
+ <ItemText>uxCriticalNesting</ItemText>
+ </Ww>
+ </WatchWindow1>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
- <FileType>2</FileType>
+ <FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>130</TopLine>
- <CurrentLine>132</CurrentLine>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
<bDave2>0</bDave2>
- <PathWithFileName>.\startup_XMC1300.s</PathWithFileName>
- <FilenameWithoutPath>startup_XMC1300.s</FilenameWithoutPath>
+ <PathWithFileName>.\System_Keil\system_XMC1300.c</PathWithFileName>
+ <FilenameWithoutPath>system_XMC1300.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
<bDave2>0</bDave2>
- <PathWithFileName>.\system_XMC1300.c</PathWithFileName>
- <FilenameWithoutPath>system_XMC1300.c</FilenameWithoutPath>
+ <PathWithFileName>.\System_Keil\system_XMC1100.c</PathWithFileName>
+ <FilenameWithoutPath>system_XMC1100.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\System_Keil\system_XMC1200.c</PathWithFileName>
+ <FilenameWithoutPath>system_XMC1200.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>3</FileNumber>
+ <FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
+ <TopLine>346</TopLine>
+ <CurrentLine>369</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\timers.c</PathWithFileName>
<FilenameWithoutPath>timers.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>4</FileNumber>
+ <FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
+ <TopLine>150</TopLine>
+ <CurrentLine>198</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\list.c</PathWithFileName>
<FilenameWithoutPath>list.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>5</FileNumber>
+ <FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>1242</TopLine>
- <CurrentLine>1259</CurrentLine>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\queue.c</PathWithFileName>
<FilenameWithoutPath>queue.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>6</FileNumber>
+ <FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
+ <TopLine>1824</TopLine>
+ <CurrentLine>1847</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\tasks.c</PathWithFileName>
<FilenameWithoutPath>tasks.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>7</FileNumber>
+ <FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
- <ColumnNumber>9</ColumnNumber>
+ <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>265</TopLine>
- <CurrentLine>279</CurrentLine>
+ <TopLine>291</TopLine>
+ <CurrentLine>292</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\RVDS\ARM_CM0\port.c</PathWithFileName>
<FilenameWithoutPath>port.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>8</FileNumber>
+ <FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
- <File>
- <GroupNumber>3</GroupNumber>
- <FileNumber>9</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>9</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>115</TopLine>
- <CurrentLine>134</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>.\ParTest.c</PathWithFileName>
- <FilenameWithoutPath>ParTest.c</FilenameWithoutPath>
- <RteFlg>0</RteFlg>
- <bShared>0</bShared>
- </File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
- <ColumnNumber>42</ColumnNumber>
+ <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>73</TopLine>
- <CurrentLine>94</CurrentLine>
+ <TopLine>112</TopLine>
+ <CurrentLine>122</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
- <ColumnNumber>44</ColumnNumber>
+ <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>203</TopLine>
- <CurrentLine>128</CurrentLine>
+ <TopLine>186</TopLine>
+ <CurrentLine>194</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\main-blinky.c</PathWithFileName>
<FilenameWithoutPath>main-blinky.c</FilenameWithoutPath>
<FileType>5</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
+ <ColumnNumber>41</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
+ <TopLine>74</TopLine>
+ <CurrentLine>98</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\FreeRTOSConfig.h</PathWithFileName>
<FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
- <ColumnNumber>36</ColumnNumber>
+ <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>293</TopLine>
- <CurrentLine>311</CurrentLine>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\main-full.c</PathWithFileName>
<FilenameWithoutPath>main-full.c</FilenameWithoutPath>
<FileType>2</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
- <ColumnNumber>5</ColumnNumber>
+ <ColumnNumber>14</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>142</TopLine>
- <CurrentLine>143</CurrentLine>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\RegTest.s</PathWithFileName>
<FilenameWithoutPath>RegTest.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>15</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\ParTest_XMC1200.c</PathWithFileName>
+ <FilenameWithoutPath>ParTest_XMC1200.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
</Group>
<Group>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>15</FileNumber>
+ <FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>16</FileNumber>
+ <FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>17</FileNumber>
+ <FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>18</FileNumber>
+ <FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<GroupName>System</GroupName>
<Files>
<File>
- <FileName>startup_XMC1300.s</FileName>
- <FileType>2</FileType>
- <FilePath>.\startup_XMC1300.s</FilePath>
+ <FileName>system_XMC1300.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_Keil\system_XMC1300.c</FilePath>
</File>
<File>
- <FileName>system_XMC1300.c</FileName>
+ <FileName>system_XMC1100.c</FileName>
<FileType>1</FileType>
- <FilePath>.\system_XMC1300.c</FilePath>
+ <FilePath>.\System_Keil\system_XMC1100.c</FilePath>
+ </File>
+ <File>
+ <FileName>system_XMC1200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_Keil\system_XMC1200.c</FilePath>
</File>
</Files>
</Group>
<GroupName>Demo App Source</GroupName>
<Files>
<File>
- <FileName>ParTest.c</FileName>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>main-blinky.c</FileName>
<FileType>1</FileType>
- <FilePath>.\ParTest.c</FilePath>
+ <FilePath>.\main-blinky.c</FilePath>
</File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\FreeRTOSConfig.h</FilePath>
+ </File>
+ <File>
+ <FileName>main-full.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main-full.c</FilePath>
+ </File>
+ <File>
+ <FileName>RegTest.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\RegTest.s</FilePath>
+ </File>
+ <File>
+ <FileName>ParTest_XMC1200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ParTest_XMC1200.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Common Demo Tasks</GroupName>
+ <Files>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>recmutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>XMC1200</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>XMC1200-200</Device>
+ <Vendor>Infineon</Vendor>
+ <Cpu>IRAM(0x20000000-0x20003FFF) IROM(0x10001000-0x10032FFF) CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile>"STARTUP\Infineon\XMC1200\startup_XMC1200.s" ("Infineon XMC1200 Startup Code")</StartupFile>
+ <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1200_200 -FS010001000 -FL032000)</FlashDriverDll>
+ <DeviceId>6777</DeviceId>
+ <RegisterFile>XMC1200.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>SFD\Infineon\XMC1200\xmc1200.SFR</SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath>Infineon\XMC1200\</RegisterFilePath>
+ <DBRegisterFilePath>Infineon\XMC1200\</DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Output\</OutputDirectory>
+ <OutputName>RTOSDemo</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>1</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>7</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>Segger\JL2CM3.dll</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4100</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>Segger\JL2CM3.dll</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>0</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x4000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x10001000</StartAddress>
+ <Size>0x32000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x10001000</StartAddress>
+ <Size>0x32000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x4000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;..\Common\include</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x10001000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <ScatterFile>.\Output\RTOSDemo.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_XMC1300.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_Keil\system_XMC1300.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>system_XMC1100.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_Keil\system_XMC1100.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>system_XMC1200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_Keil\system_XMC1200.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS source</GroupName>
+ <Files>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\RVDS\ARM_CM0\port.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Demo App Source</GroupName>
+ <Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FileType>2</FileType>
<FilePath>.\RegTest.s</FilePath>
</File>
+ <File>
+ <FileName>ParTest_XMC1200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ParTest_XMC1200.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
</Files>
</Group>
<Group>
--- /dev/null
+;*****************************************************************************/\r
+; * @file startup_XMC1300.s\r
+; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
+; * Infineon XMC1300 Device Series\r
+; * @version V1.00\r
+; * @date 21. Jan. 2013\r
+; *\r
+; * @note\r
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
+; *\r
+; * @par\r
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+; * processor based microcontrollers. This file can be freely distributed\r
+; * within development tools that are supporting such ARM based processors.\r
+; *\r
+; * @par\r
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; *\r
+; ******************************************************************************/\r
+\r
+\r
+;* <<< Use Configuration Wizard in Context Menu >>>\r
+\r
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000200\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+; <h> Clock system handling by SSW\r
+; <h> CLK_VAL1 Configuration\r
+; <o0.0..7> FDIV Fractional Divider Selection\r
+; <o0.8..15> IDIV Divider Selection\r
+; <0=> Divider is bypassed\r
+; <1=> MCLK = 32 MHz\r
+; <2=> MCLK = 16 MHz\r
+; <3=> MCLK = 10.67 MHz\r
+; <4=> MCLK = 8 MHz\r
+; <254=> MCLK = 126 kHz\r
+; <255=> MCLK = 125.5 kHz\r
+; <o0.16> PCLKSEL PCLK Clock Select\r
+; <0=> PCLK = MCLK\r
+; <1=> PCLK = 2 x MCLK\r
+; <o0.17..19> RTCCLKSEL RTC Clock Select\r
+; <0=> 32.768kHz standby clock\r
+; <1=> 32.768kHz external clock from ERU0.IOUT0\r
+; <2=> 32.768kHz external clock from ACMP0.OUT\r
+; <3=> 32.768kHz external clock from ACMP1.OUT\r
+; <4=> 32.768kHz external clock from ACMP2.OUT\r
+; <5=> Reserved\r
+; <6=> Reserved\r
+; <7=> Reserved\r
+; <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]\r
+; </h>\r
+CLK_VAL1_Val EQU 0x80000000 ; 0xF0000000\r
+\r
+; <h> CLK_VAL2 Configuration\r
+; <o0.0> disable VADC and SHS Gating\r
+; <o0.1> disable CCU80 Gating\r
+; <o0.2> disable CCU40 Gating\r
+; <o0.3> disable USIC0 Gating\r
+; <o0.4> disable BCCU0 Gating\r
+; <o0.5> disable LEDTS0 Gating\r
+; <o0.6> disable LEDTS1 Gating\r
+; <o0.7> disable POSIF0 Gating\r
+; <o0.8> disable MATH Gating\r
+; <o0.9> disable WDT Gating\r
+; <o0.10> disable RTC Gating\r
+; <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]\r
+; </h>\r
+CLK_VAL2_Val EQU 0x80000000 ; 0xF0000000\r
+; </h>\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
+;* Vector Table Mapped to Address 0 at Reset\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+\r
+\r
+__Vectors\r
+ DCD __initial_sp ;* Top of Stack\r
+ DCD Reset_Handler ;* Reset Handler\r
+ DCD 0 ;* Not used\r
+ DCD 0 ;* Not Used\r
+ DCD CLK_VAL1_Val ;* CLK_VAL1\r
+ DCD CLK_VAL2_Val ;* CLK_VAL2\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+;* ================== END OF VECTOR TABLE DEFINITION ======================== */\r
+\r
+\r
+;* ================== START OF VECTOR ROUTINES ============================== */\r
+ AREA |.text|, CODE, READONLY\r
+\r
+;* Reset Handler\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT __main\r
+ IMPORT SystemInit\r
+\r
+ ;* C routines are likely to be called. Setup the stack now\r
+ LDR R0, =__initial_sp\r
+ MOV SP, R0\r
+\r
+ ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"\r
+ ; The real veneers will be copied later from the scatter loader before reaching main.\r
+ ; This init code should handle an exception before the real veneers are copied.\r
+SRAM_BASE EQU 0x20000000\r
+VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B .\r
+\r
+ LDR R1, =SRAM_BASE\r
+ LDR R2, =VENEER_INIT_CODE \r
+ MOVS R0, #48 ; Veneer 0..47\r
+Init_Veneers\r
+ STR R2, [R1]\r
+ ADDS R1, #4\r
+ SUBS R0, R0, #1\r
+ BNE Init_Veneers\r
+\r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+\r
+\r
+ ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
+ ; weakly defined here though for a potential override.\r
+\r
+ LDR R0, = SystemInit_DAVE3\r
+ BLX R0\r
+\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+\r
+\r
+ ALIGN\r
+ ENDP\r
+\r
+;* ========================================================================== */\r
+\r
+\r
+\r
+;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */\r
+;* Default exception Handlers - Users may override this default functionality\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler\\r
+ PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler\\r
+ PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler\\r
+ PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
+\r
+\r
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
+;* IRQ Handlers\r
+\r
+Default_Handler PROC\r
+ EXPORT SCU_0_IRQHandler [WEAK]\r
+ EXPORT SCU_1_IRQHandler [WEAK]\r
+ EXPORT SCU_2_IRQHandler [WEAK]\r
+ EXPORT ERU0_0_IRQHandler [WEAK]\r
+ EXPORT ERU0_1_IRQHandler [WEAK]\r
+ EXPORT ERU0_2_IRQHandler [WEAK]\r
+ EXPORT ERU0_3_IRQHandler [WEAK]\r
+ EXPORT MATH0_0_IRQHandler [WEAK]\r
+ EXPORT USIC0_0_IRQHandler [WEAK]\r
+ EXPORT USIC0_1_IRQHandler [WEAK]\r
+ EXPORT USIC0_2_IRQHandler [WEAK]\r
+ EXPORT USIC0_3_IRQHandler [WEAK]\r
+ EXPORT USIC0_4_IRQHandler [WEAK]\r
+ EXPORT USIC0_5_IRQHandler [WEAK]\r
+ EXPORT VADC0_C0_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_C0_1_IRQHandler [WEAK]\r
+ EXPORT VADC0_G0_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_G0_1_IRQHandler [WEAK]\r
+ EXPORT VADC0_G1_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_G1_1_IRQHandler [WEAK]\r
+ EXPORT CCU40_0_IRQHandler [WEAK]\r
+ EXPORT CCU40_1_IRQHandler [WEAK]\r
+ EXPORT CCU40_2_IRQHandler [WEAK]\r
+ EXPORT CCU40_3_IRQHandler [WEAK]\r
+ EXPORT CCU80_0_IRQHandler [WEAK]\r
+ EXPORT CCU80_1_IRQHandler [WEAK]\r
+ EXPORT POSIF0_0_IRQHandler [WEAK]\r
+ EXPORT POSIF0_1_IRQHandler [WEAK]\r
+ EXPORT LEDTS0_0_IRQHandler [WEAK]\r
+ EXPORT LEDTS1_0_IRQHandler [WEAK]\r
+ EXPORT BCCU0_0_IRQHandler [WEAK]\r
+\r
+SCU_0_IRQHandler\r
+SCU_1_IRQHandler\r
+SCU_2_IRQHandler\r
+ERU0_0_IRQHandler\r
+ERU0_1_IRQHandler\r
+ERU0_2_IRQHandler\r
+ERU0_3_IRQHandler\r
+MATH0_0_IRQHandler\r
+USIC0_0_IRQHandler\r
+USIC0_1_IRQHandler\r
+USIC0_2_IRQHandler\r
+USIC0_3_IRQHandler\r
+USIC0_4_IRQHandler\r
+USIC0_5_IRQHandler\r
+VADC0_C0_0_IRQHandler\r
+VADC0_C0_1_IRQHandler\r
+VADC0_G0_0_IRQHandler\r
+VADC0_G0_1_IRQHandler\r
+VADC0_G1_0_IRQHandler\r
+VADC0_G1_1_IRQHandler\r
+CCU40_0_IRQHandler\r
+CCU40_1_IRQHandler\r
+CCU40_2_IRQHandler\r
+CCU40_3_IRQHandler\r
+CCU80_0_IRQHandler\r
+CCU80_1_IRQHandler\r
+POSIF0_0_IRQHandler\r
+POSIF0_1_IRQHandler\r
+LEDTS0_0_IRQHandler\r
+LEDTS1_0_IRQHandler\r
+BCCU0_0_IRQHandler\r
+\r
+ B .\r
+\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
+\r
+;* Definition of the default weak SystemInit_DAVE3 function.\r
+;* This function will be called by the CMSIS SystemInit function.\r
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
+;* which will overule this weak definition\r
+SystemInit_DAVE3 PROC\r
+ EXPORT SystemInit_DAVE3 [WEAK]\r
+ NOP\r
+ BX LR\r
+ ENDP\r
+\r
+;* Definition of the default weak DAVE3 function for clock App usage.\r
+;* AllowClkInitByStartup Handler */\r
+AllowClkInitByStartup PROC\r
+ EXPORT AllowClkInitByStartup [WEAK]\r
+ MOVS R0,#1\r
+ BX LR\r
+ ENDP\r
+\r
+\r
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+\r
+;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */\r
+; Veneers are located to fix SRAM Address 0x2000'0000\r
+ AREA |.ARM.__at_0x20000000|, CODE, READWRITE\r
+\r
+; Each Veneer has exactly a lengs of 4 Byte\r
+\r
+ MACRO\r
+ STAYHERE $IrqNumber\r
+ LDR R0, =$IrqNumber\r
+ B .\r
+ MEND\r
+\r
+ MACRO\r
+ JUMPTO $Handler\r
+ LDR R0, =$Handler\r
+ BX R0\r
+ MEND\r
+\r
+ STAYHERE 0x0 ;* Reserved\r
+ STAYHERE 0x1 ;* Reserved \r
+ STAYHERE 0x2 ;* Reserved \r
+ JUMPTO HardFault_Handler ;* HardFault Veneer \r
+ STAYHERE 0x4 ;* Reserved \r
+ STAYHERE 0x5 ;* Reserved \r
+ STAYHERE 0x6 ;* Reserved \r
+ STAYHERE 0x7 ;* Reserved \r
+ STAYHERE 0x8 ;* Reserved \r
+ STAYHERE 0x9 ;* Reserved \r
+ STAYHERE 0xA ;* Reserved\r
+ JUMPTO SVC_Handler ;* SVC Veneer \r
+ STAYHERE 0xC ;* Reserved\r
+ STAYHERE 0xD ;* Reserved\r
+ JUMPTO PendSV_Handler ;* PendSV Veneer \r
+ JUMPTO SysTick_Handler ;* SysTick Veneer \r
+ JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer \r
+ JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer \r
+ JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer \r
+ JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer \r
+ JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer \r
+ JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer \r
+ JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer \r
+ JUMPTO MATH0_0_IRQHandler ;* SCU_7 Veneer \r
+ STAYHERE 0x18 ;* Reserved\r
+ JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer \r
+ JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer \r
+ JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer \r
+ JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer \r
+ JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer \r
+ JUMPTO LEDTS0_0_IRQHandler ;* USIC0_5 Veneer \r
+ JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer \r
+ JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer \r
+ JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer \r
+ JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer \r
+ JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer \r
+ JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer \r
+ JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer \r
+ JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer \r
+ JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer \r
+ JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer \r
+ JUMPTO CCU80_0_IRQHandler ;* CCU80_0 Veneer \r
+ JUMPTO CCU80_1_IRQHandler ;* CCU80_1 Veneer \r
+ JUMPTO POSIF0_0_IRQHandler ;* POSIF0_0 Veneer \r
+ JUMPTO POSIF0_1_IRQHandler ;* POSIF0_1 Veneer \r
+ JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer \r
+ JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer \r
+ JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer \r
+\r
+ ALIGN\r
+\r
+;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */\r
+\r
+ END\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1100.c\r
+ * @brief Device specific initialization for the XMC1100-Series according \r
+ * to CMSIS\r
+ * @version V1.2\r
+ * @date 13 Dec 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with \r
+ * Infineon\92s microcontrollers.\r
+ * \r
+ * This file can be freely distributed within development tools that are \r
+ * supporting such microcontrollers.\r
+ * \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/*\r
+ * *************************** Change history ********************************\r
+ * V1.2, 13 Dec 2012, PKB : Created change history table\r
+ */\r
+\r
+#include "system_XMC1100.h"\r
+#include <XMC1100.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ Extern definitions \r
+ *--------------------------------------------------------------------------*/\r
+extern uint32_t AllowClkInitByStartup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Global defines\r
+ *----------------------------------------------------------------------------*/\r
+#define DCO_DCLK 64000000UL\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{ \r
+ /*\r
+ * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
+ * Clock app.\r
+ */ \r
+ if(AllowClkInitByStartup()){ \r
+ /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
+ /* ====== Default configuration ======= */\r
+ /*\r
+ * MCLK = DCO_DCLK\r
+ * PCLK = MCLK\r
+ * RTC CLK = Standby clock\r
+ */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t IDIV, CLKCR;\r
+\r
+ CLKCR = SCU_CLOCK -> CLKCR;\r
+ \r
+ IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
+ \r
+ if(IDIV)\r
+ {\r
+ SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
+ }\r
+ else\r
+ {\r
+ /* Divider bypassed */\r
+ SystemCoreClock = DCO_DCLK;\r
+ }\r
+}\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1200.c\r
+ * @brief Device specific initialization for the XMC1200-Series according \r
+ * to CMSIS\r
+ * @version V1.2\r
+ * @date 13 Dec 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with \r
+ * Infineon\92s microcontrollers.\r
+ * \r
+ * This file can be freely distributed within development tools that are \r
+ * supporting such microcontrollers.\r
+ * \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/*\r
+ * *************************** Change history ********************************\r
+ * V1.2, 13 Dec 2012, PKB : Created change history table\r
+ */\r
+\r
+#include "System_XMC1200.h"\r
+#include <XMC1200.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ Extern definitions \r
+ *--------------------------------------------------------------------------*/\r
+extern uint32_t AllowClkInitByStartup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Global defines\r
+ *----------------------------------------------------------------------------*/\r
+#define DCO_DCLK 64000000UL\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{ \r
+ /*\r
+ * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
+ * Clock app.\r
+ */ \r
+ if(AllowClkInitByStartup()){ \r
+ /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
+ /* ====== Default configuration ======= */\r
+ /*\r
+ * MCLK = DCO_DCLK\r
+ * PCLK = MCLK\r
+ * RTC CLK = Standby clock\r
+ */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t IDIV, CLKCR;\r
+\r
+ CLKCR = SCU_CLOCK -> CLKCR;\r
+ \r
+ IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
+ \r
+ if(IDIV)\r
+ {\r
+ SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
+ }\r
+ else\r
+ {\r
+ /* Divider bypassed */\r
+ SystemCoreClock = DCO_DCLK;\r
+ }\r
+}\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1300.c\r
+ * @brief Device specific initialization for the XMC1300-Series according \r
+ * to CMSIS\r
+ * @version V1.2\r
+ * @date 13 Dec 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with \r
+ * Infineon\92s microcontrollers.\r
+ * \r
+ * This file can be freely distributed within development tools that are \r
+ * supporting such microcontrollers.\r
+ * \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/*\r
+ * ************************** Change history *********************************\r
+ * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_\r
+ */\r
+\r
+#include "system_XMC1300.h"\r
+#include <XMC1300.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ Extern definitions \r
+ *--------------------------------------------------------------------------*/\r
+extern uint32_t AllowClkInitByStartup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Global defines\r
+ *----------------------------------------------------------------------------*/\r
+#define DCO_DCLK 64000000UL\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{ \r
+ /*\r
+ * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
+ * Clock app.\r
+ */ \r
+ if(AllowClkInitByStartup()){ \r
+ /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
+ /* ====== Default configuration ======= */\r
+ /*\r
+ * MCLK = DCO_DCLK\r
+ * PCLK = MCLK\r
+ * RTC CLK = Standby clock\r
+ */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t IDIV, CLKCR;\r
+\r
+ CLKCR = SCU_CLOCK -> CLKCR;\r
+ \r
+ IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
+ \r
+ if(IDIV)\r
+ {\r
+ SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
+ }\r
+ else\r
+ {\r
+ /* Divider bypassed */\r
+ SystemCoreClock = DCO_DCLK;\r
+ }\r
+}\r
+\r
{\r
/* Start the two tasks as described in the comments at the top of this\r
file. */\r
- xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
- ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
- configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
- ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
- mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
- NULL ); /* The task handle is not required, so NULL is passed. */\r
+// xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+// ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+// configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+// ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
+// mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+// NULL ); /* The task handle is not required, so NULL is passed. */\r
\r
xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
\r
portTickType xNextWakeTime;\r
const unsigned long ulValueToSend = 100UL;\r
\r
+for( ;; )\r
+{\r
+ vTaskDelay( 100 );\r
+ vParTestToggleLED( 0 );\r
+}\r
+ \r
/* Check the task parameter is as expected. */\r
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
\r
const size_t xRegTestStackSize = 25U;\r
\r
/* Create the standard demo tasks */\r
- vCreateBlockTimeTasks();\r
- vStartCountingSemaphoreTasks();\r
- vStartRecursiveMutexTasks();\r
- vStartDynamicPriorityTasks();\r
+// vCreateBlockTimeTasks();\r
+// vStartCountingSemaphoreTasks();\r
+// vStartRecursiveMutexTasks();\r
+// vStartDynamicPriorityTasks();\r
\r
/* Create the register test tasks as described at the top of this file.\r
These are naked functions that don't use any stack. A stack still has\r
\r
if( xTimer != NULL )\r
{\r
- xTimerStart( xTimer, mainDONT_BLOCK );\r
+// xTimerStart( xTimer, mainDONT_BLOCK );\r
}\r
}\r
\r
/* Create the software timer that performs the 'check' functionality,\r
as described at the top of this file. */\r
- xTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
- ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
- pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
- ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
- prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
- );\r
+// xTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+// ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
+// pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+// ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+// prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+// );\r
\r
/* If the software timer was created successfully, start it. It won't\r
actually start running until the scheduler starts. A block time of\r
time will be ignored because the scheduler has not started yet. */\r
if( xTimer != NULL )\r
{\r
- xTimerStart( xTimer, mainDONT_BLOCK );\r
+// xTimerStart( xTimer, mainDONT_BLOCK );\r
}\r
\r
/* Start the kernel. From here on, only tasks and interrupts will run. */\r
*/\r
static void prvSetupHardware( void );\r
\r
-/* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
-main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. \r
+ */\r
extern void main_blinky( void );\r
extern void main_full( void );\r
\r
+/* \r
+ * CMSIS clock configuration function. \r
+ */\r
+extern void SystemCoreClockUpdate( void );\r
+\r
/*-----------------------------------------------------------*/\r
\r
int main( void )\r
\r
static void prvSetupHardware( void )\r
{\r
+ SystemCoreClockUpdate();\r
vParTestInitialise();\r
}\r
/*-----------------------------------------------------------*/\r
+++ /dev/null
-;*****************************************************************************/\r
-; * @file startup_XMC1300.s\r
-; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
-; * Infineon XMC1300 Device Series\r
-; * @version V1.00\r
-; * @date 21. Jan. 2013\r
-; *\r
-; * @note\r
-; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
-; *\r
-; * @par\r
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
-; * processor based microcontrollers. This file can be freely distributed\r
-; * within development tools that are supporting such ARM based processors.\r
-; *\r
-; * @par\r
-; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
-; *\r
-; ******************************************************************************/\r
-\r
-\r
-;* <<< Use Configuration Wizard in Context Menu >>>\r
-\r
-; Amount of memory (in bytes) allocated for Stack\r
-; Tailor this value to your application needs\r
-; <h> Stack Configuration\r
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-; </h>\r
-\r
-Stack_Size EQU 0x00000400\r
-\r
- AREA STACK, NOINIT, READWRITE, ALIGN=3\r
-Stack_Mem SPACE Stack_Size\r
-__initial_sp\r
-\r
-\r
-; <h> Heap Configuration\r
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-; </h>\r
-\r
-Heap_Size EQU 0x00000200\r
-\r
- AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
-__heap_base\r
-Heap_Mem SPACE Heap_Size\r
-__heap_limit\r
-\r
-; <h> Clock system handling by SSW\r
-; <h> CLK_VAL1 Configuration\r
-; <o0.0..7> FDIV Fractional Divider Selection\r
-; <o0.8..15> IDIV Divider Selection\r
-; <0=> Divider is bypassed\r
-; <1=> MCLK = 32 MHz\r
-; <2=> MCLK = 16 MHz\r
-; <3=> MCLK = 10.67 MHz\r
-; <4=> MCLK = 8 MHz\r
-; <254=> MCLK = 126 kHz\r
-; <255=> MCLK = 125.5 kHz\r
-; <o0.16> PCLKSEL PCLK Clock Select\r
-; <0=> PCLK = MCLK\r
-; <1=> PCLK = 2 x MCLK\r
-; <o0.17..19> RTCCLKSEL RTC Clock Select\r
-; <0=> 32.768kHz standby clock\r
-; <1=> 32.768kHz external clock from ERU0.IOUT0\r
-; <2=> 32.768kHz external clock from ACMP0.OUT\r
-; <3=> 32.768kHz external clock from ACMP1.OUT\r
-; <4=> 32.768kHz external clock from ACMP2.OUT\r
-; <5=> Reserved\r
-; <6=> Reserved\r
-; <7=> Reserved\r
-; <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]\r
-; </h>\r
-CLK_VAL1_Val EQU 0x80000000 ; 0xF0000000\r
-\r
-; <h> CLK_VAL2 Configuration\r
-; <o0.0> disable VADC and SHS Gating\r
-; <o0.1> disable CCU80 Gating\r
-; <o0.2> disable CCU40 Gating\r
-; <o0.3> disable USIC0 Gating\r
-; <o0.4> disable BCCU0 Gating\r
-; <o0.5> disable LEDTS0 Gating\r
-; <o0.6> disable LEDTS1 Gating\r
-; <o0.7> disable POSIF0 Gating\r
-; <o0.8> disable MATH Gating\r
-; <o0.9> disable WDT Gating\r
-; <o0.10> disable RTC Gating\r
-; <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]\r
-; </h>\r
-CLK_VAL2_Val EQU 0x80000000 ; 0xF0000000\r
-; </h>\r
-\r
- PRESERVE8\r
- THUMB\r
-\r
-;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
-;* Vector Table Mapped to Address 0 at Reset\r
- AREA RESET, DATA, READONLY\r
- EXPORT __Vectors\r
- EXPORT __Vectors_End\r
- EXPORT __Vectors_Size\r
-\r
-\r
-\r
-__Vectors\r
- DCD __initial_sp ;* Top of Stack\r
- DCD Reset_Handler ;* Reset Handler\r
- DCD 0 ;* Not used\r
- DCD 0 ;* Not Used\r
- DCD CLK_VAL1_Val ;* CLK_VAL1\r
- DCD CLK_VAL2_Val ;* CLK_VAL2\r
-__Vectors_End\r
-\r
-__Vectors_Size EQU __Vectors_End - __Vectors\r
-\r
-;* ================== END OF VECTOR TABLE DEFINITION ======================== */\r
-\r
-\r
-;* ================== START OF VECTOR ROUTINES ============================== */\r
- AREA |.text|, CODE, READONLY\r
-\r
-;* Reset Handler\r
-Reset_Handler PROC\r
- EXPORT Reset_Handler [WEAK]\r
- IMPORT __main\r
- IMPORT SystemInit\r
-\r
- ;* C routines are likely to be called. Setup the stack now\r
- LDR R0, =__initial_sp\r
- MOV SP, R0\r
-\r
- ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"\r
- ; The real veneers will be copied later from the scatter loader before reaching main.\r
- ; This init code should handle an exception before the real veneers are copied.\r
-SRAM_BASE EQU 0x20000000\r
-VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B .\r
-\r
- LDR R1, =SRAM_BASE\r
- LDR R2, =VENEER_INIT_CODE \r
- MOVS R0, #48 ; Veneer 0..47\r
-Init_Veneers\r
- STR R2, [R1]\r
- ADDS R1, #4\r
- SUBS R0, R0, #1\r
- BNE Init_Veneers\r
-\r
-\r
- LDR R0, =SystemInit\r
- BLX R0\r
-\r
-\r
- ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
- ; weakly defined here though for a potential override.\r
-\r
- LDR R0, = SystemInit_DAVE3\r
- BLX R0\r
-\r
-\r
- LDR R0, =__main\r
- BX R0\r
-\r
-\r
- ALIGN\r
- ENDP\r
-\r
-;* ========================================================================== */\r
-\r
-\r
-\r
-;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */\r
-;* Default exception Handlers - Users may override this default functionality\r
-\r
-NMI_Handler PROC\r
- EXPORT NMI_Handler [WEAK]\r
- B .\r
- ENDP\r
-HardFault_Handler\\r
- PROC\r
- EXPORT HardFault_Handler [WEAK]\r
- B .\r
- ENDP\r
-SVC_Handler\\r
- PROC\r
- EXPORT SVC_Handler [WEAK]\r
- B .\r
- ENDP\r
-PendSV_Handler\\r
- PROC\r
- EXPORT PendSV_Handler [WEAK]\r
- B .\r
- ENDP\r
-SysTick_Handler\\r
- PROC\r
- EXPORT SysTick_Handler [WEAK]\r
- B .\r
- ENDP\r
-\r
-;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
-\r
-\r
-;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
-;* IRQ Handlers\r
-\r
-Default_Handler PROC\r
- EXPORT SCU_0_IRQHandler [WEAK]\r
- EXPORT SCU_1_IRQHandler [WEAK]\r
- EXPORT SCU_2_IRQHandler [WEAK]\r
- EXPORT ERU0_0_IRQHandler [WEAK]\r
- EXPORT ERU0_1_IRQHandler [WEAK]\r
- EXPORT ERU0_2_IRQHandler [WEAK]\r
- EXPORT ERU0_3_IRQHandler [WEAK]\r
- EXPORT MATH0_0_IRQHandler [WEAK]\r
- EXPORT USIC0_0_IRQHandler [WEAK]\r
- EXPORT USIC0_1_IRQHandler [WEAK]\r
- EXPORT USIC0_2_IRQHandler [WEAK]\r
- EXPORT USIC0_3_IRQHandler [WEAK]\r
- EXPORT USIC0_4_IRQHandler [WEAK]\r
- EXPORT USIC0_5_IRQHandler [WEAK]\r
- EXPORT VADC0_C0_0_IRQHandler [WEAK]\r
- EXPORT VADC0_C0_1_IRQHandler [WEAK]\r
- EXPORT VADC0_G0_0_IRQHandler [WEAK]\r
- EXPORT VADC0_G0_1_IRQHandler [WEAK]\r
- EXPORT VADC0_G1_0_IRQHandler [WEAK]\r
- EXPORT VADC0_G1_1_IRQHandler [WEAK]\r
- EXPORT CCU40_0_IRQHandler [WEAK]\r
- EXPORT CCU40_1_IRQHandler [WEAK]\r
- EXPORT CCU40_2_IRQHandler [WEAK]\r
- EXPORT CCU40_3_IRQHandler [WEAK]\r
- EXPORT CCU80_0_IRQHandler [WEAK]\r
- EXPORT CCU80_1_IRQHandler [WEAK]\r
- EXPORT POSIF0_0_IRQHandler [WEAK]\r
- EXPORT POSIF0_1_IRQHandler [WEAK]\r
- EXPORT LEDTS0_0_IRQHandler [WEAK]\r
- EXPORT LEDTS1_0_IRQHandler [WEAK]\r
- EXPORT BCCU0_0_IRQHandler [WEAK]\r
-\r
-SCU_0_IRQHandler\r
-SCU_1_IRQHandler\r
-SCU_2_IRQHandler\r
-ERU0_0_IRQHandler\r
-ERU0_1_IRQHandler\r
-ERU0_2_IRQHandler\r
-ERU0_3_IRQHandler\r
-MATH0_0_IRQHandler\r
-USIC0_0_IRQHandler\r
-USIC0_1_IRQHandler\r
-USIC0_2_IRQHandler\r
-USIC0_3_IRQHandler\r
-USIC0_4_IRQHandler\r
-USIC0_5_IRQHandler\r
-VADC0_C0_0_IRQHandler\r
-VADC0_C0_1_IRQHandler\r
-VADC0_G0_0_IRQHandler\r
-VADC0_G0_1_IRQHandler\r
-VADC0_G1_0_IRQHandler\r
-VADC0_G1_1_IRQHandler\r
-CCU40_0_IRQHandler\r
-CCU40_1_IRQHandler\r
-CCU40_2_IRQHandler\r
-CCU40_3_IRQHandler\r
-CCU80_0_IRQHandler\r
-CCU80_1_IRQHandler\r
-POSIF0_0_IRQHandler\r
-POSIF0_1_IRQHandler\r
-LEDTS0_0_IRQHandler\r
-LEDTS1_0_IRQHandler\r
-BCCU0_0_IRQHandler\r
-\r
- B .\r
-\r
- ENDP\r
-\r
- ALIGN\r
-\r
-;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
-\r
-;* Definition of the default weak SystemInit_DAVE3 function.\r
-;* This function will be called by the CMSIS SystemInit function.\r
-;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
-;* which will overule this weak definition\r
-SystemInit_DAVE3 PROC\r
- EXPORT SystemInit_DAVE3 [WEAK]\r
- NOP\r
- BX LR\r
- ENDP\r
-\r
-;* Definition of the default weak DAVE3 function for clock App usage.\r
-;* AllowClkInitByStartup Handler */\r
-AllowClkInitByStartup PROC\r
- EXPORT AllowClkInitByStartup [WEAK]\r
- MOVS R0,#1\r
- BX LR\r
- ENDP\r
-\r
-\r
-;*******************************************************************************\r
-; User Stack and Heap initialization\r
-;*******************************************************************************\r
- IF :DEF:__MICROLIB\r
-\r
- EXPORT __initial_sp\r
- EXPORT __heap_base\r
- EXPORT __heap_limit\r
-\r
- ELSE\r
-\r
- IMPORT __use_two_region_memory\r
- EXPORT __user_initial_stackheap\r
-\r
-__user_initial_stackheap\r
-\r
- LDR R0, = Heap_Mem\r
- LDR R1, =(Stack_Mem + Stack_Size)\r
- LDR R2, = (Heap_Mem + Heap_Size)\r
- LDR R3, = Stack_Mem\r
- BX LR\r
-\r
- ALIGN\r
-\r
- ENDIF\r
-\r
-\r
-;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */\r
-; Veneers are located to fix SRAM Address 0x2000'0000\r
- AREA |.ARM.__at_0x20000000|, CODE, READWRITE\r
-\r
-; Each Veneer has exactly a lengs of 4 Byte\r
-\r
- MACRO\r
- STAYHERE $IrqNumber\r
- LDR R0, =$IrqNumber\r
- B .\r
- MEND\r
-\r
- MACRO\r
- JUMPTO $Handler\r
- LDR R0, =$Handler\r
- BX R0\r
- MEND\r
-\r
- STAYHERE 0x0 ;* Reserved\r
- STAYHERE 0x1 ;* Reserved \r
- STAYHERE 0x2 ;* Reserved \r
- JUMPTO HardFault_Handler ;* HardFault Veneer \r
- STAYHERE 0x4 ;* Reserved \r
- STAYHERE 0x5 ;* Reserved \r
- STAYHERE 0x6 ;* Reserved \r
- STAYHERE 0x7 ;* Reserved \r
- STAYHERE 0x8 ;* Reserved \r
- STAYHERE 0x9 ;* Reserved \r
- STAYHERE 0xA ;* Reserved\r
- JUMPTO SVC_Handler ;* SVC Veneer \r
- STAYHERE 0xC ;* Reserved\r
- STAYHERE 0xD ;* Reserved\r
- JUMPTO PendSV_Handler ;* PendSV Veneer \r
- JUMPTO SysTick_Handler ;* SysTick Veneer \r
- JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer \r
- JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer \r
- JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer \r
- JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer \r
- JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer \r
- JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer \r
- JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer \r
- JUMPTO MATH0_0_IRQHandler ;* SCU_7 Veneer \r
- STAYHERE 0x18 ;* Reserved\r
- JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer \r
- JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer \r
- JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer \r
- JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer \r
- JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer \r
- JUMPTO LEDTS0_0_IRQHandler ;* USIC0_5 Veneer \r
- JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer \r
- JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer \r
- JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer \r
- JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer \r
- JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer \r
- JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer \r
- JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer \r
- JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer \r
- JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer \r
- JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer \r
- JUMPTO CCU80_0_IRQHandler ;* CCU80_0 Veneer \r
- JUMPTO CCU80_1_IRQHandler ;* CCU80_1 Veneer \r
- JUMPTO POSIF0_0_IRQHandler ;* POSIF0_0 Veneer \r
- JUMPTO POSIF0_1_IRQHandler ;* POSIF0_1 Veneer \r
- JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer \r
- JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer \r
- JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer \r
-\r
- ALIGN\r
-\r
-;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */\r
-\r
- END\r
+++ /dev/null
-/******************************************************************************\r
- * @file system_XMC1300.c\r
- * @brief Device specific initialization for the XMC1300-Series according \r
- * to CMSIS\r
- * @version V1.2\r
- * @date 13 Dec 2012\r
- *\r
- * @note\r
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with \r
- * Infineon\92s microcontrollers.\r
- * \r
- * This file can be freely distributed within development tools that are \r
- * supporting such microcontrollers.\r
- * \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-/*\r
- * ************************** Change history *********************************\r
- * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_\r
- */\r
-\r
-#include "system_XMC1300.h"\r
-#include <XMC1300.h>\r
-\r
-/*---------------------------------------------------------------------------\r
- Extern definitions \r
- *--------------------------------------------------------------------------*/\r
-extern uint32_t AllowClkInitByStartup(void);\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Global defines\r
- *----------------------------------------------------------------------------*/\r
-#define DCO_DCLK 64000000UL\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock;\r
-\r
-\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit(void)\r
-{ \r
- /*\r
- * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
- * Clock app.\r
- */ \r
- if(AllowClkInitByStartup()){ \r
- /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
- /* ====== Default configuration ======= */\r
- /*\r
- * MCLK = DCO_DCLK\r
- * PCLK = MCLK\r
- * RTC CLK = Standby clock\r
- */\r
- }\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate(void)\r
-{\r
- uint32_t IDIV, CLKCR;\r
-\r
- CLKCR = SCU_CLOCK -> CLKCR;\r
- \r
- IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
- \r
- if(IDIV)\r
- {\r
- SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
- }\r
- else\r
- {\r
- /* Divider bypassed */\r
- SystemCoreClock = DCO_DCLK;\r
- }\r
-}\r
-\r
projects / freertos / commitdiff