--- /dev/null
+<?xml version="1.0" encoding="ASCII"?>\r
+<com.renesas.linkersection.model:SectionContainer xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:com.renesas.linkersection.model="http:///LinkerSection.ecore" targets="GNU_RX">\r
+ <definedRegionsList name="RAM">\r
+ <startAddress xsi:type="com.renesas.linkersection.model:FixedAddress"/>\r
+ <endAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="20479"/>\r
+ </definedRegionsList>\r
+ <definedRegionsList name="ROM">\r
+ <startAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294836224"/>\r
+ <endAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294967295"/>\r
+ </definedRegionsList>\r
+ <sections name=".fvectors" isKeep="true">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294967248"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".fvectors"/>\r
+ </sections>\r
+ <sections name=".option_bytes" isKeep="true">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294967176"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".option_bytes"/>\r
+ </sections>\r
+ <sections name=".endian_bytes" isKeep="true">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294967168"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".endian_bytes"/>\r
+ </sections>\r
+ <sections name=".text">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294836224"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".text"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".text.*"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="P"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="etext"/>\r
+ </sections>\r
+ <sections name=".rvectors">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.3"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_rvectors_start"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".rvectors"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_rvectors_end"/>\r
+ </sections>\r
+ <sections name=".init">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.4"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".init"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__preinit_array_start"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".preinit_array"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__preinit_array_end"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__init_array_start = (. + 3) & ~ 3"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".init_array"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="SORT(.init_array.*)"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__init_array_end"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__fini_array_start"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".fini_array"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="SORT(.fini_array.*)"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__fini_array_end"/>\r
+ </sections>\r
+ <sections name=".fini">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.5"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".fini"/>\r
+ </sections>\r
+ <sections name=".got">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.6"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".got"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".got.plt"/>\r
+ </sections>\r
+ <sections name=".rodata">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.7"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".rodata"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".rodata.*"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="C_1"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="C_2"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="C"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_erodata"/>\r
+ </sections>\r
+ <sections name=".eh_frame_hdr">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.8"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".eh_frame_hdr"/>\r
+ </sections>\r
+ <sections name=".eh_frame">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.9"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".eh_frame"/>\r
+ </sections>\r
+ <sections name=".jcr">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.10"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".jcr"/>\r
+ </sections>\r
+ <sections name=".tors">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.11"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__CTOR_LIST__"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="___ctors"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".ctors"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="___ctors_end"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__CTOR_END__"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__DTOR_LIST__"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="___dtors"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".dtors"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="___dtors_end"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__DTOR_END__"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_mdata"/>\r
+ </sections>\r
+ <sections name=".data">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="512"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_data"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".data"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".data.*"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="D"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="D_1"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="D_2"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_edata"/>\r
+ <reservedMemAddress xsi:type="com.renesas.linkersection.model:ReferencedLabelAddress" label="//@sections.12/@contents.10"/>\r
+ </sections>\r
+ <sections name=".gcc_exc">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.13"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".gcc_exc"/>\r
+ </sections>\r
+ <sections name=".bss">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.14"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_bss"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".bss"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".bss.**"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="COMMON"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="B"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="B_1"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="B_2"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_ebss"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_end"/>\r
+ </sections>\r
+ <sections name=".ustack">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="511"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_ustack"/>\r
+ </sections>\r
+ <sections name=".istack">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="507"/>\r
+ <contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_istack"/>\r
+ </sections>\r
+</com.renesas.linkersection.model:SectionContainer>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?>\r
+\r
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+ <storageModule moduleId="org.eclipse.cdt.core.settings">\r
+ <cconfiguration id="%com.renesas.cdt.rx.hardwaredebug.win32.configuration.Id.1038200195">\r
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="%com.renesas.cdt.rx.hardwaredebug.win32.configuration.Id.1038200195" moduleId="org.eclipse.cdt.core.settings" name="HardwareDebug">\r
+ <externalSettings/>\r
+ <extensions>\r
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+ <extension id="org.eclipse.cdt.core.PE" point="org.eclipse.cdt.core.BinaryParser"/>\r
+ <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ </extensions>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+ <configuration artifactName="RTOSDemo_GCC" buildArtefactType="com.renesas.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.renesas.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf *.lst *.lis *.lpp *.map" description="" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.VCErrorParser" id="%com.renesas.cdt.rx.hardwaredebug.win32.configuration.Id.1038200195" name="HardwareDebug" parent="%com.renesas.cdt.rx.hardwaredebug.win32.configuration.Id">\r
+ <folderInfo id="%com.renesas.cdt.rx.hardwaredebug.win32.configuration.Id.1038200195." name="/" resourcePath="">\r
+ <toolChain id="%com.renesas.cdt.rx.hardwaredebug.win32.toolChain.Id.1200713553" name="KPIT GNURX-ELF Toolchain" superClass="%com.renesas.cdt.rx.hardwaredebug.win32.toolChain.Id">\r
+ <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.PE" id="com.renesas.cdt.rx.hardwaredebug.win32.targetPlatform.Id.2026223031" osList="win32" superClass="com.renesas.cdt.rx.hardwaredebug.win32.targetPlatform.Id"/>\r
+ <builder buildPath="${workspace_loc:/RTOSDemo_GCC/HardwareDebug}" id="com.renesas.cdt.rx.hardwaredebug.win32.builder.Id.53784355" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU Make Builder" superClass="com.renesas.cdt.rx.hardwaredebug.win32.builder.Id"/>\r
+ <tool command="rx-elf-libgen" id="com.renesas.cdt.rx.hardwaredebug.win32.tool.libgen.Id.454501696" name="Library Generator" superClass="com.renesas.cdt.rx.hardwaredebug.win32.tool.libgen.Id">\r
+ <option id="com.renesas.cdt.core.LibraryGenerator.option.stdlib.1751934062" name="stdlib.h : Performs C program statndard processing such as storage area management" superClass="com.renesas.cdt.core.LibraryGenerator.option.stdlib" value="true" valueType="boolean"/>\r
+ <option id="com.renesas.cdt.core.LibraryGenerator.option.string.223218455" name="string.h : Performs string comparison, copying " superClass="com.renesas.cdt.core.LibraryGenerator.option.string" value="true" valueType="boolean"/>\r
+ <option id="com.renesas.cdt.core.LibraryGenerator.option.selectLibrary.850493556" name="Select library" superClass="com.renesas.cdt.core.LibraryGenerator.option.selectLibrary" value="Optimized" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.core.LibraryGenerator.option.libraryType.1978494303" name="Library type" superClass="com.renesas.cdt.core.LibraryGenerator.option.libraryType" value="Project-Built" valueType="enumerated"/>\r
+ </tool>\r
+ <tool id="com.renesas.cdt.rx.hardwaredebug.win32.tool.compiler.Id.1144539497" name="Compiler" superClass="com.renesas.cdt.rx.hardwaredebug.win32.tool.compiler.Id">\r
+ <option id="com.renesas.cdt.rx.HardwareDebug.Compiler.option.dataEndian.769042703" name="Data Endian" superClass="com.renesas.cdt.rx.HardwareDebug.Compiler.option.dataEndian" value="Little-endian data" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType.2018307272" name="CPU type" superClass="com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType" value="RX100" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.core.Compiler.option.includeFileDir.316833280" name="Include file directories" superClass="com.renesas.cdt.core.Compiler.option.includeFileDir" valueType="includePath">\r
+ <listOptionValue builtIn="false" value=""${TCINSTALL}\rx-elf\optlibinc""/>\r
+ <listOptionValue builtIn="false" value=""${TCINSTALL}\rx-elf\include""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Common_Demo_Tasks/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/FreeRTOS_Source/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/FreeRTOS_Source/portable/GCC/RX100}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Renesas_Files/r_bsp}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Renesas_Files/r_switches}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Renesas_Files/r_switches/src}""/>\r
+ </option>\r
+ <option id="com.renesas.cdt.core.Compiler.option.CPUSeries.2032738140" name="Cpu Series" superClass="com.renesas.cdt.core.Compiler.option.CPUSeries" value="RX111" valueType="string"/>\r
+ <option id="com.renesas.cdt.rx.HardwareDebug.Compiler.option.debugLevel.1225535928" name="Debug level" superClass="com.renesas.cdt.rx.HardwareDebug.Compiler.option.debugLevel" value="com.renesas.cdt.rx.HardwareDebug.Compiler.option.debugLevel.none" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rx.HardwareDebug.Compiler.option.optimizationLevel.1088290642" name="Optimization level" superClass="com.renesas.cdt.rx.HardwareDebug.Compiler.option.optimizationLevel" value="com.renesas.cdt.rx.HardwareDebug.Compiler.option.optimizationLevel.speedCodeSize" valueType="enumerated"/>\r
+ <inputType id="%Base.Compiler.C.InputType.Id.962451183" name="C Input" superClass="%Base.Compiler.C.InputType.Id"/>\r
+ </tool>\r
+ <tool id="com.renesas.cdt.rx.hardwaredebug.win32.tool.assembler.Id.1642705589" name="Assembler" superClass="com.renesas.cdt.rx.hardwaredebug.win32.tool.assembler.Id">\r
+ <option id="com.renesas.cdt.rx.HardwareDebug.Assembler.option.dataEndian.67883143" name="Data Endian" superClass="com.renesas.cdt.rx.HardwareDebug.Assembler.option.dataEndian" value="Little-endian data" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.core.Assembler.option.includeFileDirectories.434361507" name="Include file directories" superClass="com.renesas.cdt.core.Assembler.option.includeFileDirectories" valueType="includePath">\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}\src""/>\r
+ </option>\r
+ <inputType id="%Base.Assembler.inputType.Id.2097860459" name="Assembler InputType" superClass="%Base.Assembler.inputType.Id"/>\r
+ </tool>\r
+ <tool command="rx-elf-ld" commandLinePattern="${COMMAND} ${OUTPUT_FLAG}${OUTPUT_PREFIX} ${OUTPUT}${INPUTS} ${FLAGS}" id="com.renesas.cdt.rx.hardwaredebug.win32.tool.linker.Id.1295703269" name="Linker" superClass="com.renesas.cdt.rx.hardwaredebug.win32.tool.linker.Id">\r
+ <option id="com.renesas.cdt.rx.HardwareDebug.Linker.option.dataEndian.1400369130" name="Data Endian" superClass="com.renesas.cdt.rx.HardwareDebug.Linker.option.dataEndian" value="Little-endian data" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveSearchDirectories.770090581" name="Archive search directories" superClass="com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveSearchDirectories" valueType="stringList">\r
+ <listOptionValue builtIn="false" value=""${CONFIGDIR}""/>\r
+ <listOptionValue builtIn="false" value=""${TCINSTALL}\lib\gcc\rx-elf\\${GCC_VERSION}""/>\r
+ </option>\r
+ <option id="com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveLibraryFiles.1867799274" name="Archive (library) files" superClass="com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveLibraryFiles" valueType="stringList">\r
+ <listOptionValue builtIn="false" value="${ProjName}"/>\r
+ <listOptionValue builtIn="false" value="gcc"/>\r
+ </option>\r
+ <option id="com.renesas.cdt.core.Linker.option.userDefinedOptions.1094627795" name="User defined options" superClass="com.renesas.cdt.core.Linker.option.userDefinedOptions" valueType="stringList">\r
+ <listOptionValue builtIn="false" value="-e_PowerON_Reset"/>\r
+ </option>\r
+ </tool>\r
+ <tool id="com.renesas.cdt.rx.hardwaredebug.win32.tool.objcopy.Id.1559563032" name="Objcopy" superClass="com.renesas.cdt.rx.hardwaredebug.win32.tool.objcopy.Id"/>\r
+ </toolChain>\r
+ </folderInfo>\r
+ <sourceEntries>\r
+ <entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>\r
+ </sourceEntries>\r
+ </configuration>\r
+ </storageModule>\r
+ <storageModule moduleId="scannerConfiguration">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+ <profile id="com.iar.cdt.v850.scanner.IAR_V850_PerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="false" filePath=""/>\r
+ <parser enabled="false"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="com.iar.cdt.v850.toolchain.scannerInfoProvider1">\r
+ <runAction arguments="" command="" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="com.iar.cdt.rl78.scanner.IAR_RL78_PerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="false" filePath=""/>\r
+ <parser enabled="false"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="com.iar.cdt.rl78.toolchain.scannerInfoProviderRL78">\r
+ <runAction arguments="" command="" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="com.iar.cdt.rx.scanner.IAR_RX_PerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="false" filePath=""/>\r
+ <parser enabled="false"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="com.iar.cdt.rx.toolchain.scannerInfoProviderRX">\r
+ <runAction arguments="" command="" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="makefileGenerator">\r
+ <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+ <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>\r
+ <storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>\r
+ </cconfiguration>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+ <project id="RTOSDemo_GCC.com.renesas.cdt.rx.projectType.Id.1714941242" name="GNURX" projectType="com.renesas.cdt.rx.projectType.Id"/>\r
+ </storageModule>\r
+</cproject>\r
--- /dev/null
+TOOL_CHAIN=KPIT GNURX-ELF Toolchain
+VERSION=v12.01
+TC_INSTALL=C:\devtools\Renesas\e2studio\GNURXV~1.01-\rx-elf\
+GCC_STRING=4.6-GNURX_v12.01
+VERISON_IDE=3.06.02.080
+E2STUDIO_VERSION=1.1.1.7
\ No newline at end of file
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>RTOSDemo_GCC</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>com.renesas.cdt.core.genmakebuilder</name>\r
+ <arguments>\r
+ <dictionary>\r
+ <key>?name?</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.append_environment</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildArguments</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+ <value>make</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+ <value>${workspace_loc:/RTOSDemo_GCC/HardwareDebug}</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
+ <value>clean</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.contents</key>\r
+ <value>org.eclipse.cdt.make.core.configurationIds</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <triggers>full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>com.renesas.cdt.core.kpitcnature</nature>\r
+ <nature>com.renesas.cdt.core.kpitccnature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ </natures>\r
+</projectDescription>\r
--- /dev/null
+#Mon Mar 11 11:21:23 GMT 2013\r
+Library\ Generator\ Command=rx-elf-libgen\r
+com.renesas.cdt.core.Assembler.option.includeFileDirectories="${workspace_loc\:/${ProjName}}\\src";\r
+com.renesas.cdt.core.Compiler.option.includeFileDir.316833280="${TCINSTALL}\\rx-elf\\optlibinc";\r
+com.renesas.cdt.core.LibraryGenerator.option.ctype=true\r
+com.renesas.cdt.core.LibraryGenerator.option.libraryType=Project-Built\r
+com.renesas.cdt.core.LibraryGenerator.option.math=false\r
+com.renesas.cdt.core.LibraryGenerator.option.selectLibrary=Optimized\r
+com.renesas.cdt.core.LibraryGenerator.option.stdio=false\r
+com.renesas.cdt.core.LibraryGenerator.option.stdlib=true\r
+com.renesas.cdt.core.LibraryGenerator.option.string=true\r
+com.renesas.cdt.core.Linker.option.userDefinedOptions=[Ljava.lang.String;@13ec853\r
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType=RX100\r
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType.2018307272=RX100\r
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.dataEndian=Little-endian data\r
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.disableFPUInstructions=false\r
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.genCodeForRX610=false\r
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.generateRXas100output=false\r
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.make64bitDouble=false\r
+com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveLibraryFiles=${ProjName};gcc;\r
+com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveSearchDirectories.770090581="${CONFIGDIR}";"${TCINSTALL}\\lib\\gcc\\rx-elf\\\\${GCC_VERSION}";\r
+eclipse.preferences.version=1\r
--- /dev/null
+REM This file should be executed from the command line prior to the first\r
+REM build. It will be necessary to refresh the Eclipse project once the\r
+REM .bat file has been executed (normally just press F5 to refresh).\r
+\r
+REM Copies all the required files from their location within the standard\r
+REM FreeRTOS directory structure to under the Eclipse project directory.\r
+REM This permits the Eclipse project to be used in 'managed' mode and without\r
+REM having to setup any linked resources.\r
+\r
+REM Standard paths\r
+SET FREERTOS_SOURCE=..\..\Source\r
+SET COMMON_SOURCE=..\Common\minimal\r
+SET COMMON_INCLUDE=..\Common\include\r
+\r
+REM Have the files already been copied?\r
+IF EXIST RTOSDemo\FreeRTOS_Source Goto END\r
+\r
+ REM Create the required directory structure.\r
+ MD RTOSDemo\FreeRTOS_Source\r
+ MD RTOSDemo\FreeRTOS_Source\include\r
+ MD RTOSDemo\FreeRTOS_Source\portable\r
+ MD RTOSDemo\FreeRTOS_Source\portable\MemMang\r
+ MD RTOSDemo\FreeRTOS_Source\portable\GCC\r
+ MD RTOSDemo\FreeRTOS_Source\portable\GCC\RX100\r
+ MD RTOSDemo\Common_Demo_Tasks\r
+ MD RTOSDemo\Common_Demo_Tasks\include\r
+\r
+ REM Copy the core kernel files into the project directory\r
+ copy %FREERTOS_SOURCE%\tasks.c RTOSDemo\FreeRTOS_Source\r
+ copy %FREERTOS_SOURCE%\queue.c RTOSDemo\FreeRTOS_Source\r
+ copy %FREERTOS_SOURCE%\list.c RTOSDemo\FreeRTOS_Source\r
+ copy %FREERTOS_SOURCE%\timers.c RTOSDemo\FreeRTOS_Source\r
+\r
+ REM Copy the common header files into the project directory\r
+ copy %FREERTOS_SOURCE%\include\*.* RTOSDemo\FreeRTOS_Source\include\r
+\r
+ REM Copy the portable layer files into the project directory\r
+ copy %FREERTOS_SOURCE%\portable\GCC\RX100\*.* RTOSDemo\FreeRTOS_Source\portable\GCC\RX100\r
+\r
+ REM Copy the memory allocation files into the project directory\r
+ copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c RTOSDemo\FreeRTOS_Source\portable\MemMang\r
+\r
+ REM Copy the files that define the common demo tasks.\r
+ copy %COMMON_SOURCE%\death.c RTOSDemo\Common_Demo_Tasks\r
+ copy %COMMON_SOURCE%\blocktim.c RTOSDemo\Common_Demo_Tasks\r
+ copy %COMMON_SOURCE%\GenQTest.c RTOSDemo\Common_Demo_Tasks\r
+ copy %COMMON_SOURCE%\recmutex.c RTOSDemo\Common_Demo_Tasks\r
+\r
+ REM Copy the common demo file headers.\r
+ copy %COMMON_INCLUDE%\*.h RTOSDemo\Common_Demo_Tasks\include\r
+\r
+: END\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+\r
+/*\r
+ * The following #error directive is to remind users that a batch file must be\r
+ * executed prior to this project being built. The batch file *cannot* be\r
+ * executed from within the IDE! Once it has been executed, re-open or refresh\r
+ * the Eclipse project and remove the #error line below.\r
+ */\r
+//#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* Hardware specifics. */\r
+#include "platform.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* DEMO SPECIFIC SETTING:\r
+ * Set configCREATE_LOW_POWER_DEMO to one to run the low power demo with tick\r
+ * suppression, or 0 to run the more comprehensive test and demo application.\r
+ * If configCREATE_LOW_POWER_DEMO is set to 1 then main() calls main_low_power().\r
+ * If configCREATE_LOW_POWER_DEMO is set to 0 then main() calls main_full().\r
+ */\r
+#define configCREATE_LOW_POWER_DEMO 1\r
+\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_TICKLESS_IDLE configCREATE_LOW_POWER_DEMO\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ICLK_HZ ) /* Set in mcu_info.h. */\r
+#define configPERIPHERAL_CLOCK_HZ ( PCLKB_HZ ) /* Set in muc_info.h. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 9 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions - only included when the demo is configured to\r
+build the full demo (as opposed to the low power demo). */\r
+#if configCREATE_LOW_POWER_DEMO == 1\r
+ #define configUSE_TIMERS 0\r
+#else\r
+ #define configUSE_TIMERS 1\r
+ #define configTIMER_TASK_PRIORITY ( 3 )\r
+ #define configTIMER_QUEUE_LENGTH 5\r
+ #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+#endif /* configCREATE_LOW_POWER_DEMO */\r
+\r
+/* The interrupt priority used by the kernel itself for the tick interrupt and\r
+the pended interrupt. This would normally be the lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+\r
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
+Interrupts that use a priority above this will not be effected by anything the\r
+kernel is doing but must not make any use of FreeRTOS functionality.\r
+interrupts that use a priority at or below configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+can make use of FreeRTOS API function but *only* functions that end in\r
+"FromISR()". */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+\r
+extern void vAssertCalled( void );\r
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled();\r
+\r
+/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros\r
+allow the application writer to add additional code before and after the MCU is\r
+placed into the low power state respectively. The implementations provided in\r
+this demo can be extended to save even more power - for example the analog\r
+input used by the low power demo could be switched off in the pre-sleep macro\r
+and back on again in the post sleep macro. */\r
+void vPreSleepProcessing( unsigned long xExpectedIdleTime );\r
+void vPostSleepProcessing( unsigned long xExpectedIdleTime );\r
+#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime );\r
+#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime );\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+#define partestNUM_LEDS ( 4 )\r
+\r
+long lParTestGetLEDState( unsigned long ulLED );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Port pin configuration is done by the low level set up prior to this\r
+ function being called. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLED, signed long xValue )\r
+{\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ if( xValue != 0 )\r
+ {\r
+ /* Turn the LED on. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0: LED0 = LED_ON;\r
+ break;\r
+ case 1: LED1 = LED_ON;\r
+ break;\r
+ case 2: LED2 = LED_ON;\r
+ break;\r
+ case 3: LED3 = LED_ON;\r
+ break;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LED off. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0: LED0 = LED_OFF;\r
+ break;\r
+ case 1: LED1 = LED_OFF;\r
+ break;\r
+ case 2: LED2 = LED_OFF;\r
+ break;\r
+ case 3: LED3 = LED_OFF;\r
+ break;\r
+ }\r
+\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( lParTestGetLEDState( ulLED ) != 0x00 )\r
+ {\r
+ vParTestSetLED( ulLED, 0 );\r
+ }\r
+ else\r
+ {\r
+ vParTestSetLED( ulLED, 1 );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+long lParTestGetLEDState( unsigned long ulLED )\r
+{\r
+long lReturn = pdTRUE;\r
+\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0 : if( LED0 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ case 1 : if( LED1 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ case 2 : if( LED2 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ case 3 : if( LED3 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : lcd.c\r
+* Device(s) : RX\r
+* H/W Platform : RSKRX111\r
+* Description : Provides variable and function declarations for lcd.c file\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Standard string manipulation & formatting functions */
+#include <stdio.h>
+#include <string.h>
+/* Defines standard variable types used in this function */
+#include <stdint.h>\r
+/* Bring in board includes. */\r
+#include "platform.h"
+/* Following header file provides function prototypes for LCD controlling functions & macro defines */
+#include "lcd.h"
+
+/***********************************************************************************************************************\r
+Private global variables and functions\r
+***********************************************************************************************************************/\r
+static void lcd_delay(volatile int32_t nsecs);\r
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value);\r
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value);\r
+
+/***********************************************************************************************************************
+* Function name : lcd_initialize
+* Description : Initializes the LCD display.
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/\r
+void lcd_initialize(void)
+{\r
+ /* Set LCD data pins as outputs. */\r
+ PORT4.PDR.BYTE |= 0x0F;\r
+\r
+ /* Set LCD control pins as outputs. */\r
+ RS_PIN_DDR = 1;\r
+ E_PIN_DDR = 1;\r
+\r
+ /* Power Up Delay for the LCD Module */\r
+ lcd_delay(50000000);\r
+\r
+ /* Display initialises in 8 bit mode - so send one write (seen as 8 bit) to set to 4 bit mode. */\r
+ lcd_nibble_write(CTRL_WR, 0x03);\r
+ lcd_delay(5000000);\r
+ lcd_nibble_write(CTRL_WR, 0x03);\r
+ lcd_delay(5000000);\r
+ lcd_nibble_write(CTRL_WR, 0x03);\r
+ lcd_delay(5000000);\r
+\r
+ /* Function Set */\r
+ lcd_nibble_write(CTRL_WR, 0x02);\r
+ lcd_delay(39000);\r
+ lcd_nibble_write(CTRL_WR, 0x02);\r
+ lcd_nibble_write(CTRL_WR, (LCD_DISPLAY_ON | LCD_TWO_LINE ));\r
+ lcd_delay(39000);\r
+\r
+ /* Display ON/OFF control */\r
+ lcd_write(CTRL_WR, LCD_CURSOR_OFF);\r
+ lcd_delay(39000);\r
+\r
+ /* Display Clear */\r
+ lcd_write(CTRL_WR, LCD_CLEAR);\r
+ lcd_delay(2000000);\r
+\r
+ /* Entry Mode Set */\r
+ lcd_write(CTRL_WR, 0x06);\r
+ lcd_delay(39000);\r
+\r
+ /* Home the cursor */\r
+ lcd_write(CTRL_WR, LCD_HOME_L1);\r
+ lcd_delay(5000000);\r
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_clear
+* Description : Clears the LCD
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_clear(void)
+{
+ /* Display Clear */\r
+ lcd_write(CTRL_WR, LCD_CLEAR);\r
+ lcd_delay(2000000);\r
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_display
+* Description : This function controls LCD writes to line 1 or 2 of the LCD.\r
+* You need to use the defines LCD_LINE1 and LCD_LINE2 in order to specify the starting position.\r
+* For example, to start at the 2nd position on line 1...\r
+* lcd_display(LCD_LINE1 + 1, "Hello")
+* Arguments : position -\r
+* Line number of display
+* string -\r
+* Pointer to null terminated string
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_display(uint8_t position, uint8_t const * string)
+{
+ /* Declare next position variable */\r
+ static uint8_t next_pos = 0xFF;\r
+\r
+ /* Set line position if needed. We don't want to if we don't need to because LCD control operations take longer\r
+ than LCD data operations. */\r
+ if (next_pos != position)\r
+ {\r
+ if(position < LCD_LINE2)\r
+ {\r
+ /* Display on Line 1 */\r
+ lcd_write(CTRL_WR, ((uint8_t)(LCD_HOME_L1 + position)));\r
+ }\r
+ else\r
+ {\r
+ /* Display on Line 2 */\r
+ lcd_write(CTRL_WR, ((uint8_t)((LCD_HOME_L2 + position) - LCD_LINE2)));\r
+ }\r
+\r
+ lcd_delay(39000);\r
+\r
+ /* set position index to known value */\r
+ next_pos = position;\r
+ }\r
+\r
+ do\r
+ {\r
+ /* Write character to LCD. */\r
+ lcd_write(DATA_WR,*string++);\r
+\r
+ lcd_delay(43000);\r
+\r
+ /* Increment position index */\r
+ next_pos++;\r
+ }\r
+ while(*string);\r
+}\r
+
+/***********************************************************************************************************************\r
+* Function name : lcd_delay\r
+* Description : Implements LCD required delays.\r
+* Arguments : nsecs -\r
+* Number of nanoseconds to delay. RX111 has max clock of 32MHz which gives a cycle time of 31.3ns.\r
+* This means that nothing under 313ns should be input. 313ns would be 10 cycles which is still\r
+* being optimistic for getting in and out of this function.\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+static void lcd_delay(volatile int32_t nsecs)\r
+{\r
+ while (0 < nsecs)\r
+ {\r
+ /* Subtract off 10 cycles per iteration. This number was obtained when using the Renesas toolchain at\r
+ optimization level 2. The number to nanoseconds to subtract off below is calculated off of the ICLK speed. */\r
+ nsecs -= (int32_t)((313.0)*(32000000.0/(float)ICLK_HZ));\r
+ }\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name : lcd_nibble_write\r
+* Description : Writes data to display. Sends command to display.\r
+* Arguments : value -\r
+* The value to write\r
+* data_or_ctrl -\r
+* Whether to write data or control.\r
+* 1 = DATA\r
+* 0 = CONTROL\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value)\r
+{\r
+ /* Set Register Select pin high for Data */\r
+ if (data_or_ctrl == DATA_WR)\r
+ {\r
+ /* Data write. */\r
+ RS_PIN = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Control write. */\r
+ RS_PIN = 0;\r
+ }\r
+\r
+ /* tsu1 delay */\r
+ lcd_delay(60);\r
+\r
+ /* EN enable chip (HIGH) */\r
+ E_PIN = 1;\r
+\r
+ /* Output the data */\r
+ PORT4.PODR.BYTE = (value & 0x0F);\r
+\r
+ /* tw delay */\r
+ lcd_delay(450);\r
+\r
+ /* Latch data by dropping E */\r
+ E_PIN = 0;\r
+\r
+ /* th2 delay */\r
+ lcd_delay(10);\r
+\r
+ /* tc delay */\r
+ lcd_delay(480);\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name : lcd_write\r
+* Description : This function controls LCD writes to line 1 or 2 of the LCD. You need to use the defines LCD_LINE1 and\r
+* LCD_LINE2 in order to specify the starting position.\r
+* For example, to start at the 2nd position on line 1...\r
+* lcd_display(LCD_LINE1 + 1, "Hello")\r
+* Arguments : value -\r
+* The value to write\r
+* data_or_ctrl -\r
+* Whether to write data or control.\r
+* 1 = DATA\r
+* 0 = CONTROL\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value)\r
+{\r
+ /* Write upper nibble first */\r
+ lcd_nibble_write(data_or_ctrl, (uint8_t)((value & 0xF0) >> 4));\r
+\r
+ /* Write lower nibble second */\r
+ lcd_nibble_write(data_or_ctrl, (uint8_t)(value & 0x0F));\r
+}\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : lcd.h\r
+* Device(s) : RX\r
+* H/W Platform : RSKRX111\r
+* Description : Provides variable and function declarations for lcd.c file\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+/* Multiple inclusion prevention macro */
+#ifndef LCD_H
+#define LCD_H
+
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/
+/* Defines standard integer variable types used in this file */
+#include <stdint.h>
+
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* RS register select pin */\r
+#define RS_PIN PORTC.PODR.BIT.B5\r
+#define RS_PIN_DDR PORTC.PDR.BIT.B5\r
+/* Display enable pin */\r
+#define E_PIN PORTB.PODR.BIT.B1\r
+#define E_PIN_DDR PORTB.PDR.BIT.B1\r
+/* Data write/read definition */\r
+#define DATA_WR 1\r
+/* Control write/read definition */\r
+#define CTRL_WR 0\r
+/* Maximum characters per line of LCD display. */\r
+#define NUMB_CHARS_PER_LINE 8\r
+/* Number of lines on the LCD display */\r
+#define MAXIMUM_LINES 2\r
+/* Character position of LCD line 1 */\r
+#define LCD_LINE1 0\r
+/* Character position of LCD line 2 */\r
+#define LCD_LINE2 16\r
+/* Clear LCD display and home cursor */\r
+#define LCD_CLEAR 0x01\r
+/* Move cursor to line 1 */\r
+#define LCD_HOME_L1 0x80\r
+/* Move cursor to line 2 */\r
+#define LCD_HOME_L2 0xC0\r
+/* Cursor auto decrement after R/W */\r
+#define CURSOR_MODE_DEC 0x04\r
+/* Cursor auto increment after R/W */\r
+#define CURSOR_MODE_INC 0x06\r
+/* Setup, 4 bits,2 lines, 5X7 */\r
+#define FUNCTION_SET 0x28\r
+/* Display ON with Cursor */\r
+#define LCD_CURSOR_ON 0x0E\r
+/* Display ON with Cursor off */\r
+#define LCD_CURSOR_OFF 0x0C\r
+/* Display on with blinking cursor */\r
+#define LCD_CURSOR_BLINK 0x0D\r
+/* Move Cursor Left One Position */\r
+#define LCD_CURSOR_LEFT 0x10\r
+/* Move Cursor Right One Position */\r
+#define LCD_CURSOR_RIGHT 0x14\r
+/* Enable LCD display */\r
+#define LCD_DISPLAY_ON 0x04\r
+/* Enable both LCD lines */\r
+#define LCD_TWO_LINE 0x08\r
+
+/***********************************************************************************************************************\r
+Exported global functions (to be accessed by other files)\r
+***********************************************************************************************************************/\r
+/* LCD initialisation function declaration */
+void lcd_initialize (void);\r
+
+/* Update display function declaration */
+void lcd_display(uint8_t position, uint8_t const * string);\r
+
+/* Clear LCD function delcaration */
+void lcd_clear (void);
+
+/* End of multiple inclusion prevention macro */
+#endif
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp.h\r
+* H/W Platform : RSKRX111\r
+* Description : Has the header files that should be included for this platform.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+#ifndef PLATFORM_BOARD_RSKRX111\r
+#define PLATFORM_BOARD_RSKRX111\r
+\r
+/* Make sure that no other platforms have already been defined. Do not touch this! */\r
+#ifdef PLATFORM_DEFINED\r
+#error "Error - Multiple platforms defined in platform.h!"\r
+#else\r
+#define PLATFORM_DEFINED\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+INCLUDE APPROPRIATE MCU AND BOARD FILES\r
+***********************************************************************************************************************/\r
+#include "r_bsp_config.h"\r
+#include ".\mcu\rx111\iodefine.h"\r
+#include ".\mcu\rx111\mcu_info.h"\r
+#include ".\board\rskrx111\rskrx111.h"\r
+#include ".\board\rskrx111\lcd.h"\r
+\r
+#endif /* PLATFORM_BOARD_RSKRX111 */\r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp_config_reference.c\r
+* Device(s) : RX111\r
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included\r
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)\r
+* is just a reference file that the user can use to make their own r_bsp_config.h file.\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description \r
+* : 07.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE\r
+#define R_BSP_CONFIG_REF_HEADER_FILE\r
+\r
+/***********************************************************************************************************************\r
+Configuration Options\r
+***********************************************************************************************************************/\r
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such \r
+ as package and memory size. \r
+ To help parse this information, the part number will be defined using multiple macros.\r
+ R 5 F 51 11 5 A D FM\r
+ | | | | | | | | | Macro Name Description\r
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch\r
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)\r
+ | | | | | | |______not used = Blank\r
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity\r
+ | | | | |___________MCU_PART_GROUP = Group name \r
+ | | | |______________MCU_PART_SERIES = Series name\r
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)\r
+ | |__________________not used = Renesas MCU\r
+ |____________________not used = Renesas semiconductor product. \r
+ */\r
+\r
+/* Package type. Set the macro definition based on values below:\r
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch\r
+ FM = 0x0 = LFQFP/64/0.50\r
+ FK = 0x1 = LQFP/64/0.80\r
+ LF = 0x2 = TFLGA/64/0.50\r
+ FL = 0x3 = LFQFP/48/0.50\r
+ NE = 0x4 = VQFN/48/0.50\r
+ NC = 0x5 = HWQFN/36/0.50\r
+ LM = 0x6 = WFLGA/36/0.50\r
+ SB = 0x7 = SSOP/36/0.80\r
+*/\r
+#define MCU_PART_PACKAGE (0x0)\r
+\r
+/* ROM, RAM, and Data Flash Capacity. \r
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size\r
+ 5 = 0x5 = 128KB/16KB/8KB\r
+ 4 = 0x4 = 96KB/16KB/8KB\r
+ 3 = 0x3 = 64KB/10KB/8KB\r
+ 1 = 0x1 = 32KB/10KB/8KB\r
+ J = 0x0 = 16KB/8KB/8KB\r
+*/\r
+#define MCU_PART_MEMORY_SIZE (0x5)\r
+\r
+/* Group name. \r
+ Character(s) = Value for macro = Description\r
+ 10 = 0x0 = RX110 Group\r
+ 11 = 0x1 = RX111 Group\r
+*/\r
+#define MCU_PART_GROUP (0x1)\r
+\r
+/* Series name. \r
+ Character(s) = Value for macro = Description\r
+ 51 = 0x0 = RX100 Series\r
+*/ \r
+#define MCU_PART_SERIES (0x0)\r
+\r
+/* Memory type. \r
+ Character(s) = Value for macro = Description\r
+ F = 0x0 = Flash memory version\r
+*/\r
+#define MCU_PART_MEMORY_TYPE (0x0)\r
+\r
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a \r
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */\r
+#if defined(BSP_DECLARE_STACK)\r
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize su=0x400\r
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize si=0x100\r
+#endif\r
+\r
+/* Heap size in bytes. */\r
+#define HEAP_BYTES (0x400)\r
+\r
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information\r
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.\r
+ 0 = Stay in Supervisor mode.\r
+ 1 = Switch to User mode.\r
+*/\r
+#define RUN_IN_USER_MODE (0)\r
+\r
+\r
+/* This macro lets other modules no if a RTOS is being used.\r
+ 0 = RTOS is not used. \r
+ 1 = RTOS is used.\r
+*/\r
+#define RTOS_USED (0)\r
+\r
+/* Clock source select (CKSEL).\r
+ 0 = Low Speed On-Chip Oscillator (LOCO)\r
+ 1 = High Speed On-Chip Oscillator (HOCO)\r
+ 2 = Main Clock Oscillator \r
+ 3 = Sub-Clock Oscillator\r
+ 4 = PLL Circuit\r
+*/ \r
+#define CLOCK_SOURCE (4)\r
+\r
+/* Clock configuration options.\r
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The\r
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the\r
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the\r
+ settings would be:\r
+\r
+ XTAL_HZ = 16000000\r
+ PLL_DIV = 2\r
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)\r
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz\r
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz\r
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz\r
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz\r
+*/\r
+/* XTAL - Input clock frequency in Hz */\r
+#define XTAL_HZ (16000000)\r
+/* PLL Input Frequency Divider Select (PLIDIV). \r
+ Available divisors = /1 (no division), /2, /4\r
+*/\r
+#define PLL_DIV (2)\r
+/* PLL Frequency Multiplication Factor Select (STC). \r
+ Available multipliers = x6, x8\r
+*/\r
+#define PLL_MUL (6)\r
+/* System Clock Divider (ICK).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define ICK_DIV (2)\r
+/* Peripheral Module Clock B Divider (PCKB). \r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKB_DIV (2)\r
+/* Peripheral Module Clock D Divider (PCKD). \r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKD_DIV (2)\r
+/* Flash IF Clock Divider (FCK). \r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define FCK_DIV (2)\r
+\r
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and \r
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a \r
+ function to be called when the event occurs. For example, if the user wanted the function \r
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would\r
+ do the following:\r
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+ If the user does not wish to be alerted of these events then they should comment out the macros.\r
+ \r
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function\r
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it\r
+ is executing. For this reason, it is recommended to keep these callback functions short as to not\r
+ decrease the real-time response of your system.\r
+*/\r
+/* Callback for Supervisor Instruction Violation Exception. */\r
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb\r
+\r
+/* Callback for Undefined Instruction Exception. */\r
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb\r
+\r
+/* Callback for Non-maskable Interrupt. */\r
+//#define NMI_ISR_CALLBACK nmi_cb\r
+\r
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source\r
+ is creating unwanted interrupts. */\r
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+\r
+/* Callback for Bus Error Interrupt. */\r
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb\r
+\r
+/* The user has the option of separately choosing little or big endian for the User Application Area */\r
+\r
+/* Endian mode for User Application.\r
+ 0 = Big Endian\r
+ Else = Little Endian (Default)\r
+*/ \r
+#define USER_APP_ENDIAN (1)\r
+\r
+\r
+/* Configure WDT and IWDT settings. \r
+ OFS0 - Option Function Select Register 0 \r
+ OFS0 - Option Function Select Register 0\r
+ b31:b15 Reserved (set to 1)\r
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)\r
+ b13 Reserved (set to 1)\r
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)\r
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)\r
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)\r
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)\r
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)\r
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)\r
+ b0 Reserved (set to 1) */\r
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.\r
+ OFS1 - Option Function Select Register 1\r
+ b31:b9 Reserved (set to 1)\r
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)\r
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select\r
+ 0 1 0 0: 3.10 V\r
+ 0 1 0 1: 3.00 V\r
+ 0 1 1 0: 2.90 V\r
+ 0 1 1 1: 2.79 V\r
+ 1 0 0 0: 2.68 V\r
+ 1 0 0 1: 2.58 V\r
+ 1 0 1 0: 2.48 V\r
+ 1 0 1 1: 2.06 V\r
+ 1 1 0 0: 1.96 V\r
+ 1 1 0 1: 1.86 V\r
+ b3:b2 Reserved (set to 1)\r
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)\r
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */\r
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Initializes C input & output library functions.\r
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.\r
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */\r
+#define IO_LIB_ENABLE (1)\r
+\r
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */\r
+\r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : rskrx111.h\r
+* H/W Platform : RSKRX111\r
+* Description : Board specific definitions for the RSKRX111.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+#ifndef RSKRX111_H
+#define RSKRX111_H
+
+/* Local defines */
+#define LED_ON (0)
+#define LED_OFF (1)
+#define SET_BIT_HIGH (1)
+#define SET_BIT_LOW (0)
+#define SET_BYTE_HIGH (0xFF)
+#define SET_BYTE_LOW (0x00)\r
+\r
+/* Switches */\r
+#define SW_ACTIVE 0\r
+#define SW1 PORT3.PIDR.BIT.B0\r
+#define SW2 PORT3.PIDR.BIT.B1\r
+#define SW3 PORTE.PIDR.BIT.B4\r
+#define SW1_PDR PORT3.PDR.BIT.B0\r
+#define SW2_PDR PORT3.PDR.BIT.B1\r
+#define SW3_PDR PORTE.PDR.BIT.B4\r
+#define SW1_PMR PORT3.PMR.BIT.B0\r
+#define SW2_PMR PORT3.PMR.BIT.B1\r
+#define SW3_PMR PORTE.PMR.BIT.B4\r
+\r
+/* LEDs */\r
+#define LED0 PORTB.PODR.BIT.B7\r
+#define LED1 PORTA.PODR.BIT.B0\r
+#define LED2 PORT5.PODR.BIT.B4\r
+#define LED3 PORT1.PODR.BIT.B7\r
+#define LED0_PDR PORTB.PDR.BIT.B7\r
+#define LED1_PDR PORTA.PDR.BIT.B0\r
+#define LED2_PDR PORT5.PDR.BIT.B4\r
+#define LED3_PDR PORT1.PDR.BIT.B7\r
+\r
+
+#endif /* RSKRX111_H */\r
--- /dev/null
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : hwsetup.c
+* Device(s) : RX
+* H/W Platform : RSKRX210
+* Description : Defines the initialization routines used each time the MCU is restarted.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+/* I/O Register and board definitions */
+#include "platform.h"
+#include "r_switches_config.h"
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* MCU I/O port configuration function delcaration */
+static void output_ports_configure(void);
+
+/* Interrupt configuration function delcaration */
+static void interrupts_configure(void);
+
+/* MCU peripheral module configuration function declaration */
+static void peripheral_modules_enable(void);
+
+/* Configure MCU clocks. */
+static void clock_source_select (void);
+void operating_frequency_set(void);
+
+/***********************************************************************************************************************
+* Function name: hardware_setup
+* Description : Contains setup functions called at device restart
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void HardwareSetup(void)
+{
+ operating_frequency_set();
+ output_ports_configure();
+ interrupts_configure();
+ peripheral_modules_enable();
+}
+
+/***********************************************************************************************************************
+* Function name: output_ports_configure
+* Description : Configures the port and pin direction settings, and sets the pin outputs to a safe level.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void output_ports_configure(void)
+{
+ /* Enable LEDs. */
+ /* Start with LEDs off. */
+ LED0 = LED_OFF;
+ LED1 = LED_OFF;
+ LED2 = LED_OFF;
+ LED3 = LED_OFF;
+
+ /* Set LED pins as outputs. */
+ LED0_PDR = 1;
+ LED1_PDR = 1;
+ LED2_PDR = 1;
+ LED3_PDR = 1;
+
+ /* Enable switches. */
+ /* Set pins as inputs. */
+ SW1_PDR = 0;
+ SW2_PDR = 0;
+ SW3_PDR = 0;
+
+ /* Set port mode registers for switches. */
+ SW1_PMR = 0;
+ SW2_PMR = 0;
+ SW3_PMR = 0;
+
+ /* Unlock MPC registers to enable writing to them. */
+ MPC.PWPR.BIT.B0WI = 0 ; /* Unlock protection register */
+ MPC.PWPR.BIT.PFSWE = 1 ; /* Unlock MPC registers */
+
+ /* TXD1 is output. */
+ PORT1.PDR.BIT.B6 = 1;
+ PORT1.PMR.BIT.B6 = 1;
+ MPC.P16PFS.BYTE = 0x0A;
+ /* RXD1 is input. */
+ PORT1.PDR.BIT.B5 = 0;
+ PORT1.PMR.BIT.B5 = 1;
+ MPC.P15PFS.BYTE = 0x0A;
+
+ /* Configure the pin connected to the ADC Pot as an input */
+ PORT4.PDR.BIT.B4 = 0;
+
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA50B;
+
+ /* Turn off module stop for the A2D converter. */
+ SYSTEM.MSTPCRA.BIT.MSTPA17 = 0;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+
+ /* Initialise the first button to generate an interrupt. */
+ R_SWITCHES_Init();
+}
+
+/***********************************************************************************************************************
+* Function name: interrupts_configure
+* Description : Configures interrupts used
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void interrupts_configure(void)
+{
+ /* Add code here to setup additional interrupts */
+}
+
+/***********************************************************************************************************************
+* Function name: peripheral_modules_enable
+* Description : Enables and configures peripheral devices on the MCU
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void peripheral_modules_enable(void)
+{
+ /* Enable triggers to start an ADC conversion. */
+ S12AD.ADCSR.BIT.TRGE = 1;
+
+ /* Only channel 4 is going to be used. */
+ S12AD.ADANSA.BIT.ANSA4 = 1;
+}
+
+/***********************************************************************************************************************
+* Function name: operating_frequency_set
+* Description : Configures the clock settings for each of the device clocks
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void operating_frequency_set(void)
+{
+ /* Used for constructing value to write to SCKCR and CKOCR registers. */
+ uint32_t temp_clock = 0;
+
+ /*
+ Clock Description Frequency
+ ----------------------------------------
+ Input Clock Frequency............ 16 MHz
+ PLL frequency (x3)............... 48 MHz
+ Internal Clock Frequency......... 24 MHz
+ Peripheral Clock Frequency....... 24 MHz
+ Clock Out Frequency.............. 1 MHz */
+
+ volatile unsigned int i;
+
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA50B;
+
+ /* Select the clock based upon user's choice. */
+ clock_source_select();
+
+
+ /* Figure out setting for FCK bits. */
+#if FCK_DIV == 1
+ /* Do nothing since FCK bits should be 0. */
+#elif FCK_DIV == 2
+ temp_clock |= 0x10000000;
+#elif FCK_DIV == 4
+ temp_clock |= 0x20000000;
+#elif FCK_DIV == 8
+ temp_clock |= 0x30000000;
+#elif FCK_DIV == 16
+ temp_clock |= 0x40000000;
+#elif FCK_DIV == 32
+ temp_clock |= 0x50000000;
+#elif FCK_DIV == 64
+ temp_clock |= 0x60000000;
+#else
+ #error "Error! Invalid setting for FCK_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for ICK bits. */
+#if ICK_DIV == 1
+ /* Do nothing since ICK bits should be 0. */
+#elif ICK_DIV == 2
+ temp_clock |= 0x01000000;
+#elif ICK_DIV == 4
+ temp_clock |= 0x02000000;
+#elif ICK_DIV == 8
+ temp_clock |= 0x03000000;
+#elif ICK_DIV == 16
+ temp_clock |= 0x04000000;
+#elif ICK_DIV == 32
+ temp_clock |= 0x05000000;
+#elif ICK_DIV == 64
+ temp_clock |= 0x06000000;
+#else
+ #error "Error! Invalid setting for ICK_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for PCKB bits. */
+#if PCKB_DIV == 1
+ /* Do nothing since PCKB bits should be 0. */
+#elif PCKB_DIV == 2
+ temp_clock |= 0x00000100;
+#elif PCKB_DIV == 4
+ temp_clock |= 0x00000200;
+#elif PCKB_DIV == 8
+ temp_clock |= 0x00000300;
+#elif PCKB_DIV == 16
+ temp_clock |= 0x00000400;
+#elif PCKB_DIV == 32
+ temp_clock |= 0x00000500;
+#elif PCKB_DIV == 64
+ temp_clock |= 0x00000600;
+#else
+ #error "Error! Invalid setting for PCKB_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for PCKD bits. */
+#if PCKD_DIV == 1
+ /* Do nothing since PCKD bits should be 0. */
+#elif PCKD_DIV == 2
+ temp_clock |= 0x00000001;
+#elif PCKD_DIV == 4
+ temp_clock |= 0x00000002;
+#elif PCKD_DIV == 8
+ temp_clock |= 0x00000003;
+#elif PCKD_DIV == 16
+ temp_clock |= 0x00000004;
+#elif PCKD_DIV == 32
+ temp_clock |= 0x00000005;
+#elif PCKD_DIV == 64
+ temp_clock |= 0x00000006;
+#else
+ #error "Error! Invalid setting for PCKD_DIV in r_bsp_config.h"
+#endif
+
+ /* Set SCKCR register. */
+ SYSTEM.SCKCR.LONG = temp_clock;
+
+ /* Choose clock source. Default for r_bsp_config.h is PLL. */
+ SYSTEM.SCKCR3.WORD = ((uint16_t)CLOCK_SOURCE) << 8;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+}
+
+/***********************************************************************************************************************
+* Function name: clock_source_select
+* Description : Enables and disables clocks as chosen by the user. This function also implements the software delays
+* needed for the clocks to stabilize.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+static void clock_source_select (void)
+{
+ /* Declared volatile for software delay purposes. */
+ volatile unsigned int i;
+
+ /* NOTE: AS OF VERSION 0.50 OF THE RX111 HARDWARE MANUAL, ALL OF THE CLOCK
+ * STABILIZATION TIMES ARE TBD. FOR NOW, WHERE EVER A WAIT COUNT REGISTER
+ * IS AVAILABLE, THE DELAY IS SET TO THE MAX NUMBER OF CYCLES. WHERE EVER
+ * DELAY LOOPS ARE PRESENT, THE VALUES FROM THE 63N ARE RE-USED. KEEP IN
+ * MIND THAT THE 63N RUNS ON A FASTER CRYSTAL.
+ */
+
+#if (CLOCK_SOURCE == 1)
+ /* HOCO is chosen. Start it operating. */
+ SYSTEM.HOCOCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the HOCO has stabilized.*/
+ for(i = 0; i< 28; i++) // tHOCOWT2 is TBD
+ {
+ __asm volatile( "NOP" );
+ }
+#else
+ /* HOCO is not chosen. Stop the HOCO. */
+ SYSTEM.HOCOCR.BYTE = 0x01;
+#endif
+
+#if (CLOCK_SOURCE == 2)
+ /* Main clock oscillator is chosen. Start it operating. */
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles
+ /* Set the main clock to operating. */
+ SYSTEM.MOSCCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the main clock has stabilized. */
+ for(i = 0; i< 140; i++) // tMAINOSCWT is TBD
+ {
+ __asm volatile( "NOT" );
+ }
+#endif
+
+#if (CLOCK_SOURCE == 3)
+ /* Sub-clock oscillator is chosen. Start it operating. */
+ /* In section 9.8.4, there is a reference to a SOSCWTCR register, but there is no
+ * description for this register in the manual nor reference for it in iodefine.h. */
+
+ /* Set the sub-clock to operating. */
+ SYSTEM.SOSCCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the sub-clock has stabilized. */
+ for(i = 0; i< 30233; i++) // tSUBOSCWT0 is TBD
+ {
+ __asm volatile( "NOP" );
+ }
+#else
+ /* Set the sub-clock to stopped. */
+ SYSTEM.SOSCCR.BYTE = 0x01;
+#endif
+
+#if (CLOCK_SOURCE == 4)
+ /* PLL is chosen. Start it operating. Must start main clock as well since PLL uses it. */
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles
+ /* Set the main clock to operating. */
+ SYSTEM.MOSCCR.BYTE = 0x00;
+
+ /* Set PLL Input Divisor. */
+ SYSTEM.PLLCR.BIT.PLIDIV = PLL_DIV >> 1;
+
+ /* Set PLL Multiplier. */
+ SYSTEM.PLLCR.BIT.STC = (PLL_MUL * 2) - 1;
+
+ /* Set the PLL to operating. */
+ SYSTEM.PLLCR2.BYTE = 0x00;
+ /* The delay period needed is to make sure that the main clock and PLL have stabilized. */
+ for(i = 0; i< 140; i++) // tPLLWT2 is TBD
+ {
+ __asm volatile( "NOP" );
+ }
+#endif
+
+ /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn
+ it off until another clock has been enabled and is ready to use. */
+#if (CLOCK_SOURCE == 0)
+ /* LOCO is chosen. This is the default out of reset. */
+ SYSTEM.LOCOCR.BYTE = 0x00;
+#else
+ /* LOCO is not chosen and another clock has already been setup. Turn off the LOCO. */
+ SYSTEM.LOCOCR.BYTE = 0x01;
+#endif
+
+ /* Make sure a valid clock was chosen. */
+#if (CLOCK_SOURCE > 4) || (CLOCK_SOURCE < 0)
+ #error "ERROR - Valid clock source must be chosen in r_bsp_config.h using CLOCK_SOURCE macro."
+#endif
+}
+
+
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp.h \r
+* Description : Has the header files that should be included for this platform.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 13.01.2012 1.00 First Release\r
+* : 27.06.2012 1.10 Updated with new information to reflect udpated r_bsp structure.\r
+***********************************************************************************************************************/\r
+\r
+#ifndef PLATFORM_BOARD_USER\r
+#define PLATFORM_BOARD_USER\r
+\r
+/* Make sure that no other platforms have already been defined. Do not touch this! */\r
+#ifdef PLATFORM_DEFINED\r
+#error "Error - Multiple platforms defined in platform.h!"\r
+#else\r
+#define PLATFORM_DEFINED\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+INCLUDE APPROPRIATE MCU AND BOARD FILES\r
+***********************************************************************************************************************/\r
+/* This is a user defined board. Start off by:\r
+ 1)Copy and rename one of the 'board' folders that most closely matches your system (same MCU Series and Group).\r
+ 2)Substitute in your MCU Group for the *MCU Group* option in the #include below for mcu_info.h.\r
+ 3)Copy the other #includes from the r_bsp.h in the 'board' folder that you copied earlier.\r
+ 4)Configure the BSP for your board by modifying the r_bsp_config_reference.h.\r
+ 5)Copy r_bsp_config_reference.h to your project directory and rename it r_bsp_config.h.\r
+ You can also add your own include files here as well. */\r
+#include "r_bsp_config.h"\r
+#include ".\mcu\*MCU Group*\mcu_info.h" \r
+\r
+#endif /* PLATFORM_BOARD_USER */\r
+\r
+\r
--- /dev/null
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : interrupt_handlers.c */
+/* DESCRIPTION : Interrupt Handler */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/\r
+\r
+\r
+\r
+\r
+#include "interrupt_handlers.h"\r
+\r
+// INT_Exception(Supervisor Instruction)\r
+void INT_Excep_SuperVisorInst(void){/* brk(); */}\r
+\r
+// Exception(Undefined Instruction)\r
+void INT_Excep_UndefinedInst(void){/* brk(); */}\r
+\r
+// Exception(Floating Point)\r
+void INT_Excep_FloatingPoint(void){/* brk(); */}\r
+\r
+// NMI\r
+void INT_NonMaskableInterrupt(void){/* brk(); */}\r
+\r
+// Dummy\r
+void Dummy(void)
+{
+ for( ;; );
+}
+\r
+// BRK\r
+void INT_Excep_BRK(void){/* wait(); */}\r
+//;0x0000 Reserved\r
+\r
+void INT_Excep_BUSERR(void){ }\r
+\r
+// ICU SWINT\r
+void INT_Excep_ICU_SWINT(void){ }
+\r
+// CMT0 CMI0\r
+void INT_Excep_CMT0_CMI0(void){ }\r
+\r
+// CMT1 CMI1\r
+void INT_Excep_CMT1_CMI1(void){ }\r
+\r
+// CAC FERRF\r
+void INT_Excep_CAC_FERRF(void){ }\r
+\r
+// CAC MENDF\r
+void INT_Excep_CAC_MENDF(void){ }\r
+\r
+// CAC OVFF\r
+void INT_Excep_CAC_OVFF(void){ }\r
+\r
+// USB0 D0FIFO0\r
+void INT_Excep_USB0_D0FIFO0(void){ }\r
+\r
+// USB0 D1FIFO0\r
+void INT_Excep_USB0_D1FIFO0(void){ }\r
+\r
+// USB0 USBI0\r
+void INT_Excep_USB0_USBI0(void){ }\r
+\r
+// RSPI0 SPEI0\r
+void INT_Excep_RSPI0_SPEI0(void){ }\r
+\r
+// RSPI0 SPRI0\r
+void INT_Excep_RSPI0_SPRI0(void){ }\r
+\r
+// RSPI0 SPTI0\r
+void INT_Excep_RSPI0_SPTI0(void){ }\r
+\r
+// RSPI0 SPII0\r
+void INT_Excep_RSPI0_SPII0(void){ }\r
+\r
+// DOC DOPCF\r
+void INT_Excep_DOC_DOPCF(void){ }\r
+\r
+// RTC CUP\r
+void INT_Excep_RTC_CUP(void){ }\r
+\r
+// ICU IRQ0\r
+void INT_Excep_ICU_IRQ0(void){ }\r
+\r
+// ICU IRQ1\r
+void INT_Excep_ICU_IRQ1(void){ }\r
+\r
+// ICU IRQ2\r
+void INT_Excep_ICU_IRQ2(void){ }\r
+\r
+// ICU IRQ3\r
+void INT_Excep_ICU_IRQ3(void){ }\r
+\r
+// ICU IRQ4\r
+void INT_Excep_ICU_IRQ4(void){ }\r
+\r
+// ICU IRQ5\r
+void INT_Excep_ICU_IRQ5(void){ }\r
+\r
+// ICU IRQ6\r
+void INT_Excep_ICU_IRQ6(void){ }\r
+\r
+// ICU IRQ7\r
+void INT_Excep_ICU_IRQ7(void){ }\r
+\r
+// LVD LVD1\r
+void INT_Excep_LVD_LVD1(void){ }\r
+\r
+// LVD LVD2\r
+void INT_Excep_LVD_LVD2(void){ }\r
+\r
+// USB0 USBR0\r
+void INT_Excep_USB0_USBR0(void){ }\r
+\r
+// RTC ALM\r
+void INT_Excep_RTC_ALM(void){ }\r
+\r
+// RTC PRD\r
+void INT_Excep_RTC_PRD(void){ }\r
+\r
+// S12AD S12ADI0\r
+void INT_Excep_S12AD_S12ADI0(void){ }\r
+\r
+// S12AD GBADI\r
+void INT_Excep_S12AD_GBADI(void){ }\r
+\r
+// ELC ELSR18I\r
+void INT_Excep_ELC_ELSR18I(void){ }\r
+\r
+// MTU0 TGIA0\r
+void INT_Excep_MTU0_TGIA0(void){ }\r
+\r
+// MTU0 TGIB0\r
+void INT_Excep_MTU0_TGIB0(void){ }\r
+\r
+// MTU0 TGIC0\r
+void INT_Excep_MTU0_TGIC0(void){ }\r
+\r
+// MTU0 TGID0\r
+void INT_Excep_MTU0_TGID0(void){ }\r
+\r
+// MTU0 TCIV0\r
+void INT_Excep_MTU0_TCIV0(void){ }\r
+\r
+// MTU0 TGIE0\r
+void INT_Excep_MTU0_TGIE0(void){ }\r
+\r
+// MTU0 TGIF0\r
+void INT_Excep_MTU0_TGIF0(void){ }\r
+\r
+// MTU1 TGIA1\r
+void INT_Excep_MTU1_TGIA1(void){ }\r
+\r
+// MTU1 TGIB1\r
+void INT_Excep_MTU1_TGIB1(void){ }\r
+\r
+// MTU1 TCIV1\r
+void INT_Excep_MTU1_TCIV1(void){ }\r
+\r
+// MTU1 TCIU1\r
+void INT_Excep_MTU1_TCIU1(void){ }\r
+\r
+// MTU2 TGIA2\r
+void INT_Excep_MTU2_TGIA2(void){ }\r
+\r
+// MTU2 TGIB2\r
+void INT_Excep_MTU2_TGIB2(void){ }\r
+\r
+// MTU2 TCIV2\r
+void INT_Excep_MTU2_TCIV2(void){ }\r
+\r
+// MTU2 TCIU2\r
+void INT_Excep_MTU2_TCIU2(void){ }\r
+\r
+// MTU3 TGIA3\r
+void INT_Excep_MTU3_TGIA3(void){ }\r
+\r
+// MTU3 TGIB3\r
+void INT_Excep_MTU3_TGIB3(void){ }\r
+\r
+// MTU3 TGIC3\r
+void INT_Excep_MTU3_TGIC3(void){ }\r
+\r
+// MTU3 TGID3\r
+void INT_Excep_MTU3_TGID3(void){ }\r
+\r
+// MTU3 TCIV3\r
+void INT_Excep_MTU3_TCIV3(void){ }\r
+\r
+// MTU4 TGIA4\r
+void INT_Excep_MTU4_TGIA4(void){ }\r
+\r
+// MTU4 TGIB4\r
+void INT_Excep_MTU4_TGIB4(void){ }\r
+\r
+// MTU4 TGIC4\r
+void INT_Excep_MTU4_TGIC4(void){ }\r
+\r
+// MTU4 TGID4\r
+void INT_Excep_MTU4_TGID4(void){ }\r
+\r
+// MTU4 TCIV4\r
+void INT_Excep_MTU4_TCIV4(void){ }\r
+\r
+// MTU5 TGIU5\r
+void INT_Excep_MTU5_TGIU5(void){ }\r
+\r
+// MTU5 TGIV5\r
+void INT_Excep_MTU5_TGIV5(void){ }\r
+\r
+// MTU5 TGIW5\r
+void INT_Excep_MTU5_TGIW5(void){ }\r
+\r
+// POE OEI1\r
+void INT_Excep_POE_OEI1(void){ }\r
+\r
+// POE OEI2\r
+void INT_Excep_POE_OEI2(void){ }\r
+\r
+// SCI1 ERI1\r
+void INT_Excep_SCI1_ERI1(void){ }\r
+\r
+// SCI1 RXI1\r
+void INT_Excep_SCI1_RXI1(void){ }\r
+\r
+// SCI1 TXI1\r
+void INT_Excep_SCI1_TXI1(void){ }\r
+\r
+// SCI1 TEI1\r
+void INT_Excep_SCI1_TEI1(void){ }\r
+\r
+// SCI5 ERI5\r
+void INT_Excep_SCI5_ERI5(void){ }\r
+\r
+// SCI5 RXI5\r
+void INT_Excep_SCI5_RXI5(void){ }\r
+\r
+// SCI5 TXI5\r
+void INT_Excep_SCI5_TXI5(void){ }\r
+\r
+// SCI5 TEI5\r
+void INT_Excep_SCI5_TEI5(void){ }\r
+\r
+// SCI12 ERI12\r
+void INT_Excep_SCI12_ERI12(void){ }\r
+\r
+// SCI12 RXI12\r
+void INT_Excep_SCI12_RXI12(void){ }\r
+\r
+// SCI12 TXI12\r
+void INT_Excep_SCI12_TXI12(void){ }\r
+\r
+// SCI12 TEI12\r
+void INT_Excep_SCI12_TEI12(void){ }\r
+\r
+// SCI12 SCIX0\r
+void INT_Excep_SCI12_SCIX0(void){ }\r
+\r
+// SCI12 SCIX1\r
+void INT_Excep_SCI12_SCIX1(void){ }\r
+\r
+// SCI12 SCIX2\r
+void INT_Excep_SCI12_SCIX2(void){ }\r
+\r
+// SCI12 SCIX3\r
+void INT_Excep_SCI12_SCIX3(void){ }\r
+\r
+// RIIC0 EEI0\r
+void INT_Excep_RIIC0_EEI0(void){ }\r
+\r
+// RIIC0 RXI0\r
+void INT_Excep_RIIC0_RXI0(void){ }\r
+\r
+// RIIC0 TXI0\r
+void INT_Excep_RIIC0_TXI0(void){ }\r
+\r
+// RIIC0 TEI0\r
+void INT_Excep_RIIC0_TEI0(void){ }\r
--- /dev/null
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : interrupt_handlers.h */
+/* DESCRIPTION : Interrupt Handler Declarations */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+#ifndef INTERRUPT_HANDLERS_H\r
+#define INTERRUPT_HANDLERS_H\r
+\r
+// Exception(Supervisor Instruction)\r
+// Exception(Supervisor Instruction)\r
+void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt));\r
+\r
+// Exception(Undefined Instruction)\r
+void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt));\r
+\r
+// Exception(Floating Point)\r
+void INT_Excep_FloatingPoint(void) __attribute__ ((interrupt));\r
+\r
+// NMI\r
+void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt));\r
+\r
+// Dummy\r
+void Dummy (void) __attribute__ ((interrupt));\r
+\r
+// BRK\r
+void INT_Excep_BRK(void) __attribute__ ((interrupt));\r
+//;0x0000 Reserved\r
+\r
+void INT_Excep_BUSERR(void) __attribute__ ((interrupt));\r
+//;0x0044 Reserved\r
+ \r
+void INT_Excep_ICU_SWINT(void) __attribute__ ((interrupt));\r
+\r
+// CMT0 CMI0\r
+\r
+void INT_Excep_CMT0_CMI0(void) __attribute__ ((interrupt));\r
+\r
+// CMT1 CMI1\r
+\r
+void INT_Excep_CMT1_CMI1(void) __attribute__ ((interrupt));\r
+\r
+// CAC FERRF\r
+\r
+void INT_Excep_CAC_FERRF(void) __attribute__ ((interrupt));\r
+\r
+// CAC MENDF\r
+\r
+\r
+void INT_Excep_CAC_MENDF(void) __attribute__ ((interrupt));\r
+\r
+// CAC OVFF\r
+\r
+void INT_Excep_CAC_OVFF(void) __attribute__ ((interrupt));\r
+\r
+// USB0 D0FIFO0\r
+\r
+void INT_Excep_USB0_D0FIFO0(void) __attribute__ ((interrupt));\r
+\r
+// USB0 D1FIFO0\r
+\r
+void INT_Excep_USB0_D1FIFO0(void) __attribute__ ((interrupt));\r
+\r
+// USB0 USBI0\r
+\r
+void INT_Excep_USB0_USBI0(void) __attribute__ ((interrupt));\r
+\r
+// RSPI0 SPEI0\r
+\r
+void INT_Excep_RSPI0_SPEI0(void) __attribute__ ((interrupt));\r
+\r
+// RSPI0 SPRI0\r
+\r
+void INT_Excep_RSPI0_SPRI0(void) __attribute__ ((interrupt));\r
+\r
+// RSPI0 SPTI0\r
+\r
+void INT_Excep_RSPI0_SPTI0(void) __attribute__ ((interrupt));\r
+\r
+// RSPI0 SPII0\r
+\r
+void INT_Excep_RSPI0_SPII0(void) __attribute__ ((interrupt));\r
+\r
+// DOC DOPCF\r
+\r
+void INT_Excep_DOC_DOPCF(void) __attribute__ ((interrupt));\r
+\r
+// RTC CUP\r
+\r
+void INT_Excep_RTC_CUP(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ0\r
+\r
+void INT_Excep_ICU_IRQ0(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ1\r
+\r
+void INT_Excep_ICU_IRQ1(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ2\r
+\r
+void INT_Excep_ICU_IRQ2(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ3\r
+\r
+void INT_Excep_ICU_IRQ3(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ4\r
+\r
+void INT_Excep_ICU_IRQ4(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ5\r
+\r
+void INT_Excep_ICU_IRQ5(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ6\r
+\r
+void INT_Excep_ICU_IRQ6(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ7\r
+\r
+void INT_Excep_ICU_IRQ7(void) __attribute__ ((interrupt));\r
+\r
+// LVD LVD1\r
+\r
+void INT_Excep_LVD_LVD1(void) __attribute__ ((interrupt));\r
+\r
+// LVD LVD2\r
+\r
+void INT_Excep_LVD_LVD2(void) __attribute__ ((interrupt));\r
+\r
+// USB0 USBR0\r
+\r
+void INT_Excep_USB0_USBR0(void) __attribute__ ((interrupt));\r
+\r
+// RTC ALM\r
+\r
+void INT_Excep_RTC_ALM(void) __attribute__ ((interrupt));\r
+\r
+// RTC PRD\r
+\r
+void INT_Excep_RTC_PRD(void) __attribute__ ((interrupt));\r
+\r
+// S12AD S12ADI0\r
+\r
+void INT_Excep_S12AD_S12ADI0(void) __attribute__ ((interrupt));\r
+\r
+// S12AD GBADI\r
+\r
+void INT_Excep_S12AD_GBADI(void) __attribute__ ((interrupt));\r
+\r
+// ELC ELSR18I\r
+\r
+void INT_Excep_ELC_ELSR18I(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGIA0\r
+\r
+void INT_Excep_MTU0_TGIA0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGIB0\r
+\r
+void INT_Excep_MTU0_TGIB0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGIC0\r
+\r
+void INT_Excep_MTU0_TGIC0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGID0\r
+\r
+void INT_Excep_MTU0_TGID0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TCIV0\r
+\r
+void INT_Excep_MTU0_TCIV0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGIE0\r
+\r
+void INT_Excep_MTU0_TGIE0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGIF0\r
+\r
+void INT_Excep_MTU0_TGIF0(void) __attribute__ ((interrupt));\r
+\r
+// MTU1 TGIA1\r
+\r
+void INT_Excep_MTU1_TGIA1(void) __attribute__ ((interrupt));\r
+\r
+// MTU1 TGIB1\r
+\r
+void INT_Excep_MTU1_TGIB1(void) __attribute__ ((interrupt));\r
+\r
+// MTU1 TCIV1\r
+\r
+void INT_Excep_MTU1_TCIV1(void) __attribute__ ((interrupt));\r
+\r
+// MTU1 TCIU1\r
+\r
+void INT_Excep_MTU1_TCIU1(void) __attribute__ ((interrupt));\r
+\r
+// MTU2 TGIA2\r
+\r
+void INT_Excep_MTU2_TGIA2(void) __attribute__ ((interrupt));\r
+\r
+// MTU2 TGIB2\r
+\r
+void INT_Excep_MTU2_TGIB2(void) __attribute__ ((interrupt));\r
+\r
+// MTU2 TCIV2\r
+\r
+void INT_Excep_MTU2_TCIV2(void) __attribute__ ((interrupt));\r
+\r
+// MTU2 TCIU2\r
+\r
+void INT_Excep_MTU2_TCIU2(void) __attribute__ ((interrupt));\r
+\r
+// MTU3 TGIA3\r
+\r
+void INT_Excep_MTU3_TGIA3(void) __attribute__ ((interrupt));\r
+\r
+// MTU3 TGIB3\r
+\r
+void INT_Excep_MTU3_TGIB3(void) __attribute__ ((interrupt));\r
+\r
+// MTU3 TGIC3\r
+\r
+void INT_Excep_MTU3_TGIC3(void) __attribute__ ((interrupt));\r
+\r
+// MTU3 TGID3\r
+\r
+void INT_Excep_MTU3_TGID3(void) __attribute__ ((interrupt));\r
+\r
+// MTU3 TCIV3\r
+\r
+void INT_Excep_MTU3_TCIV3(void) __attribute__ ((interrupt));\r
+\r
+// MTU4 TGIA4\r
+\r
+void INT_Excep_MTU4_TGIA4(void) __attribute__ ((interrupt));\r
+\r
+// MTU4 TGIB4\r
+\r
+void INT_Excep_MTU4_TGIB4(void) __attribute__ ((interrupt));\r
+\r
+// MTU4 TGIC4\r
+\r
+void INT_Excep_MTU4_TGIC4(void) __attribute__ ((interrupt));\r
+\r
+// MTU4 TGID4\r
+\r
+void INT_Excep_MTU4_TGID4(void) __attribute__ ((interrupt));\r
+\r
+// MTU4 TCIV4\r
+\r
+void INT_Excep_MTU4_TCIV4(void) __attribute__ ((interrupt));\r
+\r
+// MTU5 TGIU5\r
+\r
+void INT_Excep_MTU5_TGIU5(void) __attribute__ ((interrupt));\r
+\r
+// MTU5 TGIV5\r
+\r
+void INT_Excep_MTU5_TGIV5(void) __attribute__ ((interrupt));\r
+\r
+// MTU5 TGIW5\r
+\r
+void INT_Excep_MTU5_TGIW5(void) __attribute__ ((interrupt));\r
+\r
+// POE OEI1\r
+\r
+void INT_Excep_POE_OEI1(void) __attribute__ ((interrupt));\r
+\r
+// POE OEI2\r
+\r
+void INT_Excep_POE_OEI2(void) __attribute__ ((interrupt));\r
+\r
+// SCI1 ERI1\r
+\r
+void INT_Excep_SCI1_ERI1(void) __attribute__ ((interrupt));\r
+\r
+// SCI1 RXI1\r
+\r
+void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt));\r
+\r
+// SCI1 TXI1\r
+\r
+void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt));\r
+\r
+// SCI1 TEI1\r
+\r
+void INT_Excep_SCI1_TEI1(void) __attribute__ ((interrupt));\r
+\r
+// SCI5 ERI5\r
+\r
+void INT_Excep_SCI5_ERI5(void) __attribute__ ((interrupt));\r
+\r
+// SCI5 RXI5\r
+\r
+void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt));\r
+\r
+// SCI5 TXI5\r
+\r
+void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt));\r
+\r
+// SCI5 TEI5\r
+\r
+void INT_Excep_SCI5_TEI5(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 ERI12\r
+\r
+void INT_Excep_SCI12_ERI12(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 RXI12\r
+\r
+void INT_Excep_SCI12_RXI12(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 TXI12\r
+\r
+void INT_Excep_SCI12_TXI12(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 TEI12\r
+\r
+void INT_Excep_SCI12_TEI12(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 SCIX0\r
+\r
+void INT_Excep_SCI12_SCIX0(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 SCIX1\r
+\r
+void INT_Excep_SCI12_SCIX1(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 SCIX2\r
+\r
+void INT_Excep_SCI12_SCIX2(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 SCIX3\r
+\r
+void INT_Excep_SCI12_SCIX3(void) __attribute__ ((interrupt));\r
+\r
+// RIIC0 EEI0\r
+\r
+void INT_Excep_RIIC0_EEI0(void) __attribute__ ((interrupt));\r
+\r
+// RIIC0 RXI0\r
+\r
+void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt));\r
+\r
+// RIIC0 TXI0\r
+\r
+void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt));\r
+\r
+// RIIC0 TEI0\r
+\r
+void INT_Excep_RIIC0_TEI0(void) __attribute__ ((interrupt));\r
+\r
+//;<<VECTOR DATA START (POWER ON RESET)>>\r
+//;Power On Reset PC\r
+extern void PowerON_Reset(void); \r
+//;<<VECTOR DATA END (POWER ON RESET)>>\r
+#endif\r
--- /dev/null
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : iodefine.h */
+/* DESCRIPTION : Definition of I/O Registers */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/\r
+\r
+\r
+\r
+\r
+/* Generated by GNURX IO Header File Converter */\r
+\r
+/********************************************************************************/\r
+/* */\r
+/* Note : This is a typical example. */\r
+/* History : V0.5 (2012-09-25) [Hardware Manual Revision : 0.50] */\r
+/* Abstract : Definition of I/O Register. */\r
+/* File Name : iodefine.h */\r
+/* Device : RX/RX100/RX111 */\r
+/* */\r
+/* Copyright(c) 2012 Renesas Electronics Corp. */\r
+/* And Renesas Solutions Corp. ,All Rights Reserved. */\r
+/* */\r
+/********************************************************************************/\r
+/* */\r
+/* CPU TYPE : RX111 */\r
+/* DESCRIPTION : Definition of ICU Register */\r
+/* */\r
+/* Usage : IR,DTCER,IER,IPR of ICU Register */\r
+/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */\r
+/* The bit access operation is "Bit_Name(interrupt source,name)". */\r
+/* A part of the name can be omitted. */\r
+/* IR(MTU0,TGIA0) = 0; expands to : */\r
+/* for example : */\r
+/* ICU.IR[114].BIT.IR = 0; */\r
+/* */\r
+/* DTCE(ICU,IRQ0) = 1; expands to : */\r
+/* ICU.DTCER[64].BIT.DTCE = 1; */\r
+/* */\r
+/* IEN(CMT0,CMI0) = 1; expands to : */\r
+/* ICU.IER[0x03].BIT.IEN4 = 1; */\r
+/* */\r
+/* IPR(MTU1,TGIA1) = 2; expands to : */\r
+/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */\r
+/* ICU.IPR[121].BIT.IPR = 2; */\r
+/* */\r
+/* IPR(SCI1,ERI1) = 3; expands to : */\r
+/* IPR(SCI1, ) = 3; // SCI1 uses single IPR for all sources. */\r
+/* ICU.IPR[218].BIT.IPR = 3; */\r
+/* */\r
+/* Usage : #pragma interrupt Function_Identifier(vect=**) */\r
+/* The number of vector is "(interrupt source, name)". */\r
+/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */\r
+/* for example : */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */\r
+/* */\r
+/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */\r
+/* The bit access operation is "MSTP(name)". */\r
+/* The name that can be used is a macro name defined with "iodefine.h". */\r
+/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */\r
+/* for example : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */\r
+/* */\r
+/* */\r
+/********************************************************************************/\r
+#ifndef __RX111IODEFINE_HEADER__\r
+#define __RX111IODEFINE_HEADER__\r
+\r
+#ifdef __RX_LITTLE_ENDIAN__\r
+\r
+struct st_bsc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char STSCLR:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } BERCLR;\r
+ char wk0[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IGAEN:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } BEREN;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IA:1;\r
+ unsigned char :3;\r
+ unsigned char MST:3;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } BERSR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADDR:13;\r
+ } BIT;\r
+ } BERSR2;\r
+ char wk3[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BPRA:2;\r
+ unsigned short BPRO:2;\r
+ unsigned short BPIB:2;\r
+ unsigned short BPGB:2;\r
+ unsigned short :2;\r
+ unsigned short BPFB:2;\r
+ unsigned short :4;\r
+ } BIT;\r
+ } BUSPRI;\r
+};\r
+\r
+struct st_cac {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CFME:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } CACR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CACREFE:1;\r
+ unsigned char FMCS:3;\r
+ unsigned char TCSS:2;\r
+ unsigned char EDGES:2;\r
+ } BIT;\r
+ } CACR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RPS:1;\r
+ unsigned char RSCS:3;\r
+ unsigned char RCDS:2;\r
+ unsigned char DFS:2;\r
+ } BIT;\r
+ } CACR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FERRIE:1;\r
+ unsigned char MENDIE:1;\r
+ unsigned char OVFIE:1;\r
+ unsigned char :1;\r
+ unsigned char FERRFCL:1;\r
+ unsigned char MENDFCL:1;\r
+ unsigned char OVFFCL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } CAICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FERRF:1;\r
+ unsigned char MENDF:1;\r
+ unsigned char OVFF:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } CASTR;\r
+ char wk0[1];\r
+ unsigned short CAULVR;\r
+ unsigned short CALLVR;\r
+ unsigned short CACNTBR;\r
+};\r
+\r
+struct st_cmt {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short STR0:1;\r
+ unsigned short STR1:1;\r
+ unsigned short :14;\r
+ } BIT;\r
+ } CMSTR0;\r
+};\r
+\r
+struct st_cmt0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CKS:2;\r
+ unsigned short :4;\r
+ unsigned short CMIE:1;\r
+ unsigned short :9;\r
+ } BIT;\r
+ } CMCR;\r
+ unsigned short CMCNT;\r
+ unsigned short CMCOR;\r
+};\r
+\r
+struct st_crc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char GPS:2;\r
+ unsigned char LMS:1;\r
+ unsigned char :4;\r
+ unsigned char DORCLR:1;\r
+ } BIT;\r
+ } CRCCR;\r
+ unsigned char CRCDIR;\r
+ unsigned short CRCDOR;\r
+};\r
+\r
+struct st_da {\r
+ unsigned short DADR0;\r
+ unsigned short DADR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAOE0:1;\r
+ unsigned char DAOE1:1;\r
+ } BIT;\r
+ } DACR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSEL:1;\r
+ } BIT;\r
+ } DADPR;\r
+};\r
+\r
+struct st_doc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OMS:2;\r
+ unsigned char DCSEL:1;\r
+ unsigned char :1;\r
+ unsigned char DOPCIE:1;\r
+ unsigned char DOPCF:1;\r
+ unsigned char DOPCFCL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } DOCR;\r
+ char wk0[1];\r
+ unsigned short DODIR;\r
+ unsigned short DODSR;\r
+};\r
+\r
+struct st_dtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char RRS:1;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } DTCCR;\r
+ char wk0[3];\r
+ void *DTCVBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SHORT:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } DTCADMOD;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DTCST:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } DTCST;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VECN:8;\r
+ unsigned short :7;\r
+ unsigned short ACT:1;\r
+ } BIT;\r
+ } DTCSTS;\r
+};\r
+\r
+struct st_elc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ELCON:1;\r
+ } BIT;\r
+ } ELCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ELS:8;\r
+ } BIT;\r
+ } ELSR[26];\r
+ char wk0[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char MTU1MD:2;\r
+ unsigned char MTU2MD:2;\r
+ unsigned char MTU3MD:2;\r
+ } BIT;\r
+ } ELOPA;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTU4MD:2;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } ELOPB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char CMT1MD:2;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } ELOPC;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PGR0:1;\r
+ unsigned char PGR1:1;\r
+ unsigned char PGR2:1;\r
+ unsigned char PGR3:1;\r
+ unsigned char PGR4:1;\r
+ unsigned char PGR5:1;\r
+ unsigned char PGR6:1;\r
+ unsigned char PGR7:1;\r
+ } BIT;\r
+ } PGR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PGCI:2;\r
+ unsigned char PGCOVE:1;\r
+ unsigned char :1;\r
+ unsigned char PGCO:3;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PGC1;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PDBF0:1;\r
+ unsigned char PDBF1:1;\r
+ unsigned char PDBF2:1;\r
+ unsigned char PDBF3:1;\r
+ unsigned char PDBF4:1;\r
+ unsigned char PDBF5:1;\r
+ unsigned char PDBF6:1;\r
+ unsigned char PDBF7:1;\r
+ } BIT;\r
+ } PDBF1;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSB:3;\r
+ unsigned char PSP:2;\r
+ unsigned char PSM:2;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PEL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSB:3;\r
+ unsigned char PSP:2;\r
+ unsigned char PSM:2;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PEL1;\r
+ char wk5[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SEG:1;\r
+ unsigned char :5;\r
+ unsigned char WE:1;\r
+ unsigned char WI:1;\r
+ } BIT;\r
+ } ELSEGR;\r
+};\r
+\r
+struct st_flash {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DFLEN:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } DFLCTL;\r
+};\r
+\r
+struct st_icu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IR:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } IR[250];\r
+ char wk0[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DTCE:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } DTCER[249];\r
+ char wk1[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IEN0:1;\r
+ unsigned char IEN1:1;\r
+ unsigned char IEN2:1;\r
+ unsigned char IEN3:1;\r
+ unsigned char IEN4:1;\r
+ unsigned char IEN5:1;\r
+ unsigned char IEN6:1;\r
+ unsigned char IEN7:1;\r
+ } BIT;\r
+ } IER[32];\r
+ char wk2[192];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SWINT:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } SWINTR;\r
+ char wk3[15];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FVCT:8;\r
+ unsigned short :7;\r
+ unsigned short FIEN:1;\r
+ } BIT;\r
+ } FIR;\r
+ char wk4[14];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IPR:4;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } IPR[250];\r
+ char wk5[262];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned char IRQMD:2;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } IRQCR[8];\r
+ char wk6[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FLTEN0:1;\r
+ unsigned char FLTEN1:1;\r
+ unsigned char FLTEN2:1;\r
+ unsigned char FLTEN3:1;\r
+ unsigned char FLTEN4:1;\r
+ unsigned char FLTEN5:1;\r
+ unsigned char FLTEN6:1;\r
+ unsigned char FLTEN7:1;\r
+ } BIT;\r
+ } IRQFLTE0;\r
+ char wk7[3];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FCLKSEL0:2;\r
+ unsigned short FCLKSEL1:2;\r
+ unsigned short FCLKSEL2:2;\r
+ unsigned short FCLKSEL3:2;\r
+ unsigned short FCLKSEL4:2;\r
+ unsigned short FCLKSEL5:2;\r
+ unsigned short FCLKSEL6:2;\r
+ unsigned short FCLKSEL7:2;\r
+ } BIT;\r
+ } IRQFLTC0;\r
+ char wk8[106];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NMIST:1;\r
+ unsigned char OSTST:1;\r
+ unsigned char :1;\r
+ unsigned char IWDTST:1;\r
+ unsigned char LVD1ST:1;\r
+ unsigned char LVD2ST:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } NMISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NMIEN:1;\r
+ unsigned char OSTEN:1;\r
+ unsigned char :1;\r
+ unsigned char IWDTEN:1;\r
+ unsigned char LVD1EN:1;\r
+ unsigned char LVD2EN:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } NMIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NMICLR:1;\r
+ unsigned char OSTCLR:1;\r
+ unsigned char :1;\r
+ unsigned char IWDTCLR:1;\r
+ unsigned char LVD1CLR:1;\r
+ unsigned char LVD2CLR:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } NMICLR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char NMIMD:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } NMICR;\r
+ char wk9[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NFLTEN:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } NMIFLTE;\r
+ char wk10[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NFCLKSEL:2;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } NMIFLTC;\r
+};\r
+\r
+struct st_iwdt {\r
+ unsigned char IWDTRR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TOPS:2;\r
+ unsigned short :2;\r
+ unsigned short CKS:4;\r
+ unsigned short RPES:2;\r
+ unsigned short :2;\r
+ unsigned short RPSS:2;\r
+ unsigned short :2;\r
+ } BIT;\r
+ } IWDTCR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CNTVAL:14;\r
+ unsigned short UNDFF:1;\r
+ unsigned short REFEF:1;\r
+ } BIT;\r
+ } IWDTSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned char RSTIRQS:1;\r
+ } BIT;\r
+ } IWDTRCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned char SLCSTP:1;\r
+ } BIT;\r
+ } IWDTCSTPR;\r
+};\r
+\r
+struct st_mpc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned char PFSWE:1;\r
+ unsigned char B0WI:1;\r
+ } BIT;\r
+ } PWPR;\r
+ char wk0[35];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P03PFS;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P05PFS;\r
+ char wk2[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } P14PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } P15PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } P16PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } P17PFS;\r
+ char wk3[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } P26PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P27PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } P30PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } P31PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } P32PFS;\r
+ char wk4[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } P35PFS;\r
+ char wk5[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P40PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P41PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P42PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P43PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P44PFS;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P46PFS;\r
+ char wk7[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } P54PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } P55PFS;\r
+ char wk8[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PA0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PA1PFS;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PA3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PA4PFS;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PA6PFS;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PB0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PB1PFS;\r
+ char wk12[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PB3PFS;\r
+ char wk13[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PB5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PB6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PB7PFS;\r
+ char wk14[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PC2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PC3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PC4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PC5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PC6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PC7PFS;\r
+ char wk15[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PE0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PE1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PE2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PE3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PE4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PE5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PE6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL:5;\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PE7PFS;\r
+ char wk16[30];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ7PFS;\r
+};\r
+\r
+struct st_mtu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OE3B:1;\r
+ unsigned char OE4A:1;\r
+ unsigned char OE4B:1;\r
+ unsigned char OE3D:1;\r
+ unsigned char OE4C:1;\r
+ unsigned char OE4D:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } TOER;\r
+ char wk0[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char UF:1;\r
+ unsigned char VF:1;\r
+ unsigned char WF:1;\r
+ unsigned char FB:1;\r
+ unsigned char P:1;\r
+ unsigned char N:1;\r
+ unsigned char BDC:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } TGCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OLSP:1;\r
+ unsigned char OLSN:1;\r
+ unsigned char TOCS:1;\r
+ unsigned char TOCL:1;\r
+ unsigned char :2;\r
+ unsigned char PSYE:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } TOCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OLS1P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS3N:1;\r
+ unsigned char BF:2;\r
+ } BIT;\r
+ } TOCR2;\r
+ char wk1[4];\r
+ unsigned short TCDR;\r
+ unsigned short TDDR;\r
+ char wk2[8];\r
+ unsigned short TCNTS;\r
+ unsigned short TCBR;\r
+ char wk3[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char T4VCOR:3;\r
+ unsigned char T4VEN:1;\r
+ unsigned char T3ACOR:3;\r
+ unsigned char T3AEN:1;\r
+ } BIT;\r
+ } TITCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char T4VCNT:3;\r
+ unsigned char :1;\r
+ unsigned char T3ACNT:3;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } TITCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BTE:2;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } TBTER;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TDER:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } TDER;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OLS1P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS3N:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } TOLBR;\r
+ char wk6[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char WRE:1;\r
+ unsigned char :6;\r
+ unsigned char CCE:1;\r
+ } BIT;\r
+ } TWCR;\r
+ char wk7[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CST0:1;\r
+ unsigned char CST1:1;\r
+ unsigned char CST2:1;\r
+ unsigned char :3;\r
+ unsigned char CST3:1;\r
+ unsigned char CST4:1;\r
+ } BIT;\r
+ } TSTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SYNC0:1;\r
+ unsigned char SYNC1:1;\r
+ unsigned char SYNC2:1;\r
+ unsigned char :3;\r
+ unsigned char SYNC3:1;\r
+ unsigned char SYNC4:1;\r
+ } BIT;\r
+ } TSYR;\r
+ char wk8[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RWE:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } TRWER;\r
+};\r
+\r
+struct st_mtu0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NFAEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCS:2;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[111];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TPSC:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char CCLR:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MD:4;\r
+ unsigned char BFA:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFE:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOA:4;\r
+ unsigned char IOB:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOC:4;\r
+ unsigned char IOD:4;\r
+ } BIT;\r
+ } TIORL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TGIEA:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TTGE:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk1[16];\r
+ unsigned short TGRE;\r
+ unsigned short TGRF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TGIEE:1;\r
+ unsigned char TGIEF:1;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } TIER2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTSA:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSE:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } TBTM;\r
+};\r
+\r
+struct st_mtu1 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NFAEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCS:2;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[238];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TPSC:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char CCLR:2;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MD:4;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOA:4;\r
+ unsigned char IOB:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TGIEA:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char :1;\r
+ unsigned char TTGE:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk3[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char I1AE:1;\r
+ unsigned char I1BE:1;\r
+ unsigned char I2AE:1;\r
+ unsigned char I2BE:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } TICCR;\r
+};\r
+\r
+struct st_mtu2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NFAEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCS:2;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[365];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TPSC:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char CCLR:2;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MD:4;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOA:4;\r
+ unsigned char IOB:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TGIEA:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char :1;\r
+ unsigned char TTGE:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_mtu3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TPSC:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char CCLR:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MD:4;\r
+ unsigned char BFA:1;\r
+ unsigned char BFB:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOA:4;\r
+ unsigned char IOB:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOC:4;\r
+ unsigned char IOD:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TGIEA:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TTGE:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk3[7];\r
+ unsigned short TCNT;\r
+ char wk4[6];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk5[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk6[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTSA:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSE:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk8[90];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NFAEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCS:2;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu4 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TPSC:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char CCLR:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MD:4;\r
+ unsigned char BFA:1;\r
+ unsigned char BFB:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOA:4;\r
+ unsigned char IOB:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOC:4;\r
+ unsigned char IOD:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TGIEA:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :1;\r
+ unsigned char TTGE2:1;\r
+ unsigned char TTGE:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk4[8];\r
+ unsigned short TCNT;\r
+ char wk5[8];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk6[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk8[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTSA:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSE:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk9[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ITB4VE:1;\r
+ unsigned short ITB3AE:1;\r
+ unsigned short ITA4VE:1;\r
+ unsigned short ITA3AE:1;\r
+ unsigned short DT4BE:1;\r
+ unsigned short UT4BE:1;\r
+ unsigned short DT4AE:1;\r
+ unsigned short UT4AE:1;\r
+ unsigned short :6;\r
+ unsigned short BF:2;\r
+ } BIT;\r
+ } TADCR;\r
+ char wk10[2];\r
+ unsigned short TADCORA;\r
+ unsigned short TADCORB;\r
+ unsigned short TADCOBRA;\r
+ unsigned short TADCOBRB;\r
+ char wk11[72];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NFAEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCS:2;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu5 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NFUEN:1;\r
+ unsigned char NFVEN:1;\r
+ unsigned char NFWEN:1;\r
+ unsigned char :1;\r
+ unsigned char NFCS:2;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[490];\r
+ unsigned short TCNTU;\r
+ unsigned short TGRU;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TPSC:2;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } TCRU;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOC:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } TIORU;\r
+ char wk3[9];\r
+ unsigned short TCNTV;\r
+ unsigned short TGRV;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TPSC:2;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } TCRV;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOC:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } TIORV;\r
+ char wk5[9];\r
+ unsigned short TCNTW;\r
+ unsigned short TGRW;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TPSC:2;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } TCRW;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOC:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } TIORW;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TGIE5W:1;\r
+ unsigned char TGIE5V:1;\r
+ unsigned char TGIE5U:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } TIER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CSTW5:1;\r
+ unsigned char CSTV5:1;\r
+ unsigned char CSTU5:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } TSTR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CMPCLR5W:1;\r
+ unsigned char CMPCLR5V:1;\r
+ unsigned char CMPCLR5U:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } TCNTCMPCLR;\r
+};\r
+\r
+struct st_poe {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char POE0M:2;\r
+ unsigned char POE1M:2;\r
+ unsigned char POE2M:2;\r
+ unsigned char POE3M:2;\r
+ unsigned char PIE1:1;\r
+ unsigned char :3;\r
+ unsigned char POE0F:1;\r
+ unsigned char POE1F:1;\r
+ unsigned char POE2F:1;\r
+ unsigned char POE3F:1;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char OIE1:1;\r
+ unsigned char OCE1:1;\r
+ unsigned char :5;\r
+ unsigned char OSF1:1;\r
+ } BIT;\r
+ } OCSR1;\r
+ char wk0[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char POE8M:2;\r
+ unsigned char :6;\r
+ unsigned char PIE2:1;\r
+ unsigned char POE8E:1;\r
+ unsigned char :2;\r
+ unsigned char POE8F:1;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CH34HIZ:1;\r
+ unsigned char CH0HIZ:1;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } SPOER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PE0ZE:1;\r
+ unsigned char PE1ZE:1;\r
+ unsigned char PE2ZE:1;\r
+ unsigned char PE3ZE:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } POECR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char P3CZEA:1;\r
+ unsigned char P2CZEA:1;\r
+ unsigned char P1CZEA:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } POECR2;\r
+ char wk1[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char OSTSTE:1;\r
+ unsigned char :2;\r
+ unsigned char OSTSTF:1;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } ICSR3;\r
+};\r
+\r
+struct st_port {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL0:1;\r
+ unsigned char PSEL1:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL3:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PSRB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char PSEL6:1;\r
+ unsigned char PSEL7:1;\r
+ } BIT;\r
+ } PSRA;\r
+};\r
+\r
+struct st_port0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[33];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[61];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } ODR0;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port4 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PMR;\r
+};\r
+\r
+struct st_port5 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porta {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :3;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[52];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[42];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :3;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[51];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[43];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[50];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porte {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[45];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[48];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0:1;\r
+ unsigned char B1:1;\r
+ unsigned char B2:1;\r
+ unsigned char B3:1;\r
+ unsigned char B4:1;\r
+ unsigned char B5:1;\r
+ unsigned char B6:1;\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_riic {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SDAI:1;\r
+ unsigned char SCLI:1;\r
+ unsigned char SDAO:1;\r
+ unsigned char SCLO:1;\r
+ unsigned char SOWP:1;\r
+ unsigned char CLO:1;\r
+ unsigned char IICRST:1;\r
+ unsigned char ICE:1;\r
+ } BIT;\r
+ } ICCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ST:1;\r
+ unsigned char RS:1;\r
+ unsigned char SP:1;\r
+ unsigned char :1;\r
+ unsigned char TRS:1;\r
+ unsigned char MST:1;\r
+ unsigned char BBSY:1;\r
+ } BIT;\r
+ } ICCR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BC:3;\r
+ unsigned char BCWP:1;\r
+ unsigned char CKS:3;\r
+ unsigned char MTWP:1;\r
+ } BIT;\r
+ } ICMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TMOS:1;\r
+ unsigned char TMOL:1;\r
+ unsigned char TMOH:1;\r
+ unsigned char TMWE:1;\r
+ unsigned char SDDL:3;\r
+ unsigned char DLCS:1;\r
+ } BIT;\r
+ } ICMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NF:2;\r
+ unsigned char ACKBR:1;\r
+ unsigned char ACKBT:1;\r
+ unsigned char ACKWP:1;\r
+ unsigned char RDRFS:1;\r
+ unsigned char WAIT:1;\r
+ unsigned char SMBS:1;\r
+ } BIT;\r
+ } ICMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TMOE:1;\r
+ unsigned char MALE:1;\r
+ unsigned char NALE:1;\r
+ unsigned char SALE:1;\r
+ unsigned char NACKE:1;\r
+ unsigned char NFE:1;\r
+ unsigned char SCLE:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ICFER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SAR0E:1;\r
+ unsigned char SAR1E:1;\r
+ unsigned char SAR2E:1;\r
+ unsigned char GCAE:1;\r
+ unsigned char :1;\r
+ unsigned char DIDE:1;\r
+ unsigned char :1;\r
+ unsigned char HOAE:1;\r
+ } BIT;\r
+ } ICSER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TMOIE:1;\r
+ unsigned char ALIE:1;\r
+ unsigned char STIE:1;\r
+ unsigned char SPIE:1;\r
+ unsigned char NAKIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char TIE:1;\r
+ } BIT;\r
+ } ICIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char AAS0:1;\r
+ unsigned char AAS1:1;\r
+ unsigned char AAS2:1;\r
+ unsigned char GCA:1;\r
+ unsigned char :1;\r
+ unsigned char DID:1;\r
+ unsigned char :1;\r
+ unsigned char HOA:1;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TMOF:1;\r
+ unsigned char AL:1;\r
+ unsigned char START:1;\r
+ unsigned char STOP:1;\r
+ unsigned char NACKF:1;\r
+ unsigned char RDRF:1;\r
+ unsigned char TEND:1;\r
+ unsigned char TDRE:1;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA0:1;\r
+ unsigned char SVA:7;\r
+ } BIT;\r
+ } SARL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTL;\r
+ };\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FS:1;\r
+ unsigned char SVA:2;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } SARU0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTH;\r
+ };\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA0:1;\r
+ unsigned char SVA:7;\r
+ } BIT;\r
+ } SARL1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FS:1;\r
+ unsigned char SVA:2;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } SARU1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA0:1;\r
+ unsigned char SVA:7;\r
+ } BIT;\r
+ } SARL2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FS:1;\r
+ unsigned char SVA:2;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } SARU2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BRL:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } ICBRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BRH:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } ICBRH;\r
+ unsigned char ICDRT;\r
+ unsigned char ICDRR;\r
+};\r
+\r
+struct st_rspi {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPMS:1;\r
+ unsigned char TXMD:1;\r
+ unsigned char MODFEN:1;\r
+ unsigned char MSTR:1;\r
+ unsigned char SPEIE:1;\r
+ unsigned char SPTIE:1;\r
+ unsigned char SPE:1;\r
+ unsigned char SPRIE:1;\r
+ } BIT;\r
+ } SPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SSL0P:1;\r
+ unsigned char SSL1P:1;\r
+ unsigned char SSL2P:1;\r
+ unsigned char SSL3P:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } SSLP;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPLP:1;\r
+ unsigned char SPLP2:1;\r
+ unsigned char :2;\r
+ unsigned char MOIFV:1;\r
+ unsigned char MOIFE:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } SPPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OVRF:1;\r
+ unsigned char IDLNF:1;\r
+ unsigned char MODF:1;\r
+ unsigned char PERF:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } SPSR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ } WORD;\r
+ } SPDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPSLN:3;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } SPSCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPCP:3;\r
+ unsigned char :1;\r
+ unsigned char SPECM:3;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } SPSSR;\r
+ unsigned char SPBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPFC:2;\r
+ unsigned char :2;\r
+ unsigned char SPRDTD:1;\r
+ unsigned char SPLW:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } SPDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SCKDL:3;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } SPCKD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SLNDL:3;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } SSLND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPNDL:3;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } SPND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPPE:1;\r
+ unsigned char SPOE:1;\r
+ unsigned char SPIIE:1;\r
+ unsigned char PTE:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } SPCR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CPHA:1;\r
+ unsigned short CPOL:1;\r
+ unsigned short BRDV:2;\r
+ unsigned short SSLA:3;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SPB:4;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SCKDEN:1;\r
+ } BIT;\r
+ } SPCMD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CPHA:1;\r
+ unsigned short CPOL:1;\r
+ unsigned short BRDV:2;\r
+ unsigned short SSLA:3;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SPB:4;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SCKDEN:1;\r
+ } BIT;\r
+ } SPCMD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CPHA:1;\r
+ unsigned short CPOL:1;\r
+ unsigned short BRDV:2;\r
+ unsigned short SSLA:3;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SPB:4;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SCKDEN:1;\r
+ } BIT;\r
+ } SPCMD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CPHA:1;\r
+ unsigned short CPOL:1;\r
+ unsigned short BRDV:2;\r
+ unsigned short SSLA:3;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SPB:4;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SCKDEN:1;\r
+ } BIT;\r
+ } SPCMD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CPHA:1;\r
+ unsigned short CPOL:1;\r
+ unsigned short BRDV:2;\r
+ unsigned short SSLA:3;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SPB:4;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SCKDEN:1;\r
+ } BIT;\r
+ } SPCMD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CPHA:1;\r
+ unsigned short CPOL:1;\r
+ unsigned short BRDV:2;\r
+ unsigned short SSLA:3;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SPB:4;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SCKDEN:1;\r
+ } BIT;\r
+ } SPCMD5;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CPHA:1;\r
+ unsigned short CPOL:1;\r
+ unsigned short BRDV:2;\r
+ unsigned short SSLA:3;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SPB:4;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SCKDEN:1;\r
+ } BIT;\r
+ } SPCMD6;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CPHA:1;\r
+ unsigned short CPOL:1;\r
+ unsigned short BRDV:2;\r
+ unsigned short SSLA:3;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SPB:4;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SCKDEN:1;\r
+ } BIT;\r
+ } SPCMD7;\r
+};\r
+\r
+struct st_rtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char F64HZ:1;\r
+ unsigned char F32HZ:1;\r
+ unsigned char F16HZ:1;\r
+ unsigned char F8HZ:1;\r
+ unsigned char F4HZ:1;\r
+ unsigned char F2HZ:1;\r
+ unsigned char F1HZ:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } R64CNT;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SEC1:4;\r
+ unsigned char SEC10:3;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } RSECCNT;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MIN1:4;\r
+ unsigned char MIN10:3;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } RMINCNT;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HR1:4;\r
+ unsigned char HR10:2;\r
+ unsigned char PM:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } RHRCNT;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAYW:3;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } RWKCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DATE1:4;\r
+ unsigned char DATE10:2;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } RDAYCNT;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MON1:4;\r
+ unsigned char MON10:1;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } RMONCNT;\r
+ char wk6[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short YR1:4;\r
+ unsigned short YR10:4;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } RYRCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SEC1:4;\r
+ unsigned char SEC10:3;\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RSECAR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MIN1:4;\r
+ unsigned char MIN10:3;\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RMINAR;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HR1:4;\r
+ unsigned char HR10:2;\r
+ unsigned char PM:1;\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RHRAR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAYW:3;\r
+ unsigned char :4;\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RWKAR;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DATE1:4;\r
+ unsigned char DATE10:2;\r
+ unsigned char :1;\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RDAYAR;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MON1:4;\r
+ unsigned char MON10:1;\r
+ unsigned char :2;\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RMONAR;\r
+ char wk12[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short YR1:4;\r
+ unsigned short YR10:4;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } RYRAR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RYRAREN;\r
+ char wk13[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char AIE:1;\r
+ unsigned char CIE:1;\r
+ unsigned char PIE:1;\r
+ unsigned char RTCOS:1;\r
+ unsigned char PES:4;\r
+ } BIT;\r
+ } RCR1;\r
+ char wk14[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char START:1;\r
+ unsigned char RESET:1;\r
+ unsigned char ADJ30:1;\r
+ unsigned char RTCOE:1;\r
+ unsigned char AADJE:1;\r
+ unsigned char AADJP:1;\r
+ unsigned char HR24:1;\r
+ unsigned char CNTMD:1;\r
+ } BIT;\r
+ } RCR2;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RTCEN:1;\r
+ unsigned char RTCDV:2;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } RCR3;\r
+ char wk16[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ADJ:6;\r
+ unsigned char PMADJ:2;\r
+ } BIT;\r
+ } RADJ;\r
+};\r
+\r
+struct st_rtcb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT0;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT1;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT3;\r
+ char wk3[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT0AR;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT1AR;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT2AR;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT3AR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT0AER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT1AER;\r
+ char wk9[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ENB:8;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } BCNT2AER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT3AER;\r
+};\r
+\r
+struct st_s12ad {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DBLANS:5;\r
+ unsigned short :1;\r
+ unsigned short GBADIE:1;\r
+ unsigned short DBLE:1;\r
+ unsigned short EXTRG:1;\r
+ unsigned short TRGE:1;\r
+ unsigned short ADHSC:1;\r
+ unsigned short :1;\r
+ unsigned short ADIE:1;\r
+ unsigned short ADCS:2;\r
+ unsigned short ADST:1;\r
+ } BIT;\r
+ } ADCSR;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ANSA0:1;\r
+ unsigned short ANSA1:1;\r
+ unsigned short ANSA2:1;\r
+ unsigned short ANSA3:1;\r
+ unsigned short ANSA4:1;\r
+ unsigned short :1;\r
+ unsigned short ANSA6:1;\r
+ unsigned short :1;\r
+ unsigned short ANSA8:1;\r
+ unsigned short ANSA9:1;\r
+ unsigned short ANSA10:1;\r
+ unsigned short ANSA11:1;\r
+ unsigned short ANSA12:1;\r
+ unsigned short ANSA13:1;\r
+ unsigned short ANSA14:1;\r
+ unsigned short ANSA15:1;\r
+ } BIT;\r
+ } ADANSA;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADS0:1;\r
+ unsigned short ADS1:1;\r
+ unsigned short ADS2:1;\r
+ unsigned short ADS3:1;\r
+ unsigned short ADS4:1;\r
+ unsigned short :1;\r
+ unsigned short ADS6:1;\r
+ unsigned short :1;\r
+ unsigned short ADS8:1;\r
+ unsigned short ADS9:1;\r
+ unsigned short ADS10:1;\r
+ unsigned short ADS11:1;\r
+ unsigned short ADS12:1;\r
+ unsigned short ADS13:1;\r
+ unsigned short ADS14:1;\r
+ unsigned short ADS15:1;\r
+ } BIT;\r
+ } ADADS;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ADC:2;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } ADADC;\r
+ char wk3[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ACE:1;\r
+ unsigned short :9;\r
+ unsigned short ADRFMT:1;\r
+ } BIT;\r
+ } ADCER;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TRSB:4;\r
+ unsigned short :4;\r
+ unsigned short TRSA:4;\r
+ unsigned short :4;\r
+ } BIT;\r
+ } ADSTRGR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :1;\r
+ unsigned short OCSAD:1;\r
+ unsigned short :6;\r
+ unsigned short TSS:1;\r
+ unsigned short OCS:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } ADEXICR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ANSB0:1;\r
+ unsigned short ANSB1:1;\r
+ unsigned short ANSB2:1;\r
+ unsigned short ANSB3:1;\r
+ unsigned short ANSB4:1;\r
+ unsigned short :1;\r
+ unsigned short ANSB6:1;\r
+ unsigned short :1;\r
+ unsigned short ANSB8:1;\r
+ unsigned short ANSB9:1;\r
+ unsigned short ANSB10:1;\r
+ unsigned short ANSB11:1;\r
+ unsigned short ANSB12:1;\r
+ unsigned short ANSB13:1;\r
+ unsigned short ANSB14:1;\r
+ unsigned short ANSB15:1;\r
+ } BIT;\r
+ } ADANSB;\r
+ char wk4[2];\r
+ unsigned short ADDBLDR;\r
+ unsigned short ADTSDR;\r
+ unsigned short ADOCDR;\r
+ char wk5[2];\r
+ unsigned short ADDR0;\r
+ unsigned short ADDR1;\r
+ unsigned short ADDR2;\r
+ unsigned short ADDR3;\r
+ unsigned short ADDR4;\r
+ char wk6[2];\r
+ unsigned short ADDR6;\r
+ char wk7[2];\r
+ unsigned short ADDR8;\r
+ unsigned short ADDR9;\r
+ unsigned short ADDR10;\r
+ unsigned short ADDR11;\r
+ unsigned short ADDR12;\r
+ unsigned short ADDR13;\r
+ unsigned short ADDR14;\r
+ unsigned short ADDR15;\r
+ char wk8[32];\r
+ unsigned char ADSSTR0;\r
+ unsigned char ADSSTRL;\r
+ char wk9[14];\r
+ unsigned char ADSSTRT;\r
+ unsigned char ADSSTRO;\r
+ char wk10[1];\r
+ unsigned char ADSSTR1;\r
+ unsigned char ADSSTR2;\r
+ unsigned char ADSSTR3;\r
+ unsigned char ADSSTR4;\r
+ char wk11[1];\r
+ unsigned char ADSSTR6;\r
+};\r
+\r
+struct st_sci1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKS:2;\r
+ unsigned char MP:1;\r
+ unsigned char STOP:1;\r
+ unsigned char PM:1;\r
+ unsigned char PE:1;\r
+ unsigned char CHR:1;\r
+ unsigned char CM:1;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKE:2;\r
+ unsigned char TEIE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char RE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TIE:1;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MPBT:1;\r
+ unsigned char MPB:1;\r
+ unsigned char TEND:1;\r
+ unsigned char PER:1;\r
+ unsigned char FER:1;\r
+ unsigned char ORER:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SMIF:1;\r
+ unsigned char :1;\r
+ unsigned char SINV:1;\r
+ unsigned char SDIR:1;\r
+ unsigned char :3;\r
+ unsigned char BCP2:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char ABCS:1;\r
+ unsigned char NFEN:1;\r
+ unsigned char :1;\r
+ unsigned char RXDESEL:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NFCS:3;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICM:1;\r
+ unsigned char :2;\r
+ unsigned char IICDL:5;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICINTM:1;\r
+ unsigned char IICCSC:1;\r
+ unsigned char :3;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSTAREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSCLS:2;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICACKR:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SSE:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char MSS:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char CKPH:1;\r
+ } BIT;\r
+ } SPMR;\r
+};\r
+\r
+struct st_sci12 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKS:2;\r
+ unsigned char MP:1;\r
+ unsigned char STOP:1;\r
+ unsigned char PM:1;\r
+ unsigned char PE:1;\r
+ unsigned char CHR:1;\r
+ unsigned char CM:1;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKE:2;\r
+ unsigned char TEIE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char RE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TIE:1;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MPBT:1;\r
+ unsigned char MPB:1;\r
+ unsigned char TEND:1;\r
+ unsigned char PER:1;\r
+ unsigned char FER:1;\r
+ unsigned char ORER:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SMIF:1;\r
+ unsigned char :1;\r
+ unsigned char SINV:1;\r
+ unsigned char SDIR:1;\r
+ unsigned char :3;\r
+ unsigned char BCP2:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char ABCS:1;\r
+ unsigned char NFEN:1;\r
+ unsigned char :1;\r
+ unsigned char RXDESEL:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NFCS:3;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICM:1;\r
+ unsigned char :2;\r
+ unsigned char IICDL:5;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICINTM:1;\r
+ unsigned char IICCSC:1;\r
+ unsigned char :3;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSTAREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSCLS:2;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICACKR:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SSE:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char MSS:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char CKPH:1;\r
+ } BIT;\r
+ } SPMR;\r
+ char wk0[18];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ESME:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } ESMER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SFSF:1;\r
+ unsigned char RXDSF:1;\r
+ unsigned char BRME:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BFE:1;\r
+ unsigned char CF0RE:1;\r
+ unsigned char CF1DS:2;\r
+ unsigned char PIBE:1;\r
+ unsigned char PIBS:3;\r
+ } BIT;\r
+ } CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DFCS:3;\r
+ unsigned char :1;\r
+ unsigned char BCCS:2;\r
+ unsigned char RTS:2;\r
+ } BIT;\r
+ } CR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SDST:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } CR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TXDXPS:1;\r
+ unsigned char RXDXPS:1;\r
+ unsigned char :2;\r
+ unsigned char SHARPS:1;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BFDIE:1;\r
+ unsigned char CF0MIE:1;\r
+ unsigned char CF1MIE:1;\r
+ unsigned char PIBDIE:1;\r
+ unsigned char BCDIE:1;\r
+ unsigned char AEDIE:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } ICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BFDF:1;\r
+ unsigned char CF0MF:1;\r
+ unsigned char CF1MF:1;\r
+ unsigned char PIBDF:1;\r
+ unsigned char BCDF:1;\r
+ unsigned char AEDF:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } STR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BFDCL:1;\r
+ unsigned char CF0MCL:1;\r
+ unsigned char CF1MCL:1;\r
+ unsigned char PIBDCL:1;\r
+ unsigned char BCDCL:1;\r
+ unsigned char AEDCL:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } STCR;\r
+ unsigned char CF0DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF0CE0:1;\r
+ unsigned char CF0CE1:1;\r
+ unsigned char CF0CE2:1;\r
+ unsigned char CF0CE3:1;\r
+ unsigned char CF0CE4:1;\r
+ unsigned char CF0CE5:1;\r
+ unsigned char CF0CE6:1;\r
+ unsigned char CF0CE7:1;\r
+ } BIT;\r
+ } CF0CR;\r
+ unsigned char CF0RR;\r
+ unsigned char PCF1DR;\r
+ unsigned char SCF1DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF1CE0:1;\r
+ unsigned char CF1CE1:1;\r
+ unsigned char CF1CE2:1;\r
+ unsigned char CF1CE3:1;\r
+ unsigned char CF1CE4:1;\r
+ unsigned char CF1CE5:1;\r
+ unsigned char CF1CE6:1;\r
+ unsigned char CF1CE7:1;\r
+ } BIT;\r
+ } CF1CR;\r
+ unsigned char CF1RR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCST:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TOMS:2;\r
+ unsigned char :1;\r
+ unsigned char TWRC:1;\r
+ unsigned char TCSS:3;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } TMR;\r
+ unsigned char TPRE;\r
+ unsigned char TCNT;\r
+};\r
+\r
+struct st_smci {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKS:2;\r
+ unsigned char BCP:2;\r
+ unsigned char PM:1;\r
+ unsigned char PE:1;\r
+ unsigned char BLK:1;\r
+ unsigned char GM:1;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKE:2;\r
+ unsigned char TEIE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char RE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TIE:1;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MPBT:1;\r
+ unsigned char MPB:1;\r
+ unsigned char TEND:1;\r
+ unsigned char PER:1;\r
+ unsigned char ERS:1;\r
+ unsigned char ORER:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SMIF:1;\r
+ unsigned char :1;\r
+ unsigned char SINV:1;\r
+ unsigned char SDIR:1;\r
+ unsigned char :3;\r
+ unsigned char BCP2:1;\r
+ } BIT;\r
+ } SCMR;\r
+};\r
+\r
+struct st_system {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short MD:1;\r
+ unsigned short :15;\r
+ } BIT;\r
+ } MDMONR;\r
+ char wk0[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RAME:1;\r
+ unsigned short :15;\r
+ } BIT;\r
+ } SYSCR1;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short SSBY:1;\r
+ } BIT;\r
+ } SBYCR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :9;\r
+ unsigned long MSTPA9:1;\r
+ unsigned long :5;\r
+ unsigned long MSTPA15:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA17:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA19:1;\r
+ unsigned long :8;\r
+ unsigned long MSTPA28:1;\r
+ unsigned long :3;\r
+ } BIT;\r
+ } MSTPCRA;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :4;\r
+ unsigned long MSTPB4:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB6:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPB9:1;\r
+ unsigned long :7;\r
+ unsigned long MSTPB17:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB21:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB23:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPB26:1;\r
+ unsigned long :3;\r
+ unsigned long MSTPB30:1;\r
+ unsigned long :1;\r
+ } BIT;\r
+ } MSTPCRB;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long MSTPC0:1;\r
+ unsigned long :18;\r
+ unsigned long MSTPC19:1;\r
+ unsigned long :11;\r
+ unsigned long DSLPE:1;\r
+ } BIT;\r
+ } MSTPCRC;\r
+ char wk3[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long PCKD:4;\r
+ unsigned long :4;\r
+ unsigned long PCKB:4;\r
+ unsigned long :12;\r
+ unsigned long ICK:4;\r
+ unsigned long FCK:4;\r
+ } BIT;\r
+ } SCKCR;\r
+ char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CKSEL:3;\r
+ unsigned short :5;\r
+ } BIT;\r
+ } SCKCR3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PLIDIV:2;\r
+ unsigned short :6;\r
+ unsigned short STC:6;\r
+ unsigned short :2;\r
+ } BIT;\r
+ } PLLCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PLLEN:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } PLLCR2;\r
+ char wk5[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MOSTP:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } MOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SOSTP:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } SOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LCSTP:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } LOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ILCSTP:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } ILOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HCSTP:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } HOCOCR;\r
+ char wk6[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MOOVF:1;\r
+ unsigned char :1;\r
+ unsigned char PLOVF:1;\r
+ unsigned char HCOVF:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } OSCOVFSR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CKOSEL:3;\r
+ unsigned short :1;\r
+ unsigned short CKODIV:3;\r
+ unsigned short CKOSTP:1;\r
+ } BIT;\r
+ } CKOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OSTDIE:1;\r
+ unsigned char :6;\r
+ unsigned char OSTDE:1;\r
+ } BIT;\r
+ } OSTDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OSTDF:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } OSTDSR;\r
+ char wk8[94];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OPCM:3;\r
+ unsigned char :1;\r
+ unsigned char OPCMTSF:1;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } OPCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTCKSEL:3;\r
+ unsigned char :4;\r
+ unsigned char RSTCKEN:1;\r
+ } BIT;\r
+ } RSTCKCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MSTS:5;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } MOSCWTCR;\r
+ char wk9[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SOPCM:1;\r
+ unsigned char :3;\r
+ unsigned char SOPCMTSF:1;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } SOPCCR;\r
+ char wk10[21];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IWDTRF:1;\r
+ unsigned char :1;\r
+ unsigned char SWRF:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } RSTSR2;\r
+ char wk11[1];\r
+ unsigned short SWRR;\r
+ char wk12[28];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD1IDTSEL:2;\r
+ unsigned char LVD1IRQSEL:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } LVD1CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD1DET:1;\r
+ unsigned char LVD1MON:1;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } LVD1SR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD2IDTSEL:2;\r
+ unsigned char LVD2IRQSEL:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } LVD2CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD2DET:1;\r
+ unsigned char LVD2MON:1;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } LVD2SR;\r
+ char wk13[794];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRC0:1;\r
+ unsigned short PRC1:1;\r
+ unsigned short :1;\r
+ unsigned short PRC3:1;\r
+ unsigned short :4;\r
+ unsigned short PRKEY:8;\r
+ } BIT;\r
+ } PRCR;\r
+ char wk14[48784];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PORF:1;\r
+ unsigned char :1;\r
+ unsigned char LVD1RF:1;\r
+ unsigned char LVD2RF:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } RSTSR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CWSF:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } RSTSR1;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MODRV21:1;\r
+ unsigned char MOSEL:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } MOFCR;\r
+ char wk16[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char EXVCCINP2:1;\r
+ unsigned char :1;\r
+ unsigned char LVD1E:1;\r
+ unsigned char LVD2E:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } LVCMPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD1LVL:4;\r
+ unsigned char LVD2LVL:2;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } LVDLVLR;\r
+ char wk17[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD1RIE:1;\r
+ unsigned char :1;\r
+ unsigned char LVD1CMPE:1;\r
+ unsigned char :3;\r
+ unsigned char LVD1RI:1;\r
+ unsigned char LVD1RN:1;\r
+ } BIT;\r
+ } LVD1CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD2RIE:1;\r
+ unsigned char :1;\r
+ unsigned char LVD2CMPE:1;\r
+ unsigned char :3;\r
+ unsigned char LVD2RI:1;\r
+ unsigned char LVD2RN:1;\r
+ } BIT;\r
+ } LVD2CR0;\r
+};\r
+\r
+struct st_usb {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short USBE:1;\r
+ unsigned short :3;\r
+ unsigned short DPRPU:1;\r
+ unsigned short DRPD:1;\r
+ unsigned short DCFM:1;\r
+ unsigned short :1;\r
+ unsigned short CNEN:1;\r
+ unsigned short :1;\r
+ unsigned short SCKE:1;\r
+ unsigned short :5;\r
+ } BIT;\r
+ } SYSCFG;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short LNST:2;\r
+ unsigned short IDMON:1;\r
+ unsigned short :3;\r
+ unsigned short HTACT:1;\r
+ unsigned short :7;\r
+ unsigned short OVCMON:2;\r
+ } BIT;\r
+ } SYSSTS0;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RHST:3;\r
+ unsigned short :1;\r
+ unsigned short UACT:1;\r
+ unsigned short RESUME:1;\r
+ unsigned short USBRST:1;\r
+ unsigned short RWUPE:1;\r
+ unsigned short WKUP:1;\r
+ unsigned short VBUSEN:1;\r
+ unsigned short EXICEN:1;\r
+ unsigned short HNPBTOA:1;\r
+ unsigned short :4;\r
+ } BIT;\r
+ } DVSTCTR0;\r
+ char wk2[10];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } CFIFO;\r
+ char wk3[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D0FIFO;\r
+ char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D1FIFO;\r
+ char wk5[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CURPIPE:4;\r
+ unsigned short :1;\r
+ unsigned short ISEL:1;\r
+ unsigned short :2;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :3;\r
+ unsigned short REW:1;\r
+ unsigned short RCNT:1;\r
+ } BIT;\r
+ } CFIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DTLN:9;\r
+ unsigned short :4;\r
+ unsigned short FRDY:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short BVAL:1;\r
+ } BIT;\r
+ } CFIFOCTR;\r
+ char wk6[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CURPIPE:4;\r
+ unsigned short :4;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short DREQE:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short REW:1;\r
+ unsigned short RCNT:1;\r
+ } BIT;\r
+ } D0FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DTLN:9;\r
+ unsigned short :4;\r
+ unsigned short FRDY:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short BVAL:1;\r
+ } BIT;\r
+ } D0FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CURPIPE:4;\r
+ unsigned short :4;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short DREQE:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short REW:1;\r
+ unsigned short RCNT:1;\r
+ } BIT;\r
+ } D1FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DTLN:9;\r
+ unsigned short :4;\r
+ unsigned short FRDY:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short BVAL:1;\r
+ } BIT;\r
+ } D1FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BRDYE:1;\r
+ unsigned short NRDYE:1;\r
+ unsigned short BEMPE:1;\r
+ unsigned short CTRE:1;\r
+ unsigned short DVSE:1;\r
+ unsigned short SOFE:1;\r
+ unsigned short RSME:1;\r
+ unsigned short VBSE:1;\r
+ } BIT;\r
+ } INTENB0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PDDETINTE0:1;\r
+ unsigned short :3;\r
+ unsigned short SACKE:1;\r
+ unsigned short SIGNE:1;\r
+ unsigned short EOFERRE:1;\r
+ unsigned short :4;\r
+ unsigned short ATTCHE:1;\r
+ unsigned short DTCHE:1;\r
+ unsigned short :1;\r
+ unsigned short BCHGE:1;\r
+ unsigned short OVRCRE:1;\r
+ } BIT;\r
+ } INTENB1;\r
+ char wk7[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PIPE0BRDYE:1;\r
+ unsigned short PIPE1BRDYE:1;\r
+ unsigned short PIPE2BRDYE:1;\r
+ unsigned short PIPE3BRDYE:1;\r
+ unsigned short PIPE4BRDYE:1;\r
+ unsigned short PIPE5BRDYE:1;\r
+ unsigned short PIPE6BRDYE:1;\r
+ unsigned short PIPE7BRDYE:1;\r
+ unsigned short PIPE8BRDYE:1;\r
+ unsigned short PIPE9BRDYE:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } BRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PIPE0NRDYE:1;\r
+ unsigned short PIPE1NRDYE:1;\r
+ unsigned short PIPE2NRDYE:1;\r
+ unsigned short PIPE3NRDYE:1;\r
+ unsigned short PIPE4NRDYE:1;\r
+ unsigned short PIPE5NRDYE:1;\r
+ unsigned short PIPE6NRDYE:1;\r
+ unsigned short PIPE7NRDYE:1;\r
+ unsigned short PIPE8NRDYE:1;\r
+ unsigned short PIPE9NRDYE:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } NRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PIPE0BEMPE:1;\r
+ unsigned short PIPE1BEMPE:1;\r
+ unsigned short PIPE2BEMPE:1;\r
+ unsigned short PIPE3BEMPE:1;\r
+ unsigned short PIPE4BEMPE:1;\r
+ unsigned short PIPE5BEMPE:1;\r
+ unsigned short PIPE6BEMPE:1;\r
+ unsigned short PIPE7BEMPE:1;\r
+ unsigned short PIPE8BEMPE:1;\r
+ unsigned short PIPE9BEMPE:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } BEMPENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4; /* FIXME: Double check pad bits here*/\r
+ unsigned short EDGESTS:1;\r
+ unsigned short :1;\r
+ unsigned short BRDYM:1;\r
+ unsigned short :1;\r
+ unsigned short TRNENSEL:1;\r
+ unsigned short :7;\r
+ } BIT;\r
+ } SOFCFG;\r
+ char wk8[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CTSQ:3;\r
+ unsigned short VALID:1;\r
+ unsigned short DVSQ:3;\r
+ unsigned short VBSTS:1;\r
+ unsigned short BRDY:1;\r
+ unsigned short NRDY:1;\r
+ unsigned short BEMP:1;\r
+ unsigned short CTRT:1;\r
+ unsigned short DVST:1;\r
+ unsigned short SOFR:1;\r
+ unsigned short RESM:1;\r
+ unsigned short VBINT:1;\r
+ } BIT;\r
+ } INTSTS0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PDDETINT0:1;\r
+ unsigned short :3;\r
+ unsigned short SACK:1;\r
+ unsigned short SIGN:1;\r
+ unsigned short EOFERR:1;\r
+ unsigned short :4;\r
+ unsigned short ATTCH:1;\r
+ unsigned short DTCH:1;\r
+ unsigned short :1;\r
+ unsigned short BCHG:1;\r
+ unsigned short OVRCR:1;\r
+ } BIT;\r
+ } INTSTS1;\r
+ char wk9[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PIPE0BRDY:1;\r
+ unsigned short PIPE1BRDY:1;\r
+ unsigned short PIPE2BRDY:1;\r
+ unsigned short PIPE3BRDY:1;\r
+ unsigned short PIPE4BRDY:1;\r
+ unsigned short PIPE5BRDY:1;\r
+ unsigned short PIPE6BRDY:1;\r
+ unsigned short PIPE7BRDY:1;\r
+ unsigned short PIPE8BRDY:1;\r
+ unsigned short PIPE9BRDY:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } BRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PIPE0NRDY:1;\r
+ unsigned short PIPE1NRDY:1;\r
+ unsigned short PIPE2NRDY:1;\r
+ unsigned short PIPE3NRDY:1;\r
+ unsigned short PIPE4NRDY:1;\r
+ unsigned short PIPE5NRDY:1;\r
+ unsigned short PIPE6NRDY:1;\r
+ unsigned short PIPE7NRDY:1;\r
+ unsigned short PIPE8NRDY:1;\r
+ unsigned short PIPE9NRDY:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } NRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PIPE0BEMP:1;\r
+ unsigned short PIPE1BEMP:1;\r
+ unsigned short PIPE2BEMP:1;\r
+ unsigned short PIPE3BEMP:1;\r
+ unsigned short PIPE4BEMP:1;\r
+ unsigned short PIPE5BEMP:1;\r
+ unsigned short PIPE6BEMP:1;\r
+ unsigned short PIPE7BEMP:1;\r
+ unsigned short PIPE8BEMP:1;\r
+ unsigned short PIPE9BEMP:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } BEMPSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FRNM:11;\r
+ unsigned short :3;\r
+ unsigned short CRCE:1;\r
+ unsigned short OVRN:1;\r
+ } BIT;\r
+ } FRMNUM;\r
+ char wk10[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BMREQUESTTYPE:8;\r
+ unsigned short BREQUEST:8;\r
+ } BIT;\r
+ } USBREQ;\r
+ unsigned short USBVAL;\r
+ unsigned short USBINDX;\r
+ unsigned short USBLENG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4; /* FIXME: Double check pad bits here. */\r
+ unsigned short DIR:1;\r
+ unsigned short :2;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } DCPCFG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short MXPS:7;\r
+ unsigned short :5;\r
+ unsigned short DEVSEL:4;\r
+ } BIT;\r
+ } DCPMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PID:2;\r
+ unsigned short CCPL:1;\r
+ unsigned short :2;\r
+ unsigned short PBUSY:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short :2;\r
+ unsigned short SUREQCLR:1;\r
+ unsigned short :2;\r
+ unsigned short SUREQ:1;\r
+ unsigned short BSTS:1;\r
+ } BIT;\r
+ } DCPCTR;\r
+ char wk11[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PIPESEL:4;\r
+ unsigned short :12;\r
+ } BIT;\r
+ } PIPESEL;\r
+ char wk12[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short EPNUM:4;\r
+ unsigned short DIR:1;\r
+ unsigned short :2;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :1;\r
+ unsigned short DBLB:1;\r
+ unsigned short BFRE:1;\r
+ unsigned short :3;\r
+ unsigned short TYPE:2;\r
+ } BIT;\r
+ } PIPECFG;\r
+ char wk13[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short MXPS:9;\r
+ unsigned short :3;\r
+ unsigned short DEVSEL:4;\r
+ } BIT;\r
+ } PIPEMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short IITV:3;\r
+ unsigned short :9;\r
+ unsigned short IFIS:1;\r
+ unsigned short :3;\r
+ } BIT;\r
+ } PIPEPERI;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PID:2;\r
+ unsigned short :3;\r
+ unsigned short PBUSY:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short ATREPM:1;\r
+ unsigned short :3;\r
+ unsigned short INBUFM:1;\r
+ unsigned short BSTS:1;\r
+ } BIT;\r
+ } PIPE1CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PID:2;\r
+ unsigned short :3;\r
+ unsigned short PBUSY:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short ATREPM:1;\r
+ unsigned short :3;\r
+ unsigned short INBUFM:1;\r
+ unsigned short BSTS:1;\r
+ } BIT;\r
+ } PIPE2CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PID:2;\r
+ unsigned short :3;\r
+ unsigned short PBUSY:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short ATREPM:1;\r
+ unsigned short :3;\r
+ unsigned short INBUFM:1;\r
+ unsigned short BSTS:1;\r
+ } BIT;\r
+ } PIPE3CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PID:2;\r
+ unsigned short :3;\r
+ unsigned short PBUSY:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short ATREPM:1;\r
+ unsigned short :3;\r
+ unsigned short INBUFM:1;\r
+ unsigned short BSTS:1;\r
+ } BIT;\r
+ } PIPE4CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PID:2;\r
+ unsigned short :3;\r
+ unsigned short PBUSY:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short ATREPM:1;\r
+ unsigned short :3;\r
+ unsigned short INBUFM:1;\r
+ unsigned short BSTS:1;\r
+ } BIT;\r
+ } PIPE5CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PID:2;\r
+ unsigned short :3;\r
+ unsigned short PBUSY:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short :5;\r
+ unsigned short BSTS:1;\r
+ } BIT;\r
+ } PIPE6CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PID:2;\r
+ unsigned short :3;\r
+ unsigned short PBUSY:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short :5;\r
+ unsigned short BSTS:1;\r
+ } BIT;\r
+ } PIPE7CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PID:2;\r
+ unsigned short :3;\r
+ unsigned short PBUSY:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short :5;\r
+ unsigned short BSTS:1;\r
+ } BIT;\r
+ } PIPE8CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PID:2;\r
+ unsigned short :3;\r
+ unsigned short PBUSY:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short :5;\r
+ unsigned short BSTS:1;\r
+ } BIT;\r
+ } PIPE9CTR;\r
+ char wk14[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TRCLR:1;\r
+ unsigned short TRENB:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } PIPE1TRE;\r
+ unsigned short PIPE1TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TRCLR:1;\r
+ unsigned short TRENB:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } PIPE2TRE;\r
+ unsigned short PIPE2TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TRCLR:1;\r
+ unsigned short TRENB:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } PIPE3TRE;\r
+ unsigned short PIPE3TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TRCLR:1;\r
+ unsigned short TRENB:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } PIPE4TRE;\r
+ unsigned short PIPE4TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TRCLR:1;\r
+ unsigned short TRENB:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } PIPE5TRE;\r
+ unsigned short PIPE5TRN;\r
+ char wk15[12];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RPDME0:1;\r
+ unsigned short IDPSRCE0:1;\r
+ unsigned short IDMSINKE0:1;\r
+ unsigned short VDPSRCE0:1;\r
+ unsigned short IDPSINKE0:1;\r
+ unsigned short VDMSRCE0:1;\r
+ unsigned short DCPMODE0:1;\r
+ unsigned short BATCHGE0:1;\r
+ unsigned short CHGDETSTS0:1;\r
+ unsigned short PDDETSTS0:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } USBBCCTRL0;\r
+ char wk16[26];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VDDUSBE:1;\r
+ unsigned short :6;\r
+ unsigned short VBRPDCUT:1;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } USBMC;\r
+ char wk17[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6; /* FIXME: Double check pad bits here. */\r
+ unsigned short USBSPD:2;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } DEVADD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6; /* FIXME: Double check pad bits here. */\r
+ unsigned short USBSPD:2;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } DEVADD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6; /* FIXME: Double check pad bits here. */\r
+ unsigned short USBSPD:2;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } DEVADD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6; /* FIXME: Double check pad bits here. */\r
+ unsigned short USBSPD:2;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } DEVADD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6; /* FIXME: Double check pad bits here. */\r
+ unsigned short USBSPD:2;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } DEVADD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6; /* FIXME: Double check pad bits here. */\r
+ unsigned short USBSPD:2;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } DEVADD5;\r
+};\r
+\r
+#elif __RX_BIG_ENDIAN__ /*Big endian*/\r
+\r
+struct st_bsc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char STSCLR:1;\r
+ } BIT;\r
+ } BERCLR;\r
+ char wk0[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IGAEN:1;\r
+ } BIT;\r
+ } BEREN;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MST:3;\r
+ unsigned char :3;\r
+ unsigned char IA:1;\r
+ } BIT;\r
+ } BERSR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADDR:13;\r
+ } BIT;\r
+ } BERSR2;\r
+ char wk3[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short BPFB:2;\r
+ unsigned short :2;\r
+ unsigned short BPGB:2;\r
+ unsigned short BPIB:2;\r
+ unsigned short BPRO:2;\r
+ unsigned short BPRA:2;\r
+ } BIT;\r
+ } BUSPRI;\r
+};\r
+\r
+struct st_cac {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CFME:1;\r
+ } BIT;\r
+ } CACR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char EDGES:2;\r
+ unsigned char TCSS:2;\r
+ unsigned char FMCS:3;\r
+ unsigned char CACREFE:1;\r
+ } BIT;\r
+ } CACR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DFS:2;\r
+ unsigned char RCDS:2;\r
+ unsigned char RSCS:3;\r
+ unsigned char RPS:1;\r
+ } BIT;\r
+ } CACR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char OVFFCL:1;\r
+ unsigned char MENDFCL:1;\r
+ unsigned char FERRFCL:1;\r
+ unsigned char :1;\r
+ unsigned char OVFIE:1;\r
+ unsigned char MENDIE:1;\r
+ unsigned char FERRIE:1;\r
+ } BIT;\r
+ } CAICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char OVFF:1;\r
+ unsigned char MENDF:1;\r
+ unsigned char FERRF:1;\r
+ } BIT;\r
+ } CASTR;\r
+ char wk0[1];\r
+ unsigned short CAULVR;\r
+ unsigned short CALLVR;\r
+ unsigned short CACNTBR;\r
+};\r
+\r
+struct st_cmt {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :14;\r
+ unsigned short STR1:1;\r
+ unsigned short STR0:1;\r
+ } BIT;\r
+ } CMSTR0;\r
+};\r
+\r
+struct st_cmt0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :9;\r
+ unsigned short CMIE:1;\r
+ unsigned short :4;\r
+ unsigned short CKS:2;\r
+ } BIT;\r
+ } CMCR;\r
+ unsigned short CMCNT;\r
+ unsigned short CMCOR;\r
+};\r
+\r
+struct st_crc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DORCLR:1;\r
+ unsigned char :4;\r
+ unsigned char LMS:1;\r
+ unsigned char GPS:2;\r
+ } BIT;\r
+ } CRCCR;\r
+ unsigned char CRCDIR;\r
+ unsigned short CRCDOR;\r
+};\r
+\r
+struct st_da {\r
+ unsigned short DADR0;\r
+ unsigned short DADR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAOE1:1;\r
+ unsigned char DAOE0:1;\r
+ } BIT;\r
+ } DACR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSEL:1;\r
+ } BIT;\r
+ } DADPR;\r
+};\r
+\r
+struct st_doc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char DOPCFCL:1;\r
+ unsigned char DOPCF:1;\r
+ unsigned char DOPCIE:1;\r
+ unsigned char :1;\r
+ unsigned char DCSEL:1;\r
+ unsigned char OMS:2;\r
+ } BIT;\r
+ } DOCR;\r
+ char wk0[1];\r
+ unsigned short DODIR;\r
+ unsigned short DODSR;\r
+};\r
+\r
+struct st_dtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char RRS:1;\r
+ } BIT;\r
+ } DTCCR;\r
+ char wk0[3];\r
+ void *DTCVBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SHORT:1;\r
+ } BIT;\r
+ } DTCADMOD;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCST:1;\r
+ } BIT;\r
+ } DTCST;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ACT:1;\r
+ unsigned short :7;\r
+ unsigned short VECN:8;\r
+ } BIT;\r
+ } DTCSTS;\r
+};\r
+\r
+struct st_elc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ELCON:1;\r
+ } BIT;\r
+ } ELCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ELS:8;\r
+ } BIT;\r
+ } ELSR[26];\r
+ char wk0[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTU3MD:2;\r
+ unsigned char MTU2MD:2;\r
+ unsigned char MTU1MD:2;\r
+ } BIT;\r
+ } ELOPA;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char MTU4MD:2;\r
+ } BIT;\r
+ } ELOPB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char CMT1MD:2;\r
+ } BIT;\r
+ } ELOPC;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PGR7:1;\r
+ unsigned char PGR6:1;\r
+ unsigned char PGR5:1;\r
+ unsigned char PGR4:1;\r
+ unsigned char PGR3:1;\r
+ unsigned char PGR2:1;\r
+ unsigned char PGR1:1;\r
+ unsigned char PGR0:1;\r
+ } BIT;\r
+ } PGR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PGCO:3;\r
+ unsigned char :1;\r
+ unsigned char PGCOVE:1;\r
+ unsigned char PGCI:2;\r
+ } BIT;\r
+ } PGC1;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PDBF7:1;\r
+ unsigned char PDBF6:1;\r
+ unsigned char PDBF5:1;\r
+ unsigned char PDBF4:1;\r
+ unsigned char PDBF3:1;\r
+ unsigned char PDBF2:1;\r
+ unsigned char PDBF1:1;\r
+ unsigned char PDBF0:1;\r
+ } BIT;\r
+ } PDBF1;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSM:2;\r
+ unsigned char PSP:2;\r
+ unsigned char PSB:3;\r
+ } BIT;\r
+ } PEL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSM:2;\r
+ unsigned char PSP:2;\r
+ unsigned char PSB:3;\r
+ } BIT;\r
+ } PEL1;\r
+ char wk5[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char WI:1;\r
+ unsigned char WE:1;\r
+ unsigned char :5;\r
+ unsigned char SEG:1;\r
+ } BIT;\r
+ } ELSEGR;\r
+};\r
+\r
+struct st_flash {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DFLEN:1;\r
+ } BIT;\r
+ } DFLCTL;\r
+};\r
+\r
+struct st_icu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IR:1;\r
+ } BIT;\r
+ } IR[250];\r
+ char wk0[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCE:1;\r
+ } BIT;\r
+ } DTCER[249];\r
+ char wk1[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IEN7:1;\r
+ unsigned char IEN6:1;\r
+ unsigned char IEN5:1;\r
+ unsigned char IEN4:1;\r
+ unsigned char IEN3:1;\r
+ unsigned char IEN2:1;\r
+ unsigned char IEN1:1;\r
+ unsigned char IEN0:1;\r
+ } BIT;\r
+ } IER[32];\r
+ char wk2[192];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SWINT:1;\r
+ } BIT;\r
+ } SWINTR;\r
+ char wk3[15];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FIEN:1;\r
+ unsigned short :7;\r
+ unsigned short FVCT:8;\r
+ } BIT;\r
+ } FIR;\r
+ char wk4[14];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IPR:4;\r
+ } BIT;\r
+ } IPR[250];\r
+ char wk5[262];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IRQMD:2;\r
+ } BIT;\r
+ } IRQCR[8];\r
+ char wk6[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FLTEN7:1;\r
+ unsigned char FLTEN6:1;\r
+ unsigned char FLTEN5:1;\r
+ unsigned char FLTEN4:1;\r
+ unsigned char FLTEN3:1;\r
+ unsigned char FLTEN2:1;\r
+ unsigned char FLTEN1:1;\r
+ unsigned char FLTEN0:1;\r
+ } BIT;\r
+ } IRQFLTE0;\r
+ char wk7[3];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FCLKSEL7:2;\r
+ unsigned short FCLKSEL6:2;\r
+ unsigned short FCLKSEL5:2;\r
+ unsigned short FCLKSEL4:2;\r
+ unsigned short FCLKSEL3:2;\r
+ unsigned short FCLKSEL2:2;\r
+ unsigned short FCLKSEL1:2;\r
+ unsigned short FCLKSEL0:2;\r
+ } BIT;\r
+ } IRQFLTC0;\r
+ char wk8[106];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2ST:1;\r
+ unsigned char LVD1ST:1;\r
+ unsigned char IWDTST:1;\r
+ unsigned char :1;\r
+ unsigned char OSTST:1;\r
+ unsigned char NMIST:1;\r
+ } BIT;\r
+ } NMISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2EN:1;\r
+ unsigned char LVD1EN:1;\r
+ unsigned char IWDTEN:1;\r
+ unsigned char :1;\r
+ unsigned char OSTEN:1;\r
+ unsigned char NMIEN:1;\r
+ } BIT;\r
+ } NMIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2CLR:1;\r
+ unsigned char LVD1CLR:1;\r
+ unsigned char IWDTCLR:1;\r
+ unsigned char :1;\r
+ unsigned char OSTCLR:1;\r
+ unsigned char NMICLR:1;\r
+ } BIT;\r
+ } NMICLR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NMIMD:1;\r
+ } BIT;\r
+ } NMICR;\r
+ char wk9[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char NFLTEN:1;\r
+ } BIT;\r
+ } NMIFLTE;\r
+ char wk10[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char NFCLKSEL:2;\r
+ } BIT;\r
+ } NMIFLTC;\r
+};\r
+\r
+struct st_iwdt {\r
+ unsigned char IWDTRR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short RPSS:2;\r
+ unsigned short :2;\r
+ unsigned short RPES:2;\r
+ unsigned short CKS:4;\r
+ unsigned short :2;\r
+ unsigned short TOPS:2;\r
+ } BIT;\r
+ } IWDTCR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short REFEF:1;\r
+ unsigned short UNDFF:1;\r
+ unsigned short CNTVAL:14;\r
+ } BIT;\r
+ } IWDTSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTIRQS:1;\r
+ } BIT;\r
+ } IWDTRCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SLCSTP:1;\r
+ } BIT;\r
+ } IWDTCSTPR;\r
+};\r
+\r
+struct st_mpc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0WI:1;\r
+ unsigned char PFSWE:1;\r
+ } BIT;\r
+ } PWPR;\r
+ char wk0[35];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P03PFS;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P05PFS;\r
+ char wk2[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P14PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P15PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P16PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P17PFS;\r
+ char wk3[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P26PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P27PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P30PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P31PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P32PFS;\r
+ char wk4[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P35PFS;\r
+ char wk5[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P40PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P41PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P42PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P43PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P44PFS;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P46PFS;\r
+ char wk7[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P54PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P55PFS;\r
+ char wk8[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA1PFS;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA4PFS;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA6PFS;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB1PFS;\r
+ char wk12[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB3PFS;\r
+ char wk13[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB7PFS;\r
+ char wk14[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC7PFS;\r
+ char wk15[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE7PFS;\r
+ char wk16[30];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ7PFS;\r
+};\r
+\r
+struct st_mtu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OE4D:1;\r
+ unsigned char OE4C:1;\r
+ unsigned char OE3D:1;\r
+ unsigned char OE4B:1;\r
+ unsigned char OE4A:1;\r
+ unsigned char OE3B:1;\r
+ } BIT;\r
+ } TOER;\r
+ char wk0[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BDC:1;\r
+ unsigned char N:1;\r
+ unsigned char P:1;\r
+ unsigned char FB:1;\r
+ unsigned char WF:1;\r
+ unsigned char VF:1;\r
+ unsigned char UF:1;\r
+ } BIT;\r
+ } TGCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSYE:1;\r
+ unsigned char :2;\r
+ unsigned char TOCL:1;\r
+ unsigned char TOCS:1;\r
+ unsigned char OLSN:1;\r
+ unsigned char OLSP:1;\r
+ } BIT;\r
+ } TOCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BF:2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOCR2;\r
+ char wk1[4];\r
+ unsigned short TCDR;\r
+ unsigned short TDDR;\r
+ char wk2[8];\r
+ unsigned short TCNTS;\r
+ unsigned short TCBR;\r
+ char wk3[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char T3AEN:1;\r
+ unsigned char T3ACOR:3;\r
+ unsigned char T4VEN:1;\r
+ unsigned char T4VCOR:3;\r
+ } BIT;\r
+ } TITCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char T3ACNT:3;\r
+ unsigned char :1;\r
+ unsigned char T4VCNT:3;\r
+ } BIT;\r
+ } TITCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char BTE:2;\r
+ } BIT;\r
+ } TBTER;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TDER:1;\r
+ } BIT;\r
+ } TDER;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOLBR;\r
+ char wk6[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCE:1;\r
+ unsigned char :6;\r
+ unsigned char WRE:1;\r
+ } BIT;\r
+ } TWCR;\r
+ char wk7[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CST4:1;\r
+ unsigned char CST3:1;\r
+ unsigned char :3;\r
+ unsigned char CST2:1;\r
+ unsigned char CST1:1;\r
+ unsigned char CST0:1;\r
+ } BIT;\r
+ } TSTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SYNC4:1;\r
+ unsigned char SYNC3:1;\r
+ unsigned char :3;\r
+ unsigned char SYNC2:1;\r
+ unsigned char SYNC1:1;\r
+ unsigned char SYNC0:1;\r
+ } BIT;\r
+ } TSYR;\r
+ char wk8[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char RWE:1;\r
+ } BIT;\r
+ } TRWER;\r
+};\r
+\r
+struct st_mtu0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[111];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BFE:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk1[16];\r
+ unsigned short TGRE;\r
+ unsigned short TGRF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TGIEF:1;\r
+ unsigned char TGIEE:1;\r
+ } BIT;\r
+ } TIER2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+};\r
+\r
+struct st_mtu1 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[238];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CCLR:2;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk3[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char I2BE:1;\r
+ unsigned char I2AE:1;\r
+ unsigned char I1BE:1;\r
+ unsigned char I1AE:1;\r
+ } BIT;\r
+ } TICCR;\r
+};\r
+\r
+struct st_mtu2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[365];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CCLR:2;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_mtu3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk3[7];\r
+ unsigned short TCNT;\r
+ char wk4[6];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk5[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk6[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk8[90];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu4 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char TTGE2:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk4[8];\r
+ unsigned short TCNT;\r
+ char wk5[8];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk6[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk8[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk9[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BF:2;\r
+ unsigned short :6;\r
+ unsigned short UT4AE:1;\r
+ unsigned short DT4AE:1;\r
+ unsigned short UT4BE:1;\r
+ unsigned short DT4BE:1;\r
+ unsigned short ITA3AE:1;\r
+ unsigned short ITA4VE:1;\r
+ unsigned short ITB3AE:1;\r
+ unsigned short ITB4VE:1;\r
+ } BIT;\r
+ } TADCR;\r
+ char wk10[2];\r
+ unsigned short TADCORA;\r
+ unsigned short TADCORB;\r
+ unsigned short TADCOBRA;\r
+ unsigned short TADCOBRB;\r
+ char wk11[72];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu5 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char :1;\r
+ unsigned char NFWEN:1;\r
+ unsigned char NFVEN:1;\r
+ unsigned char NFUEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[490];\r
+ unsigned short TCNTU;\r
+ unsigned short TGRU;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRU;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORU;\r
+ char wk3[9];\r
+ unsigned short TCNTV;\r
+ unsigned short TGRV;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRV;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORV;\r
+ char wk5[9];\r
+ unsigned short TCNTW;\r
+ unsigned short TGRW;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRW;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORW;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TGIE5U:1;\r
+ unsigned char TGIE5V:1;\r
+ unsigned char TGIE5W:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CSTU5:1;\r
+ unsigned char CSTV5:1;\r
+ unsigned char CSTW5:1;\r
+ } BIT;\r
+ } TSTR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CMPCLR5U:1;\r
+ unsigned char CMPCLR5V:1;\r
+ unsigned char CMPCLR5W:1;\r
+ } BIT;\r
+ } TCNTCMPCLR;\r
+};\r
+\r
+struct st_poe {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char POE3F:1;\r
+ unsigned char POE2F:1;\r
+ unsigned char POE1F:1;\r
+ unsigned char POE0F:1;\r
+ unsigned char :3;\r
+ unsigned char PIE1:1;\r
+ unsigned char POE3M:2;\r
+ unsigned char POE2M:2;\r
+ unsigned char POE1M:2;\r
+ unsigned char POE0M:2;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char OSF1:1;\r
+ unsigned char :5;\r
+ unsigned char OCE1:1;\r
+ unsigned char OIE1:1;\r
+ } BIT;\r
+ } OCSR1;\r
+ char wk0[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char POE8F:1;\r
+ unsigned char :2;\r
+ unsigned char POE8E:1;\r
+ unsigned char PIE2:1;\r
+ unsigned char :6;\r
+ unsigned char POE8M:2;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char CH0HIZ:1;\r
+ unsigned char CH34HIZ:1;\r
+ } BIT;\r
+ } SPOER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PE3ZE:1;\r
+ unsigned char PE2ZE:1;\r
+ unsigned char PE1ZE:1;\r
+ unsigned char PE0ZE:1;\r
+ } BIT;\r
+ } POECR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char P1CZEA:1;\r
+ unsigned char P2CZEA:1;\r
+ unsigned char P3CZEA:1;\r
+ } BIT;\r
+ } POECR2;\r
+ char wk1[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char OSTSTF:1;\r
+ unsigned char :2;\r
+ unsigned char OSTSTE:1;\r
+ } BIT;\r
+ } ICSR3;\r
+};\r
+\r
+struct st_port {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char PSEL5:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL3:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL1:1;\r
+ unsigned char PSEL0:1;\r
+ } BIT;\r
+ } PSRB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL7:1;\r
+ unsigned char PSEL6:1;\r
+ } BIT;\r
+ } PSRA;\r
+};\r
+\r
+struct st_port0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[33];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[61];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port4 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+};\r
+\r
+struct st_port5 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porta {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :3;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char :3;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[52];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[42];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :3;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[51];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[43];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[50];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porte {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[45];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[48];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_riic {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICE:1;\r
+ unsigned char IICRST:1;\r
+ unsigned char CLO:1;\r
+ unsigned char SOWP:1;\r
+ unsigned char SCLO:1;\r
+ unsigned char SDAO:1;\r
+ unsigned char SCLI:1;\r
+ unsigned char SDAI:1;\r
+ } BIT;\r
+ } ICCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BBSY:1;\r
+ unsigned char MST:1;\r
+ unsigned char TRS:1;\r
+ unsigned char :1;\r
+ unsigned char SP:1;\r
+ unsigned char RS:1;\r
+ unsigned char ST:1;\r
+ } BIT;\r
+ } ICCR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTWP:1;\r
+ unsigned char CKS:3;\r
+ unsigned char BCWP:1;\r
+ unsigned char BC:3;\r
+ } BIT;\r
+ } ICMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DLCS:1;\r
+ unsigned char SDDL:3;\r
+ unsigned char TMWE:1;\r
+ unsigned char TMOH:1;\r
+ unsigned char TMOL:1;\r
+ unsigned char TMOS:1;\r
+ } BIT;\r
+ } ICMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SMBS:1;\r
+ unsigned char WAIT:1;\r
+ unsigned char RDRFS:1;\r
+ unsigned char ACKWP:1;\r
+ unsigned char ACKBT:1;\r
+ unsigned char ACKBR:1;\r
+ unsigned char NF:2;\r
+ } BIT;\r
+ } ICMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SCLE:1;\r
+ unsigned char NFE:1;\r
+ unsigned char NACKE:1;\r
+ unsigned char SALE:1;\r
+ unsigned char NALE:1;\r
+ unsigned char MALE:1;\r
+ unsigned char TMOE:1;\r
+ } BIT;\r
+ } ICFER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOAE:1;\r
+ unsigned char :1;\r
+ unsigned char DIDE:1;\r
+ unsigned char :1;\r
+ unsigned char GCAE:1;\r
+ unsigned char SAR2E:1;\r
+ unsigned char SAR1E:1;\r
+ unsigned char SAR0E:1;\r
+ } BIT;\r
+ } ICSER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char NAKIE:1;\r
+ unsigned char SPIE:1;\r
+ unsigned char STIE:1;\r
+ unsigned char ALIE:1;\r
+ unsigned char TMOIE:1;\r
+ } BIT;\r
+ } ICIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOA:1;\r
+ unsigned char :1;\r
+ unsigned char DID:1;\r
+ unsigned char :1;\r
+ unsigned char GCA:1;\r
+ unsigned char AAS2:1;\r
+ unsigned char AAS1:1;\r
+ unsigned char AAS0:1;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TDRE:1;\r
+ unsigned char TEND:1;\r
+ unsigned char RDRF:1;\r
+ unsigned char NACKF:1;\r
+ unsigned char STOP:1;\r
+ unsigned char START:1;\r
+ unsigned char AL:1;\r
+ unsigned char TMOF:1;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTL;\r
+ };\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTH;\r
+ };\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRL:5;\r
+ } BIT;\r
+ } ICBRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRH:5;\r
+ } BIT;\r
+ } ICBRH;\r
+ unsigned char ICDRT;\r
+ unsigned char ICDRR;\r
+};\r
+\r
+struct st_rspi {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPRIE:1;\r
+ unsigned char SPE:1;\r
+ unsigned char SPTIE:1;\r
+ unsigned char SPEIE:1;\r
+ unsigned char MSTR:1;\r
+ unsigned char MODFEN:1;\r
+ unsigned char TXMD:1;\r
+ unsigned char SPMS:1;\r
+ } BIT;\r
+ } SPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char SSL3P:1;\r
+ unsigned char SSL2P:1;\r
+ unsigned char SSL1P:1;\r
+ unsigned char SSL0P:1;\r
+ } BIT;\r
+ } SSLP;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char MOIFE:1;\r
+ unsigned char MOIFV:1;\r
+ unsigned char :2;\r
+ unsigned char SPLP2:1;\r
+ unsigned char SPLP:1;\r
+ } BIT;\r
+ } SPPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PERF:1;\r
+ unsigned char MODF:1;\r
+ unsigned char IDLNF:1;\r
+ unsigned char OVRF:1;\r
+ } BIT;\r
+ } SPSR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ } WORD;\r
+ } SPDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPSLN:3;\r
+ } BIT;\r
+ } SPSCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SPECM:3;\r
+ unsigned char :1;\r
+ unsigned char SPCP:3;\r
+ } BIT;\r
+ } SPSSR;\r
+ unsigned char SPBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char SPLW:1;\r
+ unsigned char SPRDTD:1;\r
+ unsigned char :2;\r
+ unsigned char SPFC:2;\r
+ } BIT;\r
+ } SPDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SCKDL:3;\r
+ } BIT;\r
+ } SPCKD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SLNDL:3;\r
+ } BIT;\r
+ } SSLND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPNDL:3;\r
+ } BIT;\r
+ } SPND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PTE:1;\r
+ unsigned char SPIIE:1;\r
+ unsigned char SPOE:1;\r
+ unsigned char SPPE:1;\r
+ } BIT;\r
+ } SPCR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD5;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD6;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD7;\r
+};\r
+\r
+struct st_rtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char F1HZ:1;\r
+ unsigned char F2HZ:1;\r
+ unsigned char F4HZ:1;\r
+ unsigned char F8HZ:1;\r
+ unsigned char F16HZ:1;\r
+ unsigned char F32HZ:1;\r
+ unsigned char F64HZ:1;\r
+ } BIT;\r
+ } R64CNT;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECCNT;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINCNT;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRCNT;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char DAYW:3;\r
+ } BIT;\r
+ } RWKCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char DATE10:2;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYCNT;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONCNT;\r
+ char wk6[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short YR10:4;\r
+ unsigned short YR1:4;\r
+ } BIT;\r
+ } RYRCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECAR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINAR;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRAR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :4;\r
+ unsigned char DAYW:3;\r
+ } BIT;\r
+ } RWKAR;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :1;\r
+ unsigned char DATE10:2;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYAR;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :2;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONAR;\r
+ char wk12[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short YR10:4;\r
+ unsigned short YR1:4;\r
+ } BIT;\r
+ } RYRAR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RYRAREN;\r
+ char wk13[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PES:4;\r
+ unsigned char RTCOS:1;\r
+ unsigned char PIE:1;\r
+ unsigned char CIE:1;\r
+ unsigned char AIE:1;\r
+ } BIT;\r
+ } RCR1;\r
+ char wk14[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CNTMD:1;\r
+ unsigned char HR24:1;\r
+ unsigned char AADJP:1;\r
+ unsigned char AADJE:1;\r
+ unsigned char RTCOE:1;\r
+ unsigned char ADJ30:1;\r
+ unsigned char RESET:1;\r
+ unsigned char START:1;\r
+ } BIT;\r
+ } RCR2;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char RTCDV:2;\r
+ unsigned char RTCEN:1;\r
+ } BIT;\r
+ } RCR3;\r
+ char wk16[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PMADJ:2;\r
+ unsigned char ADJ:6;\r
+ } BIT;\r
+ } RADJ;\r
+};\r
+\r
+struct st_rtcb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT0;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT1;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT3;\r
+ char wk3[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT0AR;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT1AR;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT2AR;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT3AR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT0AER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT1AER;\r
+ char wk9[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short ENB:8;\r
+ } BIT;\r
+ } BCNT2AER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT3AER;\r
+};\r
+\r
+struct st_s12ad {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADST:1;\r
+ unsigned short ADCS:2;\r
+ unsigned short ADIE:1;\r
+ unsigned short :1;\r
+ unsigned short ADHSC:1;\r
+ unsigned short TRGE:1;\r
+ unsigned short EXTRG:1;\r
+ unsigned short DBLE:1;\r
+ unsigned short GBADIE:1;\r
+ unsigned short :1;\r
+ unsigned short DBLANS:5;\r
+ } BIT;\r
+ } ADCSR;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ANSA15:1;\r
+ unsigned short ANSA14:1;\r
+ unsigned short ANSA13:1;\r
+ unsigned short ANSA12:1;\r
+ unsigned short ANSA11:1;\r
+ unsigned short ANSA10:1;\r
+ unsigned short ANSA9:1;\r
+ unsigned short ANSA8:1;\r
+ unsigned short :1;\r
+ unsigned short ANSA6:1;\r
+ unsigned short :1;\r
+ unsigned short ANSA4:1;\r
+ unsigned short ANSA3:1;\r
+ unsigned short ANSA2:1;\r
+ unsigned short ANSA1:1;\r
+ unsigned short ANSA0:1;\r
+ } BIT;\r
+ } ADANSA;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADS15:1;\r
+ unsigned short ADS14:1;\r
+ unsigned short ADS13:1;\r
+ unsigned short ADS12:1;\r
+ unsigned short ADS11:1;\r
+ unsigned short ADS10:1;\r
+ unsigned short ADS9:1;\r
+ unsigned short ADS8:1;\r
+ unsigned short :1;\r
+ unsigned short ADS6:1;\r
+ unsigned short :1;\r
+ unsigned short ADS4:1;\r
+ unsigned short ADS3:1;\r
+ unsigned short ADS2:1;\r
+ unsigned short ADS1:1;\r
+ unsigned short ADS0:1;\r
+ } BIT;\r
+ } ADADS;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char ADC:2;\r
+ } BIT;\r
+ } ADADC;\r
+ char wk3[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADRFMT:1;\r
+ unsigned short :9;\r
+ unsigned short ACE:1;\r
+ } BIT;\r
+ } ADCER;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short TRSA:4;\r
+ unsigned short :4;\r
+ unsigned short TRSB:4;\r
+ } BIT;\r
+ } ADSTRGR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short OCS:1;\r
+ unsigned short TSS:1;\r
+ unsigned short :6;\r
+ unsigned short OCSAD:1;\r
+ } BIT;\r
+ } ADEXICR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ANSB15:1;\r
+ unsigned short ANSB14:1;\r
+ unsigned short ANSB13:1;\r
+ unsigned short ANSB12:1;\r
+ unsigned short ANSB11:1;\r
+ unsigned short ANSB10:1;\r
+ unsigned short ANSB9:1;\r
+ unsigned short ANSB8:1;\r
+ unsigned short :1;\r
+ unsigned short ANSB6:1;\r
+ unsigned short :1;\r
+ unsigned short ANSB4:1;\r
+ unsigned short ANSB3:1;\r
+ unsigned short ANSB2:1;\r
+ unsigned short ANSB1:1;\r
+ unsigned short ANSB0:1;\r
+ } BIT;\r
+ } ADANSB;\r
+ char wk4[2];\r
+ unsigned short ADDBLDR;\r
+ unsigned short ADTSDR;\r
+ unsigned short ADOCDR;\r
+ char wk5[2];\r
+ unsigned short ADDR0;\r
+ unsigned short ADDR1;\r
+ unsigned short ADDR2;\r
+ unsigned short ADDR3;\r
+ unsigned short ADDR4;\r
+ char wk6[2];\r
+ unsigned short ADDR6;\r
+ char wk7[2];\r
+ unsigned short ADDR8;\r
+ unsigned short ADDR9;\r
+ unsigned short ADDR10;\r
+ unsigned short ADDR11;\r
+ unsigned short ADDR12;\r
+ unsigned short ADDR13;\r
+ unsigned short ADDR14;\r
+ unsigned short ADDR15;\r
+ char wk8[32];\r
+ unsigned char ADSSTR0;\r
+ unsigned char ADSSTRL;\r
+ char wk9[14];\r
+ unsigned char ADSSTRT;\r
+ unsigned char ADSSTRO;\r
+ char wk10[1];\r
+ unsigned char ADSSTR1;\r
+ unsigned char ADSSTR2;\r
+ unsigned char ADSSTR3;\r
+ unsigned char ADSSTR4;\r
+ char wk11[1];\r
+ unsigned char ADSSTR6;\r
+};\r
+\r
+struct st_sci1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RXDESEL:1;\r
+ unsigned char :1;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+};\r
+\r
+struct st_sci12 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RXDESEL:1;\r
+ unsigned char :1;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+ char wk0[18];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ESME:1;\r
+ } BIT;\r
+ } ESMER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char BRME:1;\r
+ unsigned char RXDSF:1;\r
+ unsigned char SFSF:1;\r
+ } BIT;\r
+ } CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PIBS:3;\r
+ unsigned char PIBE:1;\r
+ unsigned char CF1DS:2;\r
+ unsigned char CF0RE:1;\r
+ unsigned char BFE:1;\r
+ } BIT;\r
+ } CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RTS:2;\r
+ unsigned char BCCS:2;\r
+ unsigned char :1;\r
+ unsigned char DFCS:3;\r
+ } BIT;\r
+ } CR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SDST:1;\r
+ } BIT;\r
+ } CR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SHARPS:1;\r
+ unsigned char :2;\r
+ unsigned char RXDXPS:1;\r
+ unsigned char TXDXPS:1;\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDIE:1;\r
+ unsigned char BCDIE:1;\r
+ unsigned char PIBDIE:1;\r
+ unsigned char CF1MIE:1;\r
+ unsigned char CF0MIE:1;\r
+ unsigned char BFDIE:1;\r
+ } BIT;\r
+ } ICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDF:1;\r
+ unsigned char BCDF:1;\r
+ unsigned char PIBDF:1;\r
+ unsigned char CF1MF:1;\r
+ unsigned char CF0MF:1;\r
+ unsigned char BFDF:1;\r
+ } BIT;\r
+ } STR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDCL:1;\r
+ unsigned char BCDCL:1;\r
+ unsigned char PIBDCL:1;\r
+ unsigned char CF1MCL:1;\r
+ unsigned char CF0MCL:1;\r
+ unsigned char BFDCL:1;\r
+ } BIT;\r
+ } STCR;\r
+ unsigned char CF0DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF0CE7:1;\r
+ unsigned char CF0CE6:1;\r
+ unsigned char CF0CE5:1;\r
+ unsigned char CF0CE4:1;\r
+ unsigned char CF0CE3:1;\r
+ unsigned char CF0CE2:1;\r
+ unsigned char CF0CE1:1;\r
+ unsigned char CF0CE0:1;\r
+ } BIT;\r
+ } CF0CR;\r
+ unsigned char CF0RR;\r
+ unsigned char PCF1DR;\r
+ unsigned char SCF1DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF1CE7:1;\r
+ unsigned char CF1CE6:1;\r
+ unsigned char CF1CE5:1;\r
+ unsigned char CF1CE4:1;\r
+ unsigned char CF1CE3:1;\r
+ unsigned char CF1CE2:1;\r
+ unsigned char CF1CE1:1;\r
+ unsigned char CF1CE0:1;\r
+ } BIT;\r
+ } CF1CR;\r
+ unsigned char CF1RR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TCST:1;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char TCSS:3;\r
+ unsigned char TWRC:1;\r
+ unsigned char :1;\r
+ unsigned char TOMS:2;\r
+ } BIT;\r
+ } TMR;\r
+ unsigned char TPRE;\r
+ unsigned char TCNT;\r
+};\r
+\r
+struct st_smci {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char GM:1;\r
+ unsigned char BLK:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char BCP:2;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char ERS:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+};\r
+\r
+struct st_system {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short MD:1;\r
+ } BIT;\r
+ } MDMONR;\r
+ char wk0[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short RAME:1;\r
+ } BIT;\r
+ } SYSCR1;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SSBY:1;\r
+ } BIT;\r
+ } SBYCR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long MSTPA28:1;\r
+ unsigned long :8;\r
+ unsigned long MSTPA19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA17:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA15:1;\r
+ unsigned long :5;\r
+ unsigned long MSTPA9:1;\r
+ } BIT;\r
+ } MSTPCRA;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long MSTPB30:1;\r
+ unsigned long :3;\r
+ unsigned long MSTPB26:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPB23:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB21:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB17:1;\r
+ unsigned long :7;\r
+ unsigned long MSTPB9:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPB6:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB4:1;\r
+ } BIT;\r
+ } MSTPCRB;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long DSLPE:1;\r
+ unsigned long :11;\r
+ unsigned long MSTPC19:1;\r
+ unsigned long :18;\r
+ unsigned long MSTPC0:1;\r
+ } BIT;\r
+ } MSTPCRC;\r
+ char wk3[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long FCK:4;\r
+ unsigned long ICK:4;\r
+ unsigned long :12;\r
+ unsigned long PCKB:4;\r
+ unsigned long :4;\r
+ unsigned long PCKD:4;\r
+ } BIT;\r
+ } SCKCR;\r
+ char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short CKSEL:3;\r
+ } BIT;\r
+ } SCKCR3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short STC:6;\r
+ unsigned short :6;\r
+ unsigned short PLIDIV:2;\r
+ } BIT;\r
+ } PLLCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char PLLEN:1;\r
+ } BIT;\r
+ } PLLCR2;\r
+ char wk5[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char MOSTP:1;\r
+ } BIT;\r
+ } MOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SOSTP:1;\r
+ } BIT;\r
+ } SOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char LCSTP:1;\r
+ } BIT;\r
+ } LOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ILCSTP:1;\r
+ } BIT;\r
+ } ILOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char HCSTP:1;\r
+ } BIT;\r
+ } HOCOCR;\r
+ char wk6[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char HCOVF:1;\r
+ unsigned char PLOVF:1;\r
+ unsigned char :1;\r
+ unsigned char MOOVF:1;\r
+ } BIT;\r
+ } OSCOVFSR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CKOSTP:1;\r
+ unsigned short CKODIV:3;\r
+ unsigned short :1;\r
+ unsigned short CKOSEL:3;\r
+ } BIT;\r
+ } CKOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OSTDE:1;\r
+ unsigned char :6;\r
+ unsigned char OSTDIE:1;\r
+ } BIT;\r
+ } OSTDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char OSTDF:1;\r
+ } BIT;\r
+ } OSTDSR;\r
+ char wk8[94];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char OPCMTSF:1;\r
+ unsigned char :1;\r
+ unsigned char OPCM:3;\r
+ } BIT;\r
+ } OPCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTCKEN:1;\r
+ unsigned char :4;\r
+ unsigned char RSTCKSEL:3;\r
+ } BIT;\r
+ } RSTCKCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MSTS:5;\r
+ } BIT;\r
+ } MOSCWTCR;\r
+ char wk9[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SOPCMTSF:1;\r
+ unsigned char :3;\r
+ unsigned char SOPCM:1;\r
+ } BIT;\r
+ } SOPCCR;\r
+ char wk10[21];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SWRF:1;\r
+ unsigned char :1;\r
+ unsigned char IWDTRF:1;\r
+ } BIT;\r
+ } RSTSR2;\r
+ char wk11[1];\r
+ unsigned short SWRR;\r
+ char wk12[28];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char LVD1IRQSEL:1;\r
+ unsigned char LVD1IDTSEL:2;\r
+ } BIT;\r
+ } LVD1CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD1MON:1;\r
+ unsigned char LVD1DET:1;\r
+ } BIT;\r
+ } LVD1SR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char LVD2IRQSEL:1;\r
+ unsigned char LVD2IDTSEL:2;\r
+ } BIT;\r
+ } LVD2CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD2MON:1;\r
+ unsigned char LVD2DET:1;\r
+ } BIT;\r
+ } LVD2SR;\r
+ char wk13[794];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRKEY:8;\r
+ unsigned short :4;\r
+ unsigned short PRC3:1;\r
+ unsigned short :1;\r
+ unsigned short PRC1:1;\r
+ unsigned short PRC0:1;\r
+ } BIT;\r
+ } PRCR;\r
+ char wk14[48784];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char LVD2RF:1;\r
+ unsigned char LVD1RF:1;\r
+ unsigned char :1;\r
+ unsigned char PORF:1;\r
+ } BIT;\r
+ } RSTSR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CWSF:1;\r
+ } BIT;\r
+ } RSTSR1;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MOSEL:1;\r
+ unsigned char MODRV21:1;\r
+ } BIT;\r
+ } MOFCR;\r
+ char wk16[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char LVD2E:1;\r
+ unsigned char LVD1E:1;\r
+ unsigned char :1;\r
+ unsigned char EXVCCINP2:1;\r
+ } BIT;\r
+ } LVCMPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2LVL:2;\r
+ unsigned char LVD1LVL:4;\r
+ } BIT;\r
+ } LVDLVLR;\r
+ char wk17[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD1RN:1;\r
+ unsigned char LVD1RI:1;\r
+ unsigned char :3;\r
+ unsigned char LVD1CMPE:1;\r
+ unsigned char :1;\r
+ unsigned char LVD1RIE:1;\r
+ } BIT;\r
+ } LVD1CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD2RN:1;\r
+ unsigned char LVD2RI:1;\r
+ unsigned char :3;\r
+ unsigned char LVD2CMPE:1;\r
+ unsigned char :1;\r
+ unsigned char LVD2RIE:1;\r
+ } BIT;\r
+ } LVD2CR0;\r
+};\r
+\r
+struct st_usb {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short SCKE:1;\r
+ unsigned short :1;\r
+ unsigned short CNEN:1;\r
+ unsigned short :1;\r
+ unsigned short DCFM:1;\r
+ unsigned short DRPD:1;\r
+ unsigned short DPRPU:1;\r
+ unsigned short :3;\r
+ unsigned short USBE:1;\r
+ } BIT;\r
+ } SYSCFG;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVCMON:2;\r
+ unsigned short :7;\r
+ unsigned short HTACT:1;\r
+ unsigned short :3;\r
+ unsigned short IDMON:1;\r
+ unsigned short LNST:2;\r
+ } BIT;\r
+ } SYSSTS0;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short HNPBTOA:1;\r
+ unsigned short EXICEN:1;\r
+ unsigned short VBUSEN:1;\r
+ unsigned short WKUP:1;\r
+ unsigned short RWUPE:1;\r
+ unsigned short USBRST:1;\r
+ unsigned short RESUME:1;\r
+ unsigned short UACT:1;\r
+ unsigned short :1;\r
+ unsigned short RHST:3;\r
+ } BIT;\r
+ } DVSTCTR0;\r
+ char wk2[10];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } CFIFO;\r
+ char wk3[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D0FIFO;\r
+ char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D1FIFO;\r
+ char wk5[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short :3;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :2;\r
+ unsigned short ISEL:1;\r
+ unsigned short :1;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } CFIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } CFIFOCTR;\r
+ char wk6[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D0FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } D0FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D1FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } D1FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBSE:1;\r
+ unsigned short RSME:1;\r
+ unsigned short SOFE:1;\r
+ unsigned short DVSE:1;\r
+ unsigned short CTRE:1;\r
+ unsigned short BEMPE:1;\r
+ unsigned short NRDYE:1;\r
+ unsigned short BRDYE:1;\r
+ } BIT;\r
+ } INTENB0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRCRE:1;\r
+ unsigned short BCHGE:1;\r
+ unsigned short :1;\r
+ unsigned short DTCHE:1;\r
+ unsigned short ATTCHE:1;\r
+ unsigned short :4;\r
+ unsigned short EOFERRE:1;\r
+ unsigned short SIGNE:1;\r
+ unsigned short SACKE:1;\r
+ unsigned short :3;\r
+ unsigned short PDDETINTE0:1;\r
+ } BIT;\r
+ } INTENB1;\r
+ char wk7[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDYE:1;\r
+ unsigned short PIPE8BRDYE:1;\r
+ unsigned short PIPE7BRDYE:1;\r
+ unsigned short PIPE6BRDYE:1;\r
+ unsigned short PIPE5BRDYE:1;\r
+ unsigned short PIPE4BRDYE:1;\r
+ unsigned short PIPE3BRDYE:1;\r
+ unsigned short PIPE2BRDYE:1;\r
+ unsigned short PIPE1BRDYE:1;\r
+ unsigned short PIPE0BRDYE:1;\r
+ } BIT;\r
+ } BRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9NRDYE:1;\r
+ unsigned short PIPE8NRDYE:1;\r
+ unsigned short PIPE7NRDYE:1;\r
+ unsigned short PIPE6NRDYE:1;\r
+ unsigned short PIPE5NRDYE:1;\r
+ unsigned short PIPE4NRDYE:1;\r
+ unsigned short PIPE3NRDYE:1;\r
+ unsigned short PIPE2NRDYE:1;\r
+ unsigned short PIPE1NRDYE:1;\r
+ unsigned short PIPE0NRDYE:1;\r
+ } BIT;\r
+ } NRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMPE:1;\r
+ unsigned short PIPE8BEMPE:1;\r
+ unsigned short PIPE7BEMPE:1;\r
+ unsigned short PIPE6BEMPE:1;\r
+ unsigned short PIPE5BEMPE:1;\r
+ unsigned short PIPE4BEMPE:1;\r
+ unsigned short PIPE3BEMPE:1;\r
+ unsigned short PIPE2BEMPE:1;\r
+ unsigned short PIPE1BEMPE:1;\r
+ unsigned short PIPE0BEMPE:1;\r
+ } BIT;\r
+ } BEMPENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short TRNENSEL:1;\r
+ unsigned short :1;\r
+ unsigned short BRDYM:1;\r
+ unsigned short :1;\r
+ unsigned short EDGESTS:1;\r
+ } BIT;\r
+ } SOFCFG;\r
+ char wk8[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBINT:1;\r
+ unsigned short RESM:1;\r
+ unsigned short SOFR:1;\r
+ unsigned short DVST:1;\r
+ unsigned short CTRT:1;\r
+ unsigned short BEMP:1;\r
+ unsigned short NRDY:1;\r
+ unsigned short BRDY:1;\r
+ unsigned short VBSTS:1;\r
+ unsigned short DVSQ:3;\r
+ unsigned short VALID:1;\r
+ unsigned short CTSQ:3;\r
+ } BIT;\r
+ } INTSTS0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRCR:1;\r
+ unsigned short BCHG:1;\r
+ unsigned short :1;\r
+ unsigned short DTCH:1;\r
+ unsigned short ATTCH:1;\r
+ unsigned short :4;\r
+ unsigned short EOFERR:1;\r
+ unsigned short SIGN:1;\r
+ unsigned short SACK:1;\r
+ unsigned short :3;\r
+ unsigned short PDDETINT0:1;\r
+ } BIT;\r
+ } INTSTS1;\r
+ char wk9[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDY:1;\r
+ unsigned short PIPE8BRDY:1;\r
+ unsigned short PIPE7BRDY:1;\r
+ unsigned short PIPE6BRDY:1;\r
+ unsigned short PIPE5BRDY:1;\r
+ unsigned short PIPE4BRDY:1;\r
+ unsigned short PIPE3BRDY:1;\r
+ unsigned short PIPE2BRDY:1;\r
+ unsigned short PIPE1BRDY:1;\r
+ unsigned short PIPE0BRDY:1;\r
+ } BIT;\r
+ } BRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9NRDY:1;\r
+ unsigned short PIPE8NRDY:1;\r
+ unsigned short PIPE7NRDY:1;\r
+ unsigned short PIPE6NRDY:1;\r
+ unsigned short PIPE5NRDY:1;\r
+ unsigned short PIPE4NRDY:1;\r
+ unsigned short PIPE3NRDY:1;\r
+ unsigned short PIPE2NRDY:1;\r
+ unsigned short PIPE1NRDY:1;\r
+ unsigned short PIPE0NRDY:1;\r
+ } BIT;\r
+ } NRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMP:1;\r
+ unsigned short PIPE8BEMP:1;\r
+ unsigned short PIPE7BEMP:1;\r
+ unsigned short PIPE6BEMP:1;\r
+ unsigned short PIPE5BEMP:1;\r
+ unsigned short PIPE4BEMP:1;\r
+ unsigned short PIPE3BEMP:1;\r
+ unsigned short PIPE2BEMP:1;\r
+ unsigned short PIPE1BEMP:1;\r
+ unsigned short PIPE0BEMP:1;\r
+ } BIT;\r
+ } BEMPSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRN:1;\r
+ unsigned short CRCE:1;\r
+ unsigned short :3;\r
+ unsigned short FRNM:11;\r
+ } BIT;\r
+ } FRMNUM;\r
+ char wk10[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BREQUEST:8;\r
+ unsigned short BMREQUESTTYPE:8;\r
+ } BIT;\r
+ } USBREQ;\r
+ unsigned short USBVAL;\r
+ unsigned short USBINDX;\r
+ unsigned short USBLENG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ } BIT;\r
+ } DCPCFG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DEVSEL:4;\r
+ unsigned short :5;\r
+ unsigned short MXPS:7;\r
+ } BIT;\r
+ } DCPMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short SUREQ:1;\r
+ unsigned short :2;\r
+ unsigned short SUREQCLR:1;\r
+ unsigned short :2;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :2;\r
+ unsigned short CCPL:1;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } DCPCTR;\r
+ char wk11[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :12;\r
+ unsigned short PIPESEL:4;\r
+ } BIT;\r
+ } PIPESEL;\r
+ char wk12[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TYPE:2;\r
+ unsigned short :3;\r
+ unsigned short BFRE:1;\r
+ unsigned short DBLB:1;\r
+ unsigned short :1;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ unsigned short EPNUM:4;\r
+ } BIT;\r
+ } PIPECFG;\r
+ char wk13[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DEVSEL:4;\r
+ unsigned short :3;\r
+ unsigned short MXPS:9;\r
+ } BIT;\r
+ } PIPEMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short IFIS:1;\r
+ unsigned short :9;\r
+ unsigned short IITV:3;\r
+ } BIT;\r
+ } PIPEPERI;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE1CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE2CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE3CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE4CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE5CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE6CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE7CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE8CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE9CTR;\r
+ char wk14[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE1TRE;\r
+ unsigned short PIPE1TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE2TRE;\r
+ unsigned short PIPE2TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE3TRE;\r
+ unsigned short PIPE3TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE4TRE;\r
+ unsigned short PIPE4TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE5TRE;\r
+ unsigned short PIPE5TRN;\r
+ char wk15[12];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PDDETSTS0:1;\r
+ unsigned short CHGDETSTS0:1;\r
+ unsigned short BATCHGE0:1;\r
+ unsigned short DCPMODE0:1;\r
+ unsigned short VDMSRCE0:1;\r
+ unsigned short IDPSINKE0:1;\r
+ unsigned short VDPSRCE0:1;\r
+ unsigned short IDMSINKE0:1;\r
+ unsigned short IDPSRCE0:1;\r
+ unsigned short RPDME0:1;\r
+ } BIT;\r
+ } USBBCCTRL0;\r
+ char wk16[26];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short VBRPDCUT:1;\r
+ unsigned short :6;\r
+ unsigned short VDDUSBE:1;\r
+ } BIT;\r
+ } USBMC;\r
+ char wk17[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD5;\r
+};\r
+\r
+#endif /*endian */\r
+\r
+enum enum_ir {\r
+IR_BSC_BUSERR=16,IR_ICU_SWINT=27,\r
+IR_CMT0_CMI0,\r
+IR_CMT1_CMI1,\r
+IR_CAC_FERRF=32,IR_CAC_MENDF,IR_CAC_OVFF,\r
+IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,\r
+IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,\r
+IR_DOC_DOPCF=57,\r
+IR_RTC_CUP=63,\r
+IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,\r
+IR_LVD_LVD1=88,IR_LVD_LVD2,\r
+IR_USB0_USBR0,\r
+IR_RTC_ALM=92,IR_RTC_PRD,\r
+IR_S12AD_S12ADI0=102,IR_S12AD_GBADI,\r
+IR_ELC_ELSR18I=106,\r
+IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,\r
+IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,\r
+IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,\r
+IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,\r
+IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,\r
+IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,\r
+IR_POE_OEI1=170,IR_POE_OEI2,\r
+IR_SCI1_ERI1=218,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,\r
+IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,\r
+IR_SCI12_ERI12=238,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3,\r
+IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0\r
+};\r
+\r
+enum enum_dtce {\r
+DTCE_ICU_SWINT=27,\r
+DTCE_CMT0_CMI0,\r
+DTCE_CMT1_CMI1,\r
+DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,\r
+DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,\r
+DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,\r
+DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI,\r
+DTCE_ELC_ELSR18I=106,\r
+DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,\r
+DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,\r
+DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,\r
+DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,\r
+DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,\r
+DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,\r
+DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,\r
+DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5,\r
+DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12,\r
+DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0\r
+};\r
+\r
+enum enum_ier {\r
+IER_BSC_BUSERR=0x02,\r
+IER_ICU_SWINT=0x03,\r
+IER_CMT0_CMI0=0x03,\r
+IER_CMT1_CMI1=0x03,\r
+IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04,\r
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,\r
+IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,\r
+IER_DOC_DOPCF=0x07,\r
+IER_RTC_CUP=0x07,\r
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,\r
+IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B,\r
+IER_USB0_USBR0=0x0B,\r
+IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,\r
+IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C,\r
+IER_ELC_ELSR18I=0x0D,\r
+IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,\r
+IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,\r
+IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,\r
+IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,\r
+IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,\r
+IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11,\r
+IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,\r
+IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,\r
+IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,\r
+IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E,\r
+IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F\r
+};\r
+\r
+enum enum_ipr {\r
+IPR_BSC_BUSERR=0,\r
+IPR_ICU_SWINT=3,\r
+IPR_CMT0_CMI0=4,\r
+IPR_CMT1_CMI1=5,\r
+IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34,\r
+IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38,\r
+IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44,\r
+IPR_DOC_DOPCF=57,\r
+IPR_RTC_CUP=63,\r
+IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,\r
+IPR_LVD_LVD1=88,IPR_LVD_LVD2=89,\r
+IPR_USB0_USBR0=90,\r
+IPR_RTC_ALM=92,IPR_RTC_PRD=93,\r
+IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103,\r
+IPR_ELC_ELSR18I=106,\r
+IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118,\r
+IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123,\r
+IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127,\r
+IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133,\r
+IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138,\r
+IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139,\r
+IPR_POE_OEI1=170,IPR_POE_OEI2=171,\r
+IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218,\r
+IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222,\r
+IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245,\r
+IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249,\r
+IPR_BSC_=0,\r
+IPR_CMT0_=4,\r
+IPR_CMT1_=5,\r
+IPR_RSPI0_=44,\r
+IPR_DOC_=57,\r
+IPR_ELC_=106,\r
+IPR_MTU1_TGI=121,\r
+IPR_MTU1_TCI=123,\r
+IPR_MTU2_TGI=125,\r
+IPR_MTU2_TCI=127,\r
+IPR_MTU3_TGI=129,\r
+IPR_MTU4_TGI=134,\r
+IPR_MTU5_=139,\r
+IPR_MTU5_TGI=139,\r
+IPR_SCI1_=218,\r
+IPR_SCI5_=222\r
+};\r
+\r
+#define IEN_BSC_BUSERR IEN0\r
+#define IEN_ICU_SWINT IEN3\r
+#define IEN_CMT0_CMI0 IEN4\r
+#define IEN_CMT1_CMI1 IEN5\r
+#define IEN_CAC_FERRF IEN0\r
+#define IEN_CAC_MENDF IEN1\r
+#define IEN_CAC_OVFF IEN2\r
+#define IEN_USB0_D0FIFO0 IEN4\r
+#define IEN_USB0_D1FIFO0 IEN5\r
+#define IEN_USB0_USBI0 IEN6\r
+#define IEN_RSPI0_SPEI0 IEN4\r
+#define IEN_RSPI0_SPRI0 IEN5\r
+#define IEN_RSPI0_SPTI0 IEN6\r
+#define IEN_RSPI0_SPII0 IEN7\r
+#define IEN_DOC_DOPCF IEN1\r
+#define IEN_RTC_CUP IEN7\r
+#define IEN_ICU_IRQ0 IEN0\r
+#define IEN_ICU_IRQ1 IEN1\r
+#define IEN_ICU_IRQ2 IEN2\r
+#define IEN_ICU_IRQ3 IEN3\r
+#define IEN_ICU_IRQ4 IEN4\r
+#define IEN_ICU_IRQ5 IEN5\r
+#define IEN_ICU_IRQ6 IEN6\r
+#define IEN_ICU_IRQ7 IEN7\r
+#define IEN_LVD_LVD1 IEN0\r
+#define IEN_LVD_LVD2 IEN1\r
+#define IEN_USB0_USBR0 IEN2\r
+#define IEN_RTC_ALM IEN4\r
+#define IEN_RTC_PRD IEN5\r
+#define IEN_S12AD_S12ADI0 IEN6\r
+#define IEN_S12AD_GBADI IEN7\r
+#define IEN_ELC_ELSR18I IEN2\r
+#define IEN_MTU0_TGIA0 IEN2\r
+#define IEN_MTU0_TGIB0 IEN3\r
+#define IEN_MTU0_TGIC0 IEN4\r
+#define IEN_MTU0_TGID0 IEN5\r
+#define IEN_MTU0_TCIV0 IEN6\r
+#define IEN_MTU0_TGIE0 IEN7\r
+#define IEN_MTU0_TGIF0 IEN0\r
+#define IEN_MTU1_TGIA1 IEN1\r
+#define IEN_MTU1_TGIB1 IEN2\r
+#define IEN_MTU1_TCIV1 IEN3\r
+#define IEN_MTU1_TCIU1 IEN4\r
+#define IEN_MTU2_TGIA2 IEN5\r
+#define IEN_MTU2_TGIB2 IEN6\r
+#define IEN_MTU2_TCIV2 IEN7\r
+#define IEN_MTU2_TCIU2 IEN0\r
+#define IEN_MTU3_TGIA3 IEN1\r
+#define IEN_MTU3_TGIB3 IEN2\r
+#define IEN_MTU3_TGIC3 IEN3\r
+#define IEN_MTU3_TGID3 IEN4\r
+#define IEN_MTU3_TCIV3 IEN5\r
+#define IEN_MTU4_TGIA4 IEN6\r
+#define IEN_MTU4_TGIB4 IEN7\r
+#define IEN_MTU4_TGIC4 IEN0\r
+#define IEN_MTU4_TGID4 IEN1\r
+#define IEN_MTU4_TCIV4 IEN2\r
+#define IEN_MTU5_TGIU5 IEN3\r
+#define IEN_MTU5_TGIV5 IEN4\r
+#define IEN_MTU5_TGIW5 IEN5\r
+#define IEN_POE_OEI1 IEN2\r
+#define IEN_POE_OEI2 IEN3\r
+#define IEN_SCI1_ERI1 IEN2\r
+#define IEN_SCI1_RXI1 IEN3\r
+#define IEN_SCI1_TXI1 IEN4\r
+#define IEN_SCI1_TEI1 IEN5\r
+#define IEN_SCI5_ERI5 IEN6\r
+#define IEN_SCI5_RXI5 IEN7\r
+#define IEN_SCI5_TXI5 IEN0\r
+#define IEN_SCI5_TEI5 IEN1\r
+#define IEN_SCI12_ERI12 IEN6\r
+#define IEN_SCI12_RXI12 IEN7\r
+#define IEN_SCI12_TXI12 IEN0\r
+#define IEN_SCI12_TEI12 IEN1\r
+#define IEN_SCI12_SCIX0 IEN2\r
+#define IEN_SCI12_SCIX1 IEN3\r
+#define IEN_SCI12_SCIX2 IEN4\r
+#define IEN_SCI12_SCIX3 IEN5\r
+#define IEN_RIIC0_EEI0 IEN6\r
+#define IEN_RIIC0_RXI0 IEN7\r
+#define IEN_RIIC0_TXI0 IEN0\r
+#define IEN_RIIC0_TEI0 IEN1\r
+\r
+#define VECT_BSC_BUSERR 16\r
+#define VECT_ICU_SWINT 27\r
+#define VECT_CMT0_CMI0 28\r
+#define VECT_CMT1_CMI1 29\r
+#define VECT_CAC_FERRF 32\r
+#define VECT_CAC_MENDF 33\r
+#define VECT_CAC_OVFF 34\r
+#define VECT_USB0_D0FIFO0 36\r
+#define VECT_USB0_D1FIFO0 37\r
+#define VECT_USB0_USBI0 38\r
+#define VECT_RSPI0_SPEI0 44\r
+#define VECT_RSPI0_SPRI0 45\r
+#define VECT_RSPI0_SPTI0 46\r
+#define VECT_RSPI0_SPII0 47\r
+#define VECT_DOC_DOPCF 57\r
+#define VECT_RTC_CUP 63\r
+#define VECT_ICU_IRQ0 64\r
+#define VECT_ICU_IRQ1 65\r
+#define VECT_ICU_IRQ2 66\r
+#define VECT_ICU_IRQ3 67\r
+#define VECT_ICU_IRQ4 68\r
+#define VECT_ICU_IRQ5 69\r
+#define VECT_ICU_IRQ6 70\r
+#define VECT_ICU_IRQ7 71\r
+#define VECT_LVD_LVD1 88\r
+#define VECT_LVD_LVD2 89\r
+#define VECT_USB0_USBR0 90\r
+#define VECT_RTC_ALM 92\r
+#define VECT_RTC_PRD 93\r
+#define VECT_S12AD_S12ADI0 102\r
+#define VECT_S12AD_GBADI 103\r
+#define VECT_ELC_ELSR18I 106\r
+#define VECT_MTU0_TGIA0 114\r
+#define VECT_MTU0_TGIB0 115\r
+#define VECT_MTU0_TGIC0 116\r
+#define VECT_MTU0_TGID0 117\r
+#define VECT_MTU0_TCIV0 118\r
+#define VECT_MTU0_TGIE0 119\r
+#define VECT_MTU0_TGIF0 120\r
+#define VECT_MTU1_TGIA1 121\r
+#define VECT_MTU1_TGIB1 122\r
+#define VECT_MTU1_TCIV1 123\r
+#define VECT_MTU1_TCIU1 124\r
+#define VECT_MTU2_TGIA2 125\r
+#define VECT_MTU2_TGIB2 126\r
+#define VECT_MTU2_TCIV2 127\r
+#define VECT_MTU2_TCIU2 128\r
+#define VECT_MTU3_TGIA3 129\r
+#define VECT_MTU3_TGIB3 130\r
+#define VECT_MTU3_TGIC3 131\r
+#define VECT_MTU3_TGID3 132\r
+#define VECT_MTU3_TCIV3 133\r
+#define VECT_MTU4_TGIA4 134\r
+#define VECT_MTU4_TGIB4 135\r
+#define VECT_MTU4_TGIC4 136\r
+#define VECT_MTU4_TGID4 137\r
+#define VECT_MTU4_TCIV4 138\r
+#define VECT_MTU5_TGIU5 139\r
+#define VECT_MTU5_TGIV5 140\r
+#define VECT_MTU5_TGIW5 141\r
+#define VECT_POE_OEI1 170\r
+#define VECT_POE_OEI2 171\r
+#define VECT_SCI1_ERI1 218\r
+#define VECT_SCI1_RXI1 219\r
+#define VECT_SCI1_TXI1 220\r
+#define VECT_SCI1_TEI1 221\r
+#define VECT_SCI5_ERI5 222\r
+#define VECT_SCI5_RXI5 223\r
+#define VECT_SCI5_TXI5 224\r
+#define VECT_SCI5_TEI5 225\r
+#define VECT_SCI12_ERI12 238\r
+#define VECT_SCI12_RXI12 239\r
+#define VECT_SCI12_TXI12 240\r
+#define VECT_SCI12_TEI12 241\r
+#define VECT_SCI12_SCIX0 242\r
+#define VECT_SCI12_SCIX1 243\r
+#define VECT_SCI12_SCIX2 244\r
+#define VECT_SCI12_SCIX3 245\r
+#define VECT_RIIC0_EEI0 246\r
+#define VECT_RIIC0_RXI0 247\r
+#define VECT_RIIC0_TXI0 248\r
+#define VECT_RIIC0_TEI0 249\r
+\r
+#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19\r
+#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17\r
+#define MSTP_CMT SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23\r
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21\r
+#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19\r
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17\r
+#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9\r
+#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6\r
+#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19\r
+#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0\r
+\r
+#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR\r
+#define _IR( x ) __IR( x )\r
+#define IR( x , y ) _IR( _ ## x ## _ ## y )\r
+#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE\r
+#define _DTCE( x ) __DTCE( x )\r
+#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )\r
+#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x\r
+#define _IEN( x ) __IEN( x )\r
+#define IEN( x , y ) _IEN( _ ## x ## _ ## y )\r
+#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR\r
+#define _IPR( x ) __IPR( x )\r
+#define IPR( x , y ) _IPR( _ ## x ## _ ## y )\r
+#define __VECT( x ) VECT ## x\r
+#define _VECT( x ) __VECT( x )\r
+#define VECT( x , y ) _VECT( _ ## x ## _ ## y )\r
+#define __MSTP( x ) MSTP ## x\r
+#define _MSTP( x ) __MSTP( x )\r
+#define MSTP( x ) _MSTP( _ ## x )\r
+\r
+#define BSC (*(volatile struct st_bsc *)0x81300)\r
+#define CAC (*(volatile struct st_cac *)0x8B000)\r
+#define CMT (*(volatile struct st_cmt *)0x88000)\r
+#define CMT0 (*(volatile struct st_cmt0 *)0x88002)\r
+#define CMT1 (*(volatile struct st_cmt0 *)0x88008)\r
+#define CRC (*(volatile struct st_crc *)0x88280)\r
+#define DA (*(volatile struct st_da *)0x880C0)\r
+#define DOC (*(volatile struct st_doc *)0x8B080)\r
+#define DTC (*(volatile struct st_dtc *)0x82400)\r
+#define ELC (*(volatile struct st_elc *)0x8B100)\r
+#define FLASH (*(volatile struct st_flash *)0x7FC090)\r
+#define ICU (*(volatile struct st_icu *)0x87000)\r
+#define IWDT (*(volatile struct st_iwdt *)0x88030)\r
+#define MPC (*(volatile struct st_mpc *)0x8C11F)\r
+#define MTU (*(volatile struct st_mtu *)0x8860A)\r
+#define MTU0 (*(volatile struct st_mtu0 *)0x88690)\r
+#define MTU1 (*(volatile struct st_mtu1 *)0x88690)\r
+#define MTU2 (*(volatile struct st_mtu2 *)0x88692)\r
+#define MTU3 (*(volatile struct st_mtu3 *)0x88600)\r
+#define MTU4 (*(volatile struct st_mtu4 *)0x88600)\r
+#define MTU5 (*(volatile struct st_mtu5 *)0x88694)\r
+#define POE (*(volatile struct st_poe *)0x88900)\r
+#define PORT (*(volatile struct st_port *)0x8C120)\r
+#define PORT0 (*(volatile struct st_port0 *)0x8C000)\r
+#define PORT1 (*(volatile struct st_port1 *)0x8C001)\r
+#define PORT2 (*(volatile struct st_port2 *)0x8C002)\r
+#define PORT3 (*(volatile struct st_port3 *)0x8C003)\r
+#define PORT4 (*(volatile struct st_port4 *)0x8C004)\r
+#define PORT5 (*(volatile struct st_port5 *)0x8C005)\r
+#define PORTA (*(volatile struct st_porta *)0x8C00A)\r
+#define PORTB (*(volatile struct st_portb *)0x8C00B)\r
+#define PORTC (*(volatile struct st_portc *)0x8C00C)\r
+#define PORTE (*(volatile struct st_porte *)0x8C00E)\r
+#define RIIC0 (*(volatile struct st_riic *)0x88300)\r
+#define RSPI0 (*(volatile struct st_rspi *)0x88380)\r
+#define RTC (*(volatile struct st_rtc *)0x8C400)\r
+#define RTCB (*(volatile struct st_rtcb *)0x8C402)\r
+#define S12AD (*(volatile struct st_s12ad *)0x89000)\r
+#define SCI1 (*(volatile struct st_sci1 *)0x8A020)\r
+#define SCI5 (*(volatile struct st_sci1 *)0x8A0A0)\r
+#define SCI12 (*(volatile struct st_sci12 *)0x8B300)\r
+#define SMCI1 (*(volatile struct st_smci *)0x8A020)\r
+#define SMCI5 (*(volatile struct st_smci *)0x8A0A0)\r
+#define SMCI12 (*(volatile struct st_smci *)0x8B300)\r
+#define SYSTEM (*(volatile struct st_system *)0x80000)\r
+#define USB0 (*(volatile struct st_usb *)0xA0000)\r
+#endif /*__RX_LITTLE_ENDIAN__*/\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : mcu_info.h\r
+* Device(s) : RX111\r
+* Description : Information about the MCU on this board (RSKRX111).\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+#ifndef _MCU_INFO\r
+#define _MCU_INFO\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Gets MCU configuration information. */\r
+#include "r_bsp_config.h"\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* MCU Series. */\r
+#if MCU_PART_SERIES == 0x0\r
+ #define MCU_SERIES_RX100 (1)\r
+#else\r
+ #error "ERROR - MCU_PART_SERIES - Unknown MCU Series chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* MCU Group name. */\r
+#if MCU_PART_GROUP == 0x1\r
+ #define MCU_RX111 (1)\r
+ #define MCU_RX11x (1)\r
+#else\r
+ #error "ERROR - MCU_PART_GROUP - Unknown MCU Group chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* Package. */\r
+#if MCU_PART_PACKAGE == 0x0\r
+ #define PACKAGE_LFQFP64 (1)\r
+#elif MCU_PART_PACKAGE == 0x1\r
+ #define PACKAGE_LQFP64 (1)\r
+#elif MCU_PART_PACKAGE == 0x2\r
+ #define PACKAGE_TFLGA64 (1)\r
+#elif MCU_PART_PACKAGE == 0x3\r
+ #define PACKAGE_LFQFP48 (1)\r
+#elif MCU_PART_PACKAGE == 0x4\r
+ #define PACKAGE_VQFN48 (1)\r
+#elif MCU_PART_PACKAGE == 0x5\r
+ #define PACKAGE_HWQFN36 (1)\r
+#elif MCU_PART_PACKAGE == 0x6\r
+ #define PACKAGE_WFLGA36 (1)\r
+#elif MCU_PART_PACKAGE == 0x7\r
+ #define PACKAGE_SSOP36 (1)\r
+#else\r
+ #error "ERROR - MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* Memory size of your MCU. */\r
+#if MCU_PART_MEMORY_SIZE == 0x0 // "J" parts\r
+ #define ROM_SIZE_BYTES (16384)\r
+ #define RAM_SIZE_BYTES (8192)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x1\r
+ #define ROM_SIZE_BYTES (32768)\r
+ #define RAM_SIZE_BYTES (10240)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x3\r
+ #define ROM_SIZE_BYTES (65536)\r
+ #define RAM_SIZE_BYTES (10240)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x4\r
+ #define ROM_SIZE_BYTES (98304)\r
+ #define RAM_SIZE_BYTES (16384)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x5\r
+ #define ROM_SIZE_BYTES (131072)\r
+ #define RAM_SIZE_BYTES (16384)\r
+ #define DF_SIZE_BYTES (8192)\r
+#else\r
+ #error "ERROR - MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* System clock speed in Hz. */\r
+#define ICLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV)\r
+/* Peripheral Module Clock B speed in Hz. */\r
+#define PCLKB_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV)\r
+/* Peripheral Module Clock D speed in Hz. */\r
+#define PCLKD_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV)\r
+/* FlashIF clock speed in Hz. */\r
+#define FCLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV)\r
+\r
+#endif /* _MCU_INFO */\r
+\r
--- /dev/null
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : reset_program.asm */
+/* DESCRIPTION : Reset Program */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/\r
+\r
+\r
+\r
+ /*reset_program.asm*/\r
+\r
+ .list\r
+ .section .text\r
+ .global _PowerON_Reset /*global Start routine */\r
+\r
+ .extern _HardwareSetup /*external Sub-routine to initialise Hardware*/\r
+ .extern _data\r
+ .extern _mdata\r
+ .extern _ebss\r
+ .extern _bss\r
+ .extern _edata\r
+ .extern _main\r
+ .extern _ustack\r
+ .extern _istack\r
+ .extern _rvectors\r
+ .extern _exit\r
+\r
+\r
+_PowerON_Reset :\r
+/* initialise user stack pointer */\r
+ mvtc #_ustack,USP\r
+\r
+/* initialise interrupt stack pointer */\r
+ mvtc #_istack,ISP\r
+\r
+/* setup intb */\r
+ mvtc #_rvectors_start, intb /* INTERRUPT VECTOR ADDRESS definition */\r
+\r
+/* load data section from ROM to RAM */\r
+\r
+ mov #_mdata,r2 /* src ROM address of data section in R2 */\r
+ mov #_data,r1 /* dest start RAM address of data section in R1 */\r
+ mov #_edata,r3 /* end RAM address of data section in R3 */\r
+ sub r1,r3 /* size of data section in R3 (R3=R3-R1) */\r
+ smovf /* block copy R3 bytes from R2 to R1 */\r
+\r
+/* bss initialisation : zero out bss */\r
+\r
+ mov #00h,r2 /* load R2 reg with zero */\r
+ mov #_ebss, r3 /* store the end address of bss in R3 */\r
+ mov #_bss, r1 /* store the start address of bss in R1 */\r
+ sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */\r
+ sstr.b\r
+/* call the hardware initialiser */\r
+ bsr.a _HardwareSetup\r
+ nop\r
+\r
+#ifdef RUN_IN_USER_MODE
+/* setup PSW */\r
+ mvtc #10000h, psw /* Set Ubit & Ibit for PSW */\r
+\r
+/* change PSW PM to user-mode */
+ MVFC PSW,R1\r
+ OR #00100000h,R1\r
+ PUSH.L R1\r
+ MVFC PC,R1\r
+ ADD #10,R1\r
+ PUSH.L R1\r
+ RTE\r
+ NOP\r
+ NOP
+#endif\r
+#ifdef CPPAPP\r
+ bsr.a __rx_init\r
+#endif\r
+/* start user program */\r
+ bsr.a _main\r
+ bsr.a _exit\r
+\r
+#ifdef CPPAPP\r
+ .global _rx_run_preinit_array\r
+ .type _rx_run_preinit_array,@function\r
+_rx_run_preinit_array:\r
+ mov #__preinit_array_start,r1\r
+ mov #__preinit_array_end,r2\r
+ bra.a _rx_run_inilist\r
+\r
+ .global _rx_run_init_array\r
+ .type _rx_run_init_array,@function\r
+_rx_run_init_array:\r
+ mov #__init_array_start,r1\r
+ mov #__init_array_end,r2\r
+ mov #4, r3\r
+ bra.a _rx_run_inilist\r
+\r
+ .global _rx_run_fini_array\r
+ .type _rx_run_fini_array,@function\r
+_rx_run_fini_array:\r
+ mov #__fini_array_start,r2\r
+ mov #__fini_array_end,r1\r
+ mov #-4, r3\r
+ /* fall through */\r
+\r
+_rx_run_inilist:\r
+next_inilist:\r
+ cmp r1,r2\r
+ beq.b done_inilist\r
+ mov.l [r1],r4\r
+ cmp #-1, r4\r
+ beq.b skip_inilist\r
+ cmp #0, r4\r
+ beq.b skip_inilist\r
+ pushm r1-r3\r
+ jsr r4\r
+ popm r1-r3\r
+skip_inilist:\r
+ add r3,r1\r
+ bra.b next_inilist\r
+done_inilist:\r
+ rts\r
+\r
+ .section .init,"ax"\r
+ .balign 4\r
+\r
+ .global __rx_init\r
+__rx_init:\r
+\r
+ .section .fini,"ax"\r
+ .balign 4\r
+\r
+ .global __rx_fini\r
+__rx_fini:\r
+ bsr.a _rx_run_fini_array\r
+\r
+ .section .sdata\r
+ .balign 4\r
+ .global __gp\r
+ .weak __gp\r
+__gp:\r
+\r
+ .section .data\r
+ .global ___dso_handle\r
+ .weak ___dso_handle\r
+___dso_handle:\r
+ .long 0\r
+\r
+ .section .init,"ax"\r
+ bsr.a _rx_run_preinit_array\r
+ bsr.a _rx_run_init_array\r
+ rts\r
+\r
+ .global __rx_init_end\r
+__rx_init_end:\r
+\r
+ .section .fini,"ax"\r
+\r
+ rts\r
+ .global __rx_fini_end\r
+__rx_fini_end:\r
+\r
+#endif\r
+\r
+/* call to exit*/\r
+_exit:\r
+ bra _loop_here\r
+_loop_here:\r
+ bra _loop_here\r
+\r
+ .text\r
+ .end\r
--- /dev/null
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : typedefine.h */
+/* DESCRIPTION : Aliases of Integer Type */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/ \r
+ \r
+ \r
+ \r
+ \r
+typedef signed char _SBYTE;\r
+typedef unsigned char _UBYTE;\r
+typedef signed short _SWORD;\r
+typedef unsigned short _UWORD;\r
+typedef signed int _SINT;\r
+typedef unsigned int _UINT;\r
+typedef signed long _SDWORD;\r
+typedef unsigned long _UDWORD;\r
+typedef signed long long _SQWORD;\r
+typedef unsigned long long _UQWORD;\r
--- /dev/null
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : vector_table.c */
+/* DESCRIPTION : Vector Table */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/\r
+\r
+\r
+\r
+\r
+\r
+#include "interrupt_handlers.h"\r
+\r
+typedef void (*fp) (void);\r
+extern void PowerON_Reset (void);\r
+extern void stack (void);
+extern void vPortSoftwareInterruptISR( void );
+extern void vPortTickISR( void );
+extern void Dummy( void );
+extern void vButtonInterrupt( void );\r
+\r
+#ifdef __RX_LITTLE_ENDIAN__\r
+const unsigned char Endian_Select[] __attribute__ ((section (".endian_bytes"))) = {\r
+ 0xff, 0xff, 0xff, 0xff\r
+};\r
+#elif __RX_BIG_ENDIAN__\r
+const unsigned char Endian_Select[] __attribute__ ((section (".endian_bytes"))) = {\r
+ 0xff, 0xff, 0xff, 0xf8\r
+};\r
+#endif\r
+\r
+// Option bytes setting for OFS1:0xFFFFFF88 and OFS0:0xFFFFFF8C\r
+const unsigned char Security_Id[] __attribute__ ((section (".option_bytes"))) = {\r
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff\r
+};\r
+\r
+\r
+#define FVECT_SECT __attribute__ ((section (".fvectors")))\r
+\r
+const void *HardwareVectors[] FVECT_SECT = {\r
+//;0xffffffd0 Exception(Supervisor Instruction)\r
+ INT_Excep_SuperVisorInst,\r
+//;0xffffffd4 Reserved\r
+ (fp)0,\r
+//;0xffffffd8 Reserved\r
+ (fp)0,\r
+//;0xffffffdc Exception(Undefined Instruction)\r
+ INT_Excep_UndefinedInst,\r
+//;0xffffffe0 Reserved\r
+ (fp)0,\r
+//;0xffffffe4 Exception(Floating Point)\r
+ INT_Excep_FloatingPoint,\r
+//;0xffffffe8 Reserved\r
+ (fp)0,\r
+//;0xffffffec Reserved\r
+ (fp)0,\r
+//;0xfffffff0 Reserved\r
+ (fp)0,\r
+//;0xfffffff4 Reserved\r
+ (fp)0,\r
+//;0xfffffff8 NMI\r
+ INT_NonMaskableInterrupt,\r
+//;0xfffffffc RESET\r
+//;<<VECTOR DATA START (POWER ON RESET)>>\r
+//;Power On Reset PC\r
+ PowerON_Reset\r
+//;<<VECTOR DATA END (POWER ON RESET)>>\r
+};\r
+#define RVECT_SECT __attribute__ ((section (".rvectors")))\r
+\r
+const fp RelocatableVectors[] RVECT_SECT = {\r
+\r
+//;0x0000 Reserved
+ (fp)0,
+//;0x0004 Reserved
+ (fp)0,
+//;0x0008 Reserved
+ (fp)0,
+//;0x000C Reserved
+ (fp)0,
+//;0x0010 Reserved
+ (fp)0,
+//;0x0014 Reserved
+ (fp)0,
+//;0x0018 Reserved
+ (fp)0,
+//;0x001C Reserved
+ (fp)0,
+//;0x0020 Reserved
+ (fp)0,
+//;0x0024 Reserved
+ (fp)0,
+//;0x0028 Reserved
+ (fp)0,
+//;0x002C Reserved
+ (fp)0,
+//;0x0030 Reserved
+ (fp)0,
+//;0x0034 Reserved
+ (fp)0,
+//;0x0038 Reserved
+ (fp)0,
+//;0x003C Reserved
+ (fp)0,
+//;0x0040
+ (fp)Dummy,
+//;0x0044 Reserved
+ (fp)0,
+//;0x0048 Reserved
+ (fp)0,
+//;0x004C Reserved
+ (fp)0,
+//;0x0050 Reserved
+ (fp)0,
+//;0x0054
+ (fp)Dummy,
+//;0x0058 Reserved
+ (fp)0,
+//;0x005C
+ (fp)Dummy,
+//;0x0060 Reserved
+ (fp)0,
+//;0x0064 Reserved
+ (fp)0,
+//;0x0068 Reserved
+ (fp)0,
+//;0x006C Reserved
+ (fp)vPortSoftwareInterruptISR,
+//;0x0070 CMTU0_CMT0
+ (fp)vPortTickISR,
+//;0x0074
+ (fp)Dummy,
+//;0x0078
+ (fp)Dummy,
+//;0x007C
+ (fp)Dummy,
+//;0x0080
+ (fp)Dummy,
+//;0x0084 Reserved
+ (fp)0,
+//;0x0088 Reserved
+ (fp)0,
+//;0x008C Reserved
+ (fp)0,
+//;0x0090 Reserved
+ (fp)0,
+//;0x0094 Reserved
+ (fp)0,
+//;0x0098 Reserved
+ (fp)0,
+//;0x009C Reserved
+ (fp)0,
+//;0x00A0 Reserved
+ (fp)0,
+//;0x00A4 Reserved
+ (fp)0,
+//;0x00A8 Reserved
+ (fp)0,
+//;0x00AC Reserved
+ (fp)0,
+//;0x00B0 Reserved
+ (fp)0,
+//;0x00B4 Reserved
+ (fp)0,
+//;0x00B8 Reserved
+ (fp)0,
+//;0x00BC Reserved
+ (fp)0,
+//;0x00C0 Reserved
+ (fp)0,
+//;0x00C4 Reserved
+ (fp)0,
+//;0x00C8 Reserved
+ (fp)0,
+//;0x00CC Reserved
+ (fp)0,
+//;0x00D0 Reserved
+ (fp)0,
+//;0x00D4 Reserved
+ (fp)0,
+//;0x00D8 Reserved
+ (fp)0,
+//;0x00DC Reserved
+ (fp)0,
+//;0x00E0 Reserved
+ (fp)0,
+//;0x00E4 Reserved
+ (fp)0,
+//;0x00E8 Reserved
+ (fp)0,
+//;0x00EC Reserved
+ (fp)0,
+//;0x00F0 Reserved
+ (fp)0,
+//;0x00F4 Reserved
+ (fp)0,
+//;0x00F8 Reserved
+ (fp)0,
+//;0x00FC Reserved
+ (fp)0,
+//;0x0100 IRQ0
+ (fp)vButtonInterrupt,
+//;0x0104 IRQ1
+ (fp)vButtonInterrupt,
+//;0x0108 IRQ2
+ (fp)Dummy,
+//;0x010C IRQ3
+ (fp)Dummy,
+//;0x0110 IRQ4
+ (fp)vButtonInterrupt,
+//;0x0114 IRQ5
+ (fp)Dummy,
+//;0x0118 IRQ6
+ (fp)Dummy,
+//;0x011C IRQ7
+ (fp)Dummy,
+//;0x0120
+ (fp)Dummy,
+//;0x0124
+ (fp)Dummy,
+//;0x0128
+ (fp)Dummy,
+//;0x012C
+ (fp)Dummy,
+//;0x0130
+ (fp)Dummy,
+//;0x0134
+ (fp)Dummy,
+//;0x0138
+ (fp)Dummy,
+//;0x013C
+ (fp)Dummy,
+//;0x0140 Reserved
+ (fp)0,
+//;0x0144 Reserved
+ (fp)0,
+//;0x0148 Reserved
+ (fp)0,
+//;0x014C Reserved
+ (fp)0,
+//;0x0150 Reserved
+ (fp)0,
+//;0x0154 Reserved
+ (fp)0,
+//;0x0158 Reserved
+ (fp)0,
+//;0x015C Reserved
+ (fp)0,
+//;0x0160 Reserved
+ (fp)0,
+//;0x0164 Reserved
+ (fp)0,
+//;0x0168 Reserved
+ (fp)0,
+//;0x016C Reserved
+ (fp)0,
+//;0x0170 Reserved
+ (fp)0,
+//;0x0174 Reserved
+ (fp)0,
+//;0x0178 Reserved
+ (fp)0,
+//;0x017C Reserved
+ (fp)0,
+//;0x0180
+ (fp)Dummy,
+//;0x0184 Reserved
+ (fp)0,
+//;0x0188
+ (fp)Dummy,
+//;0x018C
+ (fp)Dummy,
+//;0x0190
+ (fp)Dummy,
+//;0x0194
+ (fp)Dummy,
+//;0x0198 Reserved
+ (fp)0,
+//;0x019C Reserved
+ (fp)0,
+//;0x01A0
+ (fp)Dummy,
+//;0x01A4
+ (fp)Dummy,
+//;0x01A8
+ (fp)Dummy,
+//;0x01AC
+ (fp)Dummy,
+//;0x01B0
+ (fp)Dummy,
+//;0x01B4 Reserved
+ (fp)0,
+//;0x01B8 Reserved
+ (fp)0,
+//;0x01BC
+ (fp)Dummy,
+//;0x01C0
+ (fp)Dummy,
+//;0x01C4 Reserved
+ (fp)Dummy,
+//;0x01C8 Reserved
+ (fp)Dummy,
+//;0x01CC
+ (fp)Dummy,
+//;0x01D0
+ (fp)Dummy,
+//;0x01D4
+ (fp)Dummy,
+//;0x01D8
+ (fp)Dummy,
+//;0x01DC Reserved
+ (fp)Dummy,
+//;0x01E0
+ (fp)Dummy,
+//;0x01E4
+ (fp)Dummy,
+//;0x01E8
+ (fp)Dummy,
+//;0x01EC
+ (fp)Dummy,
+//;0x01F0
+ (fp)Dummy,
+//;0x01F4
+ (fp)Dummy,
+//;0x01F8
+ (fp)Dummy,
+//;0x01FC
+ (fp)Dummy,
+//;0x0200
+ (fp)Dummy,
+//;0x0204 Reserved
+ (fp)Dummy,
+//;0x0208 Reserved
+ (fp)Dummy,
+//;0x020C
+ (fp)Dummy,
+//;0x0210
+ (fp)Dummy,
+//;0x0214
+ (fp)Dummy,
+//;0x0218
+ (fp)Dummy,
+//;0x021C Reserved
+ (fp)Dummy,
+//;0x0220
+ (fp)Dummy,
+//;0x0224
+ (fp)Dummy,
+//;0x0228
+ (fp)Dummy,
+//;0x022C
+ (fp)Dummy,
+//;0x0230
+ (fp)Dummy,
+//;0x0234
+ (fp)Dummy,
+//;0x0238
+ (fp)Dummy,
+//;0x023C Reserved
+ (fp)Dummy,
+//;0x0240 Reserved
+ (fp)Dummy,
+//;0x0244
+ (fp)Dummy,
+//;0x0248
+ (fp)Dummy,
+//;0x024C Reserved
+ (fp)Dummy,
+//;0x0250 Reserved
+ (fp)Dummy,
+//;0x0254
+ (fp)Dummy,
+//;0x0258
+ (fp)Dummy,
+//;0x025C
+ (fp)Dummy,
+//;0x0260
+ (fp)Dummy,
+//;0x0264 Reserved
+ (fp)Dummy,
+//;0x0268
+ (fp)Dummy,
+//;0x026C
+ (fp)Dummy,
+//;0x0270
+ (fp)Dummy,
+//;0x0274
+ (fp)Dummy,
+//;0x0278
+ (fp)Dummy,
+//;0x027C
+ (fp)Dummy,
+//;0x0280
+ (fp)Dummy,
+//;0x0284
+ (fp)Dummy,
+//;0x0288
+ (fp)Dummy,
+//;0x028C Reserved
+ (fp)Dummy,
+//;0x0290 Reserved
+ (fp)Dummy,
+//;0x0294
+ (fp)Dummy,
+//;0x0298
+ (fp)Dummy,
+//;0x029C
+ (fp)Dummy,
+//;0x02A0
+ (fp)Dummy,
+//;0x02A4 Reserved
+ (fp)Dummy,
+//;0x02A8
+ (fp)Dummy,
+//;0x02AC
+ (fp)Dummy,
+//;0x02B0 Reserved
+ (fp)Dummy,
+//;0x02B4 Reserved
+ (fp)Dummy,
+//;0x02B8
+ (fp)Dummy,
+//;0x02BC
+ (fp)Dummy,
+//;0x02C0
+ (fp)Dummy,
+//;0x02C4
+ (fp)Dummy,
+//;0x02C8
+ (fp)Dummy,
+//;0x02CC
+ (fp)Dummy,
+//;0x02D0
+ (fp)Dummy,
+//;0x02D4
+ (fp)Dummy,
+//;0x02D8
+ (fp)Dummy,
+//;0x02DC
+ (fp)Dummy,
+//;0x02E0
+ (fp)Dummy,
+//;0x02E4
+ (fp)Dummy,
+//;0x02E8 Reserved
+ (fp)Dummy,
+//;0x02EC Reserved
+ (fp)Dummy,
+//;0x02F0 Reserved
+ (fp)Dummy,
+//;0x02F4 Reserved
+ (fp)Dummy,
+//;0x02F8 Reserved
+ (fp)Dummy,
+//;0x02FC Reserved
+ (fp)Dummy,
+//;0x0300 Reserved
+ (fp)Dummy,
+//;0x0304 Reserved
+ (fp)Dummy,
+//;0x0308 Reserved
+ (fp)Dummy,
+//;0x030C Reserved
+ (fp)Dummy,
+//;0x0310 Reserved
+ (fp)Dummy,
+//;0x0314 Reserved
+ (fp)Dummy,
+//;0x0318
+ (fp)Dummy,
+//;0x031C
+ (fp)Dummy,
+//;0x0320
+ (fp)Dummy,
+//;0x0324
+ (fp)Dummy,
+//;0x0328 Reserved
+ (fp)Dummy,
+//;0x032C Reserved
+ (fp)Dummy,
+//;0x0330 Reserved
+ (fp)Dummy,
+//;0x0334 Reserved
+ (fp)Dummy,
+//;0x0338 Reserved
+ (fp)Dummy,
+//;0x033C Reserved
+ (fp)Dummy,
+//;0x0340 Reserved
+ (fp)Dummy,
+//;0x0344 Reserved
+ (fp)Dummy,
+//;0x0348 Reserved
+ (fp)Dummy,
+//;0x034C Reserved
+ (fp)Dummy,
+//;0x0350 Reserved
+ (fp)Dummy,
+//;0x0354 Reserved
+ (fp)Dummy,
+//;0x0358
+ (fp)Dummy,
+//;0x035C
+ (fp)Dummy,
+//;0x0360
+ (fp)Dummy,
+//;0x0364
+ (fp)Dummy,
+//;0x0368
+ (fp)Dummy,
+//;0x036C
+ (fp)Dummy,
+//;0x0370
+ (fp)Dummy,
+//;0x0374
+ (fp)Dummy,
+//;0x0378
+ (fp)Dummy,
+//;0x037C
+ (fp)Dummy,
+//;0x0380
+ (fp)Dummy,
+//;0x0384
+ (fp)Dummy,
+//;0x0388
+ (fp)Dummy,
+//;0x038C
+ (fp)Dummy,
+//;0x0390
+ (fp)Dummy,
+//;0x0394
+ (fp)Dummy,
+//;0x0398
+ (fp)Dummy,
+//;0x039C
+ (fp)Dummy,
+//;0x03A0
+ (fp)Dummy,
+//;0x03A4
+ (fp)Dummy,
+//;0x03A8
+ (fp)Dummy,
+//;0x03AC
+ (fp)Dummy,
+//;0x03B0
+ (fp)Dummy,
+//;0x03B4
+ (fp)Dummy,
+//;0x03B8
+ (fp)Dummy,
+//;0x03BC
+ (fp)Dummy,
+//;0x03C0
+ (fp)Dummy,
+//;0x03C4
+ (fp)Dummy,
+//;0x03C8 Reserved
+ (fp)Dummy,
+//;0x03CC Reserved
+ (fp)Dummy,
+//;0x03D0 Reserved
+ (fp)Dummy,
+//;0x03D4 Reserved
+ (fp)Dummy,
+//;0x03D8
+ (fp)Dummy,
+//;0x03DC
+ (fp)Dummy,
+//;0x03E0
+ (fp)Dummy,
+//;0x03E4
+ (fp)Dummy,
+//;0x03E8
+ (fp)Dummy,
+//;0x03EC
+ (fp)Dummy,
+//;0x03F0
+ (fp)Dummy,
+//;0x03F4
+ (fp)Dummy,
+//;0x03F8 Reserved
+ (fp)0,
+//;0x03FC Reserved
+ (fp)0,
+};\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : platform.h\r
+* Description : The user chooses which MCU and board they are developing for in this file. If the board you are using\r
+* is not listed below, please add your own or use the default 'User Board'.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 30.11.2011 1.00 First Release\r
+* : 13.01.2012 1.10 Moved from having platform defined using macro defintion, to having platform defined\r
+* by choosing an include path. This makes this file simpler and cleans up the issue\r
+* where HEW shows all header files for all platforms under 'Dependencies'.\r
+* : 14.02.2012 1.20 Added RX210 BSP.\r
+* : 18.04.2012 1.30 Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding\r
+* locking.c and locking.h in board folders. Also, r_bsp can now be configured through\r
+* r_bsp_config.h.\r
+* : 26.06.2012 1.40 Added new options such as exception callbacks and the ability to choose your MCU using\r
+* its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort\r
+* to remove any extra files that the user would need to touch. Removed the flash_options.c\r
+* file and put its contents in vecttbl.c.\r
+* : 17.07.2012 1.50 Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT \r
+* macro options in r_bsp_config.h. Added some extra code to handle exceptions in\r
+* vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks.\r
+* : 08.11.2012 1.60 Added RX111 BSP\r
+***********************************************************************************************************************/\r
+\r
+#ifndef _PLATFORM_H_\r
+#define _PLATFORM_H_\r
+\r
+/***********************************************************************************************************************\r
+DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING.\r
+***********************************************************************************************************************/\r
+/* RSKRX610 */\r
+//#include "./board/rskrx610/r_bsp.h"\r
+\r
+/* RSKRX62N */\r
+//#include "./board/rskrx62n/r_bsp.h"\r
+\r
+/* RSKRX62T */\r
+//#include "./board/rskrx62t/r_bsp.h"\r
+\r
+/* RDKRX62N */\r
+//#include "./board/rdkrx62n/r_bsp.h"\r
+\r
+/* RSKRX630 */\r
+//#include "./board/rskrx630/r_bsp.h"\r
+\r
+/* RSKRX63N */\r
+//#include "./board/rskrx63n/r_bsp.h"\r
+\r
+/* RDKRX63N */\r
+//#include "./board/rdkrx63n/r_bsp.h"\r
+\r
+/* RSKRX210 */\r
+//#include "./board/rskrx210/r_bsp.h"\r
+\r
+/* RSKRX111 */\r
+#include "./board/rskrx111/r_bsp.h"\r
+\r
+/* User Board - Define your own board here. */\r
+//#include "./board/user/r_bsp.h"\r
+\r
+/***********************************************************************************************************************\r
+MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT\r
+***********************************************************************************************************************/\r
+#ifndef PLATFORM_DEFINED\r
+#error "Error - No platform defined in platform.h!"\r
+#endif\r
+\r
+#endif /* _PLATFORM_H_ */\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp_config_reference.c\r
+* Device(s) : RX111\r
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included\r
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)\r
+* is just a reference file that the user can use to make their own r_bsp_config.h file.\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 07.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE\r
+#define R_BSP_CONFIG_REF_HEADER_FILE\r
+\r
+/***********************************************************************************************************************\r
+Configuration Options\r
+***********************************************************************************************************************/\r
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such\r
+ as package and memory size.\r
+ To help parse this information, the part number will be defined using multiple macros.\r
+ R 5 F 51 11 5 A D FM\r
+ | | | | | | | | | Macro Name Description\r
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch\r
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)\r
+ | | | | | | |______not used = Blank\r
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity\r
+ | | | | |___________MCU_PART_GROUP = Group name\r
+ | | | |______________MCU_PART_SERIES = Series name\r
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)\r
+ | |__________________not used = Renesas MCU\r
+ |____________________not used = Renesas semiconductor product.\r
+ */\r
+\r
+/* Package type. Set the macro definition based on values below:\r
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch\r
+ FM = 0x0 = LFQFP/64/0.50\r
+ FK = 0x1 = LQFP/64/0.80\r
+ LF = 0x2 = TFLGA/64/0.50\r
+ FL = 0x3 = LFQFP/48/0.50\r
+ NE = 0x4 = VQFN/48/0.50\r
+ NC = 0x5 = HWQFN/36/0.50\r
+ LM = 0x6 = WFLGA/36/0.50\r
+ SB = 0x7 = SSOP/36/0.80\r
+*/\r
+#define MCU_PART_PACKAGE (0x0)\r
+\r
+/* ROM, RAM, and Data Flash Capacity.\r
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size\r
+ 5 = 0x5 = 128KB/16KB/8KB\r
+ 4 = 0x4 = 96KB/16KB/8KB\r
+ 3 = 0x3 = 64KB/10KB/8KB\r
+ 1 = 0x1 = 32KB/10KB/8KB\r
+ J = 0x0 = 16KB/8KB/8KB\r
+*/\r
+#define MCU_PART_MEMORY_SIZE (0x5)\r
+\r
+/* Group name.\r
+ Character(s) = Value for macro = Description\r
+ 10 = 0x0 = RX110 Group\r
+ 11 = 0x1 = RX111 Group\r
+*/\r
+#define MCU_PART_GROUP (0x1)\r
+\r
+/* Series name.\r
+ Character(s) = Value for macro = Description\r
+ 51 = 0x0 = RX100 Series\r
+*/\r
+#define MCU_PART_SERIES (0x0)\r
+\r
+/* Memory type.\r
+ Character(s) = Value for macro = Description\r
+ F = 0x0 = Flash memory version\r
+*/\r
+#define MCU_PART_MEMORY_TYPE (0x0)\r
+\r
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a\r
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */\r
+#if defined(BSP_DECLARE_STACK)\r
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize su=0x400\r
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize si=0x100\r
+#endif\r
+\r
+/* Heap size in bytes. */\r
+#define HEAP_BYTES (0x001)\r
+\r
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information\r
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.\r
+ 0 = Stay in Supervisor mode.\r
+ 1 = Switch to User mode.\r
+*/\r
+#define RUN_IN_USER_MODE (0)\r
+\r
+\r
+/* This macro lets other modules no if a RTOS is being used.\r
+ 0 = RTOS is not used.\r
+ 1 = RTOS is used.\r
+*/\r
+#define RTOS_USED (0)\r
+\r
+/* Clock source select (CKSEL).\r
+ 0 = Low Speed On-Chip Oscillator (LOCO)\r
+ 1 = High Speed On-Chip Oscillator (HOCO)\r
+ 2 = Main Clock Oscillator\r
+ 3 = Sub-Clock Oscillator\r
+ 4 = PLL Circuit\r
+*/\r
+#define CLOCK_SOURCE (4) // GI org 4\r
+\r
+/* Clock configuration options.\r
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The\r
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the\r
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the\r
+ settings would be:\r
+\r
+ XTAL_HZ = 16000000\r
+ PLL_DIV = 2\r
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)\r
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz\r
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz\r
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz\r
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz\r
+*/\r
+/* XTAL - Input clock frequency in Hz */\r
+#define XTAL_HZ (16000000)\r
+/* PLL Input Frequency Divider Select (PLIDIV).\r
+ Available divisors = /1 (no division), /2, /4\r
+*/\r
+#define PLL_DIV (2) // GI org 2\r
+/* PLL Frequency Multiplication Factor Select (STC).\r
+ Available multipliers = x6, x8\r
+*/\r
+#define PLL_MUL (6) // GI org 6\r
+/* System Clock Divider (ICK).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define ICK_DIV (2) // NOTE: ICLK CANNOT BE SLOWER THAN PCLK!\r
+/* Peripheral Module Clock B Divider (PCKB).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKB_DIV (2) // GI org 2\r
+/* Peripheral Module Clock D Divider (PCKD).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKD_DIV (2)\r
+/* Flash IF Clock Divider (FCK).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define FCK_DIV (2)\r
+\r
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and\r
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a\r
+ function to be called when the event occurs. For example, if the user wanted the function\r
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would\r
+ do the following:\r
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+ If the user does not wish to be alerted of these events then they should comment out the macros.\r
+\r
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function\r
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it\r
+ is executing. For this reason, it is recommended to keep these callback functions short as to not\r
+ decrease the real-time response of your system.\r
+*/\r
+/* Callback for Supervisor Instruction Violation Exception. */\r
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb\r
+\r
+/* Callback for Undefined Instruction Exception. */\r
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb\r
+\r
+/* Callback for Non-maskable Interrupt. */\r
+//#define NMI_ISR_CALLBACK nmi_cb\r
+\r
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source\r
+ is creating unwanted interrupts. */\r
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+\r
+/* Callback for Bus Error Interrupt. */\r
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb\r
+\r
+/* The user has the option of separately choosing little or big endian for the User Application Area */\r
+\r
+/* Endian mode for User Application.\r
+ 0 = Big Endian\r
+ Else = Little Endian (Default)\r
+*/\r
+#define USER_APP_ENDIAN (1)\r
+\r
+\r
+/* Configure WDT and IWDT settings.\r
+ OFS0 - Option Function Select Register 0\r
+ OFS0 - Option Function Select Register 0\r
+ b31:b15 Reserved (set to 1)\r
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)\r
+ b13 Reserved (set to 1)\r
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)\r
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)\r
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)\r
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)\r
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)\r
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)\r
+ b0 Reserved (set to 1) */\r
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.\r
+ OFS1 - Option Function Select Register 1\r
+ b31:b9 Reserved (set to 1)\r
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)\r
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select\r
+ 0 1 0 0: 3.10 V\r
+ 0 1 0 1: 3.00 V\r
+ 0 1 1 0: 2.90 V\r
+ 0 1 1 1: 2.79 V\r
+ 1 0 0 0: 2.68 V\r
+ 1 0 0 1: 2.58 V\r
+ 1 0 1 0: 2.48 V\r
+ 1 0 1 1: 2.06 V\r
+ 1 1 0 0: 1.96 V\r
+ 1 1 0 1: 1.86 V\r
+ b3:b2 Reserved (set to 1)\r
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)\r
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */\r
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Initializes C input & output library functions.\r
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.\r
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */\r
+#define IO_LIB_ENABLE (0)\r
+\r
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */\r
+\r
+\r
+\r
--- /dev/null
+r_bsp Package\r
+=============\r
+\r
+Document Number\r
+---------------\r
+N/A\r
+\r
+Version\r
+-------\r
+v1.60\r
+\r
+Overview\r
+--------\r
+The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU\r
+information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder has iodefine\r
+files and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board\r
+and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help \r
+configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each \r
+supported board. Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which \r
+board they are using by uncommenting the include path that applies to their board. For example, if you are using the \r
+RSK+RX62N then you would uncomment the #include "./board/rskrx62n/r_bsp.h" include path. Users are encouraged to add \r
+their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a \r
+reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it \r
+to r_bsp_config.h, and use the options inside the file to configure the BSP for their project.\r
+\r
+Features\r
+--------\r
+* Provides foundation to build code on top of.\r
+* Provides MCU startup code.\r
+* Provides SFR access through iodefine.h\r
+* Stores details of MCU in 'mcu_info.h' to help configure Renesas middleware.\r
+* Easily configure BSP through r_bsp_config.h.\r
+* Choose MCU easily by inputting part number details in r_bsp_config.h.\r
+* Provides callbacks for MCU exceptions and the bus error interrupt.\r
+ \r
+Limitations\r
+-----------\r
+N/A\r
+\r
+Peripherals Used Directly\r
+-------------------------\r
+N/A\r
+\r
+Required Packages\r
+-----------------\r
+* r_glyph [required if you want to use LCD for RDK boards]\r
+* r_rspi_rx [required if you want to use LCD for RDK boards]\r
+\r
+How to add to your project\r
+--------------------------\r
+* Copy the r_bsp folder to your project.\r
+* Add an include path to the 'r_bsp' directory. \r
+* Add all of the source files for your board from the 'r_bsp\board\--YOUR_BOARD--' directory to your project. \r
+* Uncomment the include path for your board in 'platform.h' which is located in the 'r_bsp' directory.\r
+* Copy the file r_bsp_config_reference.h from the 'r_bsp\board\--YOUR_BOARD--' directory and copy it to your project's\r
+ source code directory. Rename the file r_bsp_config.h.\r
+* Open r_bsp_config.h and use the macros to configure the BSP for your project.\r
+\r
+File Structure\r
+--------------\r
+r_bsp\r
+| platform.h (choose which board is being used)\r
+| readme.txt\r
+|\r
++---board (contains supported boards)\r
+| +---rdkrx62n (contains BSP source and header files)\r
+| |\r
+| +---rdkrx63n\r
+| |\r
+| +---rskrx111\r
+| |\r
+| +---rskrx210\r
+| |\r
+| +---rskrx610\r
+| |\r
+| +---rskrx62n\r
+| |\r
+| +---rskrx62t\r
+| |\r
+| +---rskrx630\r
+| |\r
+| +---rskrx63n\r
+| |\r
+| \---user\r
+|\r
+\---mcu\r
+ +---rx111 (contains common files to this MCU group, e.g. iodefine.h)\r
+ |\r
+ +---rx210 \r
+ |\r
+ +---rx610\r
+ |\r
+ +---rx62n\r
+ |\r
+ +---rx62t\r
+ |\r
+ +---rx630\r
+ |\r
+ \---rx63n\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_switches_config.c\r
+* Description : Configures the switches code\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 17.01.2012 1.00 First Release\r
+* : 17.02.2012 1.10 Added RSKRX210 support.\r
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).\r
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.\r
+***********************************************************************************************************************/\r
+#ifndef SWITCHES_CONFIG_HEADER_FILE\r
+#define SWITCHES_CONFIG_HEADER_FILE\r
+\r
+/***********************************************************************************************************************\r
+Configuration Options\r
+***********************************************************************************************************************/\r
+/* This macro sets whether interrupts or polling is used for detecting switch presses. The benefit of using interrupts\r
+ is that no extra processing is used for polling and the use of a system timer tick is not a requirement. The downside\r
+ of using interrupts is that callback functions are called from within an interrupt so if your ISR is long then it can\r
+ degrade the real-time response of your system. The benefit of polling is that functions are called at the application\r
+ level and debouncing is supported. The downside to polling is that your system must call the R_SWITCHES_Update() on a\r
+ regular basis which requires extra processing.\r
+\r
+ 0 = Use interrupts\r
+ 1 = Use polling\r
+ */\r
+#define SWITCHES_DETECTION_MODE (0)\r
+\r
+#endif /* SWITCHES_CONFIG_HEADER_FILE */\r
--- /dev/null
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches_if.h
+* Description : Functions for using switches with callback functions.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+***********************************************************************************************************************/
+
+#ifndef SWITCHES_API_HEADER_FILE
+#define SWITCHES_API_HEADER_FILE
+
+/***********************************************************************************************************************
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/
+/* Fixed width integer support. */\r
+#include <stdint.h>\r
+/* Used for configuring the code */
+#include "r_switches_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Version Number of API. */
+#define SWITCHES_VERSION_MAJOR (1)
+#define SWITCHES_VERSION_MINOR (0)
+/* The process of getting the version number is done through the macro below. The version number is encoded where the
+ top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example,
+ Version 4.25 would be returned as 0x00040019. */
+#define R_SWITCHES_GetVersion() ((((uint32_t)SWITCHES_VERSION_MAJOR) << 16) | (uint32_t)SWITCHES_VERSION_MINOR)
+
+/***********************************************************************************************************************
+Public Functions
+***********************************************************************************************************************/
+void R_SWITCHES_Init(void);
+void R_SWITCHES_Update(void);
+
+/* Callback prototypes. */
+#if defined(SW1_CALLBACK_FUNCTION)
+void SW1_CALLBACK_FUNCTION(void);
+#endif
+
+#if defined(SW2_CALLBACK_FUNCTION)
+void SW2_CALLBACK_FUNCTION(void);
+#endif
+
+#if defined(SW3_CALLBACK_FUNCTION)
+void SW3_CALLBACK_FUNCTION(void);
+#endif
+
+#endif /* SWITCHES_API_HEADER_FILE */
+
--- /dev/null
+PLEASE REFER TO THE APPLICATION NOTE FOR THIS MIDDLEWARE FOR MORE INFORMATION\r
+\r
+Switches\r
+========\r
+\r
+Document Number \r
+---------------\r
+N/A\r
+\r
+Version\r
+-------\r
+v1.40\r
+\r
+Overview\r
+--------\r
+Configures port pins for switches and calls user defined function on switch press. Switch presses can be detected using \r
+IRQ interrupts or by polling. The benefit of using interrupts is that no extra processing is used for polling and the \r
+use of a system timer tick is not a requirement. The downside of using interrupts is that callback functions are called \r
+from within an interrupt so if your ISR is long then it can degrade the real-time response of your system. The benefit \r
+of polling is that functions are called at the application level and debouncing is supported. The downside to polling is \r
+that your system must call the R_SWITCHES_Update() on a regular basis which requires extra processing.\r
+\r
+Features\r
+--------\r
+* Call one function to setup switches.\r
+* Define function to call when switch is pressed.\r
+* Can be configured to be interrupt or poll driven.\r
+\r
+Supported MCUs\r
+--------------\r
+* RX610 Group\r
+* RX621, RX62N Group\r
+* RX62T Group\r
+* RX630 Group\r
+* RX631, RX63N Group\r
+* RX210 Group\r
+* RX111 Group\r
+\r
+Boards Tested On\r
+----------------\r
+* RSKRX610\r
+* RSK+RX62N\r
+* RSKRX62T\r
+* RDKRX62N\r
+* RSKRX630\r
+* RSKRX63N\r
+* RDKRX63N\r
+* RSKRX111\r
+\r
+Limitations\r
+-----------\r
+* None\r
+\r
+Peripherals Used Directly\r
+-------------------------\r
+* None\r
+\r
+Required Packages\r
+-----------------\r
+* None\r
+\r
+How to add to your project\r
+--------------------------\r
+* Add src\r_switches.c to your project.\r
+* Add an include path to the 'r_switches' directory. \r
+* Add an include path to the 'r_switches\src' directory.\r
+* Configure middleware through r_switches_config.h.\r
+* Add a #include for r_switches_if.h to files that need to use this package. \r
+\r
+Toolchain(s) Used\r
+-----------------\r
+* Renesas RX v1.02\r
+\r
+File Structure\r
+--------------\r
+r_switches\r
+| readme.txt\r
+| r_switches_config.h\r
+| r_switches_if.h\r
+|\r
+\---src\r
+ r_switches.c\r
+ \r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_switches.c\r
+* Description : Functions for using switches with callback functions.\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 17.01.2012 1.00 First Release\r
+* : 17.02.2012 1.10 Added RSKRX210 support.\r
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).\r
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.\r
+* : 07.11.2012 1.40 Added support for RSKRX111\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Board and MCU support. */\r
+#include "platform.h"\r
+/* Switches prototypes. */\r
+#include "r_switches_if.h"\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+typedef int bool;\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* This helps reduce the amount of unique code for each supported board. */\r
+#define X_IRQ( x ) XX_IRQ( x )\r
+#define XX_IRQ( x ) _ICU_IRQ##x\r
+\r
+/* These macros define which IRQ pins are used for the switches. Note that these defintions cannot have parentheses\r
+ around them. */\r
+#if defined(PLATFORM_BOARD_RSKRX111)\r
+ #define SW1_IRQ_NUMBER 0\r
+ #define SW2_IRQ_NUMBER 1\r
+ #define SW3_IRQ_NUMBER 4\r
+#else\r
+ #error This file is only for use on the RX100 RSK\r
+#endif\r
+\r
+/* Number of switches on this board. */\r
+#define SWITCHES_NUM (3)\r
+\r
+/* Register definitions not yet correct in iodefine.h. */\r
+#define MPC_P30PFS_REG ( * ( unsigned char * ) 0x0008C158 )\r
+#define MPC_P31PFS_REG ( * ( unsigned char * ) 0x0008C159 )\r
+#define MPC_PE4PFS_REG ( * ( unsigned char * ) 0x0008C1B4 )\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+typedef struct\r
+{\r
+ bool active;\r
+ int32_t debounce_cnt;\r
+} switch_t;\r
+\r
+/***********************************************************************************************************************\r
+Private global variables and functions\r
+***********************************************************************************************************************/\r
+#if SWITCHES_DETECTION_MODE == 1\r
+/* Update Hz */\r
+static uint32_t g_sw_debounce_cnts;\r
+/* Used for debounce. */\r
+switch_t g_switches[SWITCHES_NUM];\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_SWITCHES_Init\r
+* Description : Initializes pins to be input and interrupt on switch presses.\r
+* Arguments :\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+\r
+void R_SWITCHES_Init (void)\r
+{\r
+ /* Unlock protection register */\r
+ MPC.PWPR.BYTE &= 0x7F;\r
+ /* Unlock MPC registers */\r
+ MPC.PWPR.BYTE |= 0x40;\r
+\r
+ /* Make switch pins inputs. */\r
+ PORT3.PDR.BYTE &= 0xFC;\r
+ PORTE.PDR.BYTE &= 0xEF;\r
+\r
+ /* Set port mode registers for switches. */\r
+ PORT3.PMR.BYTE &= 0xFC;\r
+ PORTE.PMR.BYTE &= 0xEF;\r
+\r
+ MPC_P30PFS_REG = 0x40; /* P30 is used as IRQ pin */\r
+ MPC_P31PFS_REG = 0x40; /* P31 is used as IRQ pin */\r
+ MPC_PE4PFS_REG = 0x40; /* PE4 is used as IRQ pin */\r
+\r
+ /* Set IRQ type (falling edge) */\r
+ ICU.IRQCR[ SW1_IRQ_NUMBER ].BYTE = 0x04;\r
+ ICU.IRQCR[ SW2_IRQ_NUMBER ].BYTE = 0x04;\r
+ ICU.IRQCR[ SW3_IRQ_NUMBER ].BYTE = 0x04;\r
+\r
+ /* Set interrupt priorities, which must be below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ _IPR( X_IRQ(SW1_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;\r
+ _IPR( X_IRQ(SW2_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;\r
+ _IPR( X_IRQ(SW3_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;\r
+\r
+ /* Clear any pending interrupts */\r
+ _IR( X_IRQ(SW1_IRQ_NUMBER) ) = 0;\r
+ _IR( X_IRQ(SW2_IRQ_NUMBER) ) = 0;\r
+ _IR( X_IRQ(SW3_IRQ_NUMBER) ) = 0;\r
+\r
+ /* Enable the interrupts */\r
+ _IEN( X_IRQ(SW1_IRQ_NUMBER) ) = 1;\r
+ _IEN( X_IRQ(SW2_IRQ_NUMBER) ) = 1;\r
+ _IEN( X_IRQ(SW3_IRQ_NUMBER) ) = 1;\r
+}\r
+\r
+/* If using polling then the user must call the update function. */\r
+\r
+/***********************************************************************************************************************\r
+* Function name: R_SWITCHES_Update\r
+* Description : Polls switches and calls callback functions as needed. If you are using IRQ mode then this function\r
+* is not needed and can be removed if desired. It is left in so that code will not fail when switching\r
+* between polling or IRQ mode.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void R_SWITCHES_Update (void)\r
+{\r
+#if SWITCHES_DETECTION_MODE == 1\r
+ /* This code is only needed for polling mode. */\r
+ /* Check switch 1. */\r
+ if (SW1 == SW_ACTIVE)\r
+ {\r
+ if (g_switches[0].active != true)\r
+ {\r
+ if (++g_switches[0].debounce_cnt >= g_sw_debounce_cnts)\r
+ {\r
+ /* Set this to true so we only call the callback function once per press. */\r
+ g_switches[0].active = true;\r
+\r
+ /* Call callback function. */\r
+ SW1_CALLBACK_FUNCTION();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (0 == g_switches[0].debounce_cnt)\r
+ {\r
+ g_switches[0].active = false;\r
+ }\r
+ else\r
+ {\r
+ g_switches[0].debounce_cnt--;\r
+ }\r
+ }\r
+\r
+ /* Check switch 2. */\r
+ if (SW2 == SW_ACTIVE)\r
+ {\r
+ if (g_switches[1].active != true)\r
+ {\r
+ if (++g_switches[1].debounce_cnt >= g_sw_debounce_cnts)\r
+ {\r
+ /* Set this to true so we only call the callback function once per press. */\r
+ g_switches[1].active = true;\r
+\r
+ /* Call callback function. */\r
+ SW2_CALLBACK_FUNCTION();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (0 == g_switches[1].debounce_cnt)\r
+ {\r
+ g_switches[1].active = false;\r
+ }\r
+ else\r
+ {\r
+ g_switches[1].debounce_cnt--;\r
+ }\r
+ }\r
+\r
+ /* Check switch 3. */\r
+ if (SW3 == SW_ACTIVE)\r
+ {\r
+ if (g_switches[2].active != true)\r
+ {\r
+ if (++g_switches[2].debounce_cnt >= g_sw_debounce_cnts)\r
+ {\r
+ /* Set this to true so we only call the callback function once per press. */\r
+ g_switches[2].active = true;\r
+\r
+ /* Call callback function. */\r
+ SW3_CALLBACK_FUNCTION();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (0 == g_switches[2].debounce_cnt)\r
+ {\r
+ g_switches[2].active = false;\r
+ }\r
+ else\r
+ {\r
+ g_switches[2].debounce_cnt--;\r
+ }\r
+ }\r
+#endif /* SWITCHES_DETECTION_MODE */\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A low power project that\r
+ * demonstrates the FreeRTOS tickless mode, and a more comprehensive test and\r
+ * demo application. The configCREATE_LOW_POWER_DEMO setting (defined at the\r
+ * top of FreeRTOSConfig.h) is used to select between the two. The low power\r
+ * demo is implemented and described in main_low_power.c. The more\r
+ * comprehensive test and demo application is implemented and described in\r
+ * main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Platform includes. */\r
+#include "lcd.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1.\r
+ * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0.\r
+ */\r
+extern void main_low_power( void );\r
+extern void main_full( void );\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the documentation page for this demo on the FreeRTOS.org web site for\r
+full information - including hardware setup requirements. */\r
+\r
+void main( void )\r
+{\r
+ lcd_initialize();\r
+ lcd_display( LCD_LINE1, "FreeRTOS" );\r
+\r
+ /* The configCREATE_LOW_POWER_DEMO setting is described in FreeRTOSConfig.h. */\r
+ #if configCREATE_LOW_POWER_DEMO == 1\r
+ {\r
+ lcd_display( LCD_LINE2, "LP Demo" );\r
+ main_low_power();\r
+ }\r
+ #else\r
+ {\r
+ lcd_display( LCD_LINE2, "Ful Demo" );\r
+ main_full();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the size\r
+ of the heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE\r
+ in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is\r
+ called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if\r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAssertCalled( void )\r
+{\r
+volatile unsigned long ul = 0;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Set ul to a non-zero value using the debugger to step out of this\r
+ function. */\r
+ while( ul == 0 )\r
+ {\r
+ __asm volatile( "NOP" );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/* ****************************************************************************\r
+ * This project includes a lot of tasks and tests and is therefore complex.\r
+ * If you would prefer a much simpler project to get started with then select\r
+ * the 'low power' demo by setting configCREATE_LOW_POWER_DEMO to 1 in\r
+ * FreeRTOSConfig.h. When configCREATE_LOW_POWER_DEMO is set to 1 main() will\r
+ * call main_low_power() instead of main_full().\r
+ * ****************************************************************************\r
+ *\r
+ * Creates all the demo application tasks, then starts the scheduler. The web\r
+ * documentation provides more details of the standard demo application tasks,\r
+ * which provide no particular functionality but do provide a good example of\r
+ * how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then\r
+ * repeatedly check that each register still contains its expected value for\r
+ * the lifetime of the tasks. Each task uses different values. The tasks run\r
+ * with very low priority so get preempted very frequently. A check variable\r
+ * is incremented on each iteration of the test loop. A register containing an\r
+ * unexpected value is indicative of an error in the context switching\r
+ * mechanism and will result in a branch to a null loop - which in turn will\r
+ * prevent the check variable from incrementing any further and allow the check\r
+ * timer (described below) to determine that an error has occurred. The nature\r
+ * of the reg test tasks necessitates that they are written in assembly code.\r
+ *\r
+ * "Check Timer" and Callback Function - The check timer period is initially\r
+ * set to three seconds. The check timer callback function checks that all the\r
+ * standard demo tasks are not only still executing, but are executing without\r
+ * reporting any errors. If the check timer discovers that a task has either\r
+ * stalled, or reported an error, then it changes its own period from the\r
+ * initial three seconds, to just 200ms. The check timer callback function\r
+ * also toggles LED 0 each time it is called. This provides a visual\r
+ * indication of the system status: If the LED toggles every three seconds,\r
+ * then no issues have been discovered. If the LED toggles every 200ms, then\r
+ * an issue has been discovered with at least one task.\r
+ *\r
+ * *NOTE 1* The CPU must be in Supervisor mode when the scheduler is started.\r
+ * The PowerON_Reset_PC() supplied in resetprg.c with this demo has\r
+ * Change_PSW_PM_to_UserMode() commented out to ensure this is the case.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Hardware specific includes. */\r
+#include "iodefine.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+#include "death.h"\r
+#include "blocktim.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+\r
+/* The code in this file is only built when configCREATE_LOW_POWER_DEMO is set\r
+to 0, otherwise the code in main_low_power.c is used. */\r
+#if configCREATE_LOW_POWER_DEMO == 0\r
+\r
+\r
+/* Values that are passed into the reg test tasks using the task parameter.\r
+The tasks check that the values are passed in correctly. */\r
+#define mainREG_TEST_1_PARAMETER ( 0x12121212UL )\r
+#define mainREG_TEST_2_PARAMETER ( 0x12345678UL )\r
+\r
+/* Priorities at which the standard demo tasks are created. */\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+\r
+/* The LED toggled by the check timer. */\r
+#define mainCHECK_LED ( 0 )\r
+\r
+/* The period at which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/* A block time of zero simple means "Don't Block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/*\r
+ * The reg test tasks as described at the top of this file.\r
+ */\r
+static void prvRegTest1Task( void *pvParameters );\r
+static void prvRegTest2Task( void *pvParameters );\r
+\r
+/*\r
+ * The actual implementation of the reg test functionality, which, because of\r
+ * the direct register access, have to be in assembly.\r
+ */\r
+static void prvRegTest1Implementation( void ) __attribute__(( naked ));\r
+static void prvRegTest2Implementation( void ) __attribute__(( naked ));\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Variables that are incremented on each iteration of the reg test tasks -\r
+provided the tasks have not reported any errors. The check timer inspects these\r
+variables to ensure they are still incrementing as expected. If a variable\r
+stops incrementing then it is likely that its associated task has stalled. */\r
+unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;\r
+\r
+/* The check timer. This uses prvCheckTimerCallback() as its callback\r
+function. */\r
+static xTimerHandle xCheckTimer = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* Start the reg test tasks which test the context switching mechanism. */\r
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the standard demo tasks. */\r
+ vCreateBlockTimeTasks();\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ );\r
+\r
+ configASSERT( xCheckTimer );\r
+\r
+ /* Start the check timer. It will actually start when the scheduler is\r
+ started. */\r
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+\r
+ /* Start the tasks running. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well execution will never reach here as the scheduler will be\r
+ running. If this null loop is reached then it is likely there was\r
+ insufficient FreeRTOS heap available for the idle task and/or timer task to\r
+ be created. See http://www.freertos.org/a00111.html. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE, lErrorStatus = pdPASS;\r
+static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL;\r
+\r
+ /* Remove compiler warnings about unused parameters. */\r
+ ( void ) xTimer;\r
+\r
+ /* Check the standard demo tasks are running without error. */\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+\r
+ /* Check the reg test tasks are still cycling. They will stop incrementing\r
+ their loop counters if they encounter an error. */\r
+ if( ulRegTest1CycleCount == ulLastRegTest1CycleCount )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+\r
+ if( ulRegTest2CycleCount == ulLastRegTest2CycleCount )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+\r
+ /* Remember the loop counter values this time around so they can be checked\r
+ again the next time this callback function executes. */\r
+ ulLastRegTest1CycleCount = ulRegTest1CycleCount;\r
+ ulLastRegTest2CycleCount = ulRegTest2CycleCount;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every three seconds then everything is ok. A faster toggle\r
+ indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+\r
+ /* Was an error detected this time through the callback execution? */\r
+ if( lErrorStatus != pdPASS )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+\r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ prvRegTest1Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ prvRegTest2Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest1Implementation( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ /* Set each register to a known value. */\r
+ " MOV.L #0x33333333, R15 \n\t"\r
+ " MVTACHI R15 \n\t"\r
+ " MOV.L #0x44444444, R15 \n\t"\r
+ " MVTACLO R15 \n\t"\r
+ " MOV.L #1, R1 \n\t"\r
+ " MOV.L #2, R2 \n\t"\r
+ " MOV.L #3, R3 \n\t"\r
+ " MOV.L #4, R4 \n\t"\r
+ " MOV.L #5, R5 \n\t"\r
+ " MOV.L #6, R6 \n\t"\r
+ " MOV.L #7, R7 \n\t"\r
+ " MOV.L #8, R8 \n\t"\r
+ " MOV.L #9, R9 \n\t"\r
+ " MOV.L #10, R10 \n\t"\r
+ " MOV.L #11, R11 \n\t"\r
+ " MOV.L #12, R12 \n\t"\r
+ " MOV.L #13, R13 \n\t"\r
+ " MOV.L #14, R14 \n\t"\r
+ " MOV.L #15, R15 \n\t"\r
+ " \n\t"\r
+ /* Loop, checking each iteration that each register still contains the\r
+ expected value. */\r
+ "TestLoop1: \n\t"\r
+ " \n\t"\r
+ /* Push the registers that are going to get clobbered. */\r
+ " PUSHM R14-R15 \n\t"\r
+ " \n\t"\r
+ /* Increment the loop counter to show this task is still getting CPU\r
+ time. */\r
+ " MOV.L #_ulRegTest1CycleCount, R14 \n\t"\r
+ " MOV.L [ R14 ], R15 \n\t"\r
+ " ADD #1, R15 \n\t"\r
+ " MOV.L R15, [ R14 ] \n\t"\r
+ " \n\t"\r
+ /* Yield to extend the text coverage. Set the bit in the ITU SWINTR\r
+ register. */\r
+ " MOV.L #1, R14 \n\t"\r
+ " MOV.L #0872E0H, R15 \n\t"\r
+ " MOV.B R14, [R15] \n\t"\r
+ " NOP \n\t"\r
+ " NOP \n\t"\r
+ " \n\t"\r
+ /* Check the accumulator value. */\r
+ " MVFACHI R15 \n\t"\r
+ " CMP #0x33333333, R15 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " MVFACMI R15 \n\t"\r
+ " CMP #0x33334444, R15 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " \n\t"\r
+ /* Restore the clobbered registers. */\r
+ " POPM R14-R15 \n\t"\r
+ " \n\t"\r
+ /* Now compare each register to ensure it still contains the value that\r
+ was set before this loop was entered. */\r
+ " CMP #1, R1 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #2, R2 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #3, R3 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #4, R4 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #5, R5 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #6, R6 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #7, R7 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #8, R8 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #9, R9 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #10, R10 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #11, R11 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #12, R12 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #13, R13 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #14, R14 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " CMP #15, R15 \n\t"\r
+ " BNE RegTest1Error \n\t"\r
+ " \n\t"\r
+ /* All comparisons passed, start a new iteration of this loop. */\r
+ " BRA TestLoop1 \n\t"\r
+ " \n\t"\r
+ /* A compare failed, just loop here so the loop counter stops\r
+ incrementing causing the check timer to indicate the error. */\r
+ "RegTest1Error: \n\t"\r
+ " BRA RegTest1Error "\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest2Implementation( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ /* Set each register to a known value. */\r
+ " MOV.L #0x11111111, R15 \n\t"\r
+ " MVTACHI R15 \n\t"\r
+ " MOV.L #0x22222222, R15 \n\t"\r
+ " MVTACLO R15 \n\t"\r
+ " MOV.L #100, R1 \n\t"\r
+ " MOV.L #200, R2 \n\t"\r
+ " MOV.L #300, R3 \n\t"\r
+ " MOV.L #400, R4 \n\t"\r
+ " MOV.L #500, R5 \n\t"\r
+ " MOV.L #600, R6 \n\t"\r
+ " MOV.L #700, R7 \n\t"\r
+ " MOV.L #800, R8 \n\t"\r
+ " MOV.L #900, R9 \n\t"\r
+ " MOV.L #1000, R10 \n\t"\r
+ " MOV.L #1001, R11 \n\t"\r
+ " MOV.L #1002, R12 \n\t"\r
+ " MOV.L #1003, R13 \n\t"\r
+ " MOV.L #1004, R14 \n\t"\r
+ " MOV.L #1005, R15 \n\t"\r
+ " \n\t"\r
+ /* Loop, checking each iteration that each register still contains the\r
+ expected value. */\r
+ "TestLoop2: \n\t"\r
+ " \n\t"\r
+ /* Push the registers that are going to get clobbered. */\r
+ " PUSHM R14-R15 \n\t"\r
+ " \n\t"\r
+ /* Increment the loop counter to show this task is still getting CPU\r
+ time. */\r
+ " MOV.L #_ulRegTest2CycleCount, R14 \n\t"\r
+ " MOV.L [ R14 ], R15 \n\t"\r
+ " ADD #1, R15 \n\t"\r
+ " MOV.L R15, [ R14 ] \n\t"\r
+ " \n\t"\r
+ /* Check the accumulator value. */\r
+ " MVFACHI R15 \n\t"\r
+ " CMP #0x11111111, R15 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " MVFACMI R15 \n\t"\r
+ " CMP #0x11112222, R15 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " \n\t"\r
+ /* Restore the clobbered registers. */\r
+ " POPM R14-R15 \n\t"\r
+ " \n\t"\r
+ /* Now compare each register to ensure it still contains the value that\r
+ was set before this loop was entered. */\r
+ " CMP #100, R1 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #200, R2 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #300, R3 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #400, R4 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #500, R5 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #600, R6 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #700, R7 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #800, R8 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #900, R9 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #1000, R10 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #1001, R11 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #1002, R12 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #1003, R13 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #1004, R14 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " CMP #1005, R15 \n\t"\r
+ " BNE RegTest2Error \n\t"\r
+ " \n\t"\r
+ /* All comparisons passed, start a new iteration of this loop. */\r
+ " BRA TestLoop2 \n\t"\r
+ " \n\t"\r
+ /* A compare failed, just loop here so the loop counter stops\r
+ incrementing causing the check timer to indicate the error. */\r
+ "RegTest2Error: \n\t"\r
+ " BRA RegTest2Error "\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#endif /* configCREATE_LOW_POWER_DEMO */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/* ****************************************************************************\r
+ * When configCREATE_LOW_POWER_DEMO is set to 1 in FreeRTOSConfig.h main() will\r
+ * call main_low_power(), which is defined in this file. main_low_power()\r
+ * demonstrates FreeRTOS tick suppression being used to allow the MCU to be\r
+ * placed into both the low power deep sleep mode and the low power software\r
+ * standby mode. When configCREATE_LOW_POWER_DEMO is set to 0 main will\r
+ * instead call main_full(), which is a more comprehensive RTOS demonstration.\r
+ * ****************************************************************************\r
+ *\r
+ * This application demonstrates the FreeRTOS tickless idle mode (tick\r
+ * suppression). See http://www.freertos.org/low-power-tickless-rtos.html\r
+ * The demo is configured to execute on the Renesas RX100 RSK.\r
+ *\r
+ * Functionality:\r
+ *\r
+ * + Two tasks are created, an Rx task and a Tx task.\r
+ *\r
+ * + The Rx task repeatedly blocks on a queue to wait for data. The Rx task\r
+ * toggles LED 0 each time is receives a value from the queue.\r
+ *\r
+ * + The Tx task repeatedly enters the Blocked state for an amount of time\r
+ * that is set by the position of the potentiometer. On exiting the blocked\r
+ * state the Tx task sends a value through the queue to the Rx task (causing\r
+ * the Rx task to exit the blocked state and toggle LED 0).\r
+ *\r
+ * If the value read from the potentiometer is less than or equal to\r
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks for the equivalent\r
+ * number of milliseconds. For example, if the sampled analog value is\r
+ * 2000, then the Tx task blocks for 2000ms. Blocking for a finite period\r
+ * allows the kernel to stop the tick interrupt and place the RX100 into\r
+ * deep sleep mode.\r
+ *\r
+ * If the value read form the potentiometer is greater than\r
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks on a semaphore with\r
+ * an infinite timeout. Blocking with an infinite timeout allows the kernel\r
+ * to stop the tick interrupt and place the RX100 into software standby\r
+ * mode. Pressing a button will generate an interrupt that causes the RX100\r
+ * to exit software standby mode. The interrupt service routine 'gives' the\r
+ * semaphore to unblock the Tx task.\r
+ *\r
+ *\r
+ * Using the Demo and Observed Behaviour:\r
+ *\r
+ * 1) Turn the potentiometer completely counter clockwise.\r
+ *\r
+ * 2) Program the RX100 with the application, then disconnect the programming/\r
+ * debugging hardware to ensure power readings are not effected by any\r
+ * connected interfaces.\r
+ *\r
+ * 3) Start the application running. LED 0 will toggle quickly because the\r
+ * potentiometer is turned to its lowest value. LED 1 will be illuminated\r
+ * when the RX100 is not in a power saving mode, but will appear to be off\r
+ * because most execution time is spent in a sleep mode. Led 2 will be\r
+ * illuminated when the RX100 is in deep sleep mode, and will appear to be\r
+ * always on, again because most execution time is spent in deep sleep mode.\r
+ * The LEDs are turned on and off by the application defined pre and post\r
+ * sleep macros (see the definitions of configPRE_SLEEP_PROCESSING() and\r
+ * configPOST_SLEEP_PROCESSING() in FreeRTOSConfig.h).\r
+ *\r
+ * 4) Slowly turn the potentiometer in the clockwise direction. This will\r
+ * increase the value read from the potentiometer, which will increase the\r
+ * time the Tx task spends in the Blocked state, which will therefore\r
+ * decrease the frequency at which the Tx task sends data to the queue (and\r
+ * the rate at which LED 0 is toggled).\r
+ *\r
+ * 5) Keep turning the potentiometer in the clockwise direction. Eventually\r
+ * the value read from the potentiometer will go above\r
+ * mainSOFTWARE_STANDBY_DELAY, causing the Tx task to block on the semaphore\r
+ * with an infinite timeout. LED 0 will stop toggling because the Tx task is\r
+ * no longer sending to the queue. LED 1 and LED 2 will both be off because\r
+ * the RX100 is neither running or in deep sleep mode (it is in software\r
+ * standby mode).\r
+ *\r
+ * 6) Turn the potentiometer counter clockwise again to ensure its value goes\r
+ * back below mainSOFTWARE_STANDBY_DELAY.\r
+ *\r
+ * 7) Press any of the three buttons to generate an interrupt. The interrupt\r
+ * will take the RX100 out of software standby mode, and the interrupt\r
+ * service routine will unblock the Tx task by 'giving' the semaphore. LED 0\r
+ * will then start to toggle again.\r
+ *\r
+ */\r
+\r
+\r
+/* Hardware specific includes. */\r
+#include "platform.h"\r
+#include "r_switches_if.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Common demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the Rx and Tx tasks are created. */\r
+#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* The number of items the queue can hold. This is 1 as the Rx task will\r
+remove items as they are added so the Tx task should always find the queue\r
+empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* The LED used to indicate that a value has been received on the queue. */\r
+#define mainQUEUE_LED ( 0 )\r
+\r
+/* The LED used to indicate that full power is being used (the MCU is not in\r
+deep sleep or software standby mode). */\r
+#define mainFULL_POWER_LED ( 1 )\r
+\r
+/* The LED used to indicate that deep sleep mode is being used. */\r
+#define mainDEEP_SLEEP_LED ( 2 )\r
+\r
+/* The Tx task sends to the queue with a frequency that is set by the value\r
+read from the potentiometer until the value goes above that set by the\r
+mainSOFTWARE_STANDBY_DELAY constant - at which time the Tx task instead blocks\r
+indefinitely on a semaphore. */\r
+#define mainSOFTWARE_STANDBY_DELAY ( 3000UL )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0 )\r
+\r
+/* The value that is sent from the Tx task to the Rx task on the queue. */\r
+#define mainQUEUED_VALUE ( 100UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The Rx and Tx tasks as described at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Reads and returns the value of the ADC connected to the potentiometer built\r
+ * onto the RSK.\r
+ */\r
+static unsigned short prvReadPOT( void );\r
+\r
+/*\r
+ * The handler for the interrupt generated when any of the buttons are pressed.\r
+ */\r
+void vButtonInterrupt( void ) __attribute__((interrupt));\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue to pass data from the Tx task to the Rx task. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/* The semaphore that is 'given' by interrupts generated from button pushes. */\r
+static xSemaphoreHandle xSemaphore = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_low_power( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+ configASSERT( xQueue );\r
+\r
+ /* Create the semaphore that is 'given' by an interrupt generated from a\r
+ button push. */\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ configASSERT( xSemaphore );\r
+\r
+ /* Make sure the semaphore starts in the expected state - no button pushes\r
+ have yet occurred. A block time of zero can be used as it is guaranteed\r
+ that the semaphore will be available because it has just been created. */\r
+ xSemaphoreTake( xSemaphore, mainDONT_BLOCK );\r
+\r
+ /* Start the two tasks as described at the top of this file. */\r
+ xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* The CPU is currently running, not sleeping, so turn on the LED that\r
+ shows the CPU is not in a sleep mode. */\r
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );\r
+\r
+ /* Start the scheduler running running. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well the next line of code will not be reached as the\r
+ scheduler will be running. If the next line is reached then it is likely\r
+ there was insufficient FreeRTOS heap available for the idle task and/or\r
+ timer task to be created. See http://www.freertos.org/a00111.html. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xDelay;\r
+const unsigned long ulValueToSend = mainQUEUED_VALUE;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* The delay period between successive sends to the queue is set by\r
+ the potentiometer reading. */\r
+ xDelay = ( portTickType ) prvReadPOT();\r
+\r
+ /* If the block time is greater than 3000 milliseconds then block\r
+ indefinitely waiting for a button push. */\r
+ if( xDelay > mainSOFTWARE_STANDBY_DELAY )\r
+ {\r
+ /* As this is an indefinite delay the kernel will place the CPU\r
+ into software standby mode the next time the idle task runs. */\r
+ xSemaphoreTake( xSemaphore, portMAX_DELAY );\r
+ }\r
+ else\r
+ {\r
+ /* Convert a time in milliseconds to a time in ticks. */\r
+ xDelay /= portTICK_RATE_MS;\r
+\r
+ /* Place this task in the blocked state until it is time to run\r
+ again. As this is not an indefinite sleep the kernel will place\r
+ the CPU into the deep sleep state when the idle task next runs. */\r
+ vTaskDelay( xDelay );\r
+ }\r
+\r
+ /* Send to the queue - causing the queue receive task to flash its LED.\r
+ It should not be necessary to block on the queue send because the Rx\r
+ task will have removed the last queued item. */\r
+ xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have arrived, but is it the expected\r
+ value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == mainQUEUED_VALUE )\r
+ {\r
+ vParTestToggleLED( mainQUEUE_LED );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPreSleepProcessing( unsigned long ulExpectedIdleTime )\r
+{\r
+ /* Called by the kernel before it places the MCU into a sleep mode because\r
+ configPRE_SLEEP_PROCESSING() is #defined to vPreSleepProcessing().\r
+\r
+ NOTE: Additional actions can be taken here to get the power consumption\r
+ even lower. For example, the ADC input used by this demo could be turned\r
+ off here, and then back on again in the power sleep processing function.\r
+ For maximum power saving ensure all unused pins are in their lowest power\r
+ state. */\r
+\r
+ /* Avoid compiler warnings about the unused parameter. */\r
+ ( void ) ulExpectedIdleTime;\r
+\r
+ /* Is the MCU about to enter deep sleep mode or software standby mode? */\r
+ if( SYSTEM.SBYCR.BIT.SSBY == 0 )\r
+ {\r
+ /* Turn on the LED that indicates deep sleep mode is being entered. */\r
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdTRUE );\r
+ }\r
+ else\r
+ {\r
+ /* Software standby mode is being used, so no LEDs are illuminated to\r
+ ensure minimum power readings are obtained. Ensure the Queue LED is\r
+ also off. */\r
+ vParTestSetLED( mainQUEUE_LED, pdFALSE );\r
+ }\r
+\r
+ /* Turn off the LED that indicates full power is being used. */\r
+ vParTestSetLED( mainFULL_POWER_LED, pdFALSE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPostSleepProcessing( unsigned long ulExpectedIdleTime )\r
+{\r
+ /* Called by the kernel when the MCU exits a sleep mode because\r
+ configPOST_SLEEP_PROCESSING is #defined to vPostSleepProcessing(). */\r
+\r
+ /* Avoid compiler warnings about the unused parameter. */\r
+ ( void ) ulExpectedIdleTime;\r
+\r
+ /* Turn off the LED that indicates deep sleep mode, and turn on the LED\r
+ that indicates full power is being used. */\r
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdFALSE );\r
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static unsigned short prvReadPOT( void )\r
+{\r
+unsigned short usADCValue;\r
+const unsigned short usMinADCValue = 128;\r
+\r
+ /* Start an ADC scan. */\r
+ S12AD.ADCSR.BIT.ADST = 1;\r
+ while( S12AD.ADCSR.BIT.ADST == 1 )\r
+ {\r
+ /* Just waiting for the ADC scan to complete. Inefficient\r
+ polling! */\r
+ }\r
+\r
+ usADCValue = S12AD.ADDR4;\r
+\r
+ /* Don't let the ADC value get too small as the LED behaviour will look\r
+ erratic. */\r
+ if( usADCValue < usMinADCValue )\r
+ {\r
+ usADCValue = usMinADCValue;\r
+ }\r
+\r
+ return usADCValue;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vButtonInterrupt( void )\r
+{\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* The semaphore is only created when the build is configured to create the\r
+ low power demo. */\r
+ if( xSemaphore != NULL )\r
+ {\r
+ /* This interrupt will bring the CPU out of deep sleep and software\r
+ standby modes. Give the semaphore that was used to place the Tx task\r
+ into an indefinite sleep. */\r
+ if( uxQueueMessagesWaitingFromISR( xSemaphore ) == 0 )\r
+ {\r
+ xSemaphoreGiveFromISR( xSemaphore, &lHigherPriorityTaskWoken );\r
+ }\r
+ else\r
+ {\r
+ /* The semaphore was already available, so the task is not blocked\r
+ on it and there is no point giving it. */\r
+ }\r
+\r
+ /* If giving the semaphore caused a task to leave the Blocked state,\r
+ and the task that left the Blocked state has a priority equal to or\r
+ above the priority of the task that this interrupt interrupted, then\r
+ lHigherPriorityTaskWoken will have been set to pdTRUE inside the call\r
+ to xSemaphoreGiveFromISR(), and calling portYIELD_FROM_ISR() will cause\r
+ a context switch to the unblocked task. */\r
+ portYIELD_FROM_ISR( lHigherPriorityTaskWoken );\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+ stdarg version contributed by Christian Ettinger\r
+\r
+ This program is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU Lesser General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ This program is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU Lesser General Public License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public License\r
+ along with this program; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+*/\r
+\r
+/*\r
+ putchar is the only external dependency for this file,\r
+ if you have a working putchar, leave it commented out.\r
+ If not, uncomment the define below and\r
+ replace outbyte(c) by your own function call.\r
+\r
+*/\r
+\r
+#define putchar(c) c\r
+\r
+#include <stdarg.h>\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+ //extern int putchar(int c);\r
+ \r
+ if (str) {\r
+ **str = (char)c;\r
+ ++(*str);\r
+ }\r
+ else\r
+ { \r
+ (void)putchar(c);\r
+ }\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+ register int pc = 0, padchar = ' ';\r
+\r
+ if (width > 0) {\r
+ register int len = 0;\r
+ register const char *ptr;\r
+ for (ptr = string; *ptr; ++ptr) ++len;\r
+ if (len >= width) width = 0;\r
+ else width -= len;\r
+ if (pad & PAD_ZERO) padchar = '0';\r
+ }\r
+ if (!(pad & PAD_RIGHT)) {\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+ }\r
+ for ( ; *string ; ++string) {\r
+ printchar (out, *string);\r
+ ++pc;\r
+ }\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+\r
+ return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+ char print_buf[PRINT_BUF_LEN];\r
+ register char *s;\r
+ register int t, neg = 0, pc = 0;\r
+ register unsigned int u = (unsigned int)i;\r
+\r
+ if (i == 0) {\r
+ print_buf[0] = '0';\r
+ print_buf[1] = '\0';\r
+ return prints (out, print_buf, width, pad);\r
+ }\r
+\r
+ if (sg && b == 10 && i < 0) {\r
+ neg = 1;\r
+ u = (unsigned int)-i;\r
+ }\r
+\r
+ s = print_buf + PRINT_BUF_LEN-1;\r
+ *s = '\0';\r
+\r
+ while (u) {\r
+ t = (unsigned int)u % b;\r
+ if( t >= 10 )\r
+ t += letbase - '0' - 10;\r
+ *--s = (char)(t + '0');\r
+ u /= b;\r
+ }\r
+\r
+ if (neg) {\r
+ if( width && (pad & PAD_ZERO) ) {\r
+ printchar (out, '-');\r
+ ++pc;\r
+ --width;\r
+ }\r
+ else {\r
+ *--s = '-';\r
+ }\r
+ }\r
+\r
+ return pc + prints (out, s, width, pad);\r
+}\r
+\r
+static int print( char **out, const char *format, va_list args )\r
+{\r
+ register int width, pad;\r
+ register int pc = 0;\r
+ char scr[2];\r
+\r
+ for (; *format != 0; ++format) {\r
+ if (*format == '%') {\r
+ ++format;\r
+ width = pad = 0;\r
+ if (*format == '\0') break;\r
+ if (*format == '%') goto out;\r
+ if (*format == '-') {\r
+ ++format;\r
+ pad = PAD_RIGHT;\r
+ }\r
+ while (*format == '0') {\r
+ ++format;\r
+ pad |= PAD_ZERO;\r
+ }\r
+ for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+ width *= 10;\r
+ width += *format - '0';\r
+ }\r
+ if( *format == 's' ) {\r
+ register char *s = (char *)va_arg( args, int );\r
+ pc += prints (out, s?s:"(null)", width, pad);\r
+ continue;\r
+ }\r
+ if( *format == 'd' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'x' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'X' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+ continue;\r
+ }\r
+ if( *format == 'u' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'c' ) {\r
+ /* char are converted to int then pushed on the stack */\r
+ scr[0] = (char)va_arg( args, int );\r
+ scr[1] = '\0';\r
+ pc += prints (out, scr, width, pad);\r
+ continue;\r
+ }\r
+ }\r
+ else {\r
+ out:\r
+ printchar (out, *format);\r
+ ++pc;\r
+ }\r
+ }\r
+ if (out) **out = '\0';\r
+ va_end( args );\r
+ return pc;\r
+}\r
+\r
+int printf(const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( &out, format, args );\r
+}\r
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+ va_list args;\r
+ \r
+ ( void ) count;\r
+ \r
+ va_start( args, format );\r
+ return print( &buf, format, args );\r
+}\r
+\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+ char *ptr = "Hello world!";\r
+ char *np = 0;\r
+ int i = 5;\r
+ unsigned int bs = sizeof(int)*8;\r
+ int mi;\r
+ char buf[80];\r
+\r
+ mi = (1 << (bs-1)) + 1;\r
+ printf("%s\n", ptr);\r
+ printf("printf test\n");\r
+ printf("%s is null pointer\n", np);\r
+ printf("%d = 5\n", i);\r
+ printf("%d = - max int\n", mi);\r
+ printf("char %c = 'a'\n", 'a');\r
+ printf("hex %x = ff\n", 0xff);\r
+ printf("hex %02x = 00\n", 0);\r
+ printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+ printf("%d %s(s)%", 0, "message");\r
+ printf("\n");\r
+ printf("%d %s(s) with %%\n", 0, "message");\r
+ sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+ sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+ sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+ return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ * printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left "\r
+ * justif: " right"\r
+ * 3: 0003 zero padded\r
+ * 3: 3 left justif.\r
+ * 3: 3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3 left justif.\r
+ * -3: -3 right justif.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/* To keep linker happy. */\r
+int write( int i, char* c, int n)\r
+{\r
+ (void)i;\r
+ (void)n;\r
+ (void)c;\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<launchConfiguration type="com.renesas.cdt.launch.dsf.gdbremote.launchConfigurationType">\r
+<intAttribute key="com.renesas.cdt.core.admPortNumber" value="61236"/>\r
+<stringAttribute key="com.renesas.cdt.core.initCommands" value=""/>\r
+<stringAttribute key="com.renesas.cdt.core.ipAddress" value="localhost"/>\r
+<stringAttribute key="com.renesas.cdt.core.jtagDevice" value="E1"/>\r
+<booleanAttribute key="com.renesas.cdt.core.loadImage" value="true"/>\r
+<stringAttribute key="com.renesas.cdt.core.optionInitCommands" value=""/>\r
+<intAttribute key="com.renesas.cdt.core.portNumber" value="61234"/>\r
+<stringAttribute key="com.renesas.cdt.core.runCommands" value=""/>\r
+<stringAttribute key="com.renesas.cdt.core.serverParam" value="-g E1 -l 0 -t R5F51115 -p 61234 -d 61236 -uClockSrcHoco= 0 -uInputClock= 12.0000 -uAllowClockSourceInternal= 1 -uUseFine= 1 -uFineBaudRate= 2.00 -w 0 -z 0 -uRegisterSetting= 0 -uModePin= 0 -uDebugMode= 0 -uExecuteProgram= 0 -uIdCode= FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -n 0 -uWorkRamAddress= 1000 -uProgReWriteIRom= 0 -uProgReWriteDFlash= 0"/>\r
+<booleanAttribute key="com.renesas.cdt.core.setResume" value="true"/>\r
+<booleanAttribute key="com.renesas.cdt.core.setStopAt" value="true"/>\r
+<booleanAttribute key="com.renesas.cdt.core.startServer" value="true"/>\r
+<stringAttribute key="com.renesas.cdt.core.stopAt" value="main"/>\r
+<stringAttribute key="com.renesas.cdt.core.targetDevice" value="R5F51115"/>\r
+<booleanAttribute key="com.renesas.cdt.core.useRemoteTarget" value="true"/>\r
+<booleanAttribute key="com.renesas.cdt.core.verboseMode" value="false"/>\r
+<stringAttribute key="com.renesas.cdt.launch.dsf.IO_MAP" value="${eclipse_home}..\internal\IoFiles\RX\RX111.sfrx"/>\r
+<booleanAttribute key="com.renesas.cdt.launch.dsf.USE_DEFAULT_IO_MAP" value="true"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.allow.clock.source.internal" value="true"/>\r
+<intAttribute key="com.renesas.hardwaredebug.e1.clock_source" value="0"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.connection.mode" value="0"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.e1_pwr" value="false"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.execute.program" value="false"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.external_memory" value=""/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.fine.baud.rate" value="2.00"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.flash_overwrite_blocks" value=""/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.hw_break" value="false"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.inputclock" value="12.0000"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.jtag.clock.freq" value="16.5"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.jtag.or.fine" value="1"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.le" value="true"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.mode" value="0"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.mode_pin" value="0"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.prog_rewrite_dflash" value="false"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.prog_rewrite_irom" value="false"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.supply.voltage" value="3.3V"/>\r
+<intAttribute key="com.renesas.hardwaredebug.e1.work_ram_start" value="4096"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e20.le" value="true"/>\r
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${eclipse_home}../DebugComp/rx-elf-gdb"/>\r
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>\r
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>\r
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="HardwareDebug\RTOSDemo_GCC.x"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RTOSDemo_GCC"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">\r
+<listEntry value="/RTOSDemo_GCC"/>\r
+</listAttribute>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">\r
+<listEntry value="4"/>\r
+</listAttribute>\r
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>\r
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>\r
+</launchConfiguration>\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* Hardware specifics. */\r
+#include "platform.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* DEMO SPECIFIC SETTING:\r
+ * Set configCREATE_LOW_POWER_DEMO to one to run the low power demo with tick\r
+ * suppression, or 0 to run the more comprehensive test and demo application.\r
+ * If configCREATE_LOW_POWER_DEMO is set to 1 then main() calls main_low_power().\r
+ * If configCREATE_LOW_POWER_DEMO is set to 0 then main() calls main_full().\r
+ */\r
+#define configCREATE_LOW_POWER_DEMO 1\r
+\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_TICKLESS_IDLE configCREATE_LOW_POWER_DEMO\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ICLK_HZ ) /* Set in mcu_info.h. */\r
+#define configPERIPHERAL_CLOCK_HZ ( PCLKB_HZ ) /* Set in muc_info.h. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 9 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions - only included when the demo is configured to\r
+build the full demo (as opposed to the low power demo). */\r
+#if configCREATE_LOW_POWER_DEMO == 1\r
+ #define configUSE_TIMERS 0\r
+#else\r
+ #define configUSE_TIMERS 1\r
+ #define configTIMER_TASK_PRIORITY ( 3 )\r
+ #define configTIMER_QUEUE_LENGTH 5\r
+ #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+#endif /* configCREATE_LOW_POWER_DEMO */\r
+\r
+/*\r
+The interrupt priority used by the kernel itself for the tick interrupt and\r
+the pended interrupt is set by configKERNEL_INTERRUPT_PRIORITY. This would\r
+normally be the lowest priority (1 in this case). The maximum interrupt\r
+priority from which FreeRTOS API calls can be made is set by\r
+configMAX_SYSCALL_INTERRUPT_PRIORITY. Interrupts that use a priority above this\r
+will not be effected by anything the kernel is doing. Interrupts at or below\r
+this priority can use FreeRTOS API functions - but *only* those that end in\r
+"FromISR". Both these constants are defined in 'PriorityDefinitions.h' so they\r
+can also be included in assembly source files.\r
+*/\r
+#include "PriorityDefinitions.h"\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+\r
+extern void vAssertCalled( void );\r
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled();\r
+\r
+/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros\r
+allow the application writer to add additional code before and after the MCU is\r
+placed into the low power state respectively. The implementations provided in\r
+this demo can be extended to save even more power - for example the analog\r
+input used by the low power demo could be switched off in the pre-sleep macro\r
+and back on again in the post sleep macro. */\r
+void vPreSleepProcessing( unsigned long xExpectedIdleTime );\r
+void vPostSleepProcessing( unsigned long xExpectedIdleTime );\r
+#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime );\r
+#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime );\r
+\r
+/* configTICK_VECTOR must be set to the interrupt vector used by the peripheral\r
+that generates the tick interrupt. */\r
+#define configTICK_VECTOR VECT_CMT0_CMI0\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+#define partestNUM_LEDS ( 4 )\r
+\r
+long lParTestGetLEDState( unsigned long ulLED );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Port pin configuration is done by the low level set up prior to this\r
+ function being called. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLED, signed long xValue )\r
+{\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ if( xValue != 0 )\r
+ {\r
+ /* Turn the LED on. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0: LED0 = LED_ON;\r
+ break;\r
+ case 1: LED1 = LED_ON;\r
+ break;\r
+ case 2: LED2 = LED_ON;\r
+ break;\r
+ case 3: LED3 = LED_ON;\r
+ break;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LED off. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0: LED0 = LED_OFF;\r
+ break;\r
+ case 1: LED1 = LED_OFF;\r
+ break;\r
+ case 2: LED2 = LED_OFF;\r
+ break;\r
+ case 3: LED3 = LED_OFF;\r
+ break;\r
+ }\r
+\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( lParTestGetLEDState( ulLED ) != 0x00 )\r
+ {\r
+ vParTestSetLED( ulLED, 0 );\r
+ }\r
+ else\r
+ {\r
+ vParTestSetLED( ulLED, 1 );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+long lParTestGetLEDState( unsigned long ulLED )\r
+{\r
+long lReturn = pdTRUE;\r
+\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0 : if( LED0 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ case 1 : if( LED1 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ case 2 : if( LED2 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ case 3 : if( LED3 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+#ifndef PRIORITY_DEFINITIONS_H\r
+#define PRIORITY_DEFINITIONS_H\r
+\r
+\r
+/* The interrupt priority used by the kernel itself for the tick interrupt and\r
+the pended interrupt. This would normally be the lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+\r
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
+Interrupts that use a priority above this will not be effected by anything the\r
+kernel is doing but must not make any use of FreeRTOS functionality.\r
+interrupts that use a priority at or below configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+can make use of FreeRTOS API function but *only* functions that end in\r
+"FromISR()". */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+#endif /* PRIORITY_DEFINITIONS_H */\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <fileChecksum>1022944783</fileChecksum>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <outputs>\r
+ <file>$PROJ_DIR$\Debug\Obj\reg_test.o</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\queue.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\RX100\port.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\port.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\heap_4.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\blocktim.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\queue.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\port_asm.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\ParTest.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\GenQTest.o</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\yvals.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\lcd.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\list.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\blocktim.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\death.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\hardware_setup.o</file>\r
+ <file>$PROJ_DIR$\FreeRTOSConfig.h</file>\r
+ <file>$PROJ_DIR$\main.c</file>\r
+ <file>$PROJ_DIR$\main_full.c</file>\r
+ <file>$PROJ_DIR$\main_low_power.c</file>\r
+ <file>$PROJ_DIR$\ParTest.c</file>\r
+ <file>$PROJ_DIR$\reg_test.s</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main_low_power.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\timers.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\list.o</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\xencoding_limits.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\DLib_Threads.h</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_bsp\platform.h</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_bsp\board\rskrx111\r_bsp.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\stddef.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\ysizet.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\stdint.h</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_bsp\r_bsp_config.h</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_bsp\mcu\rx111\mcu_info.h</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_bsp\board\rskrx111\lcd.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\portable.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\tasks.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\timers.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\lcd.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\queue.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main_full.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main_low_power.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Exe\templproj.out</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\RTOSDemo_IAR.pbd</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\limits.h</file>\r
+ <file>$PROJ_DIR$\PriorityDefinitions.h</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_bsp\board\rskrx111\rskrx111.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\heap_4.o</file>\r
+ <file>$TOOLKIT_DIR$\inc\intrinsics.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\iorx111.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\port.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\hardware_setup.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\r_switches.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\death.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\GenQTest.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\recmutex.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main_full.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main.o</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\ParTest.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\tasks.o</file>\r
+ <file>$TOOLKIT_DIR$\lib\dlrxfllsn.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\mpu_wrappers.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\string.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\list.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\recmutex.o</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\stdlib.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\machine.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\task.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\timers.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\RX100\port_asm.s</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\RX100\portmacro.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\list.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\queue.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\tasks.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\timers.c</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_bsp\board\user\hardware_setup.c</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_switches\src\r_switches.c</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_bsp\board\rskrx111\lcd.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\blocktim.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\death.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\recmutex.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\r_switches.o</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_switches\r_switches_if.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\ystdio.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\StackMacros.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\c\stdio.h</file>\r
+ <file>$PROJ_DIR$\Renesas_Files\r_switches\r_switches_config.h</file>\r
+ </outputs>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\RX100\port.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 56</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 5</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 50 30 12 28 66 29 31 32 2 35 36 3 19 33 34 38 55 39 52 40 37 51 41 76 54 72 67 73 69 68</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 63</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 13</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main_full.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 62</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 46</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main_low_power.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 25</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 47</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 10</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 64</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\reg_test.s</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ARX</name>\r
+ <file> 0</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>[ROOT_NODE]</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ILINK</name>\r
+ <file> 48</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\RX100\port_asm.s</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ARX</name>\r
+ <file> 9</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 53</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 6</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 71 30 12 28 66 29 31 32 36 2 35 3 19 33 34 38 55 39 52 40 37 51 41 76 54 72 67 73 69</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 27</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 15</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 71 30 12 28 66 29 31 32 36 2 35 3 19 33 34 38 55 39 52 40 37 51 41 76 54 72 67 69</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 45</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 8</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 71 30 12 28 66 29 31 32 36 68 2 35 3 19 33 34 38 55 39 52 40 37 51 41 76 54 72 67 73 69 1</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 65</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 42</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 93 30 12 28 66 29 31 32 36 91 71 68 2 35 3 19 33 34 38 55 39 52 40 37 51 41 76 54 72 67 73 69 74 92</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 26</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 43</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 2 35 30 12 28 66 29 31 32 36 3 19 33 34 38 55 39 52 40 37 51 41 76 54 72 67 73 69 1 74</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Renesas_Files\r_bsp\board\user\hardware_setup.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 18</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 57</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 33 34 38 55 39 52 40 37 30 12 28 66 29 31 32 90 94</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Renesas_Files\r_switches\src\r_switches.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 89</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 58</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Renesas_Files\r_bsp\board\rskrx111\lcd.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 14</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 44</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 16</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 7</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 17</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 59</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 11</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 60</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCRX</name>\r
+ <file> 70</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 61</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>RX</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>5</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CMandatory</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>DebuggerProcessorVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CRunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CMacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DynDriver</name>\r
+ <state>RXEMUE20</state>\r
+ </option>\r
+ <option>\r
+ <name>DDFOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DDFFile</name>\r
+ <state>$TOOLKIT_DIR$\config\debugger\ior5f51115.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>DebuggerUseExtraOptions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DebuggerExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ODebuggerByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ODebuggerDoubleSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ODebuggerCore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ODebuggerIntSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RXEMUE20</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>EmuMandatory</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCEmuUseUSBSerialNo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCEmuUSBSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttach</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDebuggingMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCExcecuteAfterFlash</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadOnlyChangedBlocks</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RXJLINK</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>4</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JlinkMandatory</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttach</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDebuggingMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkExcecuteAfterFlash</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkScanChainEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkDevicePosition</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkOtherDeviceTypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkPreceedingIRBits</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkUseUSBSerialNo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkUSBSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>SIMRX</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>SimMandatory</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>SimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SimPspConfigFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\iocf.psp.config</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>RX</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>4</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OGChipSelectMenu</name>\r
+ <state>R5F51115 R5F51115</state>\r
+ </option>\r
+ <option>\r
+ <name>GenDoubleSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenCodeModel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenDataModel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GenByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRTDescription</name>\r
+ <state>Use the normal configuration of the C/EC++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dlrxfllsn.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLibInFormatter</name>\r
+ <version>1</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLibInFormatterDescription</name>\r
+ <state>No specifier n, no float, no scan set, no assignment suppressing, without multibyte support.</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLibOutFormatter</name>\r
+ <version>1</version>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLibOutFormatterDescription</name>\r
+ <state>No specifier a or A, no specifier n, no float or long long, no flags.</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>StackSize</name>\r
+ <state>0x4</state>\r
+ </option>\r
+ <option>\r
+ <name>IStackSize</name>\r
+ <state>0x200</state>\r
+ </option>\r
+ <option>\r
+ <name>HeapSize</name>\r
+ <state>0x4</state>\r
+ </option>\r
+ <option>\r
+ <name>GenSubnormalNumbers</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GenIntSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCRX</name>\r
+ <archiveVersion>5</archiveVersion>\r
+ <data>\r
+ <version>14</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IccLockRegisters</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLockR8</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLockR9</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLockR10</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLockR11</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLockR12</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLockR13</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLanguageConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCharIs</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccOptLevel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccOptStrategy</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccOptLevelSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccOptAllowList</name>\r
+ <version>1</version>\r
+ <state>0000000</state>\r
+ </option>\r
+ <option>\r
+ <name>IccGenerateDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccOutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>IccProcessor</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccDoubleSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccDataModel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmMacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccByteOrder</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>Pa082</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\.</state>\r
+ <state>$PROJ_DIR$\..\Common\include</state>\r
+ <state>$PROJ_DIR$\..\..\Source\include</state>\r
+ <state>$PROJ_DIR$\..\..\Source\portable\IAR\RX100</state>\r
+ <state>$PROJ_DIR$/Renesas_Files/r_bsp/mcu/rx111</state>\r
+ <state>$PROJ_DIR$/Renesas_Files/r_bsp</state>\r
+ <state>$PROJ_DIR$/Renesas_Files/r_bsp/board/rskrx111</state>\r
+ <state>$PROJ_DIR$/Renesas_Files/r_switches</state>\r
+ <state>$PROJ_DIR$/Renesas_Files/r_switches/src}"</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>IccUseExtraOptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExtraOptions</name>\r
+ <state>--no_clustering</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerCpuCore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRequirePrototypes2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccIntSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccPosIndRopi</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerFpu</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NoSizeConstraints</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARX</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>AsmCaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmAllowMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmAllowDirectives</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmMacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmListFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmListNoDiagnostics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmListIncludeCrossRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmListMacroDefinitions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmListNoMacroExpansion</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmListAssembledOnly</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmListTruncateMultiline</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmIncludePath</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ <state>$PROJ_DIR$\.</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmPreprocOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmPreprocComment</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDiagnosticsSuppress</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDiagnosticsRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDiagnosticsWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDiagnosticsError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDiagnosticsWarningsAreErrors</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmLimitNumberOfErrors</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmMaxNumberOfErrors</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmProcessor</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmOutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmByteOrder</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmUseExtraOptions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDataModel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDoubleSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmStdIncludeIgnore2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmIntSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmPosIndRopi</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmCpuCore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>OBJCOPY</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OOCOutputFormat</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCOutputOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCOutputFile</name>\r
+ <state>RTOSDemo_IAR.srec</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCCommandLineProducer</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCObjCopyEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ILINK</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>4</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IlinkLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkInputFileSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOutputFile</name>\r
+ <state>templproj.out</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkDebugInfoEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkKeepSymbols</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinaryFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinarySymbol</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkConfigDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkMapFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogInitialization</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogModule</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogSection</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogVeneer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\lnkr5f51115.icf</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkSuppressDiags</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsRem</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkWarningsAreErrors</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkUStackSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIStackSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkHeapSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkUseExtraOptions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAutoLibEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAdditionalLibs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabel</name>\r
+ <state>__iar_program_start</state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerStart</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerEnd</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcFullSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCspyDebugSupportEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCspyBufferedWrite</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogAutoLibSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkSubnormal</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgorithm</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcUnitSize</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARCHIVE</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IarchiveInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>FreeRTOS Source</name>\r
+ <group>\r
+ <name>include</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\projdefs.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\queue.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\semphr.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\task.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\timers.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>portable</name>\r
+ <group>\r
+ <name>IAR</name>\r
+ <group>\r
+ <name>RX100</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\RX100\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\RX100\port_asm.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\RX100\portmacro.h</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <group>\r
+ <name>MemMang</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Renesas Files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Renesas_Files\r_bsp\board\user\hardware_setup.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Renesas_Files\r_bsp\board\rskrx111\lcd.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Renesas_Files\r_switches\src\r_switches.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Standard Demo Tasks</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\FreeRTOSConfig.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main_full.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main_low_power.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\reg_test.s</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo_IAR.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+[Sfr]\r
+\r
+\r
+[SfrGroupInfo]
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : lcd.c\r
+* Device(s) : RX\r
+* H/W Platform : RSKRX111\r
+* Description : Provides variable and function declarations for lcd.c file\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Standard string manipulation & formatting functions */\r
+#include <stdio.h>\r
+#include <string.h>\r
+/* Defines standard variable types used in this function */\r
+#include <stdint.h>\r
+/* Bring in board includes. */\r
+#include "platform.h"\r
+/* Following header file provides function prototypes for LCD controlling functions & macro defines */\r
+#include "lcd.h"\r
+\r
+/***********************************************************************************************************************\r
+Private global variables and functions\r
+***********************************************************************************************************************/\r
+static void lcd_delay(volatile int32_t nsecs);\r
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value);\r
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value);\r
+\r
+/***********************************************************************************************************************\r
+* Function name : lcd_initialize\r
+* Description : Initializes the LCD display.\r
+* Arguments : none\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+void lcd_initialize(void)\r
+{\r
+ /* Set LCD data pins as outputs. */\r
+ PORT4.PDR.BYTE |= 0x0F;\r
+\r
+ /* Set LCD control pins as outputs. */\r
+ RS_PIN_DDR = 1;\r
+ E_PIN_DDR = 1;\r
+\r
+ /* Power Up Delay for the LCD Module */\r
+ lcd_delay(50000000);\r
+\r
+ /* Display initialises in 8 bit mode - so send one write (seen as 8 bit) to set to 4 bit mode. */\r
+ lcd_nibble_write(CTRL_WR, 0x03);\r
+ lcd_delay(5000000);\r
+ lcd_nibble_write(CTRL_WR, 0x03);\r
+ lcd_delay(5000000);\r
+ lcd_nibble_write(CTRL_WR, 0x03);\r
+ lcd_delay(5000000);\r
+\r
+ /* Function Set */\r
+ lcd_nibble_write(CTRL_WR, 0x02);\r
+ lcd_delay(39000);\r
+ lcd_nibble_write(CTRL_WR, 0x02);\r
+ lcd_nibble_write(CTRL_WR, (LCD_DISPLAY_ON | LCD_TWO_LINE ));\r
+ lcd_delay(39000);\r
+\r
+ /* Display ON/OFF control */\r
+ lcd_write(CTRL_WR, LCD_CURSOR_OFF);\r
+ lcd_delay(39000);\r
+\r
+ /* Display Clear */\r
+ lcd_write(CTRL_WR, LCD_CLEAR);\r
+ lcd_delay(2000000);\r
+\r
+ /* Entry Mode Set */\r
+ lcd_write(CTRL_WR, 0x06);\r
+ lcd_delay(39000);\r
+\r
+ /* Home the cursor */\r
+ lcd_write(CTRL_WR, LCD_HOME_L1);\r
+ lcd_delay(5000000);\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name : lcd_clear\r
+* Description : Clears the LCD\r
+* Arguments : none\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+void lcd_clear(void)\r
+{\r
+ /* Display Clear */\r
+ lcd_write(CTRL_WR, LCD_CLEAR);\r
+ lcd_delay(2000000);\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name : lcd_display\r
+* Description : This function controls LCD writes to line 1 or 2 of the LCD.\r
+* You need to use the defines LCD_LINE1 and LCD_LINE2 in order to specify the starting position.\r
+* For example, to start at the 2nd position on line 1...\r
+* lcd_display(LCD_LINE1 + 1, "Hello")\r
+* Arguments : position -\r
+* Line number of display\r
+* string -\r
+* Pointer to null terminated string\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+void lcd_display(uint8_t position, uint8_t const * string)\r
+{\r
+ /* Declare next position variable */\r
+ static uint8_t next_pos = 0xFF;\r
+\r
+ /* Set line position if needed. We don't want to if we don't need to because LCD control operations take longer\r
+ than LCD data operations. */\r
+ if (next_pos != position)\r
+ {\r
+ if(position < LCD_LINE2)\r
+ {\r
+ /* Display on Line 1 */\r
+ lcd_write(CTRL_WR, ((uint8_t)(LCD_HOME_L1 + position)));\r
+ }\r
+ else\r
+ {\r
+ /* Display on Line 2 */\r
+ lcd_write(CTRL_WR, ((uint8_t)((LCD_HOME_L2 + position) - LCD_LINE2)));\r
+ }\r
+\r
+ lcd_delay(39000);\r
+\r
+ /* set position index to known value */\r
+ next_pos = position;\r
+ }\r
+\r
+ do\r
+ {\r
+ /* Write character to LCD. */\r
+ lcd_write(DATA_WR,*string++);\r
+\r
+ lcd_delay(43000);\r
+\r
+ /* Increment position index */\r
+ next_pos++;\r
+ }\r
+ while(*string);\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name : lcd_delay\r
+* Description : Implements LCD required delays.\r
+* Arguments : nsecs -\r
+* Number of nanoseconds to delay. RX111 has max clock of 32MHz which gives a cycle time of 31.3ns.\r
+* This means that nothing under 313ns should be input. 313ns would be 10 cycles which is still\r
+* being optimistic for getting in and out of this function.\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+static void lcd_delay(volatile int32_t nsecs)\r
+{\r
+ while (0 < nsecs)\r
+ {\r
+ /* Subtract off 10 cycles per iteration. This number was obtained when using the Renesas toolchain at\r
+ optimization level 2. The number to nanoseconds to subtract off below is calculated off of the ICLK speed. */\r
+ nsecs -= (int32_t)((313.0)*(32000000.0/(float)ICLK_HZ));\r
+ }\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name : lcd_nibble_write\r
+* Description : Writes data to display. Sends command to display.\r
+* Arguments : value -\r
+* The value to write\r
+* data_or_ctrl -\r
+* Whether to write data or control.\r
+* 1 = DATA\r
+* 0 = CONTROL\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value)\r
+{\r
+ /* Set Register Select pin high for Data */\r
+ if (data_or_ctrl == DATA_WR)\r
+ {\r
+ /* Data write. */\r
+ RS_PIN = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Control write. */\r
+ RS_PIN = 0;\r
+ }\r
+\r
+ /* tsu1 delay */\r
+ lcd_delay(60);\r
+\r
+ /* EN enable chip (HIGH) */\r
+ E_PIN = 1;\r
+\r
+ /* Output the data */\r
+ PORT4.PODR.BYTE = (value & 0x0F);\r
+\r
+ /* tw delay */\r
+ lcd_delay(450);\r
+\r
+ /* Latch data by dropping E */\r
+ E_PIN = 0;\r
+\r
+ /* th2 delay */\r
+ lcd_delay(10);\r
+\r
+ /* tc delay */\r
+ lcd_delay(480);\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name : lcd_write\r
+* Description : This function controls LCD writes to line 1 or 2 of the LCD. You need to use the defines LCD_LINE1 and\r
+* LCD_LINE2 in order to specify the starting position.\r
+* For example, to start at the 2nd position on line 1...\r
+* lcd_display(LCD_LINE1 + 1, "Hello")\r
+* Arguments : value -\r
+* The value to write\r
+* data_or_ctrl -\r
+* Whether to write data or control.\r
+* 1 = DATA\r
+* 0 = CONTROL\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value)\r
+{\r
+ /* Write upper nibble first */\r
+ lcd_nibble_write(data_or_ctrl, (uint8_t)((value & 0xF0) >> 4));\r
+\r
+ /* Write lower nibble second */\r
+ lcd_nibble_write(data_or_ctrl, (uint8_t)(value & 0x0F));\r
+}\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : lcd.h\r
+* Device(s) : RX\r
+* H/W Platform : RSKRX111\r
+* Description : Provides variable and function declarations for lcd.c file\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+/* Multiple inclusion prevention macro */\r
+#ifndef LCD_H\r
+#define LCD_H\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Defines standard integer variable types used in this file */\r
+#include <stdint.h>\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* RS register select pin */\r
+#define RS_PIN PORTC.PODR.BIT.B5\r
+#define RS_PIN_DDR PORTC.PDR.BIT.B5\r
+/* Display enable pin */\r
+#define E_PIN PORTB.PODR.BIT.B1\r
+#define E_PIN_DDR PORTB.PDR.BIT.B1\r
+/* Data write/read definition */\r
+#define DATA_WR 1\r
+/* Control write/read definition */\r
+#define CTRL_WR 0\r
+/* Maximum characters per line of LCD display. */\r
+#define NUMB_CHARS_PER_LINE 8\r
+/* Number of lines on the LCD display */\r
+#define MAXIMUM_LINES 2\r
+/* Character position of LCD line 1 */\r
+#define LCD_LINE1 0\r
+/* Character position of LCD line 2 */\r
+#define LCD_LINE2 16\r
+/* Clear LCD display and home cursor */\r
+#define LCD_CLEAR 0x01\r
+/* Move cursor to line 1 */\r
+#define LCD_HOME_L1 0x80\r
+/* Move cursor to line 2 */\r
+#define LCD_HOME_L2 0xC0\r
+/* Cursor auto decrement after R/W */\r
+#define CURSOR_MODE_DEC 0x04\r
+/* Cursor auto increment after R/W */\r
+#define CURSOR_MODE_INC 0x06\r
+/* Setup, 4 bits,2 lines, 5X7 */\r
+#define FUNCTION_SET 0x28\r
+/* Display ON with Cursor */\r
+#define LCD_CURSOR_ON 0x0E\r
+/* Display ON with Cursor off */\r
+#define LCD_CURSOR_OFF 0x0C\r
+/* Display on with blinking cursor */\r
+#define LCD_CURSOR_BLINK 0x0D\r
+/* Move Cursor Left One Position */\r
+#define LCD_CURSOR_LEFT 0x10\r
+/* Move Cursor Right One Position */\r
+#define LCD_CURSOR_RIGHT 0x14\r
+/* Enable LCD display */\r
+#define LCD_DISPLAY_ON 0x04\r
+/* Enable both LCD lines */\r
+#define LCD_TWO_LINE 0x08\r
+\r
+/***********************************************************************************************************************\r
+Exported global functions (to be accessed by other files)\r
+***********************************************************************************************************************/\r
+/* LCD initialisation function declaration */\r
+void lcd_initialize (void);\r
+\r
+/* Update display function declaration */\r
+void lcd_display(uint8_t position, uint8_t const * string);\r
+\r
+/* Clear LCD function delcaration */\r
+void lcd_clear (void);\r
+\r
+/* End of multiple inclusion prevention macro */\r
+#endif\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp.h\r
+* H/W Platform : RSKRX111\r
+* Description : Has the header files that should be included for this platform.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+#ifndef PLATFORM_BOARD_RSKRX111\r
+#define PLATFORM_BOARD_RSKRX111\r
+\r
+/* Make sure that no other platforms have already been defined. Do not touch this! */\r
+#ifdef PLATFORM_DEFINED\r
+#error "Error - Multiple platforms defined in platform.h!"\r
+#else\r
+#define PLATFORM_DEFINED\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+INCLUDE APPROPRIATE MCU AND BOARD FILES\r
+***********************************************************************************************************************/\r
+#include "r_bsp_config.h"\r
+#include "iorx111.h"\r
+#include ".\mcu\rx111\mcu_info.h"\r
+#include ".\board\rskrx111\rskrx111.h"\r
+#include ".\board\rskrx111\lcd.h"\r
+\r
+#endif /* PLATFORM_BOARD_RSKRX111 */\r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp_config_reference.c\r
+* Device(s) : RX111\r
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included\r
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)\r
+* is just a reference file that the user can use to make their own r_bsp_config.h file.\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description \r
+* : 07.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE\r
+#define R_BSP_CONFIG_REF_HEADER_FILE\r
+\r
+/***********************************************************************************************************************\r
+Configuration Options\r
+***********************************************************************************************************************/\r
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such \r
+ as package and memory size. \r
+ To help parse this information, the part number will be defined using multiple macros.\r
+ R 5 F 51 11 5 A D FM\r
+ | | | | | | | | | Macro Name Description\r
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch\r
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)\r
+ | | | | | | |______not used = Blank\r
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity\r
+ | | | | |___________MCU_PART_GROUP = Group name \r
+ | | | |______________MCU_PART_SERIES = Series name\r
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)\r
+ | |__________________not used = Renesas MCU\r
+ |____________________not used = Renesas semiconductor product. \r
+ */\r
+\r
+/* Package type. Set the macro definition based on values below:\r
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch\r
+ FM = 0x0 = LFQFP/64/0.50\r
+ FK = 0x1 = LQFP/64/0.80\r
+ LF = 0x2 = TFLGA/64/0.50\r
+ FL = 0x3 = LFQFP/48/0.50\r
+ NE = 0x4 = VQFN/48/0.50\r
+ NC = 0x5 = HWQFN/36/0.50\r
+ LM = 0x6 = WFLGA/36/0.50\r
+ SB = 0x7 = SSOP/36/0.80\r
+*/\r
+#define MCU_PART_PACKAGE (0x0)\r
+\r
+/* ROM, RAM, and Data Flash Capacity. \r
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size\r
+ 5 = 0x5 = 128KB/16KB/8KB\r
+ 4 = 0x4 = 96KB/16KB/8KB\r
+ 3 = 0x3 = 64KB/10KB/8KB\r
+ 1 = 0x1 = 32KB/10KB/8KB\r
+ J = 0x0 = 16KB/8KB/8KB\r
+*/\r
+#define MCU_PART_MEMORY_SIZE (0x5)\r
+\r
+/* Group name. \r
+ Character(s) = Value for macro = Description\r
+ 10 = 0x0 = RX110 Group\r
+ 11 = 0x1 = RX111 Group\r
+*/\r
+#define MCU_PART_GROUP (0x1)\r
+\r
+/* Series name. \r
+ Character(s) = Value for macro = Description\r
+ 51 = 0x0 = RX100 Series\r
+*/ \r
+#define MCU_PART_SERIES (0x0)\r
+\r
+/* Memory type. \r
+ Character(s) = Value for macro = Description\r
+ F = 0x0 = Flash memory version\r
+*/\r
+#define MCU_PART_MEMORY_TYPE (0x0)\r
+\r
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a \r
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */\r
+#if defined(BSP_DECLARE_STACK)\r
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize su=0x400\r
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize si=0x100\r
+#endif\r
+\r
+/* Heap size in bytes. */\r
+#define HEAP_BYTES (0x400)\r
+\r
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information\r
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.\r
+ 0 = Stay in Supervisor mode.\r
+ 1 = Switch to User mode.\r
+*/\r
+#define RUN_IN_USER_MODE (0)\r
+\r
+\r
+/* This macro lets other modules no if a RTOS is being used.\r
+ 0 = RTOS is not used. \r
+ 1 = RTOS is used.\r
+*/\r
+#define RTOS_USED (0)\r
+\r
+/* Clock source select (CKSEL).\r
+ 0 = Low Speed On-Chip Oscillator (LOCO)\r
+ 1 = High Speed On-Chip Oscillator (HOCO)\r
+ 2 = Main Clock Oscillator \r
+ 3 = Sub-Clock Oscillator\r
+ 4 = PLL Circuit\r
+*/ \r
+#define CLOCK_SOURCE (4)\r
+\r
+/* Clock configuration options.\r
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The\r
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the\r
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the\r
+ settings would be:\r
+\r
+ XTAL_HZ = 16000000\r
+ PLL_DIV = 2\r
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)\r
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz\r
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz\r
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz\r
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz\r
+*/\r
+/* XTAL - Input clock frequency in Hz */\r
+#define XTAL_HZ (16000000)\r
+/* PLL Input Frequency Divider Select (PLIDIV). \r
+ Available divisors = /1 (no division), /2, /4\r
+*/\r
+#define PLL_DIV (2)\r
+/* PLL Frequency Multiplication Factor Select (STC). \r
+ Available multipliers = x6, x8\r
+*/\r
+#define PLL_MUL (6)\r
+/* System Clock Divider (ICK).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define ICK_DIV (2)\r
+/* Peripheral Module Clock B Divider (PCKB). \r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKB_DIV (2)\r
+/* Peripheral Module Clock D Divider (PCKD). \r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKD_DIV (2)\r
+/* Flash IF Clock Divider (FCK). \r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define FCK_DIV (2)\r
+\r
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and \r
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a \r
+ function to be called when the event occurs. For example, if the user wanted the function \r
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would\r
+ do the following:\r
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+ If the user does not wish to be alerted of these events then they should comment out the macros.\r
+ \r
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function\r
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it\r
+ is executing. For this reason, it is recommended to keep these callback functions short as to not\r
+ decrease the real-time response of your system.\r
+*/\r
+/* Callback for Supervisor Instruction Violation Exception. */\r
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb\r
+\r
+/* Callback for Undefined Instruction Exception. */\r
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb\r
+\r
+/* Callback for Non-maskable Interrupt. */\r
+//#define NMI_ISR_CALLBACK nmi_cb\r
+\r
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source\r
+ is creating unwanted interrupts. */\r
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+\r
+/* Callback for Bus Error Interrupt. */\r
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb\r
+\r
+/* The user has the option of separately choosing little or big endian for the User Application Area */\r
+\r
+/* Endian mode for User Application.\r
+ 0 = Big Endian\r
+ Else = Little Endian (Default)\r
+*/ \r
+#define USER_APP_ENDIAN (1)\r
+\r
+\r
+/* Configure WDT and IWDT settings. \r
+ OFS0 - Option Function Select Register 0 \r
+ OFS0 - Option Function Select Register 0\r
+ b31:b15 Reserved (set to 1)\r
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)\r
+ b13 Reserved (set to 1)\r
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)\r
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)\r
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)\r
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)\r
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)\r
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)\r
+ b0 Reserved (set to 1) */\r
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.\r
+ OFS1 - Option Function Select Register 1\r
+ b31:b9 Reserved (set to 1)\r
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)\r
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select\r
+ 0 1 0 0: 3.10 V\r
+ 0 1 0 1: 3.00 V\r
+ 0 1 1 0: 2.90 V\r
+ 0 1 1 1: 2.79 V\r
+ 1 0 0 0: 2.68 V\r
+ 1 0 0 1: 2.58 V\r
+ 1 0 1 0: 2.48 V\r
+ 1 0 1 1: 2.06 V\r
+ 1 1 0 0: 1.96 V\r
+ 1 1 0 1: 1.86 V\r
+ b3:b2 Reserved (set to 1)\r
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)\r
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */\r
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Initializes C input & output library functions.\r
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.\r
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */\r
+#define IO_LIB_ENABLE (1)\r
+\r
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */\r
+\r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : rskrx111.h\r
+* H/W Platform : RSKRX111\r
+* Description : Board specific definitions for the RSKRX111.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+#ifndef RSKRX111_H\r
+#define RSKRX111_H\r
+\r
+/* Local defines */\r
+#define LED_ON (0)\r
+#define LED_OFF (1)\r
+#define SET_BIT_HIGH (1)\r
+#define SET_BIT_LOW (0)\r
+#define SET_BYTE_HIGH (0xFF)\r
+#define SET_BYTE_LOW (0x00)\r
+\r
+/* Switches */\r
+#define SW_ACTIVE 0\r
+#define SW1 PORT3.PIDR.BIT.B0\r
+#define SW2 PORT3.PIDR.BIT.B1\r
+#define SW3 PORTE.PIDR.BIT.B4\r
+#define SW1_PDR PORT3.PDR.BIT.B0\r
+#define SW2_PDR PORT3.PDR.BIT.B1\r
+#define SW3_PDR PORTE.PDR.BIT.B4\r
+#define SW1_PMR PORT3.PMR.BIT.B0\r
+#define SW2_PMR PORT3.PMR.BIT.B1\r
+#define SW3_PMR PORTE.PMR.BIT.B4\r
+\r
+/* LEDs */\r
+#define LED0 PORTB.PODR.BIT.B7\r
+#define LED1 PORTA.PODR.BIT.B0\r
+#define LED2 PORT5.PODR.BIT.B4\r
+#define LED3 PORT1.PODR.BIT.B7\r
+#define LED0_PDR PORTB.PDR.BIT.B7\r
+#define LED1_PDR PORTA.PDR.BIT.B0\r
+#define LED2_PDR PORT5.PDR.BIT.B4\r
+#define LED3_PDR PORT1.PDR.BIT.B7\r
+\r
+\r
+#endif /* RSKRX111_H */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : hwsetup.c\r
+* Device(s) : RX\r
+* H/W Platform : RSKRX210\r
+* Description : Defines the initialization routines used each time the MCU is restarted.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* I/O Register and board definitions */\r
+#include "platform.h"\r
+#include "r_switches_if.h"\r
+/***********************************************************************************************************************\r
+Private global variables and functions\r
+***********************************************************************************************************************/\r
+/* MCU I/O port configuration function delcaration */\r
+static void output_ports_configure(void);\r
+\r
+/* Interrupt configuration function delcaration */\r
+static void interrupts_configure(void);\r
+\r
+/* MCU peripheral module configuration function declaration */\r
+static void peripheral_modules_enable(void);\r
+\r
+/* Configure MCU clocks. */\r
+static void clock_source_select (void);\r
+void operating_frequency_set(void);\r
+\r
+/***********************************************************************************************************************\r
+* Function name: hardware_setup\r
+* Description : Contains setup functions called at device restart\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void vHardwareSetup(void)\r
+{\r
+ operating_frequency_set();\r
+ output_ports_configure();\r
+ interrupts_configure();\r
+ peripheral_modules_enable();\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name: output_ports_configure\r
+* Description : Configures the port and pin direction settings, and sets the pin outputs to a safe level.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void output_ports_configure(void)\r
+{\r
+ /* Enable LEDs. */\r
+ /* Start with LEDs off. */\r
+ LED0 = LED_OFF;\r
+ LED1 = LED_OFF;\r
+ LED2 = LED_OFF;\r
+ LED3 = LED_OFF;\r
+\r
+ /* Set LED pins as outputs. */\r
+ LED0_PDR = 1;\r
+ LED1_PDR = 1;\r
+ LED2_PDR = 1;\r
+ LED3_PDR = 1;\r
+\r
+ /* Enable switches. */\r
+ /* Set pins as inputs. */\r
+ SW1_PDR = 0;\r
+ SW2_PDR = 0;\r
+ SW3_PDR = 0;\r
+\r
+ /* Set port mode registers for switches. */\r
+ SW1_PMR = 0;\r
+ SW2_PMR = 0;\r
+ SW3_PMR = 0;\r
+\r
+ /* Unlock MPC registers to enable writing to them. */\r
+ MPC.PWPR.BIT.B0WI = 0 ; /* Unlock protection register */\r
+ MPC.PWPR.BIT.PFSWE = 1 ; /* Unlock MPC registers */\r
+\r
+ /* TXD1 is output. */\r
+ PORT1.PDR.BIT.B6 = 1;\r
+ PORT1.PMR.BIT.B6 = 1;\r
+ MPC.P16PFS.BYTE = 0x0A;\r
+ /* RXD1 is input. */\r
+ PORT1.PDR.BIT.B5 = 0;\r
+ PORT1.PMR.BIT.B5 = 1;\r
+ MPC.P15PFS.BYTE = 0x0A;\r
+\r
+ /* Configure the pin connected to the ADC Pot as an input */\r
+ PORT4.PDR.BIT.B4 = 0;\r
+\r
+ /* Protect off. */\r
+ SYSTEM.PRCR.WORD = 0xA50B;\r
+\r
+ /* Turn off module stop for the A2D converter. */\r
+ SYSTEM.MSTPCRA.BIT.MSTPA17 = 0;\r
+\r
+ /* Protect on. */\r
+ SYSTEM.PRCR.WORD = 0xA500;\r
+\r
+ /* Initialise the first button to generate an interrupt. */\r
+ R_SWITCHES_Init();\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name: interrupts_configure\r
+* Description : Configures interrupts used\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void interrupts_configure(void)\r
+{\r
+ /* Add code here to setup additional interrupts */\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name: peripheral_modules_enable\r
+* Description : Enables and configures peripheral devices on the MCU\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void peripheral_modules_enable(void)\r
+{\r
+ /* Enable triggers to start an ADC conversion. */\r
+ S12AD.ADCSR.BIT.TRGE = 1;\r
+\r
+ /* Only channel 4 is going to be used. */\r
+ S12AD.ADANSA.BIT.ANSA4 = 1;\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name: operating_frequency_set\r
+* Description : Configures the clock settings for each of the device clocks\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void operating_frequency_set(void)\r
+{\r
+ /* Used for constructing value to write to SCKCR and CKOCR registers. */\r
+ uint32_t temp_clock = 0;\r
+\r
+ /*\r
+ Clock Description Frequency\r
+ ----------------------------------------\r
+ Input Clock Frequency............ 16 MHz\r
+ PLL frequency (x3)............... 48 MHz\r
+ Internal Clock Frequency......... 24 MHz\r
+ Peripheral Clock Frequency....... 24 MHz\r
+ Clock Out Frequency.............. 1 MHz */\r
+\r
+ volatile unsigned int i;\r
+\r
+ /* Protect off. */\r
+ SYSTEM.PRCR.WORD = 0xA50B;\r
+\r
+ /* Select the clock based upon user's choice. */\r
+ clock_source_select();\r
+\r
+\r
+ /* Figure out setting for FCK bits. */\r
+#if FCK_DIV == 1\r
+ /* Do nothing since FCK bits should be 0. */\r
+#elif FCK_DIV == 2\r
+ temp_clock |= 0x10000000;\r
+#elif FCK_DIV == 4\r
+ temp_clock |= 0x20000000;\r
+#elif FCK_DIV == 8\r
+ temp_clock |= 0x30000000;\r
+#elif FCK_DIV == 16\r
+ temp_clock |= 0x40000000;\r
+#elif FCK_DIV == 32\r
+ temp_clock |= 0x50000000;\r
+#elif FCK_DIV == 64\r
+ temp_clock |= 0x60000000;\r
+#else\r
+ #error "Error! Invalid setting for FCK_DIV in r_bsp_config.h"\r
+#endif\r
+\r
+ /* Figure out setting for ICK bits. */\r
+#if ICK_DIV == 1\r
+ /* Do nothing since ICK bits should be 0. */\r
+#elif ICK_DIV == 2\r
+ temp_clock |= 0x01000000;\r
+#elif ICK_DIV == 4\r
+ temp_clock |= 0x02000000;\r
+#elif ICK_DIV == 8\r
+ temp_clock |= 0x03000000;\r
+#elif ICK_DIV == 16\r
+ temp_clock |= 0x04000000;\r
+#elif ICK_DIV == 32\r
+ temp_clock |= 0x05000000;\r
+#elif ICK_DIV == 64\r
+ temp_clock |= 0x06000000;\r
+#else\r
+ #error "Error! Invalid setting for ICK_DIV in r_bsp_config.h"\r
+#endif\r
+\r
+ /* Figure out setting for PCKB bits. */\r
+#if PCKB_DIV == 1\r
+ /* Do nothing since PCKB bits should be 0. */\r
+#elif PCKB_DIV == 2\r
+ temp_clock |= 0x00000100;\r
+#elif PCKB_DIV == 4\r
+ temp_clock |= 0x00000200;\r
+#elif PCKB_DIV == 8\r
+ temp_clock |= 0x00000300;\r
+#elif PCKB_DIV == 16\r
+ temp_clock |= 0x00000400;\r
+#elif PCKB_DIV == 32\r
+ temp_clock |= 0x00000500;\r
+#elif PCKB_DIV == 64\r
+ temp_clock |= 0x00000600;\r
+#else\r
+ #error "Error! Invalid setting for PCKB_DIV in r_bsp_config.h"\r
+#endif\r
+\r
+ /* Figure out setting for PCKD bits. */\r
+#if PCKD_DIV == 1\r
+ /* Do nothing since PCKD bits should be 0. */\r
+#elif PCKD_DIV == 2\r
+ temp_clock |= 0x00000001;\r
+#elif PCKD_DIV == 4\r
+ temp_clock |= 0x00000002;\r
+#elif PCKD_DIV == 8\r
+ temp_clock |= 0x00000003;\r
+#elif PCKD_DIV == 16\r
+ temp_clock |= 0x00000004;\r
+#elif PCKD_DIV == 32\r
+ temp_clock |= 0x00000005;\r
+#elif PCKD_DIV == 64\r
+ temp_clock |= 0x00000006;\r
+#else\r
+ #error "Error! Invalid setting for PCKD_DIV in r_bsp_config.h"\r
+#endif\r
+\r
+ /* Set SCKCR register. */\r
+ SYSTEM.SCKCR.LONG = temp_clock;\r
+\r
+ /* Choose clock source. Default for r_bsp_config.h is PLL. */\r
+ SYSTEM.SCKCR3.WORD = ((uint16_t)CLOCK_SOURCE) << 8;\r
+\r
+ /* Protect on. */\r
+ SYSTEM.PRCR.WORD = 0xA500;\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name: clock_source_select\r
+* Description : Enables and disables clocks as chosen by the user. This function also implements the software delays\r
+* needed for the clocks to stabilize.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+static void clock_source_select (void)\r
+{\r
+ /* Declared volatile for software delay purposes. */\r
+ volatile unsigned int i;\r
+\r
+ /* NOTE: AS OF VERSION 0.50 OF THE RX111 HARDWARE MANUAL, ALL OF THE CLOCK\r
+ * STABILIZATION TIMES ARE TBD. FOR NOW, WHERE EVER A WAIT COUNT REGISTER\r
+ * IS AVAILABLE, THE DELAY IS SET TO THE MAX NUMBER OF CYCLES. WHERE EVER\r
+ * DELAY LOOPS ARE PRESENT, THE VALUES FROM THE 63N ARE RE-USED. KEEP IN\r
+ * MIND THAT THE 63N RUNS ON A FASTER CRYSTAL.\r
+ */\r
+\r
+#if (CLOCK_SOURCE == 1)\r
+ /* HOCO is chosen. Start it operating. */\r
+ SYSTEM.HOCOCR.BYTE = 0x00;\r
+ /* The delay period needed is to make sure that the HOCO has stabilized.*/\r
+ for(i = 0; i< 28; i++) // tHOCOWT2 is TBD\r
+ {\r
+ __asm volatile( "NOP" );\r
+ }\r
+#else\r
+ /* HOCO is not chosen. Stop the HOCO. */\r
+ SYSTEM.HOCOCR.BYTE = 0x01;\r
+#endif\r
+\r
+#if (CLOCK_SOURCE == 2)\r
+ /* Main clock oscillator is chosen. Start it operating. */\r
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles\r
+ /* Set the main clock to operating. */\r
+ SYSTEM.MOSCCR.BYTE = 0x00;\r
+ /* The delay period needed is to make sure that the main clock has stabilized. */\r
+ for(i = 0; i< 140; i++) // tMAINOSCWT is TBD\r
+ {\r
+ __asm volatile( "NOT" );\r
+ }\r
+#endif\r
+\r
+#if (CLOCK_SOURCE == 3)\r
+ /* Sub-clock oscillator is chosen. Start it operating. */\r
+ /* In section 9.8.4, there is a reference to a SOSCWTCR register, but there is no\r
+ * description for this register in the manual nor reference for it in iorx111.h. */\r
+\r
+ /* Set the sub-clock to operating. */\r
+ SYSTEM.SOSCCR.BYTE = 0x00;\r
+ /* The delay period needed is to make sure that the sub-clock has stabilized. */\r
+ for(i = 0; i< 30233; i++) // tSUBOSCWT0 is TBD\r
+ {\r
+ __asm volatile( "NOP" );\r
+ }\r
+#else\r
+ /* Set the sub-clock to stopped. */\r
+ SYSTEM.SOSCCR.BYTE = 0x01;\r
+#endif\r
+\r
+#if (CLOCK_SOURCE == 4)\r
+ /* PLL is chosen. Start it operating. Must start main clock as well since PLL uses it. */\r
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles\r
+ /* Set the main clock to operating. */\r
+ SYSTEM.MOSCCR.BYTE = 0x00;\r
+\r
+ /* Set PLL Input Divisor. */\r
+ SYSTEM.PLLCR.BIT.PLIDIV = PLL_DIV >> 1;\r
+\r
+ /* Set PLL Multiplier. */\r
+ SYSTEM.PLLCR.BIT.STC = (PLL_MUL * 2) - 1;\r
+\r
+ /* Set the PLL to operating. */\r
+ SYSTEM.PLLCR2.BYTE = 0x00;\r
+ /* The delay period needed is to make sure that the main clock and PLL have stabilized. */\r
+ for(i = 0; i< 140; i++) // tPLLWT2 is TBD\r
+ {\r
+ __asm volatile( "NOP" );\r
+ }\r
+#endif\r
+\r
+ /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn\r
+ it off until another clock has been enabled and is ready to use. */\r
+#if (CLOCK_SOURCE == 0)\r
+ /* LOCO is chosen. This is the default out of reset. */\r
+ SYSTEM.LOCOCR.BYTE = 0x00;\r
+#else\r
+ /* LOCO is not chosen and another clock has already been setup. Turn off the LOCO. */\r
+ SYSTEM.LOCOCR.BYTE = 0x01;\r
+#endif\r
+\r
+ /* Make sure a valid clock was chosen. */\r
+#if (CLOCK_SOURCE > 4) || (CLOCK_SOURCE < 0)\r
+ #error "ERROR - Valid clock source must be chosen in r_bsp_config.h using CLOCK_SOURCE macro."\r
+#endif\r
+}\r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp.h \r
+* Description : Has the header files that should be included for this platform.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 13.01.2012 1.00 First Release\r
+* : 27.06.2012 1.10 Updated with new information to reflect udpated r_bsp structure.\r
+***********************************************************************************************************************/\r
+\r
+#ifndef PLATFORM_BOARD_USER\r
+#define PLATFORM_BOARD_USER\r
+\r
+/* Make sure that no other platforms have already been defined. Do not touch this! */\r
+#ifdef PLATFORM_DEFINED\r
+#error "Error - Multiple platforms defined in platform.h!"\r
+#else\r
+#define PLATFORM_DEFINED\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+INCLUDE APPROPRIATE MCU AND BOARD FILES\r
+***********************************************************************************************************************/\r
+/* This is a user defined board. Start off by:\r
+ 1)Copy and rename one of the 'board' folders that most closely matches your system (same MCU Series and Group).\r
+ 2)Substitute in your MCU Group for the *MCU Group* option in the #include below for mcu_info.h.\r
+ 3)Copy the other #includes from the r_bsp.h in the 'board' folder that you copied earlier.\r
+ 4)Configure the BSP for your board by modifying the r_bsp_config_reference.h.\r
+ 5)Copy r_bsp_config_reference.h to your project directory and rename it r_bsp_config.h.\r
+ You can also add your own include files here as well. */\r
+#include "r_bsp_config.h"\r
+#include ".\mcu\*MCU Group*\mcu_info.h" \r
+\r
+#endif /* PLATFORM_BOARD_USER */\r
+\r
+\r
--- /dev/null
+/********************************************************************************/\r
+/* */\r
+/* Device : RX/RX100/RX111 */\r
+/* File Name : iodefine.h */\r
+/* Abstract : Definition of I/O Register. */\r
+/* History : V0.5 (2012-09-25) [Hardware Manual Revision : 0.50] */\r
+/* Note : This is a typical example. */\r
+/* */\r
+/* Copyright(c) 2012 Renesas Electronics Corp. */\r
+/* And Renesas Solutions Corp. ,All Rights Reserved. */\r
+/* */\r
+/********************************************************************************/\r
+/* */\r
+/* DESCRIPTION : Definition of ICU Register */\r
+/* CPU TYPE : RX111 */\r
+/* */\r
+/* Usage : IR,DTCER,IER,IPR of ICU Register */\r
+/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */\r
+/* The bit access operation is "Bit_Name(interrupt source,name)". */\r
+/* A part of the name can be omitted. */\r
+/* for example : */\r
+/* IR(MTU0,TGIA0) = 0; expands to : */\r
+/* ICU.IR[114].BIT.IR = 0; */\r
+/* */\r
+/* DTCE(ICU,IRQ0) = 1; expands to : */\r
+/* ICU.DTCER[64].BIT.DTCE = 1; */\r
+/* */\r
+/* IEN(CMT0,CMI0) = 1; expands to : */\r
+/* ICU.IER[0x03].BIT.IEN4 = 1; */\r
+/* */\r
+/* IPR(MTU1,TGIA1) = 2; expands to : */\r
+/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */\r
+/* ICU.IPR[121].BIT.IPR = 2; */\r
+/* */\r
+/* IPR(SCI1,ERI1) = 3; expands to : */\r
+/* IPR(SCI1, ) = 3; // SCI1 uses single IPR for all sources. */\r
+/* ICU.IPR[218].BIT.IPR = 3; */\r
+/* */\r
+/* Usage : #pragma interrupt Function_Identifier(vect=**) */\r
+/* The number of vector is "(interrupt source, name)". */\r
+/* for example : */\r
+/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */\r
+/* #pragma interrupt INT_IRQ0(vect=64) */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=28) */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */\r
+/* */\r
+/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */\r
+/* The bit access operation is "MSTP(name)". */\r
+/* The name that can be used is a macro name defined with "iodefine.h". */\r
+/* for example : */\r
+/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */\r
+/* */\r
+/* */\r
+/********************************************************************************/\r
+#ifndef __RX111IODEFINE_HEADER__\r
+#define __RX111IODEFINE_HEADER__\r
+\r
+\r
+struct st_bsc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char STSCLR:1;\r
+ } BIT;\r
+ } BERCLR;\r
+ char wk0[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IGAEN:1;\r
+ } BIT;\r
+ } BEREN;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MST:3;\r
+ unsigned char :3;\r
+ unsigned char IA:1;\r
+ } BIT;\r
+ } BERSR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADDR:13;\r
+ } BIT;\r
+ } BERSR2;\r
+ char wk3[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short BPFB:2;\r
+ unsigned short :2;\r
+ unsigned short BPGB:2;\r
+ unsigned short BPIB:2;\r
+ unsigned short BPRO:2;\r
+ unsigned short BPRA:2;\r
+ } BIT;\r
+ } BUSPRI;\r
+};\r
+\r
+struct st_cac {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CFME:1;\r
+ } BIT;\r
+ } CACR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char EDGES:2;\r
+ unsigned char TCSS:2;\r
+ unsigned char FMCS:3;\r
+ unsigned char CACREFE:1;\r
+ } BIT;\r
+ } CACR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DFS:2;\r
+ unsigned char RCDS:2;\r
+ unsigned char RSCS:3;\r
+ unsigned char RPS:1;\r
+ } BIT;\r
+ } CACR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char OVFFCL:1;\r
+ unsigned char MENDFCL:1;\r
+ unsigned char FERRFCL:1;\r
+ unsigned char :1;\r
+ unsigned char OVFIE:1;\r
+ unsigned char MENDIE:1;\r
+ unsigned char FERRIE:1;\r
+ } BIT;\r
+ } CAICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char OVFF:1;\r
+ unsigned char MENDF:1;\r
+ unsigned char FERRF:1;\r
+ } BIT;\r
+ } CASTR;\r
+ char wk0[1];\r
+ unsigned short CAULVR;\r
+ unsigned short CALLVR;\r
+ unsigned short CACNTBR;\r
+};\r
+\r
+struct st_cmt {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :14;\r
+ unsigned short STR1:1;\r
+ unsigned short STR0:1;\r
+ } BIT;\r
+ } CMSTR0;\r
+};\r
+\r
+struct st_cmt0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :9;\r
+ unsigned short CMIE:1;\r
+ unsigned short :4;\r
+ unsigned short CKS:2;\r
+ } BIT;\r
+ } CMCR;\r
+ unsigned short CMCNT;\r
+ unsigned short CMCOR;\r
+};\r
+\r
+struct st_crc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DORCLR:1;\r
+ unsigned char :4;\r
+ unsigned char LMS:1;\r
+ unsigned char GPS:2;\r
+ } BIT;\r
+ } CRCCR;\r
+ unsigned char CRCDIR;\r
+ unsigned short CRCDOR;\r
+};\r
+\r
+struct st_da {\r
+ unsigned short DADR0;\r
+ unsigned short DADR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAOE1:1;\r
+ unsigned char DAOE0:1;\r
+ } BIT;\r
+ } DACR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSEL:1;\r
+ } BIT;\r
+ } DADPR;\r
+};\r
+\r
+struct st_doc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char DOPCFCL:1;\r
+ unsigned char DOPCF:1;\r
+ unsigned char DOPCIE:1;\r
+ unsigned char :1;\r
+ unsigned char DCSEL:1;\r
+ unsigned char OMS:2;\r
+ } BIT;\r
+ } DOCR;\r
+ char wk0[1];\r
+ unsigned short DODIR;\r
+ unsigned short DODSR;\r
+};\r
+\r
+struct st_dtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char RRS:1;\r
+ } BIT;\r
+ } DTCCR;\r
+ char wk0[3];\r
+ void *DTCVBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SHORT:1;\r
+ } BIT;\r
+ } DTCADMOD;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCST:1;\r
+ } BIT;\r
+ } DTCST;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ACT:1;\r
+ unsigned short :7;\r
+ unsigned short VECN:8;\r
+ } BIT;\r
+ } DTCSTS;\r
+};\r
+\r
+struct st_elc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ELCON:1;\r
+ } BIT;\r
+ } ELCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ELS:8;\r
+ } BIT;\r
+ } ELSR[26];\r
+ char wk0[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTU3MD:2;\r
+ unsigned char MTU2MD:2;\r
+ unsigned char MTU1MD:2;\r
+ } BIT;\r
+ } ELOPA;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char MTU4MD:2;\r
+ } BIT;\r
+ } ELOPB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char CMT1MD:2;\r
+ } BIT;\r
+ } ELOPC;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PGR7:1;\r
+ unsigned char PGR6:1;\r
+ unsigned char PGR5:1;\r
+ unsigned char PGR4:1;\r
+ unsigned char PGR3:1;\r
+ unsigned char PGR2:1;\r
+ unsigned char PGR1:1;\r
+ unsigned char PGR0:1;\r
+ } BIT;\r
+ } PGR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PGCO:3;\r
+ unsigned char :1;\r
+ unsigned char PGCOVE:1;\r
+ unsigned char PGCI:2;\r
+ } BIT;\r
+ } PGC1;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PDBF7:1;\r
+ unsigned char PDBF6:1;\r
+ unsigned char PDBF5:1;\r
+ unsigned char PDBF4:1;\r
+ unsigned char PDBF3:1;\r
+ unsigned char PDBF2:1;\r
+ unsigned char PDBF1:1;\r
+ unsigned char PDBF0:1;\r
+ } BIT;\r
+ } PDBF1;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSM:2;\r
+ unsigned char PSP:2;\r
+ unsigned char PSB:3;\r
+ } BIT;\r
+ } PEL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSM:2;\r
+ unsigned char PSP:2;\r
+ unsigned char PSB:3;\r
+ } BIT;\r
+ } PEL1;\r
+ char wk5[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char WI:1;\r
+ unsigned char WE:1;\r
+ unsigned char :5;\r
+ unsigned char SEG:1;\r
+ } BIT;\r
+ } ELSEGR;\r
+};\r
+\r
+struct st_flash {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DFLEN:1;\r
+ } BIT;\r
+ } DFLCTL;\r
+};\r
+\r
+struct st_icu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IR:1;\r
+ } BIT;\r
+ } IR[250];\r
+ char wk0[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCE:1;\r
+ } BIT;\r
+ } DTCER[249];\r
+ char wk1[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IEN7:1;\r
+ unsigned char IEN6:1;\r
+ unsigned char IEN5:1;\r
+ unsigned char IEN4:1;\r
+ unsigned char IEN3:1;\r
+ unsigned char IEN2:1;\r
+ unsigned char IEN1:1;\r
+ unsigned char IEN0:1;\r
+ } BIT;\r
+ } IER[32];\r
+ char wk2[192];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SWINT:1;\r
+ } BIT;\r
+ } SWINTR;\r
+ char wk3[15];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FIEN:1;\r
+ unsigned short :7;\r
+ unsigned short FVCT:8;\r
+ } BIT;\r
+ } FIR;\r
+ char wk4[14];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IPR:4;\r
+ } BIT;\r
+ } IPR[250];\r
+ char wk5[262];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IRQMD:2;\r
+ } BIT;\r
+ } IRQCR[8];\r
+ char wk6[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FLTEN7:1;\r
+ unsigned char FLTEN6:1;\r
+ unsigned char FLTEN5:1;\r
+ unsigned char FLTEN4:1;\r
+ unsigned char FLTEN3:1;\r
+ unsigned char FLTEN2:1;\r
+ unsigned char FLTEN1:1;\r
+ unsigned char FLTEN0:1;\r
+ } BIT;\r
+ } IRQFLTE0;\r
+ char wk7[3];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FCLKSEL7:2;\r
+ unsigned short FCLKSEL6:2;\r
+ unsigned short FCLKSEL5:2;\r
+ unsigned short FCLKSEL4:2;\r
+ unsigned short FCLKSEL3:2;\r
+ unsigned short FCLKSEL2:2;\r
+ unsigned short FCLKSEL1:2;\r
+ unsigned short FCLKSEL0:2;\r
+ } BIT;\r
+ } IRQFLTC0;\r
+ char wk8[106];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2ST:1;\r
+ unsigned char LVD1ST:1;\r
+ unsigned char IWDTST:1;\r
+ unsigned char :1;\r
+ unsigned char OSTST:1;\r
+ unsigned char NMIST:1;\r
+ } BIT;\r
+ } NMISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2EN:1;\r
+ unsigned char LVD1EN:1;\r
+ unsigned char IWDTEN:1;\r
+ unsigned char :1;\r
+ unsigned char OSTEN:1;\r
+ unsigned char NMIEN:1;\r
+ } BIT;\r
+ } NMIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2CLR:1;\r
+ unsigned char LVD1CLR:1;\r
+ unsigned char IWDTCLR:1;\r
+ unsigned char :1;\r
+ unsigned char OSTCLR:1;\r
+ unsigned char NMICLR:1;\r
+ } BIT;\r
+ } NMICLR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NMIMD:1;\r
+ } BIT;\r
+ } NMICR;\r
+ char wk9[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char NFLTEN:1;\r
+ } BIT;\r
+ } NMIFLTE;\r
+ char wk10[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char NFCLKSEL:2;\r
+ } BIT;\r
+ } NMIFLTC;\r
+};\r
+\r
+struct st_iwdt {\r
+ unsigned char IWDTRR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short RPSS:2;\r
+ unsigned short :2;\r
+ unsigned short RPES:2;\r
+ unsigned short CKS:4;\r
+ unsigned short :2;\r
+ unsigned short TOPS:2;\r
+ } BIT;\r
+ } IWDTCR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short REFEF:1;\r
+ unsigned short UNDFF:1;\r
+ unsigned short CNTVAL:14;\r
+ } BIT;\r
+ } IWDTSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTIRQS:1;\r
+ } BIT;\r
+ } IWDTRCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SLCSTP:1;\r
+ } BIT;\r
+ } IWDTCSTPR;\r
+};\r
+\r
+struct st_mpc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0WI:1;\r
+ unsigned char PFSWE:1;\r
+ } BIT;\r
+ } PWPR;\r
+ char wk0[35];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P03PFS;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P05PFS;\r
+ char wk2[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P14PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P15PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P16PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P17PFS;\r
+ char wk3[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P26PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P27PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P30PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P31PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P32PFS;\r
+ char wk4[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P35PFS;\r
+ char wk5[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P40PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P41PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P42PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P43PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P44PFS;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P46PFS;\r
+ char wk7[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P54PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P55PFS;\r
+ char wk8[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA1PFS;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA4PFS;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA6PFS;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB1PFS;\r
+ char wk12[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB3PFS;\r
+ char wk13[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB7PFS;\r
+ char wk14[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC7PFS;\r
+ char wk15[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE7PFS;\r
+ char wk16[30];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ7PFS;\r
+};\r
+\r
+struct st_mtu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OE4D:1;\r
+ unsigned char OE4C:1;\r
+ unsigned char OE3D:1;\r
+ unsigned char OE4B:1;\r
+ unsigned char OE4A:1;\r
+ unsigned char OE3B:1;\r
+ } BIT;\r
+ } TOER;\r
+ char wk0[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BDC:1;\r
+ unsigned char N:1;\r
+ unsigned char P:1;\r
+ unsigned char FB:1;\r
+ unsigned char WF:1;\r
+ unsigned char VF:1;\r
+ unsigned char UF:1;\r
+ } BIT;\r
+ } TGCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSYE:1;\r
+ unsigned char :2;\r
+ unsigned char TOCL:1;\r
+ unsigned char TOCS:1;\r
+ unsigned char OLSN:1;\r
+ unsigned char OLSP:1;\r
+ } BIT;\r
+ } TOCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BF:2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOCR2;\r
+ char wk1[4];\r
+ unsigned short TCDR;\r
+ unsigned short TDDR;\r
+ char wk2[8];\r
+ unsigned short TCNTS;\r
+ unsigned short TCBR;\r
+ char wk3[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char T3AEN:1;\r
+ unsigned char T3ACOR:3;\r
+ unsigned char T4VEN:1;\r
+ unsigned char T4VCOR:3;\r
+ } BIT;\r
+ } TITCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char T3ACNT:3;\r
+ unsigned char :1;\r
+ unsigned char T4VCNT:3;\r
+ } BIT;\r
+ } TITCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char BTE:2;\r
+ } BIT;\r
+ } TBTER;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TDER:1;\r
+ } BIT;\r
+ } TDER;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOLBR;\r
+ char wk6[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCE:1;\r
+ unsigned char :6;\r
+ unsigned char WRE:1;\r
+ } BIT;\r
+ } TWCR;\r
+ char wk7[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CST4:1;\r
+ unsigned char CST3:1;\r
+ unsigned char :3;\r
+ unsigned char CST2:1;\r
+ unsigned char CST1:1;\r
+ unsigned char CST0:1;\r
+ } BIT;\r
+ } TSTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SYNC4:1;\r
+ unsigned char SYNC3:1;\r
+ unsigned char :3;\r
+ unsigned char SYNC2:1;\r
+ unsigned char SYNC1:1;\r
+ unsigned char SYNC0:1;\r
+ } BIT;\r
+ } TSYR;\r
+ char wk8[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char RWE:1;\r
+ } BIT;\r
+ } TRWER;\r
+};\r
+\r
+struct st_mtu0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[111];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BFE:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk1[16];\r
+ unsigned short TGRE;\r
+ unsigned short TGRF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TGIEF:1;\r
+ unsigned char TGIEE:1;\r
+ } BIT;\r
+ } TIER2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+};\r
+\r
+struct st_mtu1 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[238];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CCLR:2;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk3[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char I2BE:1;\r
+ unsigned char I2AE:1;\r
+ unsigned char I1BE:1;\r
+ unsigned char I1AE:1;\r
+ } BIT;\r
+ } TICCR;\r
+};\r
+\r
+struct st_mtu2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[365];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CCLR:2;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_mtu3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk3[7];\r
+ unsigned short TCNT;\r
+ char wk4[6];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk5[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk6[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk8[90];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu4 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char TTGE2:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk4[8];\r
+ unsigned short TCNT;\r
+ char wk5[8];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk6[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk8[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk9[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BF:2;\r
+ unsigned short :6;\r
+ unsigned short UT4AE:1;\r
+ unsigned short DT4AE:1;\r
+ unsigned short UT4BE:1;\r
+ unsigned short DT4BE:1;\r
+ unsigned short ITA3AE:1;\r
+ unsigned short ITA4VE:1;\r
+ unsigned short ITB3AE:1;\r
+ unsigned short ITB4VE:1;\r
+ } BIT;\r
+ } TADCR;\r
+ char wk10[2];\r
+ unsigned short TADCORA;\r
+ unsigned short TADCORB;\r
+ unsigned short TADCOBRA;\r
+ unsigned short TADCOBRB;\r
+ char wk11[72];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu5 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char :1;\r
+ unsigned char NFWEN:1;\r
+ unsigned char NFVEN:1;\r
+ unsigned char NFUEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[490];\r
+ unsigned short TCNTU;\r
+ unsigned short TGRU;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRU;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORU;\r
+ char wk3[9];\r
+ unsigned short TCNTV;\r
+ unsigned short TGRV;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRV;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORV;\r
+ char wk5[9];\r
+ unsigned short TCNTW;\r
+ unsigned short TGRW;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRW;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORW;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TGIE5U:1;\r
+ unsigned char TGIE5V:1;\r
+ unsigned char TGIE5W:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CSTU5:1;\r
+ unsigned char CSTV5:1;\r
+ unsigned char CSTW5:1;\r
+ } BIT;\r
+ } TSTR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CMPCLR5U:1;\r
+ unsigned char CMPCLR5V:1;\r
+ unsigned char CMPCLR5W:1;\r
+ } BIT;\r
+ } TCNTCMPCLR;\r
+};\r
+\r
+struct st_poe {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char POE3F:1;\r
+ unsigned char POE2F:1;\r
+ unsigned char POE1F:1;\r
+ unsigned char POE0F:1;\r
+ unsigned char :3;\r
+ unsigned char PIE1:1;\r
+ unsigned char POE3M:2;\r
+ unsigned char POE2M:2;\r
+ unsigned char POE1M:2;\r
+ unsigned char POE0M:2;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char OSF1:1;\r
+ unsigned char :5;\r
+ unsigned char OCE1:1;\r
+ unsigned char OIE1:1;\r
+ } BIT;\r
+ } OCSR1;\r
+ char wk0[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char POE8F:1;\r
+ unsigned char :2;\r
+ unsigned char POE8E:1;\r
+ unsigned char PIE2:1;\r
+ unsigned char :6;\r
+ unsigned char POE8M:2;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char CH0HIZ:1;\r
+ unsigned char CH34HIZ:1;\r
+ } BIT;\r
+ } SPOER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PE3ZE:1;\r
+ unsigned char PE2ZE:1;\r
+ unsigned char PE1ZE:1;\r
+ unsigned char PE0ZE:1;\r
+ } BIT;\r
+ } POECR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char P1CZEA:1;\r
+ unsigned char P2CZEA:1;\r
+ unsigned char P3CZEA:1;\r
+ } BIT;\r
+ } POECR2;\r
+ char wk1[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char OSTSTF:1;\r
+ unsigned char :2;\r
+ unsigned char OSTSTE:1;\r
+ } BIT;\r
+ } ICSR3;\r
+};\r
+\r
+struct st_port {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char PSEL5:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL3:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL1:1;\r
+ unsigned char PSEL0:1;\r
+ } BIT;\r
+ } PSRB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL7:1;\r
+ unsigned char PSEL6:1;\r
+ } BIT;\r
+ } PSRA;\r
+};\r
+\r
+struct st_port0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[33];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[61];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port4 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+};\r
+\r
+struct st_port5 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porta {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :3;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char :3;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[52];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[42];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :3;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[51];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[43];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[50];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porte {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[45];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[48];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_riic {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICE:1;\r
+ unsigned char IICRST:1;\r
+ unsigned char CLO:1;\r
+ unsigned char SOWP:1;\r
+ unsigned char SCLO:1;\r
+ unsigned char SDAO:1;\r
+ unsigned char SCLI:1;\r
+ unsigned char SDAI:1;\r
+ } BIT;\r
+ } ICCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BBSY:1;\r
+ unsigned char MST:1;\r
+ unsigned char TRS:1;\r
+ unsigned char :1;\r
+ unsigned char SP:1;\r
+ unsigned char RS:1;\r
+ unsigned char ST:1;\r
+ } BIT;\r
+ } ICCR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTWP:1;\r
+ unsigned char CKS:3;\r
+ unsigned char BCWP:1;\r
+ unsigned char BC:3;\r
+ } BIT;\r
+ } ICMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DLCS:1;\r
+ unsigned char SDDL:3;\r
+ unsigned char TMWE:1;\r
+ unsigned char TMOH:1;\r
+ unsigned char TMOL:1;\r
+ unsigned char TMOS:1;\r
+ } BIT;\r
+ } ICMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SMBS:1;\r
+ unsigned char WAIT:1;\r
+ unsigned char RDRFS:1;\r
+ unsigned char ACKWP:1;\r
+ unsigned char ACKBT:1;\r
+ unsigned char ACKBR:1;\r
+ unsigned char NF:2;\r
+ } BIT;\r
+ } ICMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SCLE:1;\r
+ unsigned char NFE:1;\r
+ unsigned char NACKE:1;\r
+ unsigned char SALE:1;\r
+ unsigned char NALE:1;\r
+ unsigned char MALE:1;\r
+ unsigned char TMOE:1;\r
+ } BIT;\r
+ } ICFER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOAE:1;\r
+ unsigned char :1;\r
+ unsigned char DIDE:1;\r
+ unsigned char :1;\r
+ unsigned char GCAE:1;\r
+ unsigned char SAR2E:1;\r
+ unsigned char SAR1E:1;\r
+ unsigned char SAR0E:1;\r
+ } BIT;\r
+ } ICSER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char NAKIE:1;\r
+ unsigned char SPIE:1;\r
+ unsigned char STIE:1;\r
+ unsigned char ALIE:1;\r
+ unsigned char TMOIE:1;\r
+ } BIT;\r
+ } ICIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOA:1;\r
+ unsigned char :1;\r
+ unsigned char DID:1;\r
+ unsigned char :1;\r
+ unsigned char GCA:1;\r
+ unsigned char AAS2:1;\r
+ unsigned char AAS1:1;\r
+ unsigned char AAS0:1;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TDRE:1;\r
+ unsigned char TEND:1;\r
+ unsigned char RDRF:1;\r
+ unsigned char NACKF:1;\r
+ unsigned char STOP:1;\r
+ unsigned char START:1;\r
+ unsigned char AL:1;\r
+ unsigned char TMOF:1;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTL;\r
+ };\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTH;\r
+ };\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRL:5;\r
+ } BIT;\r
+ } ICBRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRH:5;\r
+ } BIT;\r
+ } ICBRH;\r
+ unsigned char ICDRT;\r
+ unsigned char ICDRR;\r
+};\r
+\r
+struct st_rspi {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPRIE:1;\r
+ unsigned char SPE:1;\r
+ unsigned char SPTIE:1;\r
+ unsigned char SPEIE:1;\r
+ unsigned char MSTR:1;\r
+ unsigned char MODFEN:1;\r
+ unsigned char TXMD:1;\r
+ unsigned char SPMS:1;\r
+ } BIT;\r
+ } SPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char SSL3P:1;\r
+ unsigned char SSL2P:1;\r
+ unsigned char SSL1P:1;\r
+ unsigned char SSL0P:1;\r
+ } BIT;\r
+ } SSLP;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char MOIFE:1;\r
+ unsigned char MOIFV:1;\r
+ unsigned char :2;\r
+ unsigned char SPLP2:1;\r
+ unsigned char SPLP:1;\r
+ } BIT;\r
+ } SPPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PERF:1;\r
+ unsigned char MODF:1;\r
+ unsigned char IDLNF:1;\r
+ unsigned char OVRF:1;\r
+ } BIT;\r
+ } SPSR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ } WORD;\r
+ } SPDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPSLN:3;\r
+ } BIT;\r
+ } SPSCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SPECM:3;\r
+ unsigned char :1;\r
+ unsigned char SPCP:3;\r
+ } BIT;\r
+ } SPSSR;\r
+ unsigned char SPBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char SPLW:1;\r
+ unsigned char SPRDTD:1;\r
+ unsigned char :2;\r
+ unsigned char SPFC:2;\r
+ } BIT;\r
+ } SPDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SCKDL:3;\r
+ } BIT;\r
+ } SPCKD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SLNDL:3;\r
+ } BIT;\r
+ } SSLND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPNDL:3;\r
+ } BIT;\r
+ } SPND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PTE:1;\r
+ unsigned char SPIIE:1;\r
+ unsigned char SPOE:1;\r
+ unsigned char SPPE:1;\r
+ } BIT;\r
+ } SPCR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD5;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD6;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD7;\r
+};\r
+\r
+struct st_rtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char F1HZ:1;\r
+ unsigned char F2HZ:1;\r
+ unsigned char F4HZ:1;\r
+ unsigned char F8HZ:1;\r
+ unsigned char F16HZ:1;\r
+ unsigned char F32HZ:1;\r
+ unsigned char F64HZ:1;\r
+ } BIT;\r
+ } R64CNT;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECCNT;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINCNT;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRCNT;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char DAYW:3;\r
+ } BIT;\r
+ } RWKCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char DATE10:2;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYCNT;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONCNT;\r
+ char wk6[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short YR10:4;\r
+ unsigned short YR1:4;\r
+ } BIT;\r
+ } RYRCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECAR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINAR;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRAR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :4;\r
+ unsigned char DAYW:3;\r
+ } BIT;\r
+ } RWKAR;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :1;\r
+ unsigned char DATE10:2;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYAR;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :2;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONAR;\r
+ char wk12[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short YR10:4;\r
+ unsigned short YR1:4;\r
+ } BIT;\r
+ } RYRAR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RYRAREN;\r
+ char wk13[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PES:4;\r
+ unsigned char RTCOS:1;\r
+ unsigned char PIE:1;\r
+ unsigned char CIE:1;\r
+ unsigned char AIE:1;\r
+ } BIT;\r
+ } RCR1;\r
+ char wk14[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CNTMD:1;\r
+ unsigned char HR24:1;\r
+ unsigned char AADJP:1;\r
+ unsigned char AADJE:1;\r
+ unsigned char RTCOE:1;\r
+ unsigned char ADJ30:1;\r
+ unsigned char RESET:1;\r
+ unsigned char START:1;\r
+ } BIT;\r
+ } RCR2;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char RTCDV:2;\r
+ unsigned char RTCEN:1;\r
+ } BIT;\r
+ } RCR3;\r
+ char wk16[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PMADJ:2;\r
+ unsigned char ADJ:6;\r
+ } BIT;\r
+ } RADJ;\r
+};\r
+\r
+struct st_rtcb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT0;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT1;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT3;\r
+ char wk3[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT0AR;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT1AR;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT2AR;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT3AR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT0AER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT1AER;\r
+ char wk9[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short ENB:8;\r
+ } BIT;\r
+ } BCNT2AER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT3AER;\r
+};\r
+\r
+struct st_s12ad {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADST:1;\r
+ unsigned short ADCS:2;\r
+ unsigned short ADIE:1;\r
+ unsigned short :1;\r
+ unsigned short ADHSC:1;\r
+ unsigned short TRGE:1;\r
+ unsigned short EXTRG:1;\r
+ unsigned short DBLE:1;\r
+ unsigned short GBADIE:1;\r
+ unsigned short :1;\r
+ unsigned short DBLANS:5;\r
+ } BIT;\r
+ } ADCSR;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ANSA15:1;\r
+ unsigned short ANSA14:1;\r
+ unsigned short ANSA13:1;\r
+ unsigned short ANSA12:1;\r
+ unsigned short ANSA11:1;\r
+ unsigned short ANSA10:1;\r
+ unsigned short ANSA9:1;\r
+ unsigned short ANSA8:1;\r
+ unsigned short :1;\r
+ unsigned short ANSA6:1;\r
+ unsigned short :1;\r
+ unsigned short ANSA4:1;\r
+ unsigned short ANSA3:1;\r
+ unsigned short ANSA2:1;\r
+ unsigned short ANSA1:1;\r
+ unsigned short ANSA0:1;\r
+ } BIT;\r
+ } ADANSA;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADS15:1;\r
+ unsigned short ADS14:1;\r
+ unsigned short ADS13:1;\r
+ unsigned short ADS12:1;\r
+ unsigned short ADS11:1;\r
+ unsigned short ADS10:1;\r
+ unsigned short ADS9:1;\r
+ unsigned short ADS8:1;\r
+ unsigned short :1;\r
+ unsigned short ADS6:1;\r
+ unsigned short :1;\r
+ unsigned short ADS4:1;\r
+ unsigned short ADS3:1;\r
+ unsigned short ADS2:1;\r
+ unsigned short ADS1:1;\r
+ unsigned short ADS0:1;\r
+ } BIT;\r
+ } ADADS;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char ADC:2;\r
+ } BIT;\r
+ } ADADC;\r
+ char wk3[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADRFMT:1;\r
+ unsigned short :9;\r
+ unsigned short ACE:1;\r
+ } BIT;\r
+ } ADCER;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short TRSA:4;\r
+ unsigned short :4;\r
+ unsigned short TRSB:4;\r
+ } BIT;\r
+ } ADSTRGR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short OCS:1;\r
+ unsigned short TSS:1;\r
+ unsigned short :6;\r
+ unsigned short OCSAD:1;\r
+ } BIT;\r
+ } ADEXICR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ANSB15:1;\r
+ unsigned short ANSB14:1;\r
+ unsigned short ANSB13:1;\r
+ unsigned short ANSB12:1;\r
+ unsigned short ANSB11:1;\r
+ unsigned short ANSB10:1;\r
+ unsigned short ANSB9:1;\r
+ unsigned short ANSB8:1;\r
+ unsigned short :1;\r
+ unsigned short ANSB6:1;\r
+ unsigned short :1;\r
+ unsigned short ANSB4:1;\r
+ unsigned short ANSB3:1;\r
+ unsigned short ANSB2:1;\r
+ unsigned short ANSB1:1;\r
+ unsigned short ANSB0:1;\r
+ } BIT;\r
+ } ADANSB;\r
+ char wk4[2];\r
+ unsigned short ADDBLDR;\r
+ unsigned short ADTSDR;\r
+ unsigned short ADOCDR;\r
+ char wk5[2];\r
+ unsigned short ADDR0;\r
+ unsigned short ADDR1;\r
+ unsigned short ADDR2;\r
+ unsigned short ADDR3;\r
+ unsigned short ADDR4;\r
+ char wk6[2];\r
+ unsigned short ADDR6;\r
+ char wk7[2];\r
+ unsigned short ADDR8;\r
+ unsigned short ADDR9;\r
+ unsigned short ADDR10;\r
+ unsigned short ADDR11;\r
+ unsigned short ADDR12;\r
+ unsigned short ADDR13;\r
+ unsigned short ADDR14;\r
+ unsigned short ADDR15;\r
+ char wk8[32];\r
+ unsigned char ADSSTR0;\r
+ unsigned char ADSSTRL;\r
+ char wk9[14];\r
+ unsigned char ADSSTRT;\r
+ unsigned char ADSSTRO;\r
+ char wk10[1];\r
+ unsigned char ADSSTR1;\r
+ unsigned char ADSSTR2;\r
+ unsigned char ADSSTR3;\r
+ unsigned char ADSSTR4;\r
+ char wk11[1];\r
+ unsigned char ADSSTR6;\r
+};\r
+\r
+struct st_sci1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RXDESEL:1;\r
+ unsigned char :1;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+};\r
+\r
+struct st_sci12 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RXDESEL:1;\r
+ unsigned char :1;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+ char wk0[18];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ESME:1;\r
+ } BIT;\r
+ } ESMER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char BRME:1;\r
+ unsigned char RXDSF:1;\r
+ unsigned char SFSF:1;\r
+ } BIT;\r
+ } CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PIBS:3;\r
+ unsigned char PIBE:1;\r
+ unsigned char CF1DS:2;\r
+ unsigned char CF0RE:1;\r
+ unsigned char BFE:1;\r
+ } BIT;\r
+ } CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RTS:2;\r
+ unsigned char BCCS:2;\r
+ unsigned char :1;\r
+ unsigned char DFCS:3;\r
+ } BIT;\r
+ } CR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SDST:1;\r
+ } BIT;\r
+ } CR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SHARPS:1;\r
+ unsigned char :2;\r
+ unsigned char RXDXPS:1;\r
+ unsigned char TXDXPS:1;\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDIE:1;\r
+ unsigned char BCDIE:1;\r
+ unsigned char PIBDIE:1;\r
+ unsigned char CF1MIE:1;\r
+ unsigned char CF0MIE:1;\r
+ unsigned char BFDIE:1;\r
+ } BIT;\r
+ } ICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDF:1;\r
+ unsigned char BCDF:1;\r
+ unsigned char PIBDF:1;\r
+ unsigned char CF1MF:1;\r
+ unsigned char CF0MF:1;\r
+ unsigned char BFDF:1;\r
+ } BIT;\r
+ } STR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDCL:1;\r
+ unsigned char BCDCL:1;\r
+ unsigned char PIBDCL:1;\r
+ unsigned char CF1MCL:1;\r
+ unsigned char CF0MCL:1;\r
+ unsigned char BFDCL:1;\r
+ } BIT;\r
+ } STCR;\r
+ unsigned char CF0DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF0CE7:1;\r
+ unsigned char CF0CE6:1;\r
+ unsigned char CF0CE5:1;\r
+ unsigned char CF0CE4:1;\r
+ unsigned char CF0CE3:1;\r
+ unsigned char CF0CE2:1;\r
+ unsigned char CF0CE1:1;\r
+ unsigned char CF0CE0:1;\r
+ } BIT;\r
+ } CF0CR;\r
+ unsigned char CF0RR;\r
+ unsigned char PCF1DR;\r
+ unsigned char SCF1DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF1CE7:1;\r
+ unsigned char CF1CE6:1;\r
+ unsigned char CF1CE5:1;\r
+ unsigned char CF1CE4:1;\r
+ unsigned char CF1CE3:1;\r
+ unsigned char CF1CE2:1;\r
+ unsigned char CF1CE1:1;\r
+ unsigned char CF1CE0:1;\r
+ } BIT;\r
+ } CF1CR;\r
+ unsigned char CF1RR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TCST:1;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char TCSS:3;\r
+ unsigned char TWRC:1;\r
+ unsigned char :1;\r
+ unsigned char TOMS:2;\r
+ } BIT;\r
+ } TMR;\r
+ unsigned char TPRE;\r
+ unsigned char TCNT;\r
+};\r
+\r
+struct st_smci {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char GM:1;\r
+ unsigned char BLK:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char BCP:2;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char ERS:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+};\r
+\r
+struct st_system {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short MD:1;\r
+ } BIT;\r
+ } MDMONR;\r
+ char wk0[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short RAME:1;\r
+ } BIT;\r
+ } SYSCR1;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SSBY:1;\r
+ } BIT;\r
+ } SBYCR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long MSTPA28:1;\r
+ unsigned long :8;\r
+ unsigned long MSTPA19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA17:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA15:1;\r
+ unsigned long :5;\r
+ unsigned long MSTPA9:1;\r
+ } BIT;\r
+ } MSTPCRA;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long MSTPB30:1;\r
+ unsigned long :3;\r
+ unsigned long MSTPB26:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPB23:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB21:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB17:1;\r
+ unsigned long :7;\r
+ unsigned long MSTPB9:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPB6:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB4:1;\r
+ } BIT;\r
+ } MSTPCRB;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long DSLPE:1;\r
+ unsigned long :11;\r
+ unsigned long MSTPC19:1;\r
+ unsigned long :18;\r
+ unsigned long MSTPC0:1;\r
+ } BIT;\r
+ } MSTPCRC;\r
+ char wk3[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long FCK:4;\r
+ unsigned long ICK:4;\r
+ unsigned long :12;\r
+ unsigned long PCKB:4;\r
+ unsigned long :4;\r
+ unsigned long PCKD:4;\r
+ } BIT;\r
+ } SCKCR;\r
+ char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short CKSEL:3;\r
+ } BIT;\r
+ } SCKCR3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short STC:6;\r
+ unsigned short :6;\r
+ unsigned short PLIDIV:2;\r
+ } BIT;\r
+ } PLLCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char PLLEN:1;\r
+ } BIT;\r
+ } PLLCR2;\r
+ char wk5[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char MOSTP:1;\r
+ } BIT;\r
+ } MOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SOSTP:1;\r
+ } BIT;\r
+ } SOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char LCSTP:1;\r
+ } BIT;\r
+ } LOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ILCSTP:1;\r
+ } BIT;\r
+ } ILOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char HCSTP:1;\r
+ } BIT;\r
+ } HOCOCR;\r
+ char wk6[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char HCOVF:1;\r
+ unsigned char PLOVF:1;\r
+ unsigned char :1;\r
+ unsigned char MOOVF:1;\r
+ } BIT;\r
+ } OSCOVFSR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CKOSTP:1;\r
+ unsigned short CKODIV:3;\r
+ unsigned short :1;\r
+ unsigned short CKOSEL:3;\r
+ } BIT;\r
+ } CKOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OSTDE:1;\r
+ unsigned char :6;\r
+ unsigned char OSTDIE:1;\r
+ } BIT;\r
+ } OSTDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char OSTDF:1;\r
+ } BIT;\r
+ } OSTDSR;\r
+ char wk8[94];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char OPCMTSF:1;\r
+ unsigned char :1;\r
+ unsigned char OPCM:3;\r
+ } BIT;\r
+ } OPCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTCKEN:1;\r
+ unsigned char :4;\r
+ unsigned char RSTCKSEL:3;\r
+ } BIT;\r
+ } RSTCKCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MSTS:5;\r
+ } BIT;\r
+ } MOSCWTCR;\r
+ char wk9[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SOPCMTSF:1;\r
+ unsigned char :3;\r
+ unsigned char SOPCM:1;\r
+ } BIT;\r
+ } SOPCCR;\r
+ char wk10[21];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SWRF:1;\r
+ unsigned char :1;\r
+ unsigned char IWDTRF:1;\r
+ } BIT;\r
+ } RSTSR2;\r
+ char wk11[1];\r
+ unsigned short SWRR;\r
+ char wk12[28];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char LVD1IRQSEL:1;\r
+ unsigned char LVD1IDTSEL:2;\r
+ } BIT;\r
+ } LVD1CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD1MON:1;\r
+ unsigned char LVD1DET:1;\r
+ } BIT;\r
+ } LVD1SR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char LVD2IRQSEL:1;\r
+ unsigned char LVD2IDTSEL:2;\r
+ } BIT;\r
+ } LVD2CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD2MON:1;\r
+ unsigned char LVD2DET:1;\r
+ } BIT;\r
+ } LVD2SR;\r
+ char wk13[794];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRKEY:8;\r
+ unsigned short :4;\r
+ unsigned short PRC3:1;\r
+ unsigned short :1;\r
+ unsigned short PRC1:1;\r
+ unsigned short PRC0:1;\r
+ } BIT;\r
+ } PRCR;\r
+ char wk14[48784];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char LVD2RF:1;\r
+ unsigned char LVD1RF:1;\r
+ unsigned char :1;\r
+ unsigned char PORF:1;\r
+ } BIT;\r
+ } RSTSR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CWSF:1;\r
+ } BIT;\r
+ } RSTSR1;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MOSEL:1;\r
+ unsigned char MODRV21:1;\r
+ } BIT;\r
+ } MOFCR;\r
+ char wk16[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char LVD2E:1;\r
+ unsigned char LVD1E:1;\r
+ unsigned char :1;\r
+ unsigned char EXVCCINP2:1;\r
+ } BIT;\r
+ } LVCMPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2LVL:2;\r
+ unsigned char LVD1LVL:4;\r
+ } BIT;\r
+ } LVDLVLR;\r
+ char wk17[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD1RN:1;\r
+ unsigned char LVD1RI:1;\r
+ unsigned char :3;\r
+ unsigned char LVD1CMPE:1;\r
+ unsigned char :1;\r
+ unsigned char LVD1RIE:1;\r
+ } BIT;\r
+ } LVD1CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD2RN:1;\r
+ unsigned char LVD2RI:1;\r
+ unsigned char :3;\r
+ unsigned char LVD2CMPE:1;\r
+ unsigned char :1;\r
+ unsigned char LVD2RIE:1;\r
+ } BIT;\r
+ } LVD2CR0;\r
+};\r
+\r
+struct st_usb {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short SCKE:1;\r
+ unsigned short :1;\r
+ unsigned short CNEN:1;\r
+ unsigned short :1;\r
+ unsigned short DCFM:1;\r
+ unsigned short DRPD:1;\r
+ unsigned short DPRPU:1;\r
+ unsigned short :3;\r
+ unsigned short USBE:1;\r
+ } BIT;\r
+ } SYSCFG;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVCMON:2;\r
+ unsigned short :7;\r
+ unsigned short HTACT:1;\r
+ unsigned short :3;\r
+ unsigned short IDMON:1;\r
+ unsigned short LNST:2;\r
+ } BIT;\r
+ } SYSSTS0;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short HNPBTOA:1;\r
+ unsigned short EXICEN:1;\r
+ unsigned short VBUSEN:1;\r
+ unsigned short WKUP:1;\r
+ unsigned short RWUPE:1;\r
+ unsigned short USBRST:1;\r
+ unsigned short RESUME:1;\r
+ unsigned short UACT:1;\r
+ unsigned short :1;\r
+ unsigned short RHST:3;\r
+ } BIT;\r
+ } DVSTCTR0;\r
+ char wk2[10];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } CFIFO;\r
+ char wk3[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D0FIFO;\r
+ char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D1FIFO;\r
+ char wk5[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short :3;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :2;\r
+ unsigned short ISEL:1;\r
+ unsigned short :1;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } CFIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } CFIFOCTR;\r
+ char wk6[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D0FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } D0FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D1FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } D1FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBSE:1;\r
+ unsigned short RSME:1;\r
+ unsigned short SOFE:1;\r
+ unsigned short DVSE:1;\r
+ unsigned short CTRE:1;\r
+ unsigned short BEMPE:1;\r
+ unsigned short NRDYE:1;\r
+ unsigned short BRDYE:1;\r
+ } BIT;\r
+ } INTENB0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRCRE:1;\r
+ unsigned short BCHGE:1;\r
+ unsigned short :1;\r
+ unsigned short DTCHE:1;\r
+ unsigned short ATTCHE:1;\r
+ unsigned short :4;\r
+ unsigned short EOFERRE:1;\r
+ unsigned short SIGNE:1;\r
+ unsigned short SACKE:1;\r
+ unsigned short :3;\r
+ unsigned short PDDETINTE0:1;\r
+ } BIT;\r
+ } INTENB1;\r
+ char wk7[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDYE:1;\r
+ unsigned short PIPE8BRDYE:1;\r
+ unsigned short PIPE7BRDYE:1;\r
+ unsigned short PIPE6BRDYE:1;\r
+ unsigned short PIPE5BRDYE:1;\r
+ unsigned short PIPE4BRDYE:1;\r
+ unsigned short PIPE3BRDYE:1;\r
+ unsigned short PIPE2BRDYE:1;\r
+ unsigned short PIPE1BRDYE:1;\r
+ unsigned short PIPE0BRDYE:1;\r
+ } BIT;\r
+ } BRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9NRDYE:1;\r
+ unsigned short PIPE8NRDYE:1;\r
+ unsigned short PIPE7NRDYE:1;\r
+ unsigned short PIPE6NRDYE:1;\r
+ unsigned short PIPE5NRDYE:1;\r
+ unsigned short PIPE4NRDYE:1;\r
+ unsigned short PIPE3NRDYE:1;\r
+ unsigned short PIPE2NRDYE:1;\r
+ unsigned short PIPE1NRDYE:1;\r
+ unsigned short PIPE0NRDYE:1;\r
+ } BIT;\r
+ } NRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMPE:1;\r
+ unsigned short PIPE8BEMPE:1;\r
+ unsigned short PIPE7BEMPE:1;\r
+ unsigned short PIPE6BEMPE:1;\r
+ unsigned short PIPE5BEMPE:1;\r
+ unsigned short PIPE4BEMPE:1;\r
+ unsigned short PIPE3BEMPE:1;\r
+ unsigned short PIPE2BEMPE:1;\r
+ unsigned short PIPE1BEMPE:1;\r
+ unsigned short PIPE0BEMPE:1;\r
+ } BIT;\r
+ } BEMPENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short TRNENSEL:1;\r
+ unsigned short :1;\r
+ unsigned short BRDYM:1;\r
+ unsigned short :1;\r
+ unsigned short EDGESTS:1;\r
+ } BIT;\r
+ } SOFCFG;\r
+ char wk8[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBINT:1;\r
+ unsigned short RESM:1;\r
+ unsigned short SOFR:1;\r
+ unsigned short DVST:1;\r
+ unsigned short CTRT:1;\r
+ unsigned short BEMP:1;\r
+ unsigned short NRDY:1;\r
+ unsigned short BRDY:1;\r
+ unsigned short VBSTS:1;\r
+ unsigned short DVSQ:3;\r
+ unsigned short VALID:1;\r
+ unsigned short CTSQ:3;\r
+ } BIT;\r
+ } INTSTS0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRCR:1;\r
+ unsigned short BCHG:1;\r
+ unsigned short :1;\r
+ unsigned short DTCH:1;\r
+ unsigned short ATTCH:1;\r
+ unsigned short :4;\r
+ unsigned short EOFERR:1;\r
+ unsigned short SIGN:1;\r
+ unsigned short SACK:1;\r
+ unsigned short :3;\r
+ unsigned short PDDETINT0:1;\r
+ } BIT;\r
+ } INTSTS1;\r
+ char wk9[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDY:1;\r
+ unsigned short PIPE8BRDY:1;\r
+ unsigned short PIPE7BRDY:1;\r
+ unsigned short PIPE6BRDY:1;\r
+ unsigned short PIPE5BRDY:1;\r
+ unsigned short PIPE4BRDY:1;\r
+ unsigned short PIPE3BRDY:1;\r
+ unsigned short PIPE2BRDY:1;\r
+ unsigned short PIPE1BRDY:1;\r
+ unsigned short PIPE0BRDY:1;\r
+ } BIT;\r
+ } BRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9NRDY:1;\r
+ unsigned short PIPE8NRDY:1;\r
+ unsigned short PIPE7NRDY:1;\r
+ unsigned short PIPE6NRDY:1;\r
+ unsigned short PIPE5NRDY:1;\r
+ unsigned short PIPE4NRDY:1;\r
+ unsigned short PIPE3NRDY:1;\r
+ unsigned short PIPE2NRDY:1;\r
+ unsigned short PIPE1NRDY:1;\r
+ unsigned short PIPE0NRDY:1;\r
+ } BIT;\r
+ } NRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMP:1;\r
+ unsigned short PIPE8BEMP:1;\r
+ unsigned short PIPE7BEMP:1;\r
+ unsigned short PIPE6BEMP:1;\r
+ unsigned short PIPE5BEMP:1;\r
+ unsigned short PIPE4BEMP:1;\r
+ unsigned short PIPE3BEMP:1;\r
+ unsigned short PIPE2BEMP:1;\r
+ unsigned short PIPE1BEMP:1;\r
+ unsigned short PIPE0BEMP:1;\r
+ } BIT;\r
+ } BEMPSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRN:1;\r
+ unsigned short CRCE:1;\r
+ unsigned short :3;\r
+ unsigned short FRNM:11;\r
+ } BIT;\r
+ } FRMNUM;\r
+ char wk10[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BREQUEST:8;\r
+ unsigned short BMREQUESTTYPE:8;\r
+ } BIT;\r
+ } USBREQ;\r
+ unsigned short USBVAL;\r
+ unsigned short USBINDX;\r
+ unsigned short USBLENG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ } BIT;\r
+ } DCPCFG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DEVSEL:4;\r
+ unsigned short :5;\r
+ unsigned short MXPS:7;\r
+ } BIT;\r
+ } DCPMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short SUREQ:1;\r
+ unsigned short :2;\r
+ unsigned short SUREQCLR:1;\r
+ unsigned short :2;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :2;\r
+ unsigned short CCPL:1;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } DCPCTR;\r
+ char wk11[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :12;\r
+ unsigned short PIPESEL:4;\r
+ } BIT;\r
+ } PIPESEL;\r
+ char wk12[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TYPE:2;\r
+ unsigned short :3;\r
+ unsigned short BFRE:1;\r
+ unsigned short DBLB:1;\r
+ unsigned short :1;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ unsigned short EPNUM:4;\r
+ } BIT;\r
+ } PIPECFG;\r
+ char wk13[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DEVSEL:4;\r
+ unsigned short :3;\r
+ unsigned short MXPS:9;\r
+ } BIT;\r
+ } PIPEMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short IFIS:1;\r
+ unsigned short :9;\r
+ unsigned short IITV:3;\r
+ } BIT;\r
+ } PIPEPERI;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE1CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE2CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE3CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE4CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE5CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE6CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE7CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE8CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE9CTR;\r
+ char wk14[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE1TRE;\r
+ unsigned short PIPE1TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE2TRE;\r
+ unsigned short PIPE2TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE3TRE;\r
+ unsigned short PIPE3TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE4TRE;\r
+ unsigned short PIPE4TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE5TRE;\r
+ unsigned short PIPE5TRN;\r
+ char wk15[12];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PDDETSTS0:1;\r
+ unsigned short CHGDETSTS0:1;\r
+ unsigned short BATCHGE0:1;\r
+ unsigned short DCPMODE0:1;\r
+ unsigned short VDMSRCE0:1;\r
+ unsigned short IDPSINKE0:1;\r
+ unsigned short VDPSRCE0:1;\r
+ unsigned short IDMSINKE0:1;\r
+ unsigned short IDPSRCE0:1;\r
+ unsigned short RPDME0:1;\r
+ } BIT;\r
+ } USBBCCTRL0;\r
+ char wk16[26];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short VBRPDCUT:1;\r
+ unsigned short :6;\r
+ unsigned short VDDUSBE:1;\r
+ } BIT;\r
+ } USBMC;\r
+ char wk17[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD5;\r
+};\r
+\r
+enum enum_ir {\r
+IR_BSC_BUSERR=16,IR_ICU_SWINT=27,\r
+IR_CMT0_CMI0,\r
+IR_CMT1_CMI1,\r
+IR_CAC_FERRF=32,IR_CAC_MENDF,IR_CAC_OVFF,\r
+IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,\r
+IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,\r
+IR_DOC_DOPCF=57,\r
+IR_RTC_CUP=63,\r
+IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,\r
+IR_LVD_LVD1=88,IR_LVD_LVD2,\r
+IR_USB0_USBR0,\r
+IR_RTC_ALM=92,IR_RTC_PRD,\r
+IR_S12AD_S12ADI0=102,IR_S12AD_GBADI,\r
+IR_ELC_ELSR18I=106,\r
+IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,\r
+IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,\r
+IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,\r
+IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,\r
+IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,\r
+IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,\r
+IR_POE_OEI1=170,IR_POE_OEI2,\r
+IR_SCI1_ERI1=218,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,\r
+IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,\r
+IR_SCI12_ERI12=238,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3,\r
+IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0\r
+};\r
+\r
+enum enum_dtce {\r
+DTCE_ICU_SWINT=27,\r
+DTCE_CMT0_CMI0,\r
+DTCE_CMT1_CMI1,\r
+DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,\r
+DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,\r
+DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,\r
+DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI,\r
+DTCE_ELC_ELSR18I=106,\r
+DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,\r
+DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,\r
+DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,\r
+DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,\r
+DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,\r
+DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,\r
+DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,\r
+DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5,\r
+DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12,\r
+DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0\r
+};\r
+\r
+enum enum_ier {\r
+IER_BSC_BUSERR=0x02,\r
+IER_ICU_SWINT=0x03,\r
+IER_CMT0_CMI0=0x03,\r
+IER_CMT1_CMI1=0x03,\r
+IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04,\r
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,\r
+IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,\r
+IER_DOC_DOPCF=0x07,\r
+IER_RTC_CUP=0x07,\r
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,\r
+IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B,\r
+IER_USB0_USBR0=0x0B,\r
+IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,\r
+IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C,\r
+IER_ELC_ELSR18I=0x0D,\r
+IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,\r
+IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,\r
+IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,\r
+IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,\r
+IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,\r
+IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11,\r
+IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,\r
+IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,\r
+IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,\r
+IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E,\r
+IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F\r
+};\r
+\r
+enum enum_ipr {\r
+IPR_BSC_BUSERR=0,\r
+IPR_ICU_SWINT=3,\r
+IPR_CMT0_CMI0=4,\r
+IPR_CMT1_CMI1=5,\r
+IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34,\r
+IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38,\r
+IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44,\r
+IPR_DOC_DOPCF=57,\r
+IPR_RTC_CUP=63,\r
+IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,\r
+IPR_LVD_LVD1=88,IPR_LVD_LVD2=89,\r
+IPR_USB0_USBR0=90,\r
+IPR_RTC_ALM=92,IPR_RTC_PRD=93,\r
+IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103,\r
+IPR_ELC_ELSR18I=106,\r
+IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118,\r
+IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123,\r
+IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127,\r
+IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133,\r
+IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138,\r
+IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139,\r
+IPR_POE_OEI1=170,IPR_POE_OEI2=171,\r
+IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218,\r
+IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222,\r
+IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245,\r
+IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249,\r
+IPR_BSC_=0,\r
+IPR_CMT0_=4,\r
+IPR_CMT1_=5,\r
+IPR_RSPI0_=44,\r
+IPR_DOC_=57,\r
+IPR_ELC_=106,\r
+IPR_MTU1_TGI=121,\r
+IPR_MTU1_TCI=123,\r
+IPR_MTU2_TGI=125,\r
+IPR_MTU2_TCI=127,\r
+IPR_MTU3_TGI=129,\r
+IPR_MTU4_TGI=134,\r
+IPR_MTU5_=139,\r
+IPR_MTU5_TGI=139,\r
+IPR_SCI1_=218,\r
+IPR_SCI5_=222\r
+};\r
+\r
+#define IEN_BSC_BUSERR IEN0\r
+#define IEN_ICU_SWINT IEN3\r
+#define IEN_CMT0_CMI0 IEN4\r
+#define IEN_CMT1_CMI1 IEN5\r
+#define IEN_CAC_FERRF IEN0\r
+#define IEN_CAC_MENDF IEN1\r
+#define IEN_CAC_OVFF IEN2\r
+#define IEN_USB0_D0FIFO0 IEN4\r
+#define IEN_USB0_D1FIFO0 IEN5\r
+#define IEN_USB0_USBI0 IEN6\r
+#define IEN_RSPI0_SPEI0 IEN4\r
+#define IEN_RSPI0_SPRI0 IEN5\r
+#define IEN_RSPI0_SPTI0 IEN6\r
+#define IEN_RSPI0_SPII0 IEN7\r
+#define IEN_DOC_DOPCF IEN1\r
+#define IEN_RTC_CUP IEN7\r
+#define IEN_ICU_IRQ0 IEN0\r
+#define IEN_ICU_IRQ1 IEN1\r
+#define IEN_ICU_IRQ2 IEN2\r
+#define IEN_ICU_IRQ3 IEN3\r
+#define IEN_ICU_IRQ4 IEN4\r
+#define IEN_ICU_IRQ5 IEN5\r
+#define IEN_ICU_IRQ6 IEN6\r
+#define IEN_ICU_IRQ7 IEN7\r
+#define IEN_LVD_LVD1 IEN0\r
+#define IEN_LVD_LVD2 IEN1\r
+#define IEN_USB0_USBR0 IEN2\r
+#define IEN_RTC_ALM IEN4\r
+#define IEN_RTC_PRD IEN5\r
+#define IEN_S12AD_S12ADI0 IEN6\r
+#define IEN_S12AD_GBADI IEN7\r
+#define IEN_ELC_ELSR18I IEN2\r
+#define IEN_MTU0_TGIA0 IEN2\r
+#define IEN_MTU0_TGIB0 IEN3\r
+#define IEN_MTU0_TGIC0 IEN4\r
+#define IEN_MTU0_TGID0 IEN5\r
+#define IEN_MTU0_TCIV0 IEN6\r
+#define IEN_MTU0_TGIE0 IEN7\r
+#define IEN_MTU0_TGIF0 IEN0\r
+#define IEN_MTU1_TGIA1 IEN1\r
+#define IEN_MTU1_TGIB1 IEN2\r
+#define IEN_MTU1_TCIV1 IEN3\r
+#define IEN_MTU1_TCIU1 IEN4\r
+#define IEN_MTU2_TGIA2 IEN5\r
+#define IEN_MTU2_TGIB2 IEN6\r
+#define IEN_MTU2_TCIV2 IEN7\r
+#define IEN_MTU2_TCIU2 IEN0\r
+#define IEN_MTU3_TGIA3 IEN1\r
+#define IEN_MTU3_TGIB3 IEN2\r
+#define IEN_MTU3_TGIC3 IEN3\r
+#define IEN_MTU3_TGID3 IEN4\r
+#define IEN_MTU3_TCIV3 IEN5\r
+#define IEN_MTU4_TGIA4 IEN6\r
+#define IEN_MTU4_TGIB4 IEN7\r
+#define IEN_MTU4_TGIC4 IEN0\r
+#define IEN_MTU4_TGID4 IEN1\r
+#define IEN_MTU4_TCIV4 IEN2\r
+#define IEN_MTU5_TGIU5 IEN3\r
+#define IEN_MTU5_TGIV5 IEN4\r
+#define IEN_MTU5_TGIW5 IEN5\r
+#define IEN_POE_OEI1 IEN2\r
+#define IEN_POE_OEI2 IEN3\r
+#define IEN_SCI1_ERI1 IEN2\r
+#define IEN_SCI1_RXI1 IEN3\r
+#define IEN_SCI1_TXI1 IEN4\r
+#define IEN_SCI1_TEI1 IEN5\r
+#define IEN_SCI5_ERI5 IEN6\r
+#define IEN_SCI5_RXI5 IEN7\r
+#define IEN_SCI5_TXI5 IEN0\r
+#define IEN_SCI5_TEI5 IEN1\r
+#define IEN_SCI12_ERI12 IEN6\r
+#define IEN_SCI12_RXI12 IEN7\r
+#define IEN_SCI12_TXI12 IEN0\r
+#define IEN_SCI12_TEI12 IEN1\r
+#define IEN_SCI12_SCIX0 IEN2\r
+#define IEN_SCI12_SCIX1 IEN3\r
+#define IEN_SCI12_SCIX2 IEN4\r
+#define IEN_SCI12_SCIX3 IEN5\r
+#define IEN_RIIC0_EEI0 IEN6\r
+#define IEN_RIIC0_RXI0 IEN7\r
+#define IEN_RIIC0_TXI0 IEN0\r
+#define IEN_RIIC0_TEI0 IEN1\r
+\r
+#define VECT_BSC_BUSERR 16\r
+#define VECT_ICU_SWINT 27\r
+#define VECT_CMT0_CMI0 28\r
+#define VECT_CMT1_CMI1 29\r
+#define VECT_CAC_FERRF 32\r
+#define VECT_CAC_MENDF 33\r
+#define VECT_CAC_OVFF 34\r
+#define VECT_USB0_D0FIFO0 36\r
+#define VECT_USB0_D1FIFO0 37\r
+#define VECT_USB0_USBI0 38\r
+#define VECT_RSPI0_SPEI0 44\r
+#define VECT_RSPI0_SPRI0 45\r
+#define VECT_RSPI0_SPTI0 46\r
+#define VECT_RSPI0_SPII0 47\r
+#define VECT_DOC_DOPCF 57\r
+#define VECT_RTC_CUP 63\r
+#define VECT_ICU_IRQ0 64\r
+#define VECT_ICU_IRQ1 65\r
+#define VECT_ICU_IRQ2 66\r
+#define VECT_ICU_IRQ3 67\r
+#define VECT_ICU_IRQ4 68\r
+#define VECT_ICU_IRQ5 69\r
+#define VECT_ICU_IRQ6 70\r
+#define VECT_ICU_IRQ7 71\r
+#define VECT_LVD_LVD1 88\r
+#define VECT_LVD_LVD2 89\r
+#define VECT_USB0_USBR0 90\r
+#define VECT_RTC_ALM 92\r
+#define VECT_RTC_PRD 93\r
+#define VECT_S12AD_S12ADI0 102\r
+#define VECT_S12AD_GBADI 103\r
+#define VECT_ELC_ELSR18I 106\r
+#define VECT_MTU0_TGIA0 114\r
+#define VECT_MTU0_TGIB0 115\r
+#define VECT_MTU0_TGIC0 116\r
+#define VECT_MTU0_TGID0 117\r
+#define VECT_MTU0_TCIV0 118\r
+#define VECT_MTU0_TGIE0 119\r
+#define VECT_MTU0_TGIF0 120\r
+#define VECT_MTU1_TGIA1 121\r
+#define VECT_MTU1_TGIB1 122\r
+#define VECT_MTU1_TCIV1 123\r
+#define VECT_MTU1_TCIU1 124\r
+#define VECT_MTU2_TGIA2 125\r
+#define VECT_MTU2_TGIB2 126\r
+#define VECT_MTU2_TCIV2 127\r
+#define VECT_MTU2_TCIU2 128\r
+#define VECT_MTU3_TGIA3 129\r
+#define VECT_MTU3_TGIB3 130\r
+#define VECT_MTU3_TGIC3 131\r
+#define VECT_MTU3_TGID3 132\r
+#define VECT_MTU3_TCIV3 133\r
+#define VECT_MTU4_TGIA4 134\r
+#define VECT_MTU4_TGIB4 135\r
+#define VECT_MTU4_TGIC4 136\r
+#define VECT_MTU4_TGID4 137\r
+#define VECT_MTU4_TCIV4 138\r
+#define VECT_MTU5_TGIU5 139\r
+#define VECT_MTU5_TGIV5 140\r
+#define VECT_MTU5_TGIW5 141\r
+#define VECT_POE_OEI1 170\r
+#define VECT_POE_OEI2 171\r
+#define VECT_SCI1_ERI1 218\r
+#define VECT_SCI1_RXI1 219\r
+#define VECT_SCI1_TXI1 220\r
+#define VECT_SCI1_TEI1 221\r
+#define VECT_SCI5_ERI5 222\r
+#define VECT_SCI5_RXI5 223\r
+#define VECT_SCI5_TXI5 224\r
+#define VECT_SCI5_TEI5 225\r
+#define VECT_SCI12_ERI12 238\r
+#define VECT_SCI12_RXI12 239\r
+#define VECT_SCI12_TXI12 240\r
+#define VECT_SCI12_TEI12 241\r
+#define VECT_SCI12_SCIX0 242\r
+#define VECT_SCI12_SCIX1 243\r
+#define VECT_SCI12_SCIX2 244\r
+#define VECT_SCI12_SCIX3 245\r
+#define VECT_RIIC0_EEI0 246\r
+#define VECT_RIIC0_RXI0 247\r
+#define VECT_RIIC0_TXI0 248\r
+#define VECT_RIIC0_TEI0 249\r
+\r
+#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19\r
+#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17\r
+#define MSTP_CMT SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23\r
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21\r
+#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19\r
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17\r
+#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9\r
+#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6\r
+#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19\r
+#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0\r
+\r
+#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR\r
+#define _IR( x ) __IR( x )\r
+#define IR( x , y ) _IR( _ ## x ## _ ## y )\r
+#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE\r
+#define _DTCE( x ) __DTCE( x )\r
+#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )\r
+#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x\r
+#define _IEN( x ) __IEN( x )\r
+#define IEN( x , y ) _IEN( _ ## x ## _ ## y )\r
+#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR\r
+#define _IPR( x ) __IPR( x )\r
+#define IPR( x , y ) _IPR( _ ## x ## _ ## y )\r
+#define __VECT( x ) VECT ## x\r
+#define _VECT( x ) __VECT( x )\r
+#define VECT( x , y ) _VECT( _ ## x ## _ ## y )\r
+#define __MSTP( x ) MSTP ## x\r
+#define _MSTP( x ) __MSTP( x )\r
+#define MSTP( x ) _MSTP( _ ## x )\r
+\r
+#define BSC (*(volatile struct st_bsc *)0x81300)\r
+#define CAC (*(volatile struct st_cac *)0x8B000)\r
+#define CMT (*(volatile struct st_cmt *)0x88000)\r
+#define CMT0 (*(volatile struct st_cmt0 *)0x88002)\r
+#define CMT1 (*(volatile struct st_cmt0 *)0x88008)\r
+#define CRC (*(volatile struct st_crc *)0x88280)\r
+#define DA (*(volatile struct st_da *)0x880C0)\r
+#define DOC (*(volatile struct st_doc *)0x8B080)\r
+#define DTC (*(volatile struct st_dtc *)0x82400)\r
+#define ELC (*(volatile struct st_elc *)0x8B100)\r
+#define FLASH (*(volatile struct st_flash *)0x7FC090)\r
+#define ICU (*(volatile struct st_icu *)0x87000)\r
+#define IWDT (*(volatile struct st_iwdt *)0x88030)\r
+#define MPC (*(volatile struct st_mpc *)0x8C11F)\r
+#define MTU (*(volatile struct st_mtu *)0x8860A)\r
+#define MTU0 (*(volatile struct st_mtu0 *)0x88690)\r
+#define MTU1 (*(volatile struct st_mtu1 *)0x88690)\r
+#define MTU2 (*(volatile struct st_mtu2 *)0x88692)\r
+#define MTU3 (*(volatile struct st_mtu3 *)0x88600)\r
+#define MTU4 (*(volatile struct st_mtu4 *)0x88600)\r
+#define MTU5 (*(volatile struct st_mtu5 *)0x88694)\r
+#define POE (*(volatile struct st_poe *)0x88900)\r
+#define PORT (*(volatile struct st_port *)0x8C120)\r
+#define PORT0 (*(volatile struct st_port0 *)0x8C000)\r
+#define PORT1 (*(volatile struct st_port1 *)0x8C001)\r
+#define PORT2 (*(volatile struct st_port2 *)0x8C002)\r
+#define PORT3 (*(volatile struct st_port3 *)0x8C003)\r
+#define PORT4 (*(volatile struct st_port4 *)0x8C004)\r
+#define PORT5 (*(volatile struct st_port5 *)0x8C005)\r
+#define PORTA (*(volatile struct st_porta *)0x8C00A)\r
+#define PORTB (*(volatile struct st_portb *)0x8C00B)\r
+#define PORTC (*(volatile struct st_portc *)0x8C00C)\r
+#define PORTE (*(volatile struct st_porte *)0x8C00E)\r
+#define RIIC0 (*(volatile struct st_riic *)0x88300)\r
+#define RSPI0 (*(volatile struct st_rspi *)0x88380)\r
+#define RTC (*(volatile struct st_rtc *)0x8C400)\r
+#define RTCB (*(volatile struct st_rtcb *)0x8C402)\r
+#define S12AD (*(volatile struct st_s12ad *)0x89000)\r
+#define SCI1 (*(volatile struct st_sci1 *)0x8A020)\r
+#define SCI5 (*(volatile struct st_sci1 *)0x8A0A0)\r
+#define SCI12 (*(volatile struct st_sci12 *)0x8B300)\r
+#define SMCI1 (*(volatile struct st_smci *)0x8A020)\r
+#define SMCI5 (*(volatile struct st_smci *)0x8A0A0)\r
+#define SMCI12 (*(volatile struct st_smci *)0x8B300)\r
+#define SYSTEM (*(volatile struct st_system *)0x80000)\r
+#define USB0 (*(volatile struct st_usb *)0xA0000)\r
+#endif\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : mcu_info.h\r
+* Device(s) : RX111\r
+* Description : Information about the MCU on this board (RSKRX111).\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+#ifndef _MCU_INFO\r
+#define _MCU_INFO\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Gets MCU configuration information. */\r
+#include "r_bsp_config.h"\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* MCU Series. */\r
+#if MCU_PART_SERIES == 0x0\r
+ #define MCU_SERIES_RX100 (1)\r
+#else\r
+ #error "ERROR - MCU_PART_SERIES - Unknown MCU Series chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* MCU Group name. */\r
+#if MCU_PART_GROUP == 0x1\r
+ #define MCU_RX111 (1)\r
+ #define MCU_RX11x (1)\r
+#else\r
+ #error "ERROR - MCU_PART_GROUP - Unknown MCU Group chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* Package. */\r
+#if MCU_PART_PACKAGE == 0x0\r
+ #define PACKAGE_LFQFP64 (1)\r
+#elif MCU_PART_PACKAGE == 0x1\r
+ #define PACKAGE_LQFP64 (1)\r
+#elif MCU_PART_PACKAGE == 0x2\r
+ #define PACKAGE_TFLGA64 (1)\r
+#elif MCU_PART_PACKAGE == 0x3\r
+ #define PACKAGE_LFQFP48 (1)\r
+#elif MCU_PART_PACKAGE == 0x4\r
+ #define PACKAGE_VQFN48 (1)\r
+#elif MCU_PART_PACKAGE == 0x5\r
+ #define PACKAGE_HWQFN36 (1)\r
+#elif MCU_PART_PACKAGE == 0x6\r
+ #define PACKAGE_WFLGA36 (1)\r
+#elif MCU_PART_PACKAGE == 0x7\r
+ #define PACKAGE_SSOP36 (1)\r
+#else\r
+ #error "ERROR - MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* Memory size of your MCU. */\r
+#if MCU_PART_MEMORY_SIZE == 0x0 // "J" parts\r
+ #define ROM_SIZE_BYTES (16384)\r
+ #define RAM_SIZE_BYTES (8192)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x1\r
+ #define ROM_SIZE_BYTES (32768)\r
+ #define RAM_SIZE_BYTES (10240)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x3\r
+ #define ROM_SIZE_BYTES (65536)\r
+ #define RAM_SIZE_BYTES (10240)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x4\r
+ #define ROM_SIZE_BYTES (98304)\r
+ #define RAM_SIZE_BYTES (16384)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x5\r
+ #define ROM_SIZE_BYTES (131072)\r
+ #define RAM_SIZE_BYTES (16384)\r
+ #define DF_SIZE_BYTES (8192)\r
+#else\r
+ #error "ERROR - MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* System clock speed in Hz. */\r
+#define ICLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV)\r
+/* Peripheral Module Clock B speed in Hz. */\r
+#define PCLKB_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV)\r
+/* Peripheral Module Clock D speed in Hz. */\r
+#define PCLKD_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV)\r
+/* FlashIF clock speed in Hz. */\r
+#define FCLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV)\r
+\r
+#endif /* _MCU_INFO */\r
+\r
--- /dev/null
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : typedefine.h */
+/* DESCRIPTION : Aliases of Integer Type */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/ \r
+ \r
+ \r
+ \r
+ \r
+typedef signed char _SBYTE;\r
+typedef unsigned char _UBYTE;\r
+typedef signed short _SWORD;\r
+typedef unsigned short _UWORD;\r
+typedef signed int _SINT;\r
+typedef unsigned int _UINT;\r
+typedef signed long _SDWORD;\r
+typedef unsigned long _UDWORD;\r
+typedef signed long long _SQWORD;\r
+typedef unsigned long long _UQWORD;\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : platform.h\r
+* Description : The user chooses which MCU and board they are developing for in this file. If the board you are using\r
+* is not listed below, please add your own or use the default 'User Board'.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 30.11.2011 1.00 First Release\r
+* : 13.01.2012 1.10 Moved from having platform defined using macro defintion, to having platform defined\r
+* by choosing an include path. This makes this file simpler and cleans up the issue\r
+* where HEW shows all header files for all platforms under 'Dependencies'.\r
+* : 14.02.2012 1.20 Added RX210 BSP.\r
+* : 18.04.2012 1.30 Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding\r
+* locking.c and locking.h in board folders. Also, r_bsp can now be configured through\r
+* r_bsp_config.h.\r
+* : 26.06.2012 1.40 Added new options such as exception callbacks and the ability to choose your MCU using\r
+* its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort\r
+* to remove any extra files that the user would need to touch. Removed the flash_options.c\r
+* file and put its contents in vecttbl.c.\r
+* : 17.07.2012 1.50 Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT \r
+* macro options in r_bsp_config.h. Added some extra code to handle exceptions in\r
+* vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks.\r
+* : 08.11.2012 1.60 Added RX111 BSP\r
+***********************************************************************************************************************/\r
+\r
+#ifndef _PLATFORM_H_\r
+#define _PLATFORM_H_\r
+\r
+/***********************************************************************************************************************\r
+DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING.\r
+***********************************************************************************************************************/\r
+/* RSKRX610 */\r
+//#include "./board/rskrx610/r_bsp.h"\r
+\r
+/* RSKRX62N */\r
+//#include "./board/rskrx62n/r_bsp.h"\r
+\r
+/* RSKRX62T */\r
+//#include "./board/rskrx62t/r_bsp.h"\r
+\r
+/* RDKRX62N */\r
+//#include "./board/rdkrx62n/r_bsp.h"\r
+\r
+/* RSKRX630 */\r
+//#include "./board/rskrx630/r_bsp.h"\r
+\r
+/* RSKRX63N */\r
+//#include "./board/rskrx63n/r_bsp.h"\r
+\r
+/* RDKRX63N */\r
+//#include "./board/rdkrx63n/r_bsp.h"\r
+\r
+/* RSKRX210 */\r
+//#include "./board/rskrx210/r_bsp.h"\r
+\r
+/* RSKRX111 */\r
+#include "./board/rskrx111/r_bsp.h"\r
+\r
+/* User Board - Define your own board here. */\r
+//#include "./board/user/r_bsp.h"\r
+\r
+/***********************************************************************************************************************\r
+MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT\r
+***********************************************************************************************************************/\r
+#ifndef PLATFORM_DEFINED\r
+#error "Error - No platform defined in platform.h!"\r
+#endif\r
+\r
+#endif /* _PLATFORM_H_ */\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp_config_reference.c\r
+* Device(s) : RX111\r
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included\r
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)\r
+* is just a reference file that the user can use to make their own r_bsp_config.h file.\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 07.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE\r
+#define R_BSP_CONFIG_REF_HEADER_FILE\r
+\r
+/***********************************************************************************************************************\r
+Configuration Options\r
+***********************************************************************************************************************/\r
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such\r
+ as package and memory size.\r
+ To help parse this information, the part number will be defined using multiple macros.\r
+ R 5 F 51 11 5 A D FM\r
+ | | | | | | | | | Macro Name Description\r
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch\r
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)\r
+ | | | | | | |______not used = Blank\r
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity\r
+ | | | | |___________MCU_PART_GROUP = Group name\r
+ | | | |______________MCU_PART_SERIES = Series name\r
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)\r
+ | |__________________not used = Renesas MCU\r
+ |____________________not used = Renesas semiconductor product.\r
+ */\r
+\r
+/* Package type. Set the macro definition based on values below:\r
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch\r
+ FM = 0x0 = LFQFP/64/0.50\r
+ FK = 0x1 = LQFP/64/0.80\r
+ LF = 0x2 = TFLGA/64/0.50\r
+ FL = 0x3 = LFQFP/48/0.50\r
+ NE = 0x4 = VQFN/48/0.50\r
+ NC = 0x5 = HWQFN/36/0.50\r
+ LM = 0x6 = WFLGA/36/0.50\r
+ SB = 0x7 = SSOP/36/0.80\r
+*/\r
+#define MCU_PART_PACKAGE (0x0)\r
+\r
+/* ROM, RAM, and Data Flash Capacity.\r
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size\r
+ 5 = 0x5 = 128KB/16KB/8KB\r
+ 4 = 0x4 = 96KB/16KB/8KB\r
+ 3 = 0x3 = 64KB/10KB/8KB\r
+ 1 = 0x1 = 32KB/10KB/8KB\r
+ J = 0x0 = 16KB/8KB/8KB\r
+*/\r
+#define MCU_PART_MEMORY_SIZE (0x5)\r
+\r
+/* Group name.\r
+ Character(s) = Value for macro = Description\r
+ 10 = 0x0 = RX110 Group\r
+ 11 = 0x1 = RX111 Group\r
+*/\r
+#define MCU_PART_GROUP (0x1)\r
+\r
+/* Series name.\r
+ Character(s) = Value for macro = Description\r
+ 51 = 0x0 = RX100 Series\r
+*/\r
+#define MCU_PART_SERIES (0x0)\r
+\r
+/* Memory type.\r
+ Character(s) = Value for macro = Description\r
+ F = 0x0 = Flash memory version\r
+*/\r
+#define MCU_PART_MEMORY_TYPE (0x0)\r
+\r
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a\r
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */\r
+#if defined(BSP_DECLARE_STACK)\r
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize su=0x400\r
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize si=0x100\r
+#endif\r
+\r
+/* Heap size in bytes. */\r
+#define HEAP_BYTES (0x001)\r
+\r
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information\r
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.\r
+ 0 = Stay in Supervisor mode.\r
+ 1 = Switch to User mode.\r
+*/\r
+#define RUN_IN_USER_MODE (0)\r
+\r
+\r
+/* This macro lets other modules no if a RTOS is being used.\r
+ 0 = RTOS is not used.\r
+ 1 = RTOS is used.\r
+*/\r
+#define RTOS_USED (0)\r
+\r
+/* Clock source select (CKSEL).\r
+ 0 = Low Speed On-Chip Oscillator (LOCO)\r
+ 1 = High Speed On-Chip Oscillator (HOCO)\r
+ 2 = Main Clock Oscillator\r
+ 3 = Sub-Clock Oscillator\r
+ 4 = PLL Circuit\r
+*/\r
+#define CLOCK_SOURCE (4) // GI org 4\r
+\r
+/* Clock configuration options.\r
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The\r
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the\r
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the\r
+ settings would be:\r
+\r
+ XTAL_HZ = 16000000\r
+ PLL_DIV = 2\r
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)\r
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz\r
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz\r
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz\r
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz\r
+*/\r
+/* XTAL - Input clock frequency in Hz */\r
+#define XTAL_HZ (16000000)\r
+/* PLL Input Frequency Divider Select (PLIDIV).\r
+ Available divisors = /1 (no division), /2, /4\r
+*/\r
+#define PLL_DIV (2) // GI org 2\r
+/* PLL Frequency Multiplication Factor Select (STC).\r
+ Available multipliers = x6, x8\r
+*/\r
+#define PLL_MUL (6) // GI org 6\r
+/* System Clock Divider (ICK).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define ICK_DIV (2) // NOTE: ICLK CANNOT BE SLOWER THAN PCLK!\r
+/* Peripheral Module Clock B Divider (PCKB).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKB_DIV (2) // GI org 2\r
+/* Peripheral Module Clock D Divider (PCKD).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKD_DIV (2)\r
+/* Flash IF Clock Divider (FCK).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define FCK_DIV (2)\r
+\r
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and\r
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a\r
+ function to be called when the event occurs. For example, if the user wanted the function\r
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would\r
+ do the following:\r
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+ If the user does not wish to be alerted of these events then they should comment out the macros.\r
+\r
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function\r
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it\r
+ is executing. For this reason, it is recommended to keep these callback functions short as to not\r
+ decrease the real-time response of your system.\r
+*/\r
+/* Callback for Supervisor Instruction Violation Exception. */\r
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb\r
+\r
+/* Callback for Undefined Instruction Exception. */\r
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb\r
+\r
+/* Callback for Non-maskable Interrupt. */\r
+//#define NMI_ISR_CALLBACK nmi_cb\r
+\r
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source\r
+ is creating unwanted interrupts. */\r
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+\r
+/* Callback for Bus Error Interrupt. */\r
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb\r
+\r
+/* The user has the option of separately choosing little or big endian for the User Application Area */\r
+\r
+/* Endian mode for User Application.\r
+ 0 = Big Endian\r
+ Else = Little Endian (Default)\r
+*/\r
+#define USER_APP_ENDIAN (1)\r
+\r
+\r
+/* Configure WDT and IWDT settings.\r
+ OFS0 - Option Function Select Register 0\r
+ OFS0 - Option Function Select Register 0\r
+ b31:b15 Reserved (set to 1)\r
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)\r
+ b13 Reserved (set to 1)\r
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)\r
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)\r
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)\r
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)\r
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)\r
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)\r
+ b0 Reserved (set to 1) */\r
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.\r
+ OFS1 - Option Function Select Register 1\r
+ b31:b9 Reserved (set to 1)\r
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)\r
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select\r
+ 0 1 0 0: 3.10 V\r
+ 0 1 0 1: 3.00 V\r
+ 0 1 1 0: 2.90 V\r
+ 0 1 1 1: 2.79 V\r
+ 1 0 0 0: 2.68 V\r
+ 1 0 0 1: 2.58 V\r
+ 1 0 1 0: 2.48 V\r
+ 1 0 1 1: 2.06 V\r
+ 1 1 0 0: 1.96 V\r
+ 1 1 0 1: 1.86 V\r
+ b3:b2 Reserved (set to 1)\r
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)\r
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */\r
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Initializes C input & output library functions.\r
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.\r
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */\r
+#define IO_LIB_ENABLE (0)\r
+\r
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */\r
+\r
+\r
+\r
--- /dev/null
+r_bsp Package\r
+=============\r
+\r
+Document Number\r
+---------------\r
+N/A\r
+\r
+Version\r
+-------\r
+v1.60\r
+\r
+Overview\r
+--------\r
+The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU\r
+information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder has iodefine\r
+files and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board\r
+and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help \r
+configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each \r
+supported board. Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which \r
+board they are using by uncommenting the include path that applies to their board. For example, if you are using the \r
+RSK+RX62N then you would uncomment the #include "./board/rskrx62n/r_bsp.h" include path. Users are encouraged to add \r
+their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a \r
+reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it \r
+to r_bsp_config.h, and use the options inside the file to configure the BSP for their project.\r
+\r
+Features\r
+--------\r
+* Provides foundation to build code on top of.\r
+* Provides MCU startup code.\r
+* Provides SFR access through iodefine.h\r
+* Stores details of MCU in 'mcu_info.h' to help configure Renesas middleware.\r
+* Easily configure BSP through r_bsp_config.h.\r
+* Choose MCU easily by inputting part number details in r_bsp_config.h.\r
+* Provides callbacks for MCU exceptions and the bus error interrupt.\r
+ \r
+Limitations\r
+-----------\r
+N/A\r
+\r
+Peripherals Used Directly\r
+-------------------------\r
+N/A\r
+\r
+Required Packages\r
+-----------------\r
+* r_glyph [required if you want to use LCD for RDK boards]\r
+* r_rspi_rx [required if you want to use LCD for RDK boards]\r
+\r
+How to add to your project\r
+--------------------------\r
+* Copy the r_bsp folder to your project.\r
+* Add an include path to the 'r_bsp' directory. \r
+* Add all of the source files for your board from the 'r_bsp\board\--YOUR_BOARD--' directory to your project. \r
+* Uncomment the include path for your board in 'platform.h' which is located in the 'r_bsp' directory.\r
+* Copy the file r_bsp_config_reference.h from the 'r_bsp\board\--YOUR_BOARD--' directory and copy it to your project's\r
+ source code directory. Rename the file r_bsp_config.h.\r
+* Open r_bsp_config.h and use the macros to configure the BSP for your project.\r
+\r
+File Structure\r
+--------------\r
+r_bsp\r
+| platform.h (choose which board is being used)\r
+| readme.txt\r
+|\r
++---board (contains supported boards)\r
+| +---rdkrx62n (contains BSP source and header files)\r
+| |\r
+| +---rdkrx63n\r
+| |\r
+| +---rskrx111\r
+| |\r
+| +---rskrx210\r
+| |\r
+| +---rskrx610\r
+| |\r
+| +---rskrx62n\r
+| |\r
+| +---rskrx62t\r
+| |\r
+| +---rskrx630\r
+| |\r
+| +---rskrx63n\r
+| |\r
+| \---user\r
+|\r
+\---mcu\r
+ +---rx111 (contains common files to this MCU group, e.g. iodefine.h)\r
+ |\r
+ +---rx210 \r
+ |\r
+ +---rx610\r
+ |\r
+ +---rx62n\r
+ |\r
+ +---rx62t\r
+ |\r
+ +---rx630\r
+ |\r
+ \---rx63n\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_switches_config.c\r
+* Description : Configures the switches code\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 17.01.2012 1.00 First Release\r
+* : 17.02.2012 1.10 Added RSKRX210 support.\r
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).\r
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.\r
+***********************************************************************************************************************/\r
+#ifndef SWITCHES_CONFIG_HEADER_FILE\r
+#define SWITCHES_CONFIG_HEADER_FILE\r
+\r
+/***********************************************************************************************************************\r
+Configuration Options\r
+***********************************************************************************************************************/\r
+/* This macro sets whether interrupts or polling is used for detecting switch presses. The benefit of using interrupts\r
+ is that no extra processing is used for polling and the use of a system timer tick is not a requirement. The downside\r
+ of using interrupts is that callback functions are called from within an interrupt so if your ISR is long then it can\r
+ degrade the real-time response of your system. The benefit of polling is that functions are called at the application\r
+ level and debouncing is supported. The downside to polling is that your system must call the R_SWITCHES_Update() on a\r
+ regular basis which requires extra processing.\r
+\r
+ 0 = Use interrupts\r
+ 1 = Use polling\r
+ */\r
+#define SWITCHES_DETECTION_MODE (0)\r
+\r
+#endif /* SWITCHES_CONFIG_HEADER_FILE */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_switches_if.h\r
+* Description : Functions for using switches with callback functions.\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 17.01.2012 1.00 First Release\r
+* : 17.02.2012 1.10 Added RSKRX210 support.\r
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).\r
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.\r
+***********************************************************************************************************************/\r
+\r
+#ifndef SWITCHES_API_HEADER_FILE\r
+#define SWITCHES_API_HEADER_FILE\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Fixed width integer support. */\r
+#include <stdint.h>\r
+/* Used for configuring the code */\r
+#include "r_switches_config.h"\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* Version Number of API. */\r
+#define SWITCHES_VERSION_MAJOR (1)\r
+#define SWITCHES_VERSION_MINOR (0)\r
+/* The process of getting the version number is done through the macro below. The version number is encoded where the\r
+ top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example,\r
+ Version 4.25 would be returned as 0x00040019. */\r
+#define R_SWITCHES_GetVersion() ((((uint32_t)SWITCHES_VERSION_MAJOR) << 16) | (uint32_t)SWITCHES_VERSION_MINOR)\r
+\r
+/***********************************************************************************************************************\r
+Public Functions\r
+***********************************************************************************************************************/\r
+void R_SWITCHES_Init(void);\r
+void R_SWITCHES_Update(void);\r
+\r
+/* Callback prototypes. */\r
+#if defined(SW1_CALLBACK_FUNCTION)\r
+void SW1_CALLBACK_FUNCTION(void);\r
+#endif\r
+\r
+#if defined(SW2_CALLBACK_FUNCTION)\r
+void SW2_CALLBACK_FUNCTION(void);\r
+#endif\r
+\r
+#if defined(SW3_CALLBACK_FUNCTION)\r
+void SW3_CALLBACK_FUNCTION(void);\r
+#endif\r
+\r
+#endif /* SWITCHES_API_HEADER_FILE */\r
+\r
--- /dev/null
+PLEASE REFER TO THE APPLICATION NOTE FOR THIS MIDDLEWARE FOR MORE INFORMATION\r
+\r
+Switches\r
+========\r
+\r
+Document Number \r
+---------------\r
+N/A\r
+\r
+Version\r
+-------\r
+v1.40\r
+\r
+Overview\r
+--------\r
+Configures port pins for switches and calls user defined function on switch press. Switch presses can be detected using \r
+IRQ interrupts or by polling. The benefit of using interrupts is that no extra processing is used for polling and the \r
+use of a system timer tick is not a requirement. The downside of using interrupts is that callback functions are called \r
+from within an interrupt so if your ISR is long then it can degrade the real-time response of your system. The benefit \r
+of polling is that functions are called at the application level and debouncing is supported. The downside to polling is \r
+that your system must call the R_SWITCHES_Update() on a regular basis which requires extra processing.\r
+\r
+Features\r
+--------\r
+* Call one function to setup switches.\r
+* Define function to call when switch is pressed.\r
+* Can be configured to be interrupt or poll driven.\r
+\r
+Supported MCUs\r
+--------------\r
+* RX610 Group\r
+* RX621, RX62N Group\r
+* RX62T Group\r
+* RX630 Group\r
+* RX631, RX63N Group\r
+* RX210 Group\r
+* RX111 Group\r
+\r
+Boards Tested On\r
+----------------\r
+* RSKRX610\r
+* RSK+RX62N\r
+* RSKRX62T\r
+* RDKRX62N\r
+* RSKRX630\r
+* RSKRX63N\r
+* RDKRX63N\r
+* RSKRX111\r
+\r
+Limitations\r
+-----------\r
+* None\r
+\r
+Peripherals Used Directly\r
+-------------------------\r
+* None\r
+\r
+Required Packages\r
+-----------------\r
+* None\r
+\r
+How to add to your project\r
+--------------------------\r
+* Add src\r_switches.c to your project.\r
+* Add an include path to the 'r_switches' directory. \r
+* Add an include path to the 'r_switches\src' directory.\r
+* Configure middleware through r_switches_config.h.\r
+* Add a #include for r_switches_if.h to files that need to use this package. \r
+\r
+Toolchain(s) Used\r
+-----------------\r
+* Renesas RX v1.02\r
+\r
+File Structure\r
+--------------\r
+r_switches\r
+| readme.txt\r
+| r_switches_config.h\r
+| r_switches_if.h\r
+|\r
+\---src\r
+ r_switches.c\r
+ \r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_switches.c\r
+* Description : Functions for using switches with callback functions.\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 17.01.2012 1.00 First Release\r
+* : 17.02.2012 1.10 Added RSKRX210 support.\r
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).\r
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.\r
+* : 07.11.2012 1.40 Added support for RSKRX111\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Board and MCU support. */\r
+#include "platform.h"\r
+/* Switches prototypes. */\r
+#include "r_switches_if.h"\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+typedef int bool;\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* This helps reduce the amount of unique code for each supported board. */\r
+#define X_IRQ( x ) XX_IRQ( x )\r
+#define XX_IRQ( x ) _ICU_IRQ##x\r
+\r
+/* These macros define which IRQ pins are used for the switches. Note that these defintions cannot have parentheses\r
+ around them. */\r
+#if defined(PLATFORM_BOARD_RSKRX111)\r
+ #define SW1_IRQ_NUMBER 0\r
+ #define SW2_IRQ_NUMBER 1\r
+ #define SW3_IRQ_NUMBER 4\r
+#else\r
+ #error This file is only for use on the RX100 RSK\r
+#endif\r
+\r
+/* Number of switches on this board. */\r
+#define SWITCHES_NUM (3)\r
+\r
+/* Register definitions not yet correct in iorx111.h. */\r
+#define MPC_P30PFS_REG ( * ( unsigned char * ) 0x0008C158 )\r
+#define MPC_P31PFS_REG ( * ( unsigned char * ) 0x0008C159 )\r
+#define MPC_PE4PFS_REG ( * ( unsigned char * ) 0x0008C1B4 )\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+typedef struct\r
+{\r
+ bool active;\r
+ int32_t debounce_cnt;\r
+} switch_t;\r
+\r
+/***********************************************************************************************************************\r
+Private global variables and functions\r
+***********************************************************************************************************************/\r
+#if SWITCHES_DETECTION_MODE == 1\r
+/* Update Hz */\r
+static uint32_t g_sw_debounce_cnts;\r
+/* Used for debounce. */\r
+switch_t g_switches[SWITCHES_NUM];\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_SWITCHES_Init\r
+* Description : Initializes pins to be input and interrupt on switch presses.\r
+* Arguments :\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+\r
+void R_SWITCHES_Init (void)\r
+{\r
+ /* Unlock protection register */\r
+ MPC.PWPR.BYTE &= 0x7F;\r
+ /* Unlock MPC registers */\r
+ MPC.PWPR.BYTE |= 0x40;\r
+\r
+ /* Make switch pins inputs. */\r
+ PORT3.PDR.BYTE &= 0xFC;\r
+ PORTE.PDR.BYTE &= 0xEF;\r
+\r
+ /* Set port mode registers for switches. */\r
+ PORT3.PMR.BYTE &= 0xFC;\r
+ PORTE.PMR.BYTE &= 0xEF;\r
+\r
+ MPC_P30PFS_REG = 0x40; /* P30 is used as IRQ pin */\r
+ MPC_P31PFS_REG = 0x40; /* P31 is used as IRQ pin */\r
+ MPC_PE4PFS_REG = 0x40; /* PE4 is used as IRQ pin */\r
+\r
+ /* Set IRQ type (falling edge) */\r
+ ICU.IRQCR[ SW1_IRQ_NUMBER ].BYTE = 0x04;\r
+ ICU.IRQCR[ SW2_IRQ_NUMBER ].BYTE = 0x04;\r
+ ICU.IRQCR[ SW3_IRQ_NUMBER ].BYTE = 0x04;\r
+\r
+ /* Set interrupt priorities, which must be below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ _IPR( X_IRQ(SW1_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;\r
+ _IPR( X_IRQ(SW2_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;\r
+ _IPR( X_IRQ(SW3_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;\r
+\r
+ /* Clear any pending interrupts */\r
+ _IR( X_IRQ(SW1_IRQ_NUMBER) ) = 0;\r
+ _IR( X_IRQ(SW2_IRQ_NUMBER) ) = 0;\r
+ _IR( X_IRQ(SW3_IRQ_NUMBER) ) = 0;\r
+\r
+ /* Enable the interrupts */\r
+ _IEN( X_IRQ(SW1_IRQ_NUMBER) ) = 1;\r
+ _IEN( X_IRQ(SW2_IRQ_NUMBER) ) = 1;\r
+ _IEN( X_IRQ(SW3_IRQ_NUMBER) ) = 1;\r
+}\r
+\r
+/* If using polling then the user must call the update function. */\r
+\r
+/***********************************************************************************************************************\r
+* Function name: R_SWITCHES_Update\r
+* Description : Polls switches and calls callback functions as needed. If you are using IRQ mode then this function\r
+* is not needed and can be removed if desired. It is left in so that code will not fail when switching\r
+* between polling or IRQ mode.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void R_SWITCHES_Update (void)\r
+{\r
+#if SWITCHES_DETECTION_MODE == 1\r
+ /* This code is only needed for polling mode. */\r
+ /* Check switch 1. */\r
+ if (SW1 == SW_ACTIVE)\r
+ {\r
+ if (g_switches[0].active != true)\r
+ {\r
+ if (++g_switches[0].debounce_cnt >= g_sw_debounce_cnts)\r
+ {\r
+ /* Set this to true so we only call the callback function once per press. */\r
+ g_switches[0].active = true;\r
+\r
+ /* Call callback function. */\r
+ SW1_CALLBACK_FUNCTION();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (0 == g_switches[0].debounce_cnt)\r
+ {\r
+ g_switches[0].active = false;\r
+ }\r
+ else\r
+ {\r
+ g_switches[0].debounce_cnt--;\r
+ }\r
+ }\r
+\r
+ /* Check switch 2. */\r
+ if (SW2 == SW_ACTIVE)\r
+ {\r
+ if (g_switches[1].active != true)\r
+ {\r
+ if (++g_switches[1].debounce_cnt >= g_sw_debounce_cnts)\r
+ {\r
+ /* Set this to true so we only call the callback function once per press. */\r
+ g_switches[1].active = true;\r
+\r
+ /* Call callback function. */\r
+ SW2_CALLBACK_FUNCTION();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (0 == g_switches[1].debounce_cnt)\r
+ {\r
+ g_switches[1].active = false;\r
+ }\r
+ else\r
+ {\r
+ g_switches[1].debounce_cnt--;\r
+ }\r
+ }\r
+\r
+ /* Check switch 3. */\r
+ if (SW3 == SW_ACTIVE)\r
+ {\r
+ if (g_switches[2].active != true)\r
+ {\r
+ if (++g_switches[2].debounce_cnt >= g_sw_debounce_cnts)\r
+ {\r
+ /* Set this to true so we only call the callback function once per press. */\r
+ g_switches[2].active = true;\r
+\r
+ /* Call callback function. */\r
+ SW3_CALLBACK_FUNCTION();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (0 == g_switches[2].debounce_cnt)\r
+ {\r
+ g_switches[2].active = false;\r
+ }\r
+ else\r
+ {\r
+ g_switches[2].debounce_cnt--;\r
+ }\r
+ }\r
+#endif /* SWITCHES_DETECTION_MODE */\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A low power project that\r
+ * demonstrates the FreeRTOS tickless mode, and a more comprehensive test and\r
+ * demo application. The configCREATE_LOW_POWER_DEMO setting (defined at the\r
+ * top of FreeRTOSConfig.h) is used to select between the two. The low power\r
+ * demo is implemented and described in main_low_power.c. The more\r
+ * comprehensive test and demo application is implemented and described in\r
+ * main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Platform includes. */\r
+#include "lcd.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Prepare the board of the demo.\r
+ */\r
+extern void vHardwareSetup( void );\r
+\r
+/*\r
+ * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1.\r
+ * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0.\r
+ */\r
+extern void main_low_power( void );\r
+extern void main_full( void );\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the documentation page for this demo on the FreeRTOS.org web site for\r
+full information - including hardware setup requirements. */\r
+\r
+void main( void )\r
+{\r
+ /* Call the Renesas provided setup. */\r
+ vHardwareSetup();\r
+ lcd_initialize();\r
+ lcd_display( LCD_LINE1, "FreeRTOS" );\r
+\r
+ /* The configCREATE_LOW_POWER_DEMO setting is described in FreeRTOSConfig.h. */\r
+ #if configCREATE_LOW_POWER_DEMO == 1\r
+ {\r
+ lcd_display( LCD_LINE2, "LP Demo" );\r
+ main_low_power();\r
+ }\r
+ #else\r
+ {\r
+ lcd_display( LCD_LINE2, "Ful Demo" );\r
+ main_full();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the size\r
+ of the heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE\r
+ in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is\r
+ called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if\r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAssertCalled( void )\r
+{\r
+volatile unsigned long ul = 0;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Set ul to a non-zero value using the debugger to step out of this\r
+ function. */\r
+ while( ul == 0 )\r
+ {\r
+ __asm volatile( "NOP" );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/* ****************************************************************************\r
+ * This project includes a lot of tasks and tests and is therefore complex.\r
+ * If you would prefer a much simpler project to get started with then select\r
+ * the 'low power' demo by setting configCREATE_LOW_POWER_DEMO to 1 in\r
+ * FreeRTOSConfig.h. When configCREATE_LOW_POWER_DEMO is set to 1 main() will\r
+ * call main_low_power() instead of main_full().\r
+ * ****************************************************************************\r
+ *\r
+ * Creates all the demo application tasks, then starts the scheduler. The web\r
+ * documentation provides more details of the standard demo application tasks,\r
+ * which provide no particular functionality but do provide a good example of\r
+ * how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then\r
+ * repeatedly check that each register still contains its expected value for\r
+ * the lifetime of the tasks. Each task uses different values. The tasks run\r
+ * with very low priority so get preempted very frequently. A check variable\r
+ * is incremented on each iteration of the test loop. A register containing an\r
+ * unexpected value is indicative of an error in the context switching\r
+ * mechanism and will result in a branch to a null loop - which in turn will\r
+ * prevent the check variable from incrementing any further and allow the check\r
+ * timer (described below) to determine that an error has occurred. The nature\r
+ * of the reg test tasks necessitates that they are written in assembly code.\r
+ *\r
+ * "Check Timer" and Callback Function - The check timer period is initially\r
+ * set to three seconds. The check timer callback function checks that all the\r
+ * standard demo tasks are not only still executing, but are executing without\r
+ * reporting any errors. If the check timer discovers that a task has either\r
+ * stalled, or reported an error, then it changes its own period from the\r
+ * initial three seconds, to just 200ms. The check timer callback function\r
+ * also toggles LED 0 each time it is called. This provides a visual\r
+ * indication of the system status: If the LED toggles every three seconds,\r
+ * then no issues have been discovered. If the LED toggles every 200ms, then\r
+ * an issue has been discovered with at least one task.\r
+ *\r
+ * *NOTE 1* The CPU must be in Supervisor mode when the scheduler is started.\r
+ * The PowerON_Reset_PC() supplied in resetprg.c with this demo has\r
+ * Change_PSW_PM_to_UserMode() commented out to ensure this is the case.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Hardware specific includes. */\r
+#include "iorx111.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+#include "death.h"\r
+#include "blocktim.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+\r
+\r
+/* Variables that are incremented on each iteration of the reg test tasks are\r
+declared outside of the #if configCREATE_LOW_POWER_DEMO conditional compilation\r
+to prevent linker issues when configCREATE_LOW_POWER_DEMO is set to 1. The\r
+check timer inspects these variables to ensure they are still incrementing as\r
+expected. If a variable stops incrementing then it is likely that its associate\r
+task has stalled. */\r
+unsigned long volatile ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;\r
+\r
+\r
+/* The code in this file is only built when configCREATE_LOW_POWER_DEMO is set\r
+to 0, otherwise the code in main_low_power.c is used. */\r
+#if configCREATE_LOW_POWER_DEMO == 0\r
+\r
+\r
+/* Values that are passed into the reg test tasks using the task parameter.\r
+The tasks check that the values are passed in correctly. */\r
+#define mainREG_TEST_1_PARAMETER ( 0x12121212UL )\r
+#define mainREG_TEST_2_PARAMETER ( 0x12345678UL )\r
+\r
+/* Priorities at which the standard demo tasks are created. */\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+\r
+/* The LED toggled by the check timer. */\r
+#define mainCHECK_LED ( 0 )\r
+\r
+/* The period at which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/* A block time of zero simple means "Don't Block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/*\r
+ * The reg test tasks as described at the top of this file.\r
+ */\r
+static void prvRegTest1Task( void *pvParameters );\r
+static void prvRegTest2Task( void *pvParameters );\r
+\r
+/*\r
+ * The actual implementation of the reg test functionality, which, because of\r
+ * the direct register access, have to be in assembly.\r
+ */\r
+void vRegTest1Implementation( void );\r
+void vRegTest2Implementation( void );\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The check timer. This uses prvCheckTimerCallback() as its callback\r
+function. */\r
+static xTimerHandle xCheckTimer = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* Start the reg test tasks which test the context switching mechanism. */\r
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the standard demo tasks. */\r
+ vCreateBlockTimeTasks();\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ );\r
+\r
+ configASSERT( xCheckTimer );\r
+\r
+ /* Start the check timer. It will actually start when the scheduler is\r
+ started. */\r
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+\r
+ /* Start the tasks running. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well execution will never reach here as the scheduler will be\r
+ running. If this null loop is reached then it is likely there was\r
+ insufficient FreeRTOS heap available for the idle task and/or timer task to\r
+ be created. See http://www.freertos.org/a00111.html. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE, lErrorStatus = pdPASS;\r
+static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL;\r
+\r
+ /* Remove compiler warnings about unused parameters. */\r
+ ( void ) xTimer;\r
+\r
+ /* Check the standard demo tasks are running without error. */\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+\r
+ /* Check the reg test tasks are still cycling. They will stop incrementing\r
+ their loop counters if they encounter an error. */\r
+ if( ulRegTest1CycleCount == ulLastRegTest1CycleCount )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+\r
+ if( ulRegTest2CycleCount == ulLastRegTest2CycleCount )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+\r
+ /* Remember the loop counter values this time around so they can be checked\r
+ again the next time this callback function executes. */\r
+ ulLastRegTest1CycleCount = ulRegTest1CycleCount;\r
+ ulLastRegTest2CycleCount = ulRegTest2CycleCount;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every three seconds then everything is ok. A faster toggle\r
+ indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+\r
+ /* Was an error detected this time through the callback execution? */\r
+ if( lErrorStatus != pdPASS )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+\r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ vRegTest1Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ vRegTest2Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#endif /* configCREATE_LOW_POWER_DEMO */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/* ****************************************************************************\r
+ * When configCREATE_LOW_POWER_DEMO is set to 1 in FreeRTOSConfig.h main() will\r
+ * call main_low_power(), which is defined in this file. main_low_power()\r
+ * demonstrates FreeRTOS tick suppression being used to allow the MCU to be\r
+ * placed into both the low power deep sleep mode and the low power software\r
+ * standby mode. When configCREATE_LOW_POWER_DEMO is set to 0 main will\r
+ * instead call main_full(), which is a more comprehensive RTOS demonstration.\r
+ * ****************************************************************************\r
+ *\r
+ * This application demonstrates the FreeRTOS tickless idle mode (tick\r
+ * suppression). See http://www.freertos.org/low-power-tickless-rtos.html\r
+ * The demo is configured to execute on the Renesas RX100 RSK.\r
+ *\r
+ * Functionality:\r
+ *\r
+ * + Two tasks are created, an Rx task and a Tx task.\r
+ *\r
+ * + The Rx task repeatedly blocks on a queue to wait for data. The Rx task\r
+ * toggles LED 0 each time is receives a value from the queue.\r
+ *\r
+ * + The Tx task repeatedly enters the Blocked state for an amount of time\r
+ * that is set by the position of the potentiometer. On exiting the blocked\r
+ * state the Tx task sends a value through the queue to the Rx task (causing\r
+ * the Rx task to exit the blocked state and toggle LED 0).\r
+ *\r
+ * If the value read from the potentiometer is less than or equal to\r
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks for the equivalent\r
+ * number of milliseconds. For example, if the sampled analog value is\r
+ * 2000, then the Tx task blocks for 2000ms. Blocking for a finite period\r
+ * allows the kernel to stop the tick interrupt and place the RX100 into\r
+ * deep sleep mode.\r
+ *\r
+ * If the value read form the potentiometer is greater than\r
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks on a semaphore with\r
+ * an infinite timeout. Blocking with an infinite timeout allows the kernel\r
+ * to stop the tick interrupt and place the RX100 into software standby\r
+ * mode. Pressing a button will generate an interrupt that causes the RX100\r
+ * to exit software standby mode. The interrupt service routine 'gives' the\r
+ * semaphore to unblock the Tx task.\r
+ *\r
+ *\r
+ * Using the Demo and Observed Behaviour:\r
+ *\r
+ * 1) Turn the potentiometer completely counter clockwise.\r
+ *\r
+ * 2) Program the RX100 with the application, then disconnect the programming/\r
+ * debugging hardware to ensure power readings are not effected by any\r
+ * connected interfaces.\r
+ *\r
+ * 3) Start the application running. LED 0 will toggle quickly because the\r
+ * potentiometer is turned to its lowest value. LED 1 will be illuminated\r
+ * when the RX100 is not in a power saving mode, but will appear to be off\r
+ * because most execution time is spent in a sleep mode. Led 2 will be\r
+ * illuminated when the RX100 is in deep sleep mode, and will appear to be\r
+ * always on, again because most execution time is spent in deep sleep mode.\r
+ * The LEDs are turned on and off by the application defined pre and post\r
+ * sleep macros (see the definitions of configPRE_SLEEP_PROCESSING() and\r
+ * configPOST_SLEEP_PROCESSING() in FreeRTOSConfig.h).\r
+ *\r
+ * 4) Slowly turn the potentiometer in the clockwise direction. This will\r
+ * increase the value read from the potentiometer, which will increase the\r
+ * time the Tx task spends in the Blocked state, which will therefore\r
+ * decrease the frequency at which the Tx task sends data to the queue (and\r
+ * the rate at which LED 0 is toggled).\r
+ *\r
+ * 5) Keep turning the potentiometer in the clockwise direction. Eventually\r
+ * the value read from the potentiometer will go above\r
+ * mainSOFTWARE_STANDBY_DELAY, causing the Tx task to block on the semaphore\r
+ * with an infinite timeout. LED 0 will stop toggling because the Tx task is\r
+ * no longer sending to the queue. LED 1 and LED 2 will both be off because\r
+ * the RX100 is neither running or in deep sleep mode (it is in software\r
+ * standby mode).\r
+ *\r
+ * 6) Turn the potentiometer counter clockwise again to ensure its value goes\r
+ * back below mainSOFTWARE_STANDBY_DELAY.\r
+ *\r
+ * 7) Press any of the three buttons to generate an interrupt. The interrupt\r
+ * will take the RX100 out of software standby mode, and the interrupt\r
+ * service routine will unblock the Tx task by 'giving' the semaphore. LED 0\r
+ * will then start to toggle again.\r
+ *\r
+ */\r
+\r
+\r
+/* Hardware specific includes. */\r
+#include "platform.h"\r
+#include "r_switches_if.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Common demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the Rx and Tx tasks are created. */\r
+#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* The number of items the queue can hold. This is 1 as the Rx task will\r
+remove items as they are added so the Tx task should always find the queue\r
+empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* The LED used to indicate that a value has been received on the queue. */\r
+#define mainQUEUE_LED ( 0 )\r
+\r
+/* The LED used to indicate that full power is being used (the MCU is not in\r
+deep sleep or software standby mode). */\r
+#define mainFULL_POWER_LED ( 1 )\r
+\r
+/* The LED used to indicate that deep sleep mode is being used. */\r
+#define mainDEEP_SLEEP_LED ( 2 )\r
+\r
+/* The Tx task sends to the queue with a frequency that is set by the value\r
+read from the potentiometer until the value goes above that set by the\r
+mainSOFTWARE_STANDBY_DELAY constant - at which time the Tx task instead blocks\r
+indefinitely on a semaphore. */\r
+#define mainSOFTWARE_STANDBY_DELAY ( 3000UL )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0 )\r
+\r
+/* The value that is sent from the Tx task to the Rx task on the queue. */\r
+#define mainQUEUED_VALUE ( 100UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The Rx and Tx tasks as described at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Reads and returns the value of the ADC connected to the potentiometer built\r
+ * onto the RSK.\r
+ */\r
+static unsigned short prvReadPOT( void );\r
+\r
+/*\r
+ * The handler for the interrupt generated when any of the buttons are pressed.\r
+ */\r
+__interrupt void vButtonInterrupt( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue to pass data from the Tx task to the Rx task. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/* The semaphore that is 'given' by interrupts generated from button pushes. */\r
+static xSemaphoreHandle xSemaphore = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_low_power( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+ configASSERT( xQueue );\r
+\r
+ /* Create the semaphore that is 'given' by an interrupt generated from a\r
+ button push. */\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ configASSERT( xSemaphore );\r
+\r
+ /* Make sure the semaphore starts in the expected state - no button pushes\r
+ have yet occurred. A block time of zero can be used as it is guaranteed\r
+ that the semaphore will be available because it has just been created. */\r
+ xSemaphoreTake( xSemaphore, mainDONT_BLOCK );\r
+\r
+ /* Start the two tasks as described at the top of this file. */\r
+ xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* The CPU is currently running, not sleeping, so turn on the LED that\r
+ shows the CPU is not in a sleep mode. */\r
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );\r
+\r
+ /* Start the scheduler running running. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well the next line of code will not be reached as the\r
+ scheduler will be running. If the next line is reached then it is likely\r
+ there was insufficient FreeRTOS heap available for the idle task and/or\r
+ timer task to be created. See http://www.freertos.org/a00111.html. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xDelay;\r
+const unsigned long ulValueToSend = mainQUEUED_VALUE;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* The delay period between successive sends to the queue is set by\r
+ the potentiometer reading. */\r
+ xDelay = ( portTickType ) prvReadPOT();\r
+\r
+ /* If the block time is greater than 3000 milliseconds then block\r
+ indefinitely waiting for a button push. */\r
+ if( xDelay > mainSOFTWARE_STANDBY_DELAY )\r
+ {\r
+ /* As this is an indefinite delay the kernel will place the CPU\r
+ into software standby mode the next time the idle task runs. */\r
+ xSemaphoreTake( xSemaphore, portMAX_DELAY );\r
+ }\r
+ else\r
+ {\r
+ /* Convert a time in milliseconds to a time in ticks. */\r
+ xDelay /= portTICK_RATE_MS;\r
+\r
+ /* Place this task in the blocked state until it is time to run\r
+ again. As this is not an indefinite sleep the kernel will place\r
+ the CPU into the deep sleep state when the idle task next runs. */\r
+ vTaskDelay( xDelay );\r
+ }\r
+\r
+ /* Send to the queue - causing the queue receive task to flash its LED.\r
+ It should not be necessary to block on the queue send because the Rx\r
+ task will have removed the last queued item. */\r
+ xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have arrived, but is it the expected\r
+ value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == mainQUEUED_VALUE )\r
+ {\r
+ vParTestToggleLED( mainQUEUE_LED );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPreSleepProcessing( unsigned long ulExpectedIdleTime )\r
+{\r
+ /* Called by the kernel before it places the MCU into a sleep mode because\r
+ configPRE_SLEEP_PROCESSING() is #defined to vPreSleepProcessing().\r
+\r
+ NOTE: Additional actions can be taken here to get the power consumption\r
+ even lower. For example, the ADC input used by this demo could be turned\r
+ off here, and then back on again in the post sleep processing function.\r
+ For maximum power saving ensure all unused pins are in their lowest power\r
+ state. */\r
+\r
+ /* Avoid compiler warnings about the unused parameter. */\r
+ ( void ) ulExpectedIdleTime;\r
+\r
+ /* Is the MCU about to enter deep sleep mode or software standby mode? */\r
+ if( SYSTEM.SBYCR.BIT.SSBY == 0 )\r
+ {\r
+ /* Turn on the LED that indicates deep sleep mode is being entered. */\r
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdTRUE );\r
+ }\r
+ else\r
+ {\r
+ /* Software standby mode is being used, so no LEDs are illuminated to\r
+ ensure minimum power readings are obtained. Ensure the Queue LED is\r
+ also off. */\r
+ vParTestSetLED( mainQUEUE_LED, pdFALSE );\r
+ }\r
+\r
+ /* Turn off the LED that indicates full power is being used. */\r
+ vParTestSetLED( mainFULL_POWER_LED, pdFALSE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPostSleepProcessing( unsigned long ulExpectedIdleTime )\r
+{\r
+ /* Called by the kernel when the MCU exits a sleep mode because\r
+ configPOST_SLEEP_PROCESSING is #defined to vPostSleepProcessing(). */\r
+\r
+ /* Avoid compiler warnings about the unused parameter. */\r
+ ( void ) ulExpectedIdleTime;\r
+\r
+ /* Turn off the LED that indicates deep sleep mode, and turn on the LED\r
+ that indicates full power is being used. */\r
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdFALSE );\r
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static unsigned short prvReadPOT( void )\r
+{\r
+unsigned short usADCValue;\r
+const unsigned short usMinADCValue = 128;\r
+\r
+ /* Start an ADC scan. */\r
+ S12AD.ADCSR.BIT.ADST = 1;\r
+ while( S12AD.ADCSR.BIT.ADST == 1 )\r
+ {\r
+ /* Just waiting for the ADC scan to complete. Inefficient\r
+ polling! */\r
+ }\r
+\r
+ usADCValue = S12AD.ADDR4;\r
+\r
+ /* Don't let the ADC value get too small as the LED behaviour will look\r
+ erratic. */\r
+ if( usADCValue < usMinADCValue )\r
+ {\r
+ usADCValue = usMinADCValue;\r
+ }\r
+\r
+ return usADCValue;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma vector = VECT_ICU_IRQ0, VECT_ICU_IRQ1, VECT_ICU_IRQ4\r
+__interrupt void vButtonInterrupt1( void )\r
+{\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* The semaphore is only created when the build is configured to create the\r
+ low power demo. */\r
+ if( xSemaphore != NULL )\r
+ {\r
+ /* This interrupt will bring the CPU out of deep sleep and software\r
+ standby modes. Give the semaphore that was used to place the Tx task\r
+ into an indefinite sleep. */\r
+ if( uxQueueMessagesWaitingFromISR( xSemaphore ) == 0 )\r
+ {\r
+ xSemaphoreGiveFromISR( xSemaphore, &lHigherPriorityTaskWoken );\r
+ }\r
+ else\r
+ {\r
+ /* The semaphore was already available, so the task is not blocked\r
+ on it and there is no point giving it. */\r
+ }\r
+\r
+ /* If giving the semaphore caused a task to leave the Blocked state,\r
+ and the task that left the Blocked state has a priority equal to or\r
+ above the priority of the task that this interrupt interrupted, then\r
+ lHigherPriorityTaskWoken will have been set to pdTRUE inside the call\r
+ to xSemaphoreGiveFromISR(), and calling portYIELD_FROM_ISR() will cause\r
+ a context switch to the unblocked task. */\r
+ portYIELD_FROM_ISR( lHigherPriorityTaskWoken );\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+ PUBLIC _vRegTest1Implementation\r
+ PUBLIC _vRegTest2Implementation\r
+\r
+ EXTERN _ulRegTest1CycleCount\r
+ EXTERN _ulRegTest2CycleCount\r
+\r
+ RSEG CODE:CODE(4)\r
+\r
+_vRegTest1Implementation:\r
+\r
+ /* Set each register to a known value. */\r
+ MOV.L #0x33333333, R15\r
+ MVTACHI R15\r
+ MOV.L #0x44444444, R15\r
+ MVTACLO R15\r
+ MOV.L #1, R1\r
+ MOV.L #2, R2\r
+ MOV.L #3, R3\r
+ MOV.L #4, R4\r
+ MOV.L #5, R5\r
+ MOV.L #6, R6\r
+ MOV.L #7, R7\r
+ MOV.L #8, R8\r
+ MOV.L #9, R9\r
+ MOV.L #10, R10\r
+ MOV.L #11, R11\r
+ MOV.L #12, R12\r
+ MOV.L #13, R13\r
+ MOV.L #14, R14\r
+ MOV.L #15, R15\r
+\r
+ /* Loop, checking each iteration that each register still contains the\r
+ expected value. */\r
+ TestLoop1:\r
+\r
+ /* Push the registers that are going to get clobbered. */\r
+ PUSHM R14-R15\r
+\r
+ /* Increment the loop counter to show this task is still getting CPU\r
+ time. */\r
+ MOV.L #_ulRegTest1CycleCount, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ /* Yield to extend the text coverage. Set the bit in the ITU SWINTR\r
+ register. */\r
+ MOV.L #1, R14\r
+ MOV.L #0872E0H, R15\r
+ MOV.B R14, [R15]\r
+ NOP\r
+ NOP\r
+\r
+ /* Check the accumulator value. */\r
+ MVFACHI R15\r
+ CMP #0x33333333, R15\r
+ BNE RegTest2Error\r
+ MVFACMI R15\r
+ CMP #0x33334444, R15\r
+ BNE RegTest2Error\r
+\r
+ /* Restore the clobbered registers. */\r
+ POPM R14-R15\r
+\r
+ /* Now compare each register to ensure it still contains the value that\r
+ was set before this loop was entered. */\r
+ CMP #1, R1\r
+ BNE RegTest1Error\r
+ CMP #2, R2\r
+ BNE RegTest1Error\r
+ CMP #3, R3\r
+ BNE RegTest1Error\r
+ CMP #4, R4\r
+ BNE RegTest1Error\r
+ CMP #5, R5\r
+ BNE RegTest1Error\r
+ CMP #6, R6\r
+ BNE RegTest1Error\r
+ CMP #7, R7\r
+ BNE RegTest1Error\r
+ CMP #8, R8\r
+ BNE RegTest1Error\r
+ CMP #9, R9\r
+ BNE RegTest1Error\r
+ CMP #10, R10\r
+ BNE RegTest1Error\r
+ CMP #11, R11\r
+ BNE RegTest1Error\r
+ CMP #12, R12\r
+ BNE RegTest1Error\r
+ CMP #13, R13\r
+ BNE RegTest1Error\r
+ CMP #14, R14\r
+ BNE RegTest1Error\r
+ CMP #15, R15\r
+ BNE RegTest1Error\r
+\r
+ /* All comparisons passed, start a new iteration of this loop. */\r
+ BRA TestLoop1\r
+\r
+ /* A compare failed, just loop here so the loop counter stops\r
+ incrementing causing the check timer to indicate the error. */\r
+ RegTest1Error:\r
+ BRA RegTest1Error\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+_vRegTest2Implementation:\r
+\r
+ /* Set each register to a known value. */\r
+ MOV.L #0x11111111, R15\r
+ MVTACHI R15\r
+ MOV.L #0x22222222, R15\r
+ MVTACLO R15\r
+ MOV.L #100, R1\r
+ MOV.L #200, R2\r
+ MOV.L #300, R3\r
+ MOV.L #400, R4\r
+ MOV.L #500, R5\r
+ MOV.L #600, R6\r
+ MOV.L #700, R7\r
+ MOV.L #800, R8\r
+ MOV.L #900, R9\r
+ MOV.L #1000, R10\r
+ MOV.L #1001, R11\r
+ MOV.L #1002, R12\r
+ MOV.L #1003, R13\r
+ MOV.L #1004, R14\r
+ MOV.L #1005, R15\r
+\r
+ /* Loop, checking each iteration that each register still contains the\r
+ expected value. */\r
+ TestLoop2:\r
+\r
+ /* Push the registers that are going to get clobbered. */\r
+ PUSHM R14-R15\r
+\r
+ /* Increment the loop counter to show this task is still getting CPU\r
+ time. */\r
+ MOV.L #_ulRegTest2CycleCount, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ /* Check the accumulator value. */\r
+ MVFACHI R15\r
+ CMP #0x11111111, R15\r
+ BNE RegTest2Error\r
+ MVFACMI R15\r
+ CMP #0x11112222, R15\r
+ BNE RegTest2Error\r
+\r
+ /* Restore the clobbered registers. */\r
+ POPM R14-R15\r
+\r
+ /* Now compare each register to ensure it still contains the value that\r
+ was set before this loop was entered. */\r
+ CMP #100, R1\r
+ BNE RegTest2Error\r
+ CMP #200, R2\r
+ BNE RegTest2Error\r
+ CMP #300, R3\r
+ BNE RegTest2Error\r
+ CMP #400, R4\r
+ BNE RegTest2Error\r
+ CMP #500, R5\r
+ BNE RegTest2Error\r
+ CMP #600, R6\r
+ BNE RegTest2Error\r
+ CMP #700, R7\r
+ BNE RegTest2Error\r
+ CMP #800, R8\r
+ BNE RegTest2Error\r
+ CMP #900, R9\r
+ BNE RegTest2Error\r
+ CMP #1000, R10\r
+ BNE RegTest2Error\r
+ CMP #1001, R11\r
+ BNE RegTest2Error\r
+ CMP #1002, R12\r
+ BNE RegTest2Error\r
+ CMP #1003, R13\r
+ BNE RegTest2Error\r
+ CMP #1004, R14\r
+ BNE RegTest2Error\r
+ CMP #1005, R15\r
+ BNE RegTest2Error\r
+\r
+ /* All comparisons passed, start a new iteration of this loop. */\r
+ BRA TestLoop2\r
+\r
+ /* A compare failed, just loop here so the loop counter stops\r
+ incrementing causing the check timer to indicate the error. */\r
+ RegTest2Error:\r
+ BRA RegTest2Error\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
+\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\rx\bin\rxproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\rx\bin\rxemue20.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\rx\bin\rxbat.dll" --backend -B "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\rx\config\debugger\ior5f51115.ddf" "--endian" "l" "--double" "32" "--core" "RX100" "--int" "32" "-d" "emue20" "--drv_mode" "debugging" "--drv_communication" "USB" \r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+ <Desktop>\r
+ <Static>\r
+ <Debug-Log>\r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>\r
+ <Build>\r
+ <ColumnWidth0>20</ColumnWidth0>\r
+ <ColumnWidth1>1216</ColumnWidth1>\r
+ <ColumnWidth2>324</ColumnWidth2>\r
+ <ColumnWidth3>81</ColumnWidth3>\r
+ </Build>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>231</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Disassembly>\r
+ <col-names>\r
+ \r
+ \r
+ <item>Disassembly</item><item>_I0</item></col-names>\r
+ <col-widths>\r
+ \r
+ \r
+ <item>599</item><item>20</item></col-widths>\r
+ <DisasmHistory/>\r
+ <PreferedWindows>\r
+ \r
+ \r
+ \r
+ \r
+ <Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>\r
+ \r
+ \r
+ <ShowCodeCoverage>1</ShowCodeCoverage><ShowInstrProfiling>1</ShowInstrProfiling></Disassembly>\r
+ <Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><WATCH_1><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><expressions><item>lErrorStatus</item><item>lChangedTimerPeriodAlready</item><item/></expressions><col-names><item>Expression</item><item>Location</item><item>Type</item><item>Value</item></col-names><col-widths><item>200</item><item>150</item><item>100</item><item>62</item></col-widths></WATCH_1></Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd0>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-27185-11031</Identity>\r
+ <TabName>Debug Log</TabName>\r
+ <Factory>Debug-Log</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab>\r
+ <Identity>TabID-26662-11041</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-5165-11034</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo_IAR</ExpandedNode><ExpandedNode>RTOSDemo_IAR/FreeRTOS Source</ExpandedNode><ExpandedNode>RTOSDemo_IAR/FreeRTOS Source/portable</ExpandedNode><ExpandedNode>RTOSDemo_IAR/FreeRTOS Source/portable/IAR</ExpandedNode><ExpandedNode>RTOSDemo_IAR/FreeRTOS Source/portable/IAR/RX100</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>104</YPos2><SelStart2>6014</SelStart2><SelEnd2>6014</SelEnd2></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\FreeRTOSConfig.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>72</YPos2><SelStart2>5237</SelStart2><SelEnd2>5237</SelEnd2></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-01349150><key>iaridepm.enu1</key></Toolbar-01349150></Sizes></Row0><Row1><Sizes><Toolbar-05ac2708><key>debuggergui.enu1</key></Toolbar-05ac2708></Sizes></Row1></Top><Left><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>716</Bottom><Right>305</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>182738</sizeVertCX><sizeVertCY>731161</sizeVertCY></Rect></Wnd1></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd0></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Project>\r
+\r
+\r
--- /dev/null
+[Stack]\r
+FillEnabled=0\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnLogOnly=1\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[DebugChecksum]\r
+Checksum=222757635\r
+[CallStack]\r
+ShowArgs=0\r
+[Disassembly]\r
+MixedMode=1\r
+[InterruptLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+SumSortOrder=0\r
+[DataLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+[Breakpoints2]\r
+Count=0\r
+[Interrupts]\r
+Enabled=1\r
+[MemoryMap]\r
+Enabled=0\r
+Base=0\r
+UseAuto=0\r
+TypeViolation=1\r
+UnspecRange=1\r
+ActionState=1\r
+[E1/E20 Emulator]\r
+BlockBits=15\r
+B0=1,0\r
+B1=1,1024\r
+B2=1,2048\r
+B3=1,3072\r
+StartEnabled=0\r
+StartSymbol=\r
+StopEnabled=0\r
+StopSymbol=\r
+TraceMode=0\r
+TraceOutput=2\r
+TraceCapacity=0\r
+TraceRestart=0\r
+OperatingFrequency=22.000000\r
+PerfEnabled=0\r
+PerfCondition=0,0\r
+PerfDisplayTime=0,0\r
+PerfOnlyOnce=0,0\r
+PerfUse64Bit=0\r
+ChipName=R5F51115\r
+PinMode=0\r
+RegMode=0\r
+Endian=0\r
+ExtMemBlockNum=0\r
+InputClock=22.000000\r
+AllowClkSrcChange=0\r
+WorkRamStart=4096\r
+ComunicationSelect=1\r
+JtagClock=0\r
+FINE=2000000\r
+FlashOvrNum=0\r
+DebugFlags=0,0\r
+EmulatorMode=0\r
+PowerTargetFromEmulator=0\r
+Voltage=0\r
+NeedInit=0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[CallStackLog]\r
+Enabled=0\r
+[DriverProfiling]\r
+Enabled=0\r
+Mode=1\r
+Graph=0\r
+Symbiont=0\r
+Exclusions=\r
+[Breakpoints]\r
+Bp0=_ "STD_CODE" "{$PROJ_DIR$\Renesas_Files\r_bsp\board\user\hardware_setup.c}.60.2" 0 0 0 0 "" 0 ""\r
+Count=1\r
+[Monitor Execution]\r
+Leave target running=0\r
+Release target=0\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
+[Trace1]\r
+Enabled=0\r
+ShowSource=1\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>RTOSDemo_IAR/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>199</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build><Select-Ambiguous-Definitions><ColumnWidth0>580</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>994</ColumnWidth2></Select-Ambiguous-Definitions><TerminalIO/><Find-in-Files><ColumnWidth0>695</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>994</ColumnWidth2></Find-in-Files></Static>\r
+ <Windows>\r
+ \r
+ <Wnd0>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-3933-19799</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo_IAR</ExpandedNode><ExpandedNode>RTOSDemo_IAR/Renesas Files</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-4909-11467</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-18506-4030</Identity><TabName>Ambiguous Definitions</TabName><Factory>Select-Ambiguous-Definitions</Factory><Session/></Tab><Tab><Identity>TabID-16773-20028</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>74</YPos2><SelStart2>6014</SelStart2><SelEnd2>6014</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-01349150><key>iaridepm.enu1</key></Toolbar-01349150></Sizes></Row0><Row1><Sizes/></Row1><Row2><Sizes/></Row2></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>648</Bottom><Right>273</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>163690</sizeVertCX><sizeVertCY>661914</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>290</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>292</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>297352</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="ASCII"?>\r
+<com.renesas.linkersection.model:SectionContainer xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:com.renesas.linkersection.model="http:///LinkerSection.ecore">\r
+ <sections name="SU">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress"/>\r
+ </sections>\r
+ <sections name="SI"/>\r
+ <sections name="B_1"/>\r
+ <sections name="R_1"/>\r
+ <sections name="B_2"/>\r
+ <sections name="R_2"/>\r
+ <sections name="B"/>\r
+ <sections name="R"/>\r
+ <sections name="PResetPRG">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294836224"/>\r
+ </sections>\r
+ <sections name="C_1">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294840320"/>\r
+ </sections>\r
+ <sections name="C_2"/>\r
+ <sections name="C"/>\r
+ <sections name="C$*"/>\r
+ <sections name="D*"/>\r
+ <sections name="W*"/>\r
+ <sections name="L"/>\r
+ <sections name="PIntPRG">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294860800"/>\r
+ </sections>\r
+ <sections name="P">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294868992"/>\r
+ </sections>\r
+ <sections name="FIXEDVECT">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294967248"/>\r
+ </sections>\r
+</com.renesas.linkersection.model:SectionContainer>\r
--- /dev/null
+<?xml version="1.0" encoding="ASCII"?>\r
+<com.renesas.linkersection.model:SectionContainer xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:com.renesas.linkersection.model="http:///LinkerSection.ecore">\r
+ <sections name="SU">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress"/>\r
+ </sections>\r
+ <sections name="SI"/>\r
+ <sections name="B_1"/>\r
+ <sections name="R_1"/>\r
+ <sections name="B_2"/>\r
+ <sections name="R_2"/>\r
+ <sections name="B"/>\r
+ <sections name="R"/>\r
+ <sections name="PResetPRG">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294836224"/>\r
+ </sections>\r
+ <sections name="C_1">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294840320"/>\r
+ </sections>\r
+ <sections name="C_2"/>\r
+ <sections name="C"/>\r
+ <sections name="C$*"/>\r
+ <sections name="D*"/>\r
+ <sections name="W*"/>\r
+ <sections name="L"/>\r
+ <sections name="PIntPRG">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294860800"/>\r
+ </sections>\r
+ <sections name="P">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294868992"/>\r
+ </sections>\r
+ <sections name="FIXEDVECT">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294967248"/>\r
+ </sections>\r
+</com.renesas.linkersection.model:SectionContainer>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?>\r
+\r
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+ <storageModule moduleId="org.eclipse.cdt.core.settings">\r
+ <cconfiguration id="com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189">\r
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189" moduleId="org.eclipse.cdt.core.settings" name="HardwareDebug">\r
+ <externalSettings/>\r
+ <extensions>\r
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+ <extension id="org.eclipse.cdt.core.PE" point="org.eclipse.cdt.core.BinaryParser"/>\r
+ <extension id="com.renesas.cdt.core.KPITGCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="com.renesas.cdt.core.KPITVCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="com.renesas.cdt.core.KPITGASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="com.renesas.cdt.core.KPITMakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="com.renesas.cdt.core.KPITGLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ </extensions>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+ <configuration artifactExtension="mot" artifactName="RTOSDemo_Renesas" buildArtefactType="com.renesas.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.renesas.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf *.lst *.lis *.lpp *.map *.x *.lbp src/*.src src/*.p src/*.pp *.bls *.libelf *.lbk *.abs" description="Debug on hardware" errorParsers="com.renesas.cdt.core.KPITMakeErrorParser;com.renesas.cdt.core.KPITGCCErrorParser;com.renesas.cdt.core.KPITGASErrorParser;com.renesas.cdt.core.KPITGLDErrorParser;com.renesas.cdt.core.KPITVCErrorParser" id="com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189" name="HardwareDebug" parent="com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id">\r
+ <folderInfo id="com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189." name="/" resourcePath="">\r
+ <toolChain id="com.renesas.cdt.rxc.hardwaredebug.win32.toolChain.Id.1936925667" name="Renesas RXC Toolchain" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.toolChain.Id" targetTool="com.renesas.cdt.rxc.debug.win32.tool.convertor.Id">\r
+ <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.PE" id="com.renesas.cdt.rxc.hardwaredebug.win32.targetPlatform.Id.1377846111" isAbstract="false" osList="win32" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.targetPlatform.Id"/>\r
+ <builder buildPath="${workspace_loc:/BSP111/HardwareDebug}" id="com.renesas.cdt.rxc.hardwaredebug.win32.builder.Id.2044615069" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="SHC Make Builder" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.builder.Id"/>\r
+ <tool id="com.renesas.cdt.rxc.hardwaredebug.win32.tool.compiler.Id.486948393" name="Compiler" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.tool.compiler.Id">\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.cpuType.982467441" name="CPU type" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.cpuType" value="RX100" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.endian.1621733056" name="Data Endian" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.endian" value="Little-endian data" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.roundTo.915599060" name="Round to" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.roundTo" value="Nearest" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.precisionDouble.786447340" name="Precision of double" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.precisionDouble" value="Single precision" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signChar.262626578" name="Sign of char" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signChar" value="unsigned" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signBitField.564578464" name="Sign of bit field" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signBitField" value="unsigned" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.allocLowerBit.767627724" name="Allocate from lower bit" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.allocLowerBit" value="Lower bit" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.widthDivergence.1950840170" name="Width of divergence of function" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.widthDivergence" value="24 bit" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.patchCode.12062932" name="Patch code generation" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.patchCode" value="None" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.registerFastInterrupt.936233376" name="Fast interrupt register" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.registerFastInterrupt" value="None" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.ROM.695038388" name="ROM" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.ROM" value="None" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.RAM.1544552703" name="RAM" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.RAM" value="None" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.addressRegister.970641430" name="Address Register" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.addressRegister" value="None" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.renesas.Compiler.option.C.441900014" name="C :" superClass="com.renesas.cdt.renesas.Compiler.option.C" value="com.renesas.cdt.renesas.Compiler.option.C99" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.renesas.Compiler.option.incFileDirectories.1933791951" name="Include file directories" superClass="com.renesas.cdt.renesas.Compiler.option.incFileDirectories" valueType="includePath">\r
+ <listOptionValue builtIn="false" value=""${INC_RX}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Common_Demo_Tasks/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/FreeRTOS_Source/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/FreeRTOS_Source/portable/Renesas/RX100}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Renesas_Files/r_bsp}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Renesas_Files/r_switches}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/RTOSDemo/Renesas_Files/r_switches/src}""/>\r
+ </option>\r
+ <option id="com.renesas.cdt.renesas.Compiler.option.CPUSeries.322057583" name="Cpu Series" superClass="com.renesas.cdt.renesas.Compiler.option.CPUSeries" value="RX111" valueType="string"/>\r
+ <option id="com.renesas.cdt.renesas.Compiler.option.UserDef.1497284878" name="User-defined options" superClass="com.renesas.cdt.renesas.Compiler.option.UserDef" valueType="stringList">\r
+ <listOptionValue builtIn="false" value="-nologo"/>\r
+ <listOptionValue builtIn="false" value="-change_message=warning"/>\r
+ </option>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.cpu.529811854" name="CPU" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.cpu" value="RX111" valueType="string"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizeLevel.1070547061" name="Optimize level" superClass="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizeLevel" value="com.renesas.cdt.rxc.HardwareDebug.Compiler.option.optimizeLevel.0" valueType="enumerated"/>\r
+ <inputType id="%Base.Compiler.Shc.C.Input.Id.1298690760" name="C Input" superClass="%Base.Compiler.Shc.C.Input.Id"/>\r
+ </tool>\r
+ <tool id="com.renesas.cdt.rxc.hardwaredebug.win32.tool.assembler.Id.299640407" name="Assembler" outputFlag="-output=" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.tool.assembler.Id">\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Assembler.option.cpu.371490144" name="CPU" superClass="com.renesas.cdt.rxc.HardwareDebug.Assembler.option.cpu" value="RX100" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Assembler.option.endian.660114428" name="Data Endian" superClass="com.renesas.cdt.rxc.HardwareDebug.Assembler.option.endian" value="Little-endian data" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.Assembler.option.address.869973823" name="Address" superClass="com.renesas.cdt.rxc.HardwareDebug.Assembler.option.address" value="00000000" valueType="string"/>\r
+ <option id="com.renesas.cdt.renesas.Assembler.option.userDefine.1248628654" name="User-defined options" superClass="com.renesas.cdt.renesas.Assembler.option.userDefine" valueType="stringList">\r
+ <listOptionValue builtIn="false" value="-nologo"/>\r
+ <listOptionValue builtIn="false" value=""/>\r
+ <listOptionValue builtIn="false" value=""/>\r
+ </option>\r
+ <inputType id="%Base.Assembler.shcInputType.Id.1801607357" name="Assembler InputType" superClass="%Base.Assembler.shcInputType.Id"/>\r
+ </tool>\r
+ <tool id="com.renesas.cdt.rxc.hardwaredebug.win32.tool.linker.Id.1083452385" name="Linker" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.tool.linker.Id">\r
+ <option id="com.renesas.cdt.renesas.Linker.option.userDefined.1041569977" name="User-defined options" superClass="com.renesas.cdt.renesas.Linker.option.userDefined" valueType="stringList">\r
+ <listOptionValue builtIn="false" value="-rom=D=R,D_1=R_1,D_2=R_2"/>\r
+ <listOptionValue builtIn="false" value="-nomessage"/>\r
+ <listOptionValue builtIn="false" value="-nologo"/>\r
+ </option>\r
+ <option id="com.renesas.cdt.renesas.Linker.option.showVector.1685941890" name="Show vector" superClass="com.renesas.cdt.renesas.Linker.option.showVector" value="true" valueType="boolean"/>\r
+ <option id="com.renesas.cdt.renesas.Linker.option.showTotalSectionSize.684296766" name="Show total section size" superClass="com.renesas.cdt.renesas.Linker.option.showTotalSectionSize" value="true" valueType="boolean"/>\r
+ <option id="com.renesas.cdt.renesas.Linker.option.showCrossReference.1722254828" name="Show cross-reference" superClass="com.renesas.cdt.renesas.Linker.option.showCrossReference" value="true" valueType="boolean"/>\r
+ <option id="com.renesas.cdt.renesas.Linker.option.showReference.912872658" name="Show reference" superClass="com.renesas.cdt.renesas.Linker.option.showReference" value="true" valueType="boolean"/>\r
+ <option id="com.renesas.cdt.renesas.Linker.option.showSymbol.382153207" name="Show symbol" superClass="com.renesas.cdt.renesas.Linker.option.showSymbol" value="true" valueType="boolean"/>\r
+ <option id="com.renesas.cdt.renesas.Linker.option.enableAll.1808678203" name="Enable all" superClass="com.renesas.cdt.renesas.Linker.option.enableAll" value="true" valueType="boolean"/>\r
+ </tool>\r
+ <tool command="lbgrx" id="%com.renesas.cdt.rxc.hardwaredebug.win32.tool.libgen.Id.1500253254" name="Standard Library" superClass="%com.renesas.cdt.rxc.hardwaredebug.win32.tool.libgen.Id">\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.cpu.1800175066" name="CPU" superClass="com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.cpu" value="RX100" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.endian.392081833" name="Data Endian" superClass="com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.endian" value="Little-endian data" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.address.1948593009" name="Address" superClass="com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.address" value="00000000" valueType="string"/>\r
+ <option id="com.renesas.cdt.renesas.StandardLibrary.option.libConfiguration.1111135642" name="Library configuration" superClass="com.renesas.cdt.renesas.StandardLibrary.option.libConfiguration" value="C99" valueType="enumerated"/>\r
+ <option id="com.renesas.cdt.renesas.StandardLibrary.option.mathc89.624663395" name="math.h (C89/C99): Mathematical/trigonometric operations (double-precision)" superClass="com.renesas.cdt.renesas.StandardLibrary.option.mathc89" value="false" valueType="boolean"/>\r
+ </tool>\r
+ <tool command="optlnk" id="com.renesas.cdt.rxc.hardwaredebug.win32.tool.convertor.Id.340881453" name="Converter" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.tool.convertor.Id"/>\r
+ </toolChain>\r
+ </folderInfo>\r
+ <folderInfo id="com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189.158419194" name="/" resourcePath="RTOSDemo/Renesas_Files/r_switches">\r
+ <toolChain id="com.renesas.cdt.rxc.hardwaredebug.win32.toolChain.Id.859624060" name="Renesas RXC Toolchain" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.toolChain.Id" unusedChildren="">\r
+ <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.PE" id="com.renesas.cdt.rxc.hardwaredebug.win32.targetPlatform.Id" isAbstract="false" osList="win32" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.targetPlatform.Id"/>\r
+ <tool id="com.renesas.cdt.rxc.hardwaredebug.win32.tool.compiler.Id.1029821514" name="Compiler" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.tool.compiler.Id.486948393">\r
+ <inputType id="%Base.Compiler.Shc.C.Input.Id.43411981" name="C Input" superClass="%Base.Compiler.Shc.C.Input.Id"/>\r
+ </tool>\r
+ <tool id="com.renesas.cdt.rxc.hardwaredebug.win32.tool.assembler.Id.1012693747" name="Assembler" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.tool.assembler.Id.299640407">\r
+ <inputType id="%Base.Assembler.shcInputType.Id.314236670" name="Assembler InputType" superClass="%Base.Assembler.shcInputType.Id"/>\r
+ </tool>\r
+ <tool id="com.renesas.cdt.rxc.hardwaredebug.win32.tool.linker.Id.1484775969" name="Linker" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.tool.linker.Id.1083452385"/>\r
+ <tool id="%com.renesas.cdt.rxc.hardwaredebug.win32.tool.libgen.Id.1649982231" name="Standard Library" superClass="%com.renesas.cdt.rxc.hardwaredebug.win32.tool.libgen.Id.1500253254"/>\r
+ <tool id="com.renesas.cdt.rxc.hardwaredebug.win32.tool.convertor.Id.357794366" name="Converter" superClass="com.renesas.cdt.rxc.hardwaredebug.win32.tool.convertor.Id.340881453"/>\r
+ </toolChain>\r
+ </folderInfo>\r
+ <sourceEntries>\r
+ <entry excluding="RTOSDemo/Renesas_Files/r_sci_multi_ch|RTOSDemo/Renesas_Files/r_delay|RTOSDemo/OriginalDemo.c|r_sci_multi_ch|r_switches|src|r_bsp" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>\r
+ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>\r
+ </sourceEntries>\r
+ </configuration>\r
+ </storageModule>\r
+ <storageModule moduleId="scannerConfiguration">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+ <profile id="com.iar.cdt.v850.scanner.IAR_V850_PerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="false" filePath=""/>\r
+ <parser enabled="false"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="com.iar.cdt.v850.toolchain.scannerInfoProvider1">\r
+ <runAction arguments="" command="" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="com.iar.cdt.rl78.scanner.IAR_RL78_PerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="false" filePath=""/>\r
+ <parser enabled="false"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="com.iar.cdt.rl78.toolchain.scannerInfoProviderRL78">\r
+ <runAction arguments="" command="" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="com.iar.cdt.rx.scanner.IAR_RX_PerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="false" filePath=""/>\r
+ <parser enabled="false"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="com.iar.cdt.rx.toolchain.scannerInfoProviderRX">\r
+ <runAction arguments="" command="" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="makefileGenerator">\r
+ <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/${specs_file}"'" command="sh" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-c 'g++ -E -P -v -dD "${plugin_state_location}/specs.cpp"'" command="sh" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+ <buildOutputProvider>\r
+ <openAction enabled="true" filePath=""/>\r
+ <parser enabled="true"/>\r
+ </buildOutputProvider>\r
+ <scannerInfoProvider id="specsFile">\r
+ <runAction arguments="-c 'gcc -E -P -v -dD "${plugin_state_location}/specs.c"'" command="sh" useDefault="true"/>\r
+ <parser enabled="true"/>\r
+ </scannerInfoProvider>\r
+ </profile>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+ <storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>\r
+ <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>\r
+ </cconfiguration>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+ <project id="BSP111.com.renesas.cdt.rxc.projectType.win32.Id.1210290450" name="RenesasRXC" projectType="com.renesas.cdt.rxc.projectType.win32.Id"/>\r
+ </storageModule>\r
+</cproject>\r
--- /dev/null
+TOOL_CHAIN=Renesas RXC Toolchain
+VERSION=v1.02.01
+TC_INSTALL=C:\Devtools\Renesas\Hew\Tools\Renesas\RX\1_2_1\
+VERSION_IDE=3.06.02.080
+E2STUDIO_VERSION=1.1.1.7
\ No newline at end of file
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>RTOSDemo_Renesas</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>com.renesas.cdt.core.genmakebuilder</name>\r
+ <arguments>\r
+ <dictionary>\r
+ <key>?name?</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.append_environment</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildArguments</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+ <value>make</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+ <value>${workspace_loc:/BSP111/HardwareDebug}</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
+ <value>clean</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.contents</key>\r
+ <value>org.eclipse.cdt.make.core.configurationIds</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <triggers>full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>com.renesas.cdt.core.kpitcnature</nature>\r
+ <nature>com.renesas.cdt.core.kpitccnature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ </natures>\r
+</projectDescription>\r
--- /dev/null
+#Tue Nov 06 09:14:28 EST 2012\r
+com.renesas.cdt.renesas.Assembler.option.userDefine=-nologo;;;\r
+com.renesas.cdt.renesas.Compiler.option.C=com.renesas.cdt.renesas.Compiler.option.C99\r
+com.renesas.cdt.renesas.Compiler.option.UserDef=-nologo;-change_message\=warning;\r
+com.renesas.cdt.renesas.Compiler.option.incFileDirectories="C\:\\PROGRA~1\\Renesas\\Hew\\Tools\\Renesas\\RX\\1_2_0\\include";\r
+com.renesas.cdt.renesas.Linker.option.userDefined=-rom\=D\=R,D_1\=R_1,D_2\=R_2;-nomessage;-nologo;\r
+com.renesas.cdt.renesas.StandardLibrary.option.complexC99=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.ctypec89=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.fenvC99=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.inttypesC99=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.libConfiguration=C99\r
+com.renesas.cdt.renesas.StandardLibrary.option.mathc89=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.mathfc89=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.runtime=true\r
+com.renesas.cdt.renesas.StandardLibrary.option.rxccomplexCPP=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.rxciosCPP=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.rxcnewCPP=true\r
+com.renesas.cdt.renesas.StandardLibrary.option.rxcstringCPP=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.stdargc89=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.stdioc89=true\r
+com.renesas.cdt.renesas.StandardLibrary.option.stdlibc89=true\r
+com.renesas.cdt.renesas.StandardLibrary.option.stringc89=true\r
+com.renesas.cdt.renesas.StandardLibrary.option.wcharC99=false\r
+com.renesas.cdt.renesas.StandardLibrary.option.wctypeC99=false\r
+com.renesas.cdt.rxc.HardwareDebug.Assembler.option.endian=Little-endian data\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.RAM=None\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.ROM=None\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.address=00000000\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.addressRegister=None\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.allocLowerBit=Lower bit\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.cpuType=RX100\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.denormalized=false\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.endian=Little-endian data\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.enumSize=false\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.packStructures=false\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.patchCode=None\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.precisionDouble=Single precision\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.registerFastInterrupt=None\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.replaceFromIntWithShort=false\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.roundTo=Nearest\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signBitField=unsigned\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signChar=unsigned\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.useDynamic=false\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.useTry=false\r
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.widthDivergence=24 bit\r
+com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.endian=Little-endian data\r
+com.renesas.cdt.rxc.Release.Assembler.option.endian=Little-endian data\r
+com.renesas.cdt.rxc.Release.Compiler.option.RAM=None\r
+com.renesas.cdt.rxc.Release.Compiler.option.ROM=None\r
+com.renesas.cdt.rxc.Release.Compiler.option.address=00000000\r
+com.renesas.cdt.rxc.Release.Compiler.option.addressRegister=None\r
+com.renesas.cdt.rxc.Release.Compiler.option.allocLowerBit=Lower bit\r
+com.renesas.cdt.rxc.Release.Compiler.option.cpuType=RX100\r
+com.renesas.cdt.rxc.Release.Compiler.option.denormalized=false\r
+com.renesas.cdt.rxc.Release.Compiler.option.endian=Little-endian data\r
+com.renesas.cdt.rxc.Release.Compiler.option.enumSize=false\r
+com.renesas.cdt.rxc.Release.Compiler.option.packStructures=false\r
+com.renesas.cdt.rxc.Release.Compiler.option.patchCode=None\r
+com.renesas.cdt.rxc.Release.Compiler.option.precisionDouble=Single precision\r
+com.renesas.cdt.rxc.Release.Compiler.option.registerFastInterrupt=None\r
+com.renesas.cdt.rxc.Release.Compiler.option.replaceFromIntWithShort=false\r
+com.renesas.cdt.rxc.Release.Compiler.option.roundTo=Nearest\r
+com.renesas.cdt.rxc.Release.Compiler.option.signBitField=unsigned\r
+com.renesas.cdt.rxc.Release.Compiler.option.signChar=unsigned\r
+com.renesas.cdt.rxc.Release.Compiler.option.useDynamic=false\r
+com.renesas.cdt.rxc.Release.Compiler.option.useTry=false\r
+com.renesas.cdt.rxc.Release.Compiler.option.widthDivergence=24 bit\r
+com.renesas.cdt.rxc.Release.StandardLibrary.option.endian=Little-endian data\r
+eclipse.preferences.version=1\r
--- /dev/null
+#Fri Nov 09 15:36:42 EST 2012\r
+eclipse.preferences.version=1\r
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/CPATH/delimiter=;\r
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/CPATH/operation=remove\r
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/C_INCLUDE_PATH/delimiter=;\r
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/C_INCLUDE_PATH/operation=remove\r
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/append=true\r
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/appendContributed=true\r
+environment/buildEnvironmentLibrary/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/LIBRARY_PATH/delimiter=;\r
+environment/buildEnvironmentLibrary/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/LIBRARY_PATH/operation=remove\r
+environment/buildEnvironmentLibrary/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/append=true\r
+environment/buildEnvironmentLibrary/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/appendContributed=true\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<launchConfiguration type="com.renesas.cdt.launch.dsf.gdbremote.launchConfigurationType">\r
+<intAttribute key="com.renesas.cdt.core.admPortNumber" value="61236"/>\r
+<stringAttribute key="com.renesas.cdt.core.initCommands" value=""/>\r
+<stringAttribute key="com.renesas.cdt.core.ipAddress" value="localhost"/>\r
+<stringAttribute key="com.renesas.cdt.core.jtagDevice" value="E1"/>\r
+<booleanAttribute key="com.renesas.cdt.core.loadImage" value="true"/>\r
+<stringAttribute key="com.renesas.cdt.core.optionInitCommands" value=""/>\r
+<intAttribute key="com.renesas.cdt.core.portNumber" value="61234"/>\r
+<stringAttribute key="com.renesas.cdt.core.runCommands" value=""/>\r
+<stringAttribute key="com.renesas.cdt.core.serverParam" value="-g E1 -l 0 -t R5F51115 -p 61234 -d 61236 -uClockSrcHoco= 0 -uInputClock= 16.0000 -uAllowClockSourceInternal= 1 -uUseFine= 1 -uFineBaudRate= 2.00 -w 0 -z 0 -uRegisterSetting= 0 -uModePin= 0 -uDebugMode= 1 -uExecuteProgram= 0 -uIdCode= FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -n 0 -uWorkRamAddress= 1000 -uProgReWriteIRom= 0 -uProgReWriteDFlash= 0"/>\r
+<booleanAttribute key="com.renesas.cdt.core.setResume" value="true"/>\r
+<booleanAttribute key="com.renesas.cdt.core.setStopAt" value="true"/>\r
+<booleanAttribute key="com.renesas.cdt.core.startServer" value="true"/>\r
+<stringAttribute key="com.renesas.cdt.core.stopAt" value="main"/>\r
+<stringAttribute key="com.renesas.cdt.core.targetDevice" value="R5F51115"/>\r
+<booleanAttribute key="com.renesas.cdt.core.useRemoteTarget" value="true"/>\r
+<booleanAttribute key="com.renesas.cdt.core.verboseMode" value="false"/>\r
+<stringAttribute key="com.renesas.cdt.launch.dsf.IO_MAP" value="${eclipse_home}..\internal\IoFiles\RX\RX111.sfrx"/>\r
+<booleanAttribute key="com.renesas.cdt.launch.dsf.USE_DEFAULT_IO_MAP" value="true"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.allow.clock.source.internal" value="true"/>\r
+<intAttribute key="com.renesas.hardwaredebug.e1.clock_source" value="0"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.connection.mode" value="1"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.e1_pwr" value="false"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.execute.program" value="false"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.external_memory" value=""/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.fine.baud.rate" value="2.00"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.flash_overwrite_blocks" value=""/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.hw_break" value="false"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.inputclock" value="16.0000"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.jtag.clock.freq" value="16.5"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.jtag.or.fine" value="1"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.le" value="true"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.mode" value="0"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.mode_pin" value="0"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.prog_rewrite_dflash" value="false"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.prog_rewrite_irom" value="false"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.supply.voltage" value="3.3V"/>\r
+<intAttribute key="com.renesas.hardwaredebug.e1.work_ram_start" value="4096"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e20.le" value="true"/>\r
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${eclipse_home}../DebugComp/rx-elf-gdb"/>\r
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>\r
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>\r
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="HardwareDebug\BSP111.x"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="BSP111"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">\r
+<listEntry value="/BSP111"/>\r
+</listAttribute>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">\r
+<listEntry value="4"/>\r
+</listAttribute>\r
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>\r
+</launchConfiguration>\r
--- /dev/null
+REM This file should be executed from the command line prior to the first\r
+REM build. It will be necessary to refresh the Eclipse project once the\r
+REM .bat file has been executed (normally just press F5 to refresh).\r
+\r
+REM Copies all the required files from their location within the standard\r
+REM FreeRTOS directory structure to under the Eclipse project directory.\r
+REM This permits the Eclipse project to be used in 'managed' mode and without\r
+REM having to setup any linked resources.\r
+\r
+REM Standard paths\r
+SET FREERTOS_SOURCE=..\..\Source\r
+SET COMMON_SOURCE=..\Common\minimal\r
+SET COMMON_INCLUDE=..\Common\include\r
+\r
+REM Have the files already been copied?\r
+IF EXIST RTOSDemo\FreeRTOS_Source Goto END\r
+\r
+ REM Create the required directory structure.\r
+ MD RTOSDemo\FreeRTOS_Source\r
+ MD RTOSDemo\FreeRTOS_Source\include\r
+ MD RTOSDemo\FreeRTOS_Source\portable\r
+ MD RTOSDemo\FreeRTOS_Source\portable\MemMang\r
+ MD RTOSDemo\FreeRTOS_Source\portable\Renesas\r
+ MD RTOSDemo\FreeRTOS_Source\portable\Renesas\RX100\r
+ MD RTOSDemo\Common_Demo_Tasks\r
+ MD RTOSDemo\Common_Demo_Tasks\include\r
+\r
+ REM Copy the core kernel files into the project directory\r
+ copy %FREERTOS_SOURCE%\tasks.c RTOSDemo\FreeRTOS_Source\r
+ copy %FREERTOS_SOURCE%\queue.c RTOSDemo\FreeRTOS_Source\r
+ copy %FREERTOS_SOURCE%\list.c RTOSDemo\FreeRTOS_Source\r
+ copy %FREERTOS_SOURCE%\timers.c RTOSDemo\FreeRTOS_Source\r
+\r
+ REM Copy the common header files into the project directory\r
+ copy %FREERTOS_SOURCE%\include\*.* RTOSDemo\FreeRTOS_Source\include\r
+\r
+ REM Copy the portable layer files into the project directory\r
+ copy %FREERTOS_SOURCE%\portable\Renesas\RX100\*.* RTOSDemo\FreeRTOS_Source\portable\Renesas\RX100\r
+\r
+ REM Copy the memory allocation files into the project directory\r
+ copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c RTOSDemo\FreeRTOS_Source\portable\MemMang\r
+\r
+ REM Copy the files that define the common demo tasks.\r
+ copy %COMMON_SOURCE%\death.c RTOSDemo\Common_Demo_Tasks\r
+ copy %COMMON_SOURCE%\blocktim.c RTOSDemo\Common_Demo_Tasks\r
+ copy %COMMON_SOURCE%\GenQTest.c RTOSDemo\Common_Demo_Tasks\r
+ copy %COMMON_SOURCE%\recmutex.c RTOSDemo\Common_Demo_Tasks\r
+\r
+ REM Copy the common demo file headers.\r
+ copy %COMMON_INCLUDE%\*.h RTOSDemo\Common_Demo_Tasks\include\r
+\r
+: END\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+\r
+/*\r
+ * The following #error directive is to remind users that a batch file must be\r
+ * executed prior to this project being built. The batch file *cannot* be\r
+ * executed from within the IDE! Once it has been executed, re-open or refresh\r
+ * the Eclipse project and remove the #error line below.\r
+ */\r
+//#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* Hardware specifics. */\r
+#include "platform.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* DEMO SPECIFIC SETTING:\r
+ * Set configCREATE_LOW_POWER_DEMO to one to run the low power demo with tick\r
+ * suppression, or 0 to run the more comprehensive test and demo application.\r
+ * If configCREATE_LOW_POWER_DEMO is set to 1 then main() calls main_low_power().\r
+ * If configCREATE_LOW_POWER_DEMO is set to 0 then main() calls main_full().\r
+ */\r
+#define configCREATE_LOW_POWER_DEMO 1\r
+\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_TICKLESS_IDLE configCREATE_LOW_POWER_DEMO\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ICLK_HZ ) /* Set in mcu_info.h. */\r
+#define configPERIPHERAL_CLOCK_HZ ( PCLKB_HZ ) /* Set in muc_info.h. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 9 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions - only included when the demo is configured to\r
+build the full demo (as opposed to the low power demo). */\r
+#if configCREATE_LOW_POWER_DEMO == 1\r
+ #define configUSE_TIMERS 0\r
+#else\r
+ #define configUSE_TIMERS 1\r
+ #define configTIMER_TASK_PRIORITY ( 3 )\r
+ #define configTIMER_QUEUE_LENGTH 5\r
+ #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+#endif /* configCREATE_LOW_POWER_DEMO */\r
+\r
+/* The interrupt priority used by the kernel itself for the tick interrupt and\r
+the pended interrupt. This would normally be the lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+\r
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
+Interrupts that use a priority above this will not be effected by anything the\r
+kernel is doing. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+\r
+extern void vAssertCalled( void );\r
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled();\r
+\r
+/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros\r
+allow the application writer to add additional code before and after the MCU is\r
+placed into the low power state respectively. The implementations provided in\r
+this demo can be extended to save even more power - for example the analog\r
+input used by the low power demo could be switched off in the pre-sleep macro\r
+and back on again in the post sleep macro. */\r
+void vPreSleepProcessing( unsigned long xExpectedIdleTime );\r
+void vPostSleepProcessing( unsigned long xExpectedIdleTime );\r
+#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime );\r
+#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime );\r
+\r
+/* configTICK_VECTOR must be set to the interrupt vector used by the peripheral\r
+that generates the tick interrupt. */\r
+#define configTICK_VECTOR VECT_CMT0_CMI0\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+#define partestNUM_LEDS ( 4 )\r
+\r
+long lParTestGetLEDState( unsigned long ulLED );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Port pin configuration is done by the low level set up prior to this\r
+ function being called. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLED, signed long xValue )\r
+{\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ if( xValue != 0 )\r
+ {\r
+ /* Turn the LED on. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0: LED0 = LED_ON;\r
+ break;\r
+ case 1: LED1 = LED_ON;\r
+ break;\r
+ case 2: LED2 = LED_ON;\r
+ break;\r
+ case 3: LED3 = LED_ON;\r
+ break;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LED off. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0: LED0 = LED_OFF;\r
+ break;\r
+ case 1: LED1 = LED_OFF;\r
+ break;\r
+ case 2: LED2 = LED_OFF;\r
+ break;\r
+ case 3: LED3 = LED_OFF;\r
+ break;\r
+ }\r
+\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( lParTestGetLEDState( ulLED ) != 0x00 )\r
+ {\r
+ vParTestSetLED( ulLED, 0 );\r
+ }\r
+ else\r
+ {\r
+ vParTestSetLED( ulLED, 1 );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+long lParTestGetLEDState( unsigned long ulLED )\r
+{\r
+long lReturn = pdTRUE;\r
+\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0 : if( LED0 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ case 1 : if( LED1 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ case 2 : if( LED2 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ case 3 : if( LED3 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : dbsct.c\r
+* Device(s) : RX\r
+* Description : Defines the structure of the ROM and RAM areas.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 26.10.2011 1.00 First Release\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Defines type structures used in this file */
+#include <stdint.h>
+
+/* Preprocessor directive */
+#pragma unpack
+
+/* Section start */
+#pragma section C C$DSEC
+
+/* MCU ROM and RAM structure definition */
+extern const struct {
+ uint8_t *rom_s; /* Start address of the initialized data section in ROM */
+ uint8_t *rom_e; /* End address of the initialized data section in ROM */
+ uint8_t *ram_s; /* Start address of the initialized data section in RAM */
+} _DTBL[] = {
+ { __sectop("D"), __secend("D"), __sectop("R") },
+ { __sectop("D_2"), __secend("D_2"), __sectop("R_2") },
+ { __sectop("D_1"), __secend("D_1"), __sectop("R_1") }
+};
+
+/* Section start */
+#pragma section C C$BSEC
+
+/* MCU ROM and RAM structure definition */
+extern const struct {
+ uint8_t *b_s; /* Start address of non-initialized data section */
+ uint8_t *b_e; /* End address of non-initialized data section */
+} _BTBL[] = {
+ { __sectop("B"), __secend("B") },
+ { __sectop("B_2"), __secend("B_2") },
+ { __sectop("B_1"), __secend("B_1") }
+};
+
+/* Section start */
+#pragma section
+
+/* CTBL prevents excessive output of L1100 messages when linking.
+ Even if CTBL is deleted, the operation of the program does not change. */
+uint8_t * const _CTBL[] = {
+ __sectop("C_1"), __sectop("C_2"), __sectop("C"),
+ __sectop("W_1"), __sectop("W_2"), __sectop("W")
+};
+
+/* Preprocessor directive */
+#pragma packoption
+\r
+/* This is to ensure compatibility with new L section in version 1.1 and up of the RXC compiler. Do not remove! */\r
+#pragma section C L\r
+const unsigned long deadSpace = 0xDEADDEAD;\r
+#pragma section \r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : hwsetup.c\r
+* Device(s) : RX\r
+* H/W Platform : RSKRX210\r
+* Description : Defines the initialization routines used each time the MCU is restarted.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* I/O Register and board definitions */\r
+#include "platform.h"\r
+/* Contains delcarations for the functions defined in this file */
+#include "hwsetup.h"\r
+#include "r_switches_config.h"\r
+/***********************************************************************************************************************\r
+Private global variables and functions\r
+***********************************************************************************************************************/\r
+/* MCU I/O port configuration function delcaration */
+static void output_ports_configure(void);\r
+
+/* Interrupt configuration function delcaration */
+static void interrupts_configure(void);\r
+
+/* MCU peripheral module configuration function declaration */
+static void peripheral_modules_enable(void);
+
+
+/***********************************************************************************************************************\r
+* Function name: hardware_setup\r
+* Description : Contains setup functions called at device restart\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void hardware_setup(void)
+{
+ output_ports_configure();
+ interrupts_configure();
+ peripheral_modules_enable();
+}
+
+/***********************************************************************************************************************\r
+* Function name: output_ports_configure
+* Description : Configures the port and pin direction settings, and sets the pin outputs to a safe level.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void output_ports_configure(void)
+{
+ /* Enable LEDs. */\r
+ /* Start with LEDs off. */\r
+ LED0 = LED_OFF;\r
+ LED1 = LED_OFF;\r
+ LED2 = LED_OFF;\r
+ LED3 = LED_OFF;\r
+\r
+ /* Set LED pins as outputs. */\r
+ LED0_PDR = 1;\r
+ LED1_PDR = 1;\r
+ LED2_PDR = 1;\r
+ LED3_PDR = 1;\r
+\r
+ /* Enable switches. */\r
+ /* Set pins as inputs. */\r
+ SW1_PDR = 0;\r
+ SW2_PDR = 0;\r
+ SW3_PDR = 0;\r
+\r
+ /* Set port mode registers for switches. */\r
+ SW1_PMR = 0;\r
+ SW2_PMR = 0;\r
+ SW3_PMR = 0;\r
+\r
+ /* Unlock MPC registers to enable writing to them. */\r
+ MPC.PWPR.BIT.B0WI = 0 ; /* Unlock protection register */\r
+ MPC.PWPR.BIT.PFSWE = 1 ; /* Unlock MPC registers */\r
+\r
+ /* TXD1 is output. */\r
+ PORT1.PDR.BIT.B6 = 1;\r
+ PORT1.PMR.BIT.B6 = 1;\r
+ MPC.P16PFS.BYTE = 0x0A;\r
+ /* RXD1 is input. */\r
+ PORT1.PDR.BIT.B5 = 0;\r
+ PORT1.PMR.BIT.B5 = 1;\r
+ MPC.P15PFS.BYTE = 0x0A;\r
+\r
+ /* Configure the pin connected to the ADC Pot as an input */\r
+ PORT4.PDR.BIT.B4 = 0;\r
+\r
+ /* Protect off. */\r
+ SYSTEM.PRCR.WORD = 0xA50B;\r
+\r
+ /* Turn off module stop for the A2D converter. */\r
+ SYSTEM.MSTPCRA.BIT.MSTPA17 = 0;\r
+\r
+ /* Protect on. */\r
+ SYSTEM.PRCR.WORD = 0xA500;\r
+\r
+ /* Initialise the first button to generate an interrupt. */\r
+ R_SWITCHES_Init();\r
+}
+
+/***********************************************************************************************************************\r
+* Function name: interrupts_configure\r
+* Description : Configures interrupts used\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void interrupts_configure(void)
+{\r
+ /* Add code here to setup additional interrupts */\r
+}
+
+/***********************************************************************************************************************\r
+* Function name: peripheral_modules_enable\r
+* Description : Enables and configures peripheral devices on the MCU\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void peripheral_modules_enable(void)
+{\r
+ /* Enable triggers to start an ADC conversion. */
+ S12AD.ADCSR.BIT.TRGE = 1;\r
+\r
+ /* Only channel 4 is going to be used. */\r
+ S12AD.ADANSA.BIT.ANSA4 = 1;\r
+}
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : hwsetup.h\r
+* Description : Hardware setup header file.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 26.10.2011 1.00 First Release\r
+***********************************************************************************************************************/\r
+
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* Multiple inclusion prevention macro */
+#ifndef HWSETUP_H
+#define HWSETUP_H
+
+/***********************************************************************************************************************\r
+Exported global functions (to be accessed by other files)\r
+***********************************************************************************************************************/\r
+/* Hardware setup funtion declaration */
+void hardware_setup(void);
+
+/* End of multiple inclusion prevention macro */
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : lcd.c\r
+* Device(s) : RX\r
+* H/W Platform : RSKRX111\r
+* Description : Provides variable and function declarations for lcd.c file\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Processor-specific details */
+#include <machine.h>
+/* Standard string manipulation & formatting functions */
+#include <stdio.h>
+#include <string.h>
+/* Defines standard variable types used in this function */
+#include <stdint.h>\r
+/* Bring in board includes. */\r
+#include "platform.h"
+/* Following header file provides function prototypes for LCD controlling functions & macro defines */
+#include "lcd.h"
+
+/***********************************************************************************************************************\r
+Private global variables and functions\r
+***********************************************************************************************************************/\r
+static void lcd_delay(volatile int32_t nsecs);\r
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value);\r
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value);\r
+
+/***********************************************************************************************************************
+* Function name : lcd_initialize
+* Description : Initializes the LCD display.
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/\r
+void lcd_initialize(void)
+{\r
+ /* Set LCD data pins as outputs. */\r
+ PORT4.PDR.BYTE |= 0x0F;\r
+ \r
+ /* Set LCD control pins as outputs. */\r
+ RS_PIN_DDR = 1;\r
+ E_PIN_DDR = 1;\r
+ \r
+ /* Power Up Delay for the LCD Module */ \r
+ lcd_delay(50000000);\r
+\r
+ /* Display initialises in 8 bit mode - so send one write (seen as 8 bit) to set to 4 bit mode. */\r
+ lcd_nibble_write(CTRL_WR, 0x03);\r
+ lcd_delay(5000000);\r
+ lcd_nibble_write(CTRL_WR, 0x03);\r
+ lcd_delay(5000000);\r
+ lcd_nibble_write(CTRL_WR, 0x03);\r
+ lcd_delay(5000000);\r
+ \r
+ /* Function Set */\r
+ lcd_nibble_write(CTRL_WR, 0x02);\r
+ lcd_delay(39000); \r
+ lcd_nibble_write(CTRL_WR, 0x02);\r
+ lcd_nibble_write(CTRL_WR, (LCD_DISPLAY_ON | LCD_TWO_LINE ));\r
+ lcd_delay(39000); \r
+ \r
+ /* Display ON/OFF control */\r
+ lcd_write(CTRL_WR, LCD_CURSOR_OFF);\r
+ lcd_delay(39000);\r
+\r
+ /* Display Clear */\r
+ lcd_write(CTRL_WR, LCD_CLEAR);\r
+ lcd_delay(2000000);\r
+\r
+ /* Entry Mode Set */\r
+ lcd_write(CTRL_WR, 0x06);\r
+ lcd_delay(39000);\r
+\r
+ /* Home the cursor */\r
+ lcd_write(CTRL_WR, LCD_HOME_L1);\r
+ lcd_delay(5000000); \r
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_clear
+* Description : Clears the LCD
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_clear(void)
+{
+ /* Display Clear */\r
+ lcd_write(CTRL_WR, LCD_CLEAR);\r
+ lcd_delay(2000000); \r
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_display
+* Description : This function controls LCD writes to line 1 or 2 of the LCD.\r
+* You need to use the defines LCD_LINE1 and LCD_LINE2 in order to specify the starting position.\r
+* For example, to start at the 2nd position on line 1...\r
+* lcd_display(LCD_LINE1 + 1, "Hello")
+* Arguments : position - \r
+* Line number of display
+* string - \r
+* Pointer to null terminated string
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_display(uint8_t position, uint8_t const * string)
+{
+ /* Declare next position variable */\r
+ static uint8_t next_pos = 0xFF;\r
+ \r
+ /* Set line position if needed. We don't want to if we don't need to because LCD control operations take longer \r
+ than LCD data operations. */\r
+ if (next_pos != position)\r
+ {\r
+ if(position < LCD_LINE2)\r
+ {\r
+ /* Display on Line 1 */\r
+ lcd_write(CTRL_WR, ((uint8_t)(LCD_HOME_L1 + position)));\r
+ }\r
+ else\r
+ {\r
+ /* Display on Line 2 */\r
+ lcd_write(CTRL_WR, ((uint8_t)((LCD_HOME_L2 + position) - LCD_LINE2)));\r
+ }\r
+\r
+ lcd_delay(39000);\r
+\r
+ /* set position index to known value */\r
+ next_pos = position; \r
+ }\r
+\r
+ do\r
+ {\r
+ /* Write character to LCD. */\r
+ lcd_write(DATA_WR,*string++);\r
+\r
+ lcd_delay(43000);\r
+ \r
+ /* Increment position index */\r
+ next_pos++; \r
+ } \r
+ while(*string); \r
+}\r
+
+/***********************************************************************************************************************\r
+* Function name : lcd_delay\r
+* Description : Implements LCD required delays.\r
+* Arguments : nsecs - \r
+* Number of nanoseconds to delay. RX111 has max clock of 32MHz which gives a cycle time of 31.3ns.\r
+* This means that nothing under 313ns should be input. 313ns would be 10 cycles which is still\r
+* being optimistic for getting in and out of this function.\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+static void lcd_delay(volatile int32_t nsecs)\r
+{\r
+ while (0 < nsecs)\r
+ {\r
+ /* Subtract off 10 cycles per iteration. This number was obtained when using the Renesas toolchain at \r
+ optimization level 2. The number to nanoseconds to subtract off below is calculated off of the ICLK speed. */\r
+ nsecs -= (int32_t)((313.0)*(32000000.0/(float)ICLK_HZ));\r
+ }\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name : lcd_nibble_write\r
+* Description : Writes data to display. Sends command to display. \r
+* Arguments : value - \r
+* The value to write\r
+* data_or_ctrl -\r
+* Whether to write data or control.\r
+* 1 = DATA\r
+* 0 = CONTROL\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value)\r
+{\r
+ /* Set Register Select pin high for Data */\r
+ if (data_or_ctrl == DATA_WR)\r
+ {\r
+ /* Data write. */\r
+ RS_PIN = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Control write. */\r
+ RS_PIN = 0;\r
+ }\r
+ \r
+ /* tsu1 delay */\r
+ lcd_delay(60); \r
+ \r
+ /* EN enable chip (HIGH) */\r
+ E_PIN = 1; \r
+ \r
+ /* Output the data */\r
+ PORT4.PODR.BYTE = (value & 0x0F);\r
+ \r
+ /* tw delay */ \r
+ lcd_delay(450); \r
+ \r
+ /* Latch data by dropping E */ \r
+ E_PIN = 0;\r
+ \r
+ /* th2 delay */ \r
+ lcd_delay(10);\r
+ \r
+ /* tc delay */\r
+ lcd_delay(480);\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name : lcd_write\r
+* Description : This function controls LCD writes to line 1 or 2 of the LCD. You need to use the defines LCD_LINE1 and \r
+* LCD_LINE2 in order to specify the starting position.\r
+* For example, to start at the 2nd position on line 1...\r
+* lcd_display(LCD_LINE1 + 1, "Hello") \r
+* Arguments : value - \r
+* The value to write\r
+* data_or_ctrl -\r
+* Whether to write data or control.\r
+* 1 = DATA\r
+* 0 = CONTROL\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value)\r
+{\r
+ /* Write upper nibble first */\r
+ lcd_nibble_write(data_or_ctrl, (uint8_t)((value & 0xF0) >> 4));\r
+ \r
+ /* Write lower nibble second */\r
+ lcd_nibble_write(data_or_ctrl, (uint8_t)(value & 0x0F));\r
+}\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : lcd.h\r
+* Device(s) : RX\r
+* H/W Platform : RSKRX111\r
+* Description : Provides variable and function declarations for lcd.c file\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+/* Multiple inclusion prevention macro */
+#ifndef LCD_H
+#define LCD_H
+
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/
+/* Defines standard integer variable types used in this file */
+#include <stdint.h>
+
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* RS register select pin */\r
+#define RS_PIN PORTC.PODR.BIT.B5\r
+#define RS_PIN_DDR PORTC.PDR.BIT.B5\r
+/* Display enable pin */ \r
+#define E_PIN PORTB.PODR.BIT.B1\r
+#define E_PIN_DDR PORTB.PDR.BIT.B1\r
+/* Data write/read definition */ \r
+#define DATA_WR 1\r
+/* Control write/read definition */\r
+#define CTRL_WR 0\r
+/* Maximum characters per line of LCD display. */ \r
+#define NUMB_CHARS_PER_LINE 8\r
+/* Number of lines on the LCD display */\r
+#define MAXIMUM_LINES 2 \r
+/* Character position of LCD line 1 */\r
+#define LCD_LINE1 0\r
+/* Character position of LCD line 2 */\r
+#define LCD_LINE2 16\r
+/* Clear LCD display and home cursor */\r
+#define LCD_CLEAR 0x01\r
+/* Move cursor to line 1 */\r
+#define LCD_HOME_L1 0x80\r
+/* Move cursor to line 2 */ \r
+#define LCD_HOME_L2 0xC0\r
+/* Cursor auto decrement after R/W */ \r
+#define CURSOR_MODE_DEC 0x04\r
+/* Cursor auto increment after R/W */\r
+#define CURSOR_MODE_INC 0x06\r
+/* Setup, 4 bits,2 lines, 5X7 */\r
+#define FUNCTION_SET 0x28\r
+/* Display ON with Cursor */\r
+#define LCD_CURSOR_ON 0x0E\r
+/* Display ON with Cursor off */\r
+#define LCD_CURSOR_OFF 0x0C\r
+/* Display on with blinking cursor */\r
+#define LCD_CURSOR_BLINK 0x0D\r
+/* Move Cursor Left One Position */\r
+#define LCD_CURSOR_LEFT 0x10\r
+/* Move Cursor Right One Position */\r
+#define LCD_CURSOR_RIGHT 0x14 \r
+/* Enable LCD display */\r
+#define LCD_DISPLAY_ON 0x04\r
+/* Enable both LCD lines */\r
+#define LCD_TWO_LINE 0x08\r
+
+/***********************************************************************************************************************\r
+Exported global functions (to be accessed by other files)\r
+***********************************************************************************************************************/\r
+/* LCD initialisation function declaration */
+void lcd_initialize (void);\r
+
+/* Update display function declaration */
+void lcd_display(uint8_t position, uint8_t const * string);\r
+
+/* Clear LCD function delcaration */
+void lcd_clear (void);
+
+/* End of multiple inclusion prevention macro */
+#endif
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : locking.c\r
+* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so\r
+* common resources can be accessed safely.\r
+***********************************************************************************************************************/\r
+/**********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 07.03.2012 1.00 First Release\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Fixed-size integer typedefs. */\r
+#include <stdint.h>\r
+/* bool support. */\r
+#include <stdbool.h>\r
+/* Has intrinsic support. Includes xchg() which is used in this code. */\r
+#include <machine.h>\r
+/* Includes board and MCU related header files. */\r
+#include "platform.h"\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Exported global variables (to be accessed by other files)\r
+***********************************************************************************************************************/\r
+ \r
+/***********************************************************************************************************************\r
+Private global variables and functions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_BSP_Lock\r
+* Description : Attempt to acquire the lock that has been sent in.\r
+* Arguments : plock -\r
+* Pointer to lock structure with lock to try and acquire.\r
+* Return Value : true -\r
+* Lock was acquired.\r
+* false -\r
+* Lock was not acquired.\r
+***********************************************************************************************************************/\r
+bool R_BSP_Lock(bsp_lock_t * plock)\r
+{\r
+ bool ret = false;\r
+\r
+ /* Variable used in trying to acquire lock. Using the xchg instruction makes this atomic */\r
+ int32_t is_locked = true;\r
+ \r
+ /* This example uses the RX MCU's atomic xchg() instruction. plock->lock is the lock we are trying to reserve. \r
+ The way this works is that 'is_locked' gets the value of the plock->lock and plock->lock gets the value of \r
+ 'is_locked' which we just set to 'true'. Basically this is an atomic 'swap' command. If the lock had not yet been \r
+ reserved then its value would be 'false' and after the xchg() instruction finished 'is_locked' would have \r
+ 'false'. If it had already been reserved then 'is_locked' would have 'true' after the xchg() instruction. Since \r
+ plock->lock was already 'true' and we just set it back to 'true' everything is ok. To see if we reserved the lock \r
+ we just need to check the value of 'is_locked' after this instruction finishes. */\r
+\r
+ /* Try to acquire semaphore to obtain lock */\r
+ xchg(&is_locked, &plock->lock);\r
+ \r
+ /* Check to see if semaphore was successfully taken */\r
+ if (is_locked == false)\r
+ { \r
+ /* Lock obtained, return success. */\r
+ ret = true;\r
+ }\r
+ else\r
+ {\r
+ /* Lock was not obtained, another task already has it. */\r
+ }\r
+\r
+ return ret; \r
+} /* End of function R_BSP_Lock() */\r
+\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_BSP_Unlock\r
+* Description : Release hold on lock.\r
+* Arguments : plock -\r
+* Pointer to lock structure with lock to release.\r
+* Return Value : true -\r
+* Lock was released.\r
+* false -\r
+* Lock was not released.\r
+***********************************************************************************************************************/\r
+bool R_BSP_Unlock(bsp_lock_t * plock)\r
+{\r
+ /* Set lock back to unlocked. */\r
+ plock->lock = false;\r
+\r
+ return true;\r
+} /* End of function R_BSP_Unlock() */\r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : locking.h\r
+* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so\r
+* common resources can be accessed safely.\r
+***********************************************************************************************************************/\r
+/**********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 07.03.2012 1.00 First Release\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Fixed-size integer typedefs. */\r
+#include <stdint.h>\r
+/* bool support. */\r
+#include <stdbool.h>\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+typedef struct\r
+{\r
+ /* The actual lock. int32_t is used because this is what the xchg() instruction takes as parameters. */\r
+ int32_t lock;\r
+ /* Could add a ID for locking and unlocking. In this could protect against any function being able to unlock. */\r
+} bsp_lock_t;\r
+\r
+/***********************************************************************************************************************\r
+Exported global variables\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Exported global functions (to be accessed by other files)\r
+***********************************************************************************************************************/\r
+bool R_BSP_Lock(bsp_lock_t * plock);\r
+bool R_BSP_Unlock(bsp_lock_t * plock);\r
+\r
+\r
+\r
+\r
--- /dev/null
+;-----------------------------------------------------------------------\r
+;\r
+; FILE :lowlvl.src\r
+; DATE :Wed, Jul 01, 2009\r
+; DESCRIPTION :Program of Low level\r
+; CPU TYPE :RX\r
+;\r
+;-----------------------------------------------------------------------\r
+ .GLB _charput\r
+ .GLB _charget\r
+\r
+FC2E0 .EQU 00084080h\r
+FE2C0 .EQU 00084090h\r
+DBGSTAT .EQU 000840C0h\r
+RXFL0EN .EQU 00001000h\r
+TXFL0EN .EQU 00000100h\r
+\r
+ .SECTION P,CODE\r
+\r
+;-----------------------------------------------------------------------\r
+; _charput:\r
+;-----------------------------------------------------------------------\r
+_charput:\r
+ .STACK _charput = 00000000h\r
+__C2ESTART: MOV.L #TXFL0EN,R3\r
+ MOV.L #DBGSTAT,R4\r
+__TXLOOP: MOV.L [R4],R5\r
+ AND R3,R5\r
+ BNZ __TXLOOP\r
+__WRITEFC2E0: MOV.L #FC2E0,R2\r
+ MOV.L R1,[R2]\r
+__CHARPUTEXIT: RTS\r
+\r
+;-----------------------------------------------------------------------\r
+; _charget:\r
+;-----------------------------------------------------------------------\r
+_charget:\r
+ .STACK _charget = 00000000h\r
+__E2CSTART: MOV.L #RXFL0EN,R3\r
+ MOV.L #DBGSTAT,R4\r
+__RXLOOP: MOV.L [R4],R5\r
+ AND R3,R5\r
+ BZ __RXLOOP\r
+__READFE2C0: MOV.L #FE2C0,R2\r
+ MOV.L [R2],R1\r
+__CHARGETEXIT: RTS\r
+\r
+;-----------------------------------------------------------------------\r
+\r
+; End of conditional code\r
+ .END\r
+\r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : lowsrc.c\r
+* Description : Functions to support stream I/O\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 26.10.2011 1.00 First Release\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+#include <string.h>\r
+#include <stdio.h>\r
+#include <stddef.h>\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/*Number of I/O Stream*/
+#define IOSTREAM 20
+
+/* file number */\r
+#define STDIN 0 /* Standard input (console) */\r
+#define STDOUT 1 /* Standard output (console) */\r
+#define STDERR 2 /* Standard error output (console) */\r
+\r
+#define FLMIN 0 /* Minimum file number */\r
+#define _MOPENR 0x1\r
+#define _MOPENW 0x2\r
+#define _MOPENA 0x4\r
+#define _MTRUNC 0x8\r
+#define _MCREAT 0x10\r
+#define _MBIN 0x20\r
+#define _MEXCL 0x40\r
+#define _MALBUF 0x40\r
+#define _MALFIL 0x80\r
+#define _MEOF 0x100\r
+#define _MERR 0x200\r
+#define _MLBF 0x400\r
+#define _MNBF 0x800\r
+#define _MREAD 0x1000\r
+#define _MWRITE 0x2000\r
+#define _MBYTE 0x4000\r
+#define _MWIDE 0x8000\r
+/* File Flags */\r
+#define O_RDONLY 0x0001 /* Read only */\r
+#define O_WRONLY 0x0002 /* Write only */\r
+#define O_RDWR 0x0004 /* Both read and Write */\r
+#define O_CREAT 0x0008 /* A file is created if it is not existed */\r
+#define O_TRUNC 0x0010 /* The file size is changed to 0 if it is existed. */\r
+#define O_APPEND 0x0020 /* The position is set for next reading/writing */\r
+ /* 0: Top of the file 1: End of file */\r
+\r
+/* Special character code */\r
+#define CR 0x0d /* Carriage return */\r
+#define LF 0x0a /* Line feed */\r
+\r
+#if defined( __RX )\r
+const long _nfiles = IOSTREAM; /* The number of files for input/output files */\r
+#else\r
+const int _nfiles = IOSTREAM; /* The number of files for input/output files */\r
+#endif\r
+char flmod[IOSTREAM]; /* The location for the mode of opened file. */\r
+\r
+unsigned char sml_buf[IOSTREAM];\r
+\r
+#define FPATH_STDIN "C:\\stdin"\r
+#define FPATH_STDOUT "C:\\stdout"\r
+#define FPATH_STDERR "C:\\stderr"\r
+\r
+/* H8 Normal mode ,SH and RX */\r
+#if defined( __2000N__ ) || defined( __2600N__ ) || defined( __300HN__ ) || defined( _SH )\r
+/* Output one character to standard output */\r
+extern void charput(char);\r
+/* Input one character from standard input */\r
+extern char charget(void);\r
+/* Output one character to the file */\r
+extern char fcharput(char, unsigned char);\r
+/* Input one character from the file */\r
+extern char fcharget(char*, unsigned char);\r
+/* Open the file */\r
+extern char fileopen(char*, unsigned char, unsigned char*);\r
+/* Close the file */\r
+extern char fileclose(unsigned char);\r
+/* Move the file offset */\r
+extern char fpseek(unsigned char, long, unsigned char);\r
+/* Get the file offset */\r
+extern char fptell(unsigned char, long*);\r
+\r
+/* RX */\r
+#elif defined( __RX )\r
+/* Output one character to standard output */\r
+extern void charput(unsigned char);\r
+/* Input one character from standard input */\r
+extern unsigned char charget(void);\r
+\r
+/* H8 Advanced mode */\r
+#elif defined( __2000A__ ) || defined( __2600A__ ) || defined( __300HA__ ) || defined( __H8SXN__ ) || defined( __H8SXA__ ) || defined( __H8SXM__ ) || defined( __H8SXX__ )\r
+/* Output one character to standard output */\r
+extern void charput(char);\r
+/* Input one character from standard input */\r
+extern char charget(void);\r
+/* Output one character to the file */\r
+extern char fcharput(char, unsigned char);\r
+/* Input one character from the file */\r
+extern char fcharget(char*, unsigned char);\r
+/* Open the file */\r
+/* Specified as the number of register which stored paramter is 3 */\r
+extern char __regparam3 fileopen(char*, unsigned char, unsigned char*);\r
+/* Close the file */\r
+extern char fileclose(unsigned char);\r
+/* Move the file offset */\r
+extern char fpseek(unsigned char, long, unsigned char);\r
+/* Get the file offset */\r
+extern char fptell(unsigned char, long*);\r
+\r
+/* H8300 and H8300L */\r
+#elif defined( __300__ ) || defined( __300L__ )\r
+/* Output one character to standard output */\r
+extern void charput(char);\r
+/* Input one character from standard input */\r
+extern char charget(void);\r
+/* Output one character to the file */\r
+extern char fcharput(char, unsigned char);\r
+/* Input one character from the file */\r
+extern char fcharget(char*, unsigned char);\r
+/* Open the file */\r
+/* Specified as the number of register which stored paramter is 3 */\r
+extern char __regparam3 fileopen(char*, unsigned char, unsigned char*);\r
+/* Close the file */\r
+extern char fileclose(unsigned char);\r
+/* Move the file offset */\r
+/* Move the file offset */\r
+extern char __regparam3 fpseek(unsigned char, long, unsigned char);\r
+/* Get the file offset */\r
+extern char fptell(unsigned char, long*);\r
+#endif\r
+\r
+#include <stdio.h>\r
+FILE *_Files[IOSTREAM]; // structure for FILE\r
+char *env_list[] = { // Array for environment variables(**environ)\r
+ "ENV1=temp01",\r
+ "ENV2=temp02",\r
+ "ENV9=end",\r
+ '\0' // Terminal for environment variables\r
+};\r
+\r
+char **environ = env_list;\r
+\r
+/****************************************************************************/\r
+/* _INIT_IOLIB */\r
+/* Initialize C library Functions, if necessary. */\r
+/* Define USES_SIMIO on Assembler Option. */\r
+/****************************************************************************/\r
+void _INIT_IOLIB( void )\r
+{\r
+ /* A file for standard input/output is opened or created. Each FILE */\r
+ /* structure members are initialized by the library. Each _Buf member */\r
+ /* in it is re-set the end of buffer pointer. */\r
+\r
+ /* Standard Input File */\r
+ if( freopen( FPATH_STDIN, "r", stdin ) == NULL )\r
+ stdin->_Mode = 0xffff; /* Not allow the access if it fails to open */\r
+ stdin->_Mode = _MOPENR; /* Read only attribute */\r
+ stdin->_Mode |= _MNBF; /* Non-buffering for data */\r
+ stdin->_Bend = stdin->_Buf + 1; /* Re-set pointer to the end of buffer */\r
+\r
+ /* Standard Output File */\r
+ if( freopen( FPATH_STDOUT, "w", stdout ) == NULL ) \r
+ stdout->_Mode = 0xffff; /* Not allow the access if it fails to open */\r
+ stdout->_Mode |= _MNBF; /* Non-buffering for data */\r
+ stdout->_Bend = stdout->_Buf + 1;/* Re-set pointer to the end of buffer */\r
+ \r
+ /* Standard Error File */\r
+ if( freopen( FPATH_STDERR, "w", stderr ) == NULL )\r
+ stderr->_Mode = 0xffff; /* Not allow the access if it fails to open */\r
+ stderr->_Mode |= _MNBF; /* Non-buffering for data */\r
+ stderr->_Bend = stderr->_Buf + 1;/* Re-set pointer to the end of buffer */\r
+}\r
+\r
+/****************************************************************************/\r
+/* _CLOSEALL */\r
+/****************************************************************************/\r
+void _CLOSEALL( void )\r
+{\r
+ long i;\r
+\r
+ for( i=0; i < _nfiles; i++ )\r
+ {\r
+ /* Checks if the file is opened or not */\r
+ if( _Files[i]->_Mode & (_MOPENR | _MOPENW | _MOPENA ) )\r
+ fclose( _Files[i] ); /* Closes the file */\r
+ }\r
+}\r
+\r
+/**************************************************************************/\r
+/* open:file open */\r
+/* Return value:File number (Pass) */\r
+/* -1 (Failure) */\r
+/**************************************************************************/\r
+#if defined( __RX )\r
+long open(const char *name, /* File name */\r
+ long mode, /* Open mode */\r
+ long flg) /* Open flag */\r
+#else\r
+int open(char *name, /* File name */\r
+ int mode, /* Open mode */\r
+ int flg) /* Open flag */\r
+#endif\r
+{\r
+\r
+\r
+ if( strcmp( name, FPATH_STDIN ) == 0 ) /* Standard Input file? */\r
+ {\r
+ if( ( mode & O_RDONLY ) == 0 ) return -1;\r
+ flmod[STDIN] = mode;\r
+ return STDIN;\r
+ }\r
+ else if( strcmp( name, FPATH_STDOUT ) == 0 )/* Standard Output file? */\r
+ {\r
+ if( ( mode & O_WRONLY ) == 0 ) return -1;\r
+ flmod[STDOUT] = mode;\r
+ return STDOUT;\r
+ }\r
+ else if(strcmp(name, FPATH_STDERR ) == 0 ) /* Standard Error file? */\r
+ {\r
+ if( ( mode & O_WRONLY ) == 0 ) return -1;\r
+ flmod[STDERR] = mode;\r
+ return STDERR;\r
+ }\r
+ else return -1; /*Others */\r
+}\r
+\r
+#if defined( __RX )\r
+long close( long fileno )\r
+#else\r
+int close( int fileno )\r
+#endif\r
+{\r
+ return 1;\r
+}\r
+\r
+/**************************************************************************/\r
+/* write:Data write */\r
+/* Return value:Number of write characters (Pass) */\r
+/* -1 (Failure) */\r
+/**************************************************************************/\r
+#if defined( __RX )\r
+long write(long fileno, /* File number */\r
+ const unsigned char *buf, /* The address of destination buffer */\r
+ long count) /* The number of chacter to write */\r
+#else\r
+int write(int fileno, /* File number */\r
+ char *buf, /* The address of destination buffer */\r
+ int count) /* The number of chacter to write */\r
+#endif\r
+{\r
+ long i; /* A variable for counter */\r
+ unsigned char c; /* An output character */\r
+\r
+ /* Checking the mode of file , output each character */\r
+ /* Checking the attribute for Write-Only, Read-Only or Read-Write */\r
+ if(flmod[fileno]&O_WRONLY || flmod[fileno]&O_RDWR)\r
+ {\r
+ if( fileno == STDIN ) return -1; /* Standard Input */\r
+ else if( (fileno == STDOUT) || (fileno == STDERR) ) \r
+ /* Standard Error/output */\r
+ {\r
+ for( i = count; i > 0; --i )\r
+ {\r
+ c = *buf++;\r
+ charput(c);\r
+ }\r
+ return count; /*Return the number of written characters */\r
+ }\r
+ else return -1; /* Incorrect file number */\r
+ }\r
+ else return -1; /* An error */\r
+}\r
+\r
+#if defined( __RX )\r
+long read( long fileno, unsigned char *buf, long count )\r
+#else\r
+int read( int fileno, char *buf, unsigned int count )\r
+#endif\r
+{\r
+ long i;\r
+\r
+ /* Checking the file mode with the file number, each character is input and stored the buffer */\r
+\r
+ if((flmod[fileno]&_MOPENR) || (flmod[fileno]&O_RDWR)){\r
+ for(i = count; i > 0; i--){\r
+ *buf = charget();\r
+ if(*buf==CR){ /* Replace the new line character */\r
+ *buf = LF;\r
+ }\r
+ buf++;\r
+ }\r
+ return count;\r
+ }\r
+ else {\r
+ return -1;\r
+ }\r
+}\r
+\r
+#if defined( __RX )\r
+long lseek( long fileno, long offset, long base )\r
+#else\r
+long lseek( int fileno, long offset, int base )\r
+#endif\r
+{\r
+ return -1L;\r
+}\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp.h\r
+* H/W Platform : RSKRX111\r
+* Description : Has the header files that should be included for this platform.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+#ifndef PLATFORM_BOARD_RSKRX111\r
+#define PLATFORM_BOARD_RSKRX111\r
+\r
+/* Make sure that no other platforms have already been defined. Do not touch this! */\r
+#ifdef PLATFORM_DEFINED\r
+#error "Error - Multiple platforms defined in platform.h!"\r
+#else\r
+#define PLATFORM_DEFINED\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+INCLUDE APPROPRIATE MCU AND BOARD FILES\r
+***********************************************************************************************************************/\r
+#include "r_bsp_config.h"\r
+#include ".\mcu\rx111\iodefine.h"\r
+#include ".\mcu\rx111\mcu_info.h"\r
+#include ".\board\rskrx111\rskrx111.h"\r
+#include ".\board\rskrx111\hwsetup.h"\r
+#include ".\board\rskrx111\lcd.h"\r
+#include ".\board\rskrx111\locking.h"\r
+#include ".\board\rskrx111\vecttbl.h"\r
+\r
+#endif /* PLATFORM_BOARD_RSKRX111 */\r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp_config_reference.c\r
+* Device(s) : RX111\r
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included\r
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)\r
+* is just a reference file that the user can use to make their own r_bsp_config.h file.\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description \r
+* : 07.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE\r
+#define R_BSP_CONFIG_REF_HEADER_FILE\r
+\r
+/***********************************************************************************************************************\r
+Configuration Options\r
+***********************************************************************************************************************/\r
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such \r
+ as package and memory size. \r
+ To help parse this information, the part number will be defined using multiple macros.\r
+ R 5 F 51 11 5 A D FM\r
+ | | | | | | | | | Macro Name Description\r
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch\r
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)\r
+ | | | | | | |______not used = Blank\r
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity\r
+ | | | | |___________MCU_PART_GROUP = Group name \r
+ | | | |______________MCU_PART_SERIES = Series name\r
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)\r
+ | |__________________not used = Renesas MCU\r
+ |____________________not used = Renesas semiconductor product. \r
+ */\r
+\r
+/* Package type. Set the macro definition based on values below:\r
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch\r
+ FM = 0x0 = LFQFP/64/0.50\r
+ FK = 0x1 = LQFP/64/0.80\r
+ LF = 0x2 = TFLGA/64/0.50\r
+ FL = 0x3 = LFQFP/48/0.50\r
+ NE = 0x4 = VQFN/48/0.50\r
+ NC = 0x5 = HWQFN/36/0.50\r
+ LM = 0x6 = WFLGA/36/0.50\r
+ SB = 0x7 = SSOP/36/0.80\r
+*/\r
+#define MCU_PART_PACKAGE (0x0)\r
+\r
+/* ROM, RAM, and Data Flash Capacity. \r
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size\r
+ 5 = 0x5 = 128KB/16KB/8KB\r
+ 4 = 0x4 = 96KB/16KB/8KB\r
+ 3 = 0x3 = 64KB/10KB/8KB\r
+ 1 = 0x1 = 32KB/10KB/8KB\r
+ J = 0x0 = 16KB/8KB/8KB\r
+*/\r
+#define MCU_PART_MEMORY_SIZE (0x5)\r
+\r
+/* Group name. \r
+ Character(s) = Value for macro = Description\r
+ 10 = 0x0 = RX110 Group\r
+ 11 = 0x1 = RX111 Group\r
+*/\r
+#define MCU_PART_GROUP (0x1)\r
+\r
+/* Series name. \r
+ Character(s) = Value for macro = Description\r
+ 51 = 0x0 = RX100 Series\r
+*/ \r
+#define MCU_PART_SERIES (0x0)\r
+\r
+/* Memory type. \r
+ Character(s) = Value for macro = Description\r
+ F = 0x0 = Flash memory version\r
+*/\r
+#define MCU_PART_MEMORY_TYPE (0x0)\r
+\r
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a \r
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */\r
+#if defined(BSP_DECLARE_STACK)\r
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize su=0x400\r
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize si=0x100\r
+#endif\r
+\r
+/* Heap size in bytes. */\r
+#define HEAP_BYTES (0x400)\r
+\r
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information\r
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.\r
+ 0 = Stay in Supervisor mode.\r
+ 1 = Switch to User mode.\r
+*/\r
+#define RUN_IN_USER_MODE (0)\r
+\r
+\r
+/* This macro lets other modules no if a RTOS is being used.\r
+ 0 = RTOS is not used. \r
+ 1 = RTOS is used.\r
+*/\r
+#define RTOS_USED (0)\r
+\r
+/* Clock source select (CKSEL).\r
+ 0 = Low Speed On-Chip Oscillator (LOCO)\r
+ 1 = High Speed On-Chip Oscillator (HOCO)\r
+ 2 = Main Clock Oscillator \r
+ 3 = Sub-Clock Oscillator\r
+ 4 = PLL Circuit\r
+*/ \r
+#define CLOCK_SOURCE (4)\r
+\r
+/* Clock configuration options.\r
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The\r
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the\r
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the\r
+ settings would be:\r
+\r
+ XTAL_HZ = 16000000\r
+ PLL_DIV = 2\r
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)\r
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz\r
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz\r
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz\r
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz\r
+*/\r
+/* XTAL - Input clock frequency in Hz */\r
+#define XTAL_HZ (16000000)\r
+/* PLL Input Frequency Divider Select (PLIDIV). \r
+ Available divisors = /1 (no division), /2, /4\r
+*/\r
+#define PLL_DIV (2)\r
+/* PLL Frequency Multiplication Factor Select (STC). \r
+ Available multipliers = x6, x8\r
+*/\r
+#define PLL_MUL (6)\r
+/* System Clock Divider (ICK).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define ICK_DIV (2)\r
+/* Peripheral Module Clock B Divider (PCKB). \r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKB_DIV (2)\r
+/* Peripheral Module Clock D Divider (PCKD). \r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKD_DIV (2)\r
+/* Flash IF Clock Divider (FCK). \r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define FCK_DIV (2)\r
+\r
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and \r
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a \r
+ function to be called when the event occurs. For example, if the user wanted the function \r
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would\r
+ do the following:\r
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+ If the user does not wish to be alerted of these events then they should comment out the macros.\r
+ \r
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function\r
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it\r
+ is executing. For this reason, it is recommended to keep these callback functions short as to not\r
+ decrease the real-time response of your system.\r
+*/\r
+/* Callback for Supervisor Instruction Violation Exception. */\r
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb\r
+\r
+/* Callback for Undefined Instruction Exception. */\r
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb\r
+\r
+/* Callback for Non-maskable Interrupt. */\r
+//#define NMI_ISR_CALLBACK nmi_cb\r
+\r
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source\r
+ is creating unwanted interrupts. */\r
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+\r
+/* Callback for Bus Error Interrupt. */\r
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb\r
+\r
+/* The user has the option of separately choosing little or big endian for the User Application Area */\r
+\r
+/* Endian mode for User Application.\r
+ 0 = Big Endian\r
+ Else = Little Endian (Default)\r
+*/ \r
+#define USER_APP_ENDIAN (1)\r
+\r
+\r
+/* Configure WDT and IWDT settings. \r
+ OFS0 - Option Function Select Register 0 \r
+ OFS0 - Option Function Select Register 0\r
+ b31:b15 Reserved (set to 1)\r
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)\r
+ b13 Reserved (set to 1)\r
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)\r
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)\r
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)\r
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)\r
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)\r
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)\r
+ b0 Reserved (set to 1) */\r
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.\r
+ OFS1 - Option Function Select Register 1\r
+ b31:b9 Reserved (set to 1)\r
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)\r
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select\r
+ 0 1 0 0: 3.10 V\r
+ 0 1 0 1: 3.00 V\r
+ 0 1 1 0: 2.90 V\r
+ 0 1 1 1: 2.79 V\r
+ 1 0 0 0: 2.68 V\r
+ 1 0 0 1: 2.58 V\r
+ 1 0 1 0: 2.48 V\r
+ 1 0 1 1: 2.06 V\r
+ 1 1 0 0: 1.96 V\r
+ 1 1 0 1: 1.86 V\r
+ b3:b2 Reserved (set to 1)\r
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)\r
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */\r
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Initializes C input & output library functions.\r
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.\r
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */\r
+#define IO_LIB_ENABLE (1)\r
+\r
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */\r
+\r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : resetprg.c\r
+* Device(s) : RX111\r
+* Description : Defines post-reset routines that are used to configure the MCU prior to the main program starting.\r
+* This is were the program counter starts on power-up or reset.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/
+/* Defines machine level functions used in this file */
+#include <machine.h>
+/* Defines MCU configuration functions used in this file */
+#include <_h_c_lib.h>
+/* Defines standard variable types used in this file */
+#include <stdbool.h>
+#include <stdint.h>\r
+\r
+/* This macro is here so that the stack will be declared here. This is used to prevent multiplication of stack size. */\r
+#define BSP_DECLARE_STACK\r
+/* Define the target platform */\r
+#include "platform.h"\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/
+#define PSW_init (0x00030000)
+
+/***********************************************************************************************************************
+Pre-processor Directives
+***********************************************************************************************************************/
+/* Declare the contents of the function 'Change_PSW_PM_to_UserMode' as assembler to the compiler */
+#pragma inline_asm Change_PSW_PM_to_UserMode
+\r
+/* Set this as the entry point from a power-on reset */
+#pragma entry PowerON_Reset_PC\r
+\r
+/***********************************************************************************************************************
+External function Prototypes
+***********************************************************************************************************************/
+/* Functions to setup I/O library */
+extern void _INIT_IOLIB(void);\r
+extern void _CLOSEALL(void);\r
+
+/***********************************************************************************************************************\r
+Private global variables and functions\r
+***********************************************************************************************************************/
+/* Power-on reset function declaration */
+void PowerON_Reset_PC(void);\r
+\r
+#if RUN_IN_USER_MODE==1\r
+ #if __RENESAS_VERSION__ < 0x01010000\r
+ /* MCU usermode switcher function declaration */
+ static void Change_PSW_PM_to_UserMode(void);\r
+ #endif
+#endif\r
+
+/* Main program function delcaration */
+void main(void);
+static void operating_frequency_set(void);\r
+static void clock_source_select(void);
+\r
+/***********************************************************************************************************************\r
+* Function name: PowerON_Reset_PC\r
+* Description : This function is the MCU's entry point from a power-on reset.\r
+* The following steps are taken in the startup code:\r
+* 1. The User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) are both set immediately after entry\r
+* to this function. The USP and ISP stack sizes are set in the file stacksct.h.\r
+* Default sizes are USP=4K and ISP=1K.\r
+* 2. The interrupt vector base register is set to point to the beginning of the relocatable interrupt\r
+* vector table.\r
+* 3. The MCU is setup for floating point operations by setting the initial value of the Floating Point\r
+* Status Word (FPSW).\r
+* 4. The MCU operating frequency is set by configuring the Clock Generation Circuit (CGC) in\r
+* operating_frequency_set.\r
+* 5. Calls are made to functions to setup the C runtime environment which involves initializing all\r
+* initialed data, zeroing all uninitialized variables, and configuring STDIO if used\r
+* (calls to _INITSCT and _INIT_IOLIB).\r
+* 6. Board-specific hardware setup, including configuring I/O pins on the MCU, in hardware_setup.\r
+* 7. Global interrupts are enabled by setting the I bit in the Program Status Word (PSW), and the stack\r
+* is switched from the ISP to the USP. The initial Interrupt Priority Level is set to zero, enabling\r
+* any interrupts with a priority greater than zero to be serviced.\r
+* 8. The processor is optionally switched to user mode. To run in user mode, set the macro\r
+* RUN_IN_USER_MODE above to a 1.\r
+* 9. The bus error interrupt is enabled to catch any accesses to invalid or reserved areas of memory.\r
+*\r
+* Once this initialization is complete, the user's main() function is called. It should not return.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+#pragma section ResetPRG // output PowerON_Reset to PResetPRG section\r
+void PowerON_Reset_PC(void)
+{\r
+ /* Stack pointers are setup prior to calling this function - see comments above */\r
+
+ /* Initialise the MCU processor word */
+#if __RENESAS_VERSION__ >= 0x01010000
+ set_intb((void *)__sectop("C$VECT"));
+#else
+ set_intb((unsigned long)__sectop("C$VECT"));
+#endif\r
+\r
+#ifdef NMI_ISR_CALLBACK\r
+ /* Enable NMI interrupt if callback is configured in r_bsp_config.h */\r
+ ICU.NMIER.BIT.NMIEN = 1;\r
+#endif\r
+\r
+ /* Switch to high-speed operation */\r
+ operating_frequency_set();
+
+ /* Initialize C runtime environment */
+ _INITSCT();
+\r
+#if IO_LIB_ENABLE == 1\r
+ /* Comment this out if not using I/O lib */\r
+ _INIT_IOLIB();\r
+#endif\r
+
+ /* Configure the MCU and YRDK hardware */
+ hardware_setup();
+
+ /* Change the MCU's usermode from supervisor to user */
+ nop();
+ set_psw(PSW_init);
+#if RUN_IN_USER_MODE==1\r
+ /* Use chg_pmusr() intrinsic if possible. */\r
+ #if __RENESAS_VERSION__ >= 0x01010000
+ chg_pmusr() ;\r
+ #else\r
+ Change_PSW_PM_to_UserMode();\r
+ #endif
+#endif\r
+\r
+ /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */\r
+ /* The ISR for this interrupt can be found in vecttbl.c in the function "bus_error_isr" */\r
+ /* Clear any pending interrupts */\r
+ IR(BSC,BUSERR) = 0;\r
+ /* Make this the highest priority interrupt (adjust as necessary for your application */\r
+ IPR(BSC,BUSERR) = 0x0F;\r
+ /* Enable the interrupt in the ICU*/\r
+ IEN(BSC,BUSERR) = 1;\r
+ /* Enable illegal address interrupt in the BSC */\r
+ BSC.BEREN.BIT.IGAEN = 1;\r
+\r
+ /* Call the main program function (should not return) */
+ main();\r
+\r
+#if IO_LIB_ENABLE == 1\r
+ /* Comment this out if not using I/O lib - cleans up open files */\r
+ _CLOSEALL();\r
+#endif\r
+
+ while(1)\r
+ {\r
+ /* Infinite loop. Put a breakpoint here if you want to catch an exit of main(). */\r
+ }\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name: operating_frequency_set\r
+* Description : Configures the clock settings for each of the device clocks\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void operating_frequency_set(void)
+{
+ /* Used for constructing value to write to SCKCR and CKOCR registers. */\r
+ uint32_t temp_clock = 0;\r
+
+ /*\r
+ Clock Description Frequency\r
+ ----------------------------------------\r
+ Input Clock Frequency............ 16 MHz\r
+ PLL frequency (x3)............... 48 MHz\r
+ Internal Clock Frequency......... 24 MHz\r
+ Peripheral Clock Frequency....... 24 MHz\r
+ Clock Out Frequency.............. 1 MHz */\r
+\r
+ volatile unsigned int i;\r
+\r
+ /* Protect off. */\r
+ SYSTEM.PRCR.WORD = 0xA50B;\r
+\r
+ /* Select the clock based upon user's choice. */\r
+ clock_source_select();\r
+\r
+\r
+ /* Figure out setting for FCK bits. */\r
+#if FCK_DIV == 1\r
+ /* Do nothing since FCK bits should be 0. */\r
+#elif FCK_DIV == 2\r
+ temp_clock |= 0x10000000;\r
+#elif FCK_DIV == 4\r
+ temp_clock |= 0x20000000;\r
+#elif FCK_DIV == 8\r
+ temp_clock |= 0x30000000;\r
+#elif FCK_DIV == 16\r
+ temp_clock |= 0x40000000;\r
+#elif FCK_DIV == 32\r
+ temp_clock |= 0x50000000;\r
+#elif FCK_DIV == 64\r
+ temp_clock |= 0x60000000;\r
+#else\r
+ #error "Error! Invalid setting for FCK_DIV in r_bsp_config.h"\r
+#endif\r
+\r
+ /* Figure out setting for ICK bits. */\r
+#if ICK_DIV == 1\r
+ /* Do nothing since ICK bits should be 0. */\r
+#elif ICK_DIV == 2\r
+ temp_clock |= 0x01000000;\r
+#elif ICK_DIV == 4\r
+ temp_clock |= 0x02000000;\r
+#elif ICK_DIV == 8\r
+ temp_clock |= 0x03000000;\r
+#elif ICK_DIV == 16\r
+ temp_clock |= 0x04000000;\r
+#elif ICK_DIV == 32\r
+ temp_clock |= 0x05000000;\r
+#elif ICK_DIV == 64\r
+ temp_clock |= 0x06000000;\r
+#else\r
+ #error "Error! Invalid setting for ICK_DIV in r_bsp_config.h"\r
+#endif\r
+\r
+ /* Figure out setting for PCKB bits. */\r
+#if PCKB_DIV == 1\r
+ /* Do nothing since PCKB bits should be 0. */\r
+#elif PCKB_DIV == 2\r
+ temp_clock |= 0x00000100;\r
+#elif PCKB_DIV == 4\r
+ temp_clock |= 0x00000200;\r
+#elif PCKB_DIV == 8\r
+ temp_clock |= 0x00000300;\r
+#elif PCKB_DIV == 16\r
+ temp_clock |= 0x00000400;\r
+#elif PCKB_DIV == 32\r
+ temp_clock |= 0x00000500;\r
+#elif PCKB_DIV == 64\r
+ temp_clock |= 0x00000600;\r
+#else\r
+ #error "Error! Invalid setting for PCKB_DIV in r_bsp_config.h"\r
+#endif\r
+\r
+ /* Figure out setting for PCKD bits. */\r
+#if PCKD_DIV == 1\r
+ /* Do nothing since PCKD bits should be 0. */\r
+#elif PCKD_DIV == 2\r
+ temp_clock |= 0x00000001;\r
+#elif PCKD_DIV == 4\r
+ temp_clock |= 0x00000002;\r
+#elif PCKD_DIV == 8\r
+ temp_clock |= 0x00000003;\r
+#elif PCKD_DIV == 16\r
+ temp_clock |= 0x00000004;\r
+#elif PCKD_DIV == 32\r
+ temp_clock |= 0x00000005;\r
+#elif PCKD_DIV == 64\r
+ temp_clock |= 0x00000006;\r
+#else\r
+ #error "Error! Invalid setting for PCKD_DIV in r_bsp_config.h"\r
+#endif\r
+\r
+ /* Set SCKCR register. */\r
+ SYSTEM.SCKCR.LONG = temp_clock;\r
+\r
+ /* Choose clock source. Default for r_bsp_config.h is PLL. */\r
+ SYSTEM.SCKCR3.WORD = ((uint16_t)CLOCK_SOURCE) << 8;\r
+\r
+ /* Protect on. */\r
+ SYSTEM.PRCR.WORD = 0xA500;
+}
+\r
+/***********************************************************************************************************************\r
+* Function name: clock_source_select\r
+* Description : Enables and disables clocks as chosen by the user. This function also implements the software delays\r
+* needed for the clocks to stabilize.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+static void clock_source_select (void)\r
+{\r
+ /* Declared volatile for software delay purposes. */\r
+ volatile unsigned int i;\r
+\r
+ /* NOTE: AS OF VERSION 0.50 OF THE RX111 HARDWARE MANUAL, ALL OF THE CLOCK\r
+ * STABILIZATION TIMES ARE TBD. FOR NOW, WHERE EVER A WAIT COUNT REGISTER\r
+ * IS AVAILABLE, THE DELAY IS SET TO THE MAX NUMBER OF CYCLES. WHERE EVER\r
+ * DELAY LOOPS ARE PRESENT, THE VALUES FROM THE 63N ARE RE-USED. KEEP IN\r
+ * MIND THAT THE 63N RUNS ON A FASTER CRYSTAL.\r
+ */\r
+\r
+#if (CLOCK_SOURCE == 1)\r
+ /* HOCO is chosen. Start it operating. */\r
+ SYSTEM.HOCOCR.BYTE = 0x00;\r
+ /* The delay period needed is to make sure that the HOCO has stabilized.*/\r
+ for(i = 0; i< 28; i++) // tHOCOWT2 is TBD\r
+ {\r
+ nop() ;\r
+ }\r
+#else\r
+ /* HOCO is not chosen. Stop the HOCO. */\r
+ SYSTEM.HOCOCR.BYTE = 0x01;\r
+#endif\r
+\r
+#if (CLOCK_SOURCE == 2)\r
+ /* Main clock oscillator is chosen. Start it operating. */\r
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles\r
+ /* Set the main clock to operating. */\r
+ SYSTEM.MOSCCR.BYTE = 0x00;\r
+ /* The delay period needed is to make sure that the main clock has stabilized. */\r
+ for(i = 0; i< 140; i++) // tMAINOSCWT is TBD\r
+ {\r
+ nop() ;\r
+ }\r
+#endif\r
+\r
+#if (CLOCK_SOURCE == 3)\r
+ /* Sub-clock oscillator is chosen. Start it operating. */\r
+ /* In section 9.8.4, there is a reference to a SOSCWTCR register, but there is no\r
+ * description for this register in the manual nor reference for it in iodefine.h. */\r
+\r
+ /* Set the sub-clock to operating. */\r
+ SYSTEM.SOSCCR.BYTE = 0x00;\r
+ /* The delay period needed is to make sure that the sub-clock has stabilized. */\r
+ for(i = 0; i< 30233; i++) // tSUBOSCWT0 is TBD\r
+ {\r
+ nop() ;\r
+ }\r
+#else\r
+ /* Set the sub-clock to stopped. */\r
+ SYSTEM.SOSCCR.BYTE = 0x01;\r
+#endif\r
+\r
+#if (CLOCK_SOURCE == 4)\r
+ /* PLL is chosen. Start it operating. Must start main clock as well since PLL uses it. */\r
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles\r
+ /* Set the main clock to operating. */\r
+ SYSTEM.MOSCCR.BYTE = 0x00;\r
+\r
+ /* Set PLL Input Divisor. */\r
+ SYSTEM.PLLCR.BIT.PLIDIV = PLL_DIV >> 1;\r
+\r
+ /* Set PLL Multiplier. */\r
+ SYSTEM.PLLCR.BIT.STC = (PLL_MUL * 2) - 1;\r
+\r
+ /* Set the PLL to operating. */\r
+ SYSTEM.PLLCR2.BYTE = 0x00;\r
+ /* The delay period needed is to make sure that the main clock and PLL have stabilized. */\r
+ for(i = 0; i< 140; i++) // tPLLWT2 is TBD\r
+ {\r
+ nop() ;\r
+ }\r
+#endif\r
+\r
+ /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn\r
+ it off until another clock has been enabled and is ready to use. */\r
+#if (CLOCK_SOURCE == 0)\r
+ /* LOCO is chosen. This is the default out of reset. */\r
+ SYSTEM.LOCOCR.BYTE = 0x00;\r
+#else\r
+ /* LOCO is not chosen and another clock has already been setup. Turn off the LOCO. */\r
+ SYSTEM.LOCOCR.BYTE = 0x01;\r
+#endif\r
+\r
+ /* Make sure a valid clock was chosen. */\r
+#if (CLOCK_SOURCE > 4) || (CLOCK_SOURCE < 0)\r
+ #error "ERROR - Valid clock source must be chosen in r_bsp_config.h using CLOCK_SOURCE macro."\r
+#endif\r
+}\r
+\r
+\r
+/***********************************************************************************************************************\r
+* Function name: Change_PSW_PM_to_UserMode\r
+* Description : Assembler function, used to change the MCU's usermode from supervisor to user.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+#if RUN_IN_USER_MODE==1\r
+ #if __RENESAS_VERSION__ < 0x01010000
+static void Change_PSW_PM_to_UserMode(void)
+{
+ MVFC PSW,R1
+ OR #00100000h,R1
+ PUSH.L R1
+ MVFC PC,R1
+ ADD #10,R1
+ PUSH.L R1
+ RTE
+ NOP
+ NOP
+}\r
+ #endif
+#endif\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : rskrx111.h\r
+* H/W Platform : RSKRX111\r
+* Description : Board specific definitions for the RSKRX111.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+#ifndef RSKRX111_H
+#define RSKRX111_H
+
+/* Local defines */
+#define LED_ON (0)
+#define LED_OFF (1)
+#define SET_BIT_HIGH (1)
+#define SET_BIT_LOW (0)
+#define SET_BYTE_HIGH (0xFF)
+#define SET_BYTE_LOW (0x00)\r
+\r
+/* Switches */\r
+#define SW_ACTIVE 0\r
+#define SW1 PORT3.PIDR.BIT.B0\r
+#define SW2 PORT3.PIDR.BIT.B1\r
+#define SW3 PORTE.PIDR.BIT.B4\r
+#define SW1_PDR PORT3.PDR.BIT.B0\r
+#define SW2_PDR PORT3.PDR.BIT.B1\r
+#define SW3_PDR PORTE.PDR.BIT.B4\r
+#define SW1_PMR PORT3.PMR.BIT.B0\r
+#define SW2_PMR PORT3.PMR.BIT.B1\r
+#define SW3_PMR PORTE.PMR.BIT.B4\r
+\r
+/* LEDs */\r
+#define LED0 PORTB.PODR.BIT.B7\r
+#define LED1 PORTA.PODR.BIT.B0\r
+#define LED2 PORT5.PODR.BIT.B4\r
+#define LED3 PORT1.PODR.BIT.B7\r
+#define LED0_PDR PORTB.PDR.BIT.B7\r
+#define LED1_PDR PORTA.PDR.BIT.B0\r
+#define LED2_PDR PORT5.PDR.BIT.B4\r
+#define LED3_PDR PORT1.PDR.BIT.B7\r
+\r
+
+#endif /* RSKRX111_H */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : sbrk.c\r
+* Device(s) : RX\r
+* Description : Configures the MCU heap memory. The size of the heap is defined by the macro HEAPSIZE below.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 26.10.2011 1.00 First Release\r
+* : 12.03.2012 1.10 Heap size is now defined in r_bsp_config.h, not sbrk.h.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Provides standard definitions used in this file */
+#include <stddef.h>
+/* Defines standard input/output functions used in this file */
+#include <stdio.h>
+/* Defines standard variable types used in this file */
+#include <stdint.h>\r
+/* Used for getting HEAP_BYTES macro. */\r
+#include "platform.h"
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+
+/***********************************************************************************************************************
+Function Prototypes
+***********************************************************************************************************************/
+/* Memory allocation function prototype declaration */
+int8_t *sbrk(size_t size);
+
+/***********************************************************************************************************************
+Global Variables
+***********************************************************************************************************************/
+//const size_t _sbrk_size= /* Specifies the minimum unit of */
+/* the defined heap area */
+extern int8_t *_s1ptr;
+
+union HEAP_TYPE
+{
+ int32_t dummy; /* Dummy for 4-byte boundary */
+ int8_t heap[HEAP_BYTES]; /* Declaration of the area managed by sbrk*/\r
+};
+/* Declare memory heap area */
+static union HEAP_TYPE heap_area;
+/* End address allocated by sbrk */
+static int8_t *brk=(int8_t *)&heap_area;
+
+/***********************************************************************************************************************\r
+* Function name: sbrk\r
+* Description : This function configures MCU memory area allocation.\r
+* Arguments : size - \r
+* assigned area size\r
+* Return value : Start address of allocated area (pass)\r
+* -1 (failure)\r
+***********************************************************************************************************************/\r
+int8_t *sbrk(size_t size)
+{
+ int8_t *p;
+
+ if (brk+size > heap_area.heap+HEAP_BYTES)
+ {
+ /* Empty area size */
+ p = (int8_t *)-1;
+ }
+ else
+ {
+ /* Area assignment */
+ p = brk;
+
+ /* End address update */
+ brk += size;
+ }
+
+ /* Return result */
+ return p;
+}
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : vecttbl.c\r
+* Device(s) : RX11x\r
+* Description : Definition of the fixed vector table and option setting memory.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Fixed size integers. */\r
+#include <stdint.h>\r
+/* Used for nop(). */\r
+#include <machine.h>\r
+/* BSP configuration. */\r
+#include "platform.h"\r
+\r
+#pragma section IntPRG\r
+\r
+/***********************************************************************************************************************\r
+* Function name: PowerON_Reset_PC\r
+* Description : The reset vector points to this function. Code execution starts in this function after reset.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+extern void PowerON_Reset_PC(void);\r
+\r
+/***********************************************************************************************************************\r
+* Function name: excep_supervisor_inst_isr\r
+* Description : Supervisor Instruction Violation ISR\r
+* Arguments : none\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+#pragma interrupt (excep_supervisor_inst_isr)\r
+void excep_supervisor_inst_isr(void)\r
+{\r
+ /* If the user defined a callback function in r_bsp_config.h then it will be called here. */\r
+#if defined(EXCEP_SUPERVISOR_ISR_CALLBACK)\r
+ EXCEP_SUPERVISOR_ISR_CALLBACK();\r
+\r
+ /* If you do not put the MCU in Supervisor mode before returning then it will just execute the same violating\r
+ instruction again and come back in here. Since the PSW is restored from the stack when returning from the\r
+ exception, you would need to alter the saved PSW on the stack to change to Supervisor mode. We do not do this\r
+ here because the only 'safe' way to do this would be to write this function in assembly. Even then most users\r
+ would probably want to handle this someway instead of just going back to the application. */\r
+#else\r
+ brk();\r
+#endif\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name: excep_undefined_inst_isr\r
+* Description : Undefined instruction exception ISR\r
+* Arguments : none\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+#pragma interrupt (excep_undefined_inst_isr)\r
+void excep_undefined_inst_isr(void)\r
+{\r
+ /* If the user defined a callback function in r_bsp_config.h then it will be called here. */\r
+#if defined(EXCEP_UNDEFINED_INSTR_ISR_CALLBACK)\r
+ EXCEP_UNDEFINED_INSTR_ISR_CALLBACK();\r
+#else\r
+ brk();\r
+#endif\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name: non_maskable_isr\r
+* Description : Non-maskable interrupt ISR\r
+* Arguments : none\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+#pragma interrupt (non_maskable_isr)\r
+void non_maskable_isr(void)\r
+{\r
+ /* If the user defined a callback function in r_bsp_config.h then it will be called here. */\r
+#if defined(NMI_ISR_CALLBACK)\r
+ NMI_ISR_CALLBACK();\r
+\r
+ /* Clear NMI flag. */\r
+ ICU.NMICLR.BIT.NMICLR = 1;\r
+#else\r
+ brk();\r
+#endif\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name: undefined_interrupt_source_isr\r
+* Description : All undefined interrupt vectors point to this function.\r
+* Set a breakpoint in this function to determine which source is creating unwanted interrupts.\r
+* Arguments : none\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+#pragma interrupt (undefined_interrupt_source_isr)\r
+void undefined_interrupt_source_isr(void)\r
+{\r
+ /* If the user defined a callback function in r_bsp_config.h then it will be called here. */\r
+#if defined(UNDEFINED_INT_ISR_CALLBACK)\r
+ UNDEFINED_INT_ISR_CALLBACK();\r
+#else\r
+ brk();\r
+#endif\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* Function name: bus_error_isr\r
+* Description : By default, this demo code enables the Bus Error Interrupt. This interrupt will fire if the user tries\r
+* to access code or data from one of the reserved areas in the memory map, including the areas covered\r
+* by disabled chip selects. A nop() statement is included here as a convenient place to set a breakpoint\r
+* during debugging and development, and further handling should be added by the user for their\r
+* application.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+#pragma interrupt (bus_error_isr(vect=VECT(BSC,BUSERR)))\r
+void bus_error_isr (void)\r
+{\r
+ /* Clear the bus error */\r
+ BSC.BERCLR.BIT.STSCLR = 1;\r
+\r
+ /*\r
+ To find the address that was accessed when the bus error occurred, read the register BSC.BERSR2.WORD. The upper\r
+ 13 bits of this register contain the upper 13-bits of the offending address (in 512K byte units)\r
+ */\r
+\r
+ /* If the user defined a callback function in r_bsp_config.h then it will be called here. */\r
+#if defined(BUS_ERROR_ISR_CALLBACK)\r
+ BUS_ERROR_ISR_CALLBACK();\r
+#else\r
+ nop();\r
+#endif\r
+}\r
+\r
+void Dummy( void )\r
+{\r
+ brk();\r
+}\r
+\r
+/***********************************************************************************************************************\r
+* The following array fills in the endian and option function select registers, and the fixed vector table\r
+* bytes.\r
+***********************************************************************************************************************/\r
+#pragma section C FIXEDVECT\r
+\r
+void (*const Fixed_Vectors[])(void) = {\r
+//;0xffffffd0 Exception(Supervisor Instruction)\r
+ excep_supervisor_inst_isr,\r
+//;0xffffffd4 Reserved\r
+ Dummy,\r
+//;0xffffffd8 Reserved\r
+ Dummy,\r
+//;0xffffffdc Exception(Undefined Instruction)\r
+ undefined_interrupt_source_isr,\r
+//;0xffffffe0 Reserved\r
+ Dummy,\r
+//;0xffffffe4 Reserved\r
+ Dummy,\r
+//;0xffffffe8 Reserved\r
+ Dummy,\r
+//;0xffffffec Reserved\r
+ Dummy,\r
+//;0xfffffff0 Reserved\r
+ Dummy,\r
+//;0xfffffff4 Reserved\r
+ Dummy,\r
+//;0xfffffff8 NMI\r
+ non_maskable_isr,\r
+//;0xfffffffc RESET\r
+//;<<VECTOR DATA START (POWER ON RESET)>>\r
+//;Power On Reset PC\r
+PowerON_Reset_PC\r
+//;<<VECTOR DATA END (POWER ON RESET)>>\r
+};\r
+\r
+#pragma address _MDEreg=0xffffff80 // MDE register (Single Chip Mode)\r
+#ifdef __BIG\r
+ const unsigned long _MDEreg = 0xfffffff8; // big\r
+#else\r
+ const unsigned long _MDEreg = 0xffffffff; // little\r
+#endif\r
+\r
+\r
+\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : vecttbl.h\r
+* Device(s) : RX111\r
+* Description : Has function prototypes for exception callback functions.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 1.20 Beta Release.\r
+***********************************************************************************************************************/\r
+\r
+#ifndef VECTTBL_HEADER_INC\r
+#define VECTTBL_HEADER_INC\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Fixed size integers. */\r
+#include <stdint.h>\r
+/* Used for nop(). */\r
+#include <machine.h>\r
+/* BSP configuration. */\r
+#include "platform.h"\r
+\r
+/***********************************************************************************************************************\r
+Exported global functions (to be accessed by other files)\r
+***********************************************************************************************************************/\r
+#if defined(EXCEP_SUPERVISOR_ISR_CALLBACK)\r
+void EXCEP_SUPERVISOR_ISR_CALLBACK(void);\r
+#endif\r
+\r
+#if defined(EXCEP_UNDEFINED_INSTR_ISR_CALLBACK)\r
+void EXCEP_UNDEFINED_INSTR_ISR_CALLBACK(void);\r
+#endif\r
+\r
+#if defined(NMI_ISR_CALLBACK)\r
+void NMI_ISR_CALLBACK(void);\r
+#endif\r
+\r
+#if defined(UNDEFINED_INT_ISR_CALLBACK)\r
+void UNDEFINED_INT_ISR_CALLBACK(void);\r
+#endif\r
+\r
+#if defined(BUS_ERROR_ISR_CALLBACK)\r
+void BUS_ERROR_ISR_CALLBACK(void);\r
+#endif\r
+\r
+#endif /* VECTTBL_HEADER_INC */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp.h \r
+* Description : Has the header files that should be included for this platform.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 13.01.2012 1.00 First Release\r
+* : 27.06.2012 1.10 Updated with new information to reflect udpated r_bsp structure.\r
+***********************************************************************************************************************/\r
+\r
+#ifndef PLATFORM_BOARD_USER\r
+#define PLATFORM_BOARD_USER\r
+\r
+/* Make sure that no other platforms have already been defined. Do not touch this! */\r
+#ifdef PLATFORM_DEFINED\r
+#error "Error - Multiple platforms defined in platform.h!"\r
+#else\r
+#define PLATFORM_DEFINED\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+INCLUDE APPROPRIATE MCU AND BOARD FILES\r
+***********************************************************************************************************************/\r
+/* This is a user defined board. Start off by:\r
+ 1)Copy and rename one of the 'board' folders that most closely matches your system (same MCU Series and Group).\r
+ 2)Substitute in your MCU Group for the *MCU Group* option in the #include below for mcu_info.h.\r
+ 3)Copy the other #includes from the r_bsp.h in the 'board' folder that you copied earlier.\r
+ 4)Configure the BSP for your board by modifying the r_bsp_config_reference.h.\r
+ 5)Copy r_bsp_config_reference.h to your project directory and rename it r_bsp_config.h.\r
+ You can also add your own include files here as well. */\r
+#include "r_bsp_config.h"\r
+#include ".\mcu\*MCU Group*\mcu_info.h" \r
+\r
+#endif /* PLATFORM_BOARD_USER */\r
+\r
+\r
--- /dev/null
+/********************************************************************************/\r
+/* */\r
+/* Device : RX/RX100/RX111 */\r
+/* File Name : iodefine.h */\r
+/* Abstract : Definition of I/O Register. */\r
+/* History : V0.5 (2012-09-25) [Hardware Manual Revision : 0.50] */\r
+/* Note : This is a typical example. */\r
+/* */\r
+/* Copyright(c) 2012 Renesas Electronics Corp. */\r
+/* And Renesas Solutions Corp. ,All Rights Reserved. */\r
+/* */\r
+/********************************************************************************/\r
+/* */\r
+/* DESCRIPTION : Definition of ICU Register */\r
+/* CPU TYPE : RX111 */\r
+/* */\r
+/* Usage : IR,DTCER,IER,IPR of ICU Register */\r
+/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */\r
+/* The bit access operation is "Bit_Name(interrupt source,name)". */\r
+/* A part of the name can be omitted. */\r
+/* for example : */\r
+/* IR(MTU0,TGIA0) = 0; expands to : */\r
+/* ICU.IR[114].BIT.IR = 0; */\r
+/* */\r
+/* DTCE(ICU,IRQ0) = 1; expands to : */\r
+/* ICU.DTCER[64].BIT.DTCE = 1; */\r
+/* */\r
+/* IEN(CMT0,CMI0) = 1; expands to : */\r
+/* ICU.IER[0x03].BIT.IEN4 = 1; */\r
+/* */\r
+/* IPR(MTU1,TGIA1) = 2; expands to : */\r
+/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */\r
+/* ICU.IPR[121].BIT.IPR = 2; */\r
+/* */\r
+/* IPR(SCI1,ERI1) = 3; expands to : */\r
+/* IPR(SCI1, ) = 3; // SCI1 uses single IPR for all sources. */\r
+/* ICU.IPR[218].BIT.IPR = 3; */\r
+/* */\r
+/* Usage : #pragma interrupt Function_Identifier(vect=**) */\r
+/* The number of vector is "(interrupt source, name)". */\r
+/* for example : */\r
+/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */\r
+/* #pragma interrupt INT_IRQ0(vect=64) */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=28) */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */\r
+/* */\r
+/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */\r
+/* The bit access operation is "MSTP(name)". */\r
+/* The name that can be used is a macro name defined with "iodefine.h". */\r
+/* for example : */\r
+/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */\r
+/* */\r
+/* */\r
+/********************************************************************************/\r
+#ifndef __RX111IODEFINE_HEADER__\r
+#define __RX111IODEFINE_HEADER__\r
+#pragma bit_order left\r
+#pragma unpack\r
+struct st_bsc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char STSCLR:1;\r
+ } BIT;\r
+ } BERCLR;\r
+ char wk0[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IGAEN:1;\r
+ } BIT;\r
+ } BEREN;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MST:3;\r
+ unsigned char :3;\r
+ unsigned char IA:1;\r
+ } BIT;\r
+ } BERSR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADDR:13;\r
+ } BIT;\r
+ } BERSR2;\r
+ char wk3[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short BPFB:2;\r
+ unsigned short :2;\r
+ unsigned short BPGB:2;\r
+ unsigned short BPIB:2;\r
+ unsigned short BPRO:2;\r
+ unsigned short BPRA:2;\r
+ } BIT;\r
+ } BUSPRI;\r
+};\r
+\r
+struct st_cac {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CFME:1;\r
+ } BIT;\r
+ } CACR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char EDGES:2;\r
+ unsigned char TCSS:2;\r
+ unsigned char FMCS:3;\r
+ unsigned char CACREFE:1;\r
+ } BIT;\r
+ } CACR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DFS:2;\r
+ unsigned char RCDS:2;\r
+ unsigned char RSCS:3;\r
+ unsigned char RPS:1;\r
+ } BIT;\r
+ } CACR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char OVFFCL:1;\r
+ unsigned char MENDFCL:1;\r
+ unsigned char FERRFCL:1;\r
+ unsigned char :1;\r
+ unsigned char OVFIE:1;\r
+ unsigned char MENDIE:1;\r
+ unsigned char FERRIE:1;\r
+ } BIT;\r
+ } CAICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char OVFF:1;\r
+ unsigned char MENDF:1;\r
+ unsigned char FERRF:1;\r
+ } BIT;\r
+ } CASTR;\r
+ char wk0[1];\r
+ unsigned short CAULVR;\r
+ unsigned short CALLVR;\r
+ unsigned short CACNTBR;\r
+};\r
+\r
+struct st_cmt {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :14;\r
+ unsigned short STR1:1;\r
+ unsigned short STR0:1;\r
+ } BIT;\r
+ } CMSTR0;\r
+};\r
+\r
+struct st_cmt0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :9;\r
+ unsigned short CMIE:1;\r
+ unsigned short :4;\r
+ unsigned short CKS:2;\r
+ } BIT;\r
+ } CMCR;\r
+ unsigned short CMCNT;\r
+ unsigned short CMCOR;\r
+};\r
+\r
+struct st_crc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DORCLR:1;\r
+ unsigned char :4;\r
+ unsigned char LMS:1;\r
+ unsigned char GPS:2;\r
+ } BIT;\r
+ } CRCCR;\r
+ unsigned char CRCDIR;\r
+ unsigned short CRCDOR;\r
+};\r
+\r
+struct st_da {\r
+ unsigned short DADR0;\r
+ unsigned short DADR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAOE1:1;\r
+ unsigned char DAOE0:1;\r
+ } BIT;\r
+ } DACR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSEL:1;\r
+ } BIT;\r
+ } DADPR;\r
+};\r
+\r
+struct st_doc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char DOPCFCL:1;\r
+ unsigned char DOPCF:1;\r
+ unsigned char DOPCIE:1;\r
+ unsigned char :1;\r
+ unsigned char DCSEL:1;\r
+ unsigned char OMS:2;\r
+ } BIT;\r
+ } DOCR;\r
+ char wk0[1];\r
+ unsigned short DODIR;\r
+ unsigned short DODSR;\r
+};\r
+\r
+struct st_dtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char RRS:1;\r
+ } BIT;\r
+ } DTCCR;\r
+ char wk0[3];\r
+ void *DTCVBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SHORT:1;\r
+ } BIT;\r
+ } DTCADMOD;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCST:1;\r
+ } BIT;\r
+ } DTCST;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ACT:1;\r
+ unsigned short :7;\r
+ unsigned short VECN:8;\r
+ } BIT;\r
+ } DTCSTS;\r
+};\r
+\r
+struct st_elc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ELCON:1;\r
+ } BIT;\r
+ } ELCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ELS:8;\r
+ } BIT;\r
+ } ELSR[26];\r
+ char wk0[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTU3MD:2;\r
+ unsigned char MTU2MD:2;\r
+ unsigned char MTU1MD:2;\r
+ } BIT;\r
+ } ELOPA;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char MTU4MD:2;\r
+ } BIT;\r
+ } ELOPB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char CMT1MD:2;\r
+ } BIT;\r
+ } ELOPC;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PGR7:1;\r
+ unsigned char PGR6:1;\r
+ unsigned char PGR5:1;\r
+ unsigned char PGR4:1;\r
+ unsigned char PGR3:1;\r
+ unsigned char PGR2:1;\r
+ unsigned char PGR1:1;\r
+ unsigned char PGR0:1;\r
+ } BIT;\r
+ } PGR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PGCO:3;\r
+ unsigned char :1;\r
+ unsigned char PGCOVE:1;\r
+ unsigned char PGCI:2;\r
+ } BIT;\r
+ } PGC1;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PDBF7:1;\r
+ unsigned char PDBF6:1;\r
+ unsigned char PDBF5:1;\r
+ unsigned char PDBF4:1;\r
+ unsigned char PDBF3:1;\r
+ unsigned char PDBF2:1;\r
+ unsigned char PDBF1:1;\r
+ unsigned char PDBF0:1;\r
+ } BIT;\r
+ } PDBF1;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSM:2;\r
+ unsigned char PSP:2;\r
+ unsigned char PSB:3;\r
+ } BIT;\r
+ } PEL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSM:2;\r
+ unsigned char PSP:2;\r
+ unsigned char PSB:3;\r
+ } BIT;\r
+ } PEL1;\r
+ char wk5[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char WI:1;\r
+ unsigned char WE:1;\r
+ unsigned char :5;\r
+ unsigned char SEG:1;\r
+ } BIT;\r
+ } ELSEGR;\r
+};\r
+\r
+struct st_flash {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DFLEN:1;\r
+ } BIT;\r
+ } DFLCTL;\r
+};\r
+\r
+struct st_icu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IR:1;\r
+ } BIT;\r
+ } IR[250];\r
+ char wk0[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCE:1;\r
+ } BIT;\r
+ } DTCER[249];\r
+ char wk1[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IEN7:1;\r
+ unsigned char IEN6:1;\r
+ unsigned char IEN5:1;\r
+ unsigned char IEN4:1;\r
+ unsigned char IEN3:1;\r
+ unsigned char IEN2:1;\r
+ unsigned char IEN1:1;\r
+ unsigned char IEN0:1;\r
+ } BIT;\r
+ } IER[32];\r
+ char wk2[192];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SWINT:1;\r
+ } BIT;\r
+ } SWINTR;\r
+ char wk3[15];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FIEN:1;\r
+ unsigned short :7;\r
+ unsigned short FVCT:8;\r
+ } BIT;\r
+ } FIR;\r
+ char wk4[14];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IPR:4;\r
+ } BIT;\r
+ } IPR[250];\r
+ char wk5[262];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IRQMD:2;\r
+ } BIT;\r
+ } IRQCR[8];\r
+ char wk6[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FLTEN7:1;\r
+ unsigned char FLTEN6:1;\r
+ unsigned char FLTEN5:1;\r
+ unsigned char FLTEN4:1;\r
+ unsigned char FLTEN3:1;\r
+ unsigned char FLTEN2:1;\r
+ unsigned char FLTEN1:1;\r
+ unsigned char FLTEN0:1;\r
+ } BIT;\r
+ } IRQFLTE0;\r
+ char wk7[3];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FCLKSEL7:2;\r
+ unsigned short FCLKSEL6:2;\r
+ unsigned short FCLKSEL5:2;\r
+ unsigned short FCLKSEL4:2;\r
+ unsigned short FCLKSEL3:2;\r
+ unsigned short FCLKSEL2:2;\r
+ unsigned short FCLKSEL1:2;\r
+ unsigned short FCLKSEL0:2;\r
+ } BIT;\r
+ } IRQFLTC0;\r
+ char wk8[106];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2ST:1;\r
+ unsigned char LVD1ST:1;\r
+ unsigned char IWDTST:1;\r
+ unsigned char :1;\r
+ unsigned char OSTST:1;\r
+ unsigned char NMIST:1;\r
+ } BIT;\r
+ } NMISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2EN:1;\r
+ unsigned char LVD1EN:1;\r
+ unsigned char IWDTEN:1;\r
+ unsigned char :1;\r
+ unsigned char OSTEN:1;\r
+ unsigned char NMIEN:1;\r
+ } BIT;\r
+ } NMIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2CLR:1;\r
+ unsigned char LVD1CLR:1;\r
+ unsigned char IWDTCLR:1;\r
+ unsigned char :1;\r
+ unsigned char OSTCLR:1;\r
+ unsigned char NMICLR:1;\r
+ } BIT;\r
+ } NMICLR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NMIMD:1;\r
+ } BIT;\r
+ } NMICR;\r
+ char wk9[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char NFLTEN:1;\r
+ } BIT;\r
+ } NMIFLTE;\r
+ char wk10[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char NFCLKSEL:2;\r
+ } BIT;\r
+ } NMIFLTC;\r
+};\r
+\r
+struct st_iwdt {\r
+ unsigned char IWDTRR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short RPSS:2;\r
+ unsigned short :2;\r
+ unsigned short RPES:2;\r
+ unsigned short CKS:4;\r
+ unsigned short :2;\r
+ unsigned short TOPS:2;\r
+ } BIT;\r
+ } IWDTCR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short REFEF:1;\r
+ unsigned short UNDFF:1;\r
+ unsigned short CNTVAL:14;\r
+ } BIT;\r
+ } IWDTSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTIRQS:1;\r
+ } BIT;\r
+ } IWDTRCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SLCSTP:1;\r
+ } BIT;\r
+ } IWDTCSTPR;\r
+};\r
+\r
+struct st_mpc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0WI:1;\r
+ unsigned char PFSWE:1;\r
+ } BIT;\r
+ } PWPR;\r
+ char wk0[35];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P03PFS;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P05PFS;\r
+ char wk2[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P14PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P15PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P16PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P17PFS;\r
+ char wk3[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P26PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P27PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P30PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P31PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P32PFS;\r
+ char wk4[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P35PFS;\r
+ char wk5[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P40PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P41PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P42PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P43PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P44PFS;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P46PFS;\r
+ char wk7[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P54PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P55PFS;\r
+ char wk8[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA1PFS;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA4PFS;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA6PFS;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB1PFS;\r
+ char wk12[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB3PFS;\r
+ char wk13[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB7PFS;\r
+ char wk14[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC7PFS;\r
+ char wk15[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE7PFS;\r
+ char wk16[30];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ7PFS;\r
+};\r
+\r
+struct st_mtu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OE4D:1;\r
+ unsigned char OE4C:1;\r
+ unsigned char OE3D:1;\r
+ unsigned char OE4B:1;\r
+ unsigned char OE4A:1;\r
+ unsigned char OE3B:1;\r
+ } BIT;\r
+ } TOER;\r
+ char wk0[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BDC:1;\r
+ unsigned char N:1;\r
+ unsigned char P:1;\r
+ unsigned char FB:1;\r
+ unsigned char WF:1;\r
+ unsigned char VF:1;\r
+ unsigned char UF:1;\r
+ } BIT;\r
+ } TGCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSYE:1;\r
+ unsigned char :2;\r
+ unsigned char TOCL:1;\r
+ unsigned char TOCS:1;\r
+ unsigned char OLSN:1;\r
+ unsigned char OLSP:1;\r
+ } BIT;\r
+ } TOCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BF:2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOCR2;\r
+ char wk1[4];\r
+ unsigned short TCDR;\r
+ unsigned short TDDR;\r
+ char wk2[8];\r
+ unsigned short TCNTS;\r
+ unsigned short TCBR;\r
+ char wk3[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char T3AEN:1;\r
+ unsigned char T3ACOR:3;\r
+ unsigned char T4VEN:1;\r
+ unsigned char T4VCOR:3;\r
+ } BIT;\r
+ } TITCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char T3ACNT:3;\r
+ unsigned char :1;\r
+ unsigned char T4VCNT:3;\r
+ } BIT;\r
+ } TITCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char BTE:2;\r
+ } BIT;\r
+ } TBTER;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TDER:1;\r
+ } BIT;\r
+ } TDER;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOLBR;\r
+ char wk6[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCE:1;\r
+ unsigned char :6;\r
+ unsigned char WRE:1;\r
+ } BIT;\r
+ } TWCR;\r
+ char wk7[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CST4:1;\r
+ unsigned char CST3:1;\r
+ unsigned char :3;\r
+ unsigned char CST2:1;\r
+ unsigned char CST1:1;\r
+ unsigned char CST0:1;\r
+ } BIT;\r
+ } TSTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SYNC4:1;\r
+ unsigned char SYNC3:1;\r
+ unsigned char :3;\r
+ unsigned char SYNC2:1;\r
+ unsigned char SYNC1:1;\r
+ unsigned char SYNC0:1;\r
+ } BIT;\r
+ } TSYR;\r
+ char wk8[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char RWE:1;\r
+ } BIT;\r
+ } TRWER;\r
+};\r
+\r
+struct st_mtu0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[111];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BFE:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk1[16];\r
+ unsigned short TGRE;\r
+ unsigned short TGRF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TGIEF:1;\r
+ unsigned char TGIEE:1;\r
+ } BIT;\r
+ } TIER2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+};\r
+\r
+struct st_mtu1 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[238];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CCLR:2;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk3[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char I2BE:1;\r
+ unsigned char I2AE:1;\r
+ unsigned char I1BE:1;\r
+ unsigned char I1AE:1;\r
+ } BIT;\r
+ } TICCR;\r
+};\r
+\r
+struct st_mtu2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[365];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CCLR:2;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_mtu3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk3[7];\r
+ unsigned short TCNT;\r
+ char wk4[6];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk5[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk6[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk8[90];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu4 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char TTGE2:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk4[8];\r
+ unsigned short TCNT;\r
+ char wk5[8];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk6[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk8[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk9[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BF:2;\r
+ unsigned short :6;\r
+ unsigned short UT4AE:1;\r
+ unsigned short DT4AE:1;\r
+ unsigned short UT4BE:1;\r
+ unsigned short DT4BE:1;\r
+ unsigned short ITA3AE:1;\r
+ unsigned short ITA4VE:1;\r
+ unsigned short ITB3AE:1;\r
+ unsigned short ITB4VE:1;\r
+ } BIT;\r
+ } TADCR;\r
+ char wk10[2];\r
+ unsigned short TADCORA;\r
+ unsigned short TADCORB;\r
+ unsigned short TADCOBRA;\r
+ unsigned short TADCOBRB;\r
+ char wk11[72];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu5 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char :1;\r
+ unsigned char NFWEN:1;\r
+ unsigned char NFVEN:1;\r
+ unsigned char NFUEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[490];\r
+ unsigned short TCNTU;\r
+ unsigned short TGRU;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRU;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORU;\r
+ char wk3[9];\r
+ unsigned short TCNTV;\r
+ unsigned short TGRV;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRV;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORV;\r
+ char wk5[9];\r
+ unsigned short TCNTW;\r
+ unsigned short TGRW;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRW;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORW;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TGIE5U:1;\r
+ unsigned char TGIE5V:1;\r
+ unsigned char TGIE5W:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CSTU5:1;\r
+ unsigned char CSTV5:1;\r
+ unsigned char CSTW5:1;\r
+ } BIT;\r
+ } TSTR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CMPCLR5U:1;\r
+ unsigned char CMPCLR5V:1;\r
+ unsigned char CMPCLR5W:1;\r
+ } BIT;\r
+ } TCNTCMPCLR;\r
+};\r
+\r
+struct st_poe {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char POE3F:1;\r
+ unsigned char POE2F:1;\r
+ unsigned char POE1F:1;\r
+ unsigned char POE0F:1;\r
+ unsigned char :3;\r
+ unsigned char PIE1:1;\r
+ unsigned char POE3M:2;\r
+ unsigned char POE2M:2;\r
+ unsigned char POE1M:2;\r
+ unsigned char POE0M:2;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char OSF1:1;\r
+ unsigned char :5;\r
+ unsigned char OCE1:1;\r
+ unsigned char OIE1:1;\r
+ } BIT;\r
+ } OCSR1;\r
+ char wk0[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char POE8F:1;\r
+ unsigned char :2;\r
+ unsigned char POE8E:1;\r
+ unsigned char PIE2:1;\r
+ unsigned char :6;\r
+ unsigned char POE8M:2;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char CH0HIZ:1;\r
+ unsigned char CH34HIZ:1;\r
+ } BIT;\r
+ } SPOER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PE3ZE:1;\r
+ unsigned char PE2ZE:1;\r
+ unsigned char PE1ZE:1;\r
+ unsigned char PE0ZE:1;\r
+ } BIT;\r
+ } POECR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char P1CZEA:1;\r
+ unsigned char P2CZEA:1;\r
+ unsigned char P3CZEA:1;\r
+ } BIT;\r
+ } POECR2;\r
+ char wk1[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char OSTSTF:1;\r
+ unsigned char :2;\r
+ unsigned char OSTSTE:1;\r
+ } BIT;\r
+ } ICSR3;\r
+};\r
+\r
+struct st_port {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char PSEL5:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL3:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL1:1;\r
+ unsigned char PSEL0:1;\r
+ } BIT;\r
+ } PSRB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL7:1;\r
+ unsigned char PSEL6:1;\r
+ } BIT;\r
+ } PSRA;\r
+};\r
+\r
+struct st_port0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[33];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[61];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port4 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+};\r
+\r
+struct st_port5 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porta {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :3;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char :3;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[52];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[42];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :3;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[51];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char :1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[43];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[50];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porte {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[45];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[48];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_riic {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICE:1;\r
+ unsigned char IICRST:1;\r
+ unsigned char CLO:1;\r
+ unsigned char SOWP:1;\r
+ unsigned char SCLO:1;\r
+ unsigned char SDAO:1;\r
+ unsigned char SCLI:1;\r
+ unsigned char SDAI:1;\r
+ } BIT;\r
+ } ICCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BBSY:1;\r
+ unsigned char MST:1;\r
+ unsigned char TRS:1;\r
+ unsigned char :1;\r
+ unsigned char SP:1;\r
+ unsigned char RS:1;\r
+ unsigned char ST:1;\r
+ } BIT;\r
+ } ICCR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTWP:1;\r
+ unsigned char CKS:3;\r
+ unsigned char BCWP:1;\r
+ unsigned char BC:3;\r
+ } BIT;\r
+ } ICMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DLCS:1;\r
+ unsigned char SDDL:3;\r
+ unsigned char TMWE:1;\r
+ unsigned char TMOH:1;\r
+ unsigned char TMOL:1;\r
+ unsigned char TMOS:1;\r
+ } BIT;\r
+ } ICMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SMBS:1;\r
+ unsigned char WAIT:1;\r
+ unsigned char RDRFS:1;\r
+ unsigned char ACKWP:1;\r
+ unsigned char ACKBT:1;\r
+ unsigned char ACKBR:1;\r
+ unsigned char NF:2;\r
+ } BIT;\r
+ } ICMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SCLE:1;\r
+ unsigned char NFE:1;\r
+ unsigned char NACKE:1;\r
+ unsigned char SALE:1;\r
+ unsigned char NALE:1;\r
+ unsigned char MALE:1;\r
+ unsigned char TMOE:1;\r
+ } BIT;\r
+ } ICFER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOAE:1;\r
+ unsigned char :1;\r
+ unsigned char DIDE:1;\r
+ unsigned char :1;\r
+ unsigned char GCAE:1;\r
+ unsigned char SAR2E:1;\r
+ unsigned char SAR1E:1;\r
+ unsigned char SAR0E:1;\r
+ } BIT;\r
+ } ICSER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char NAKIE:1;\r
+ unsigned char SPIE:1;\r
+ unsigned char STIE:1;\r
+ unsigned char ALIE:1;\r
+ unsigned char TMOIE:1;\r
+ } BIT;\r
+ } ICIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOA:1;\r
+ unsigned char :1;\r
+ unsigned char DID:1;\r
+ unsigned char :1;\r
+ unsigned char GCA:1;\r
+ unsigned char AAS2:1;\r
+ unsigned char AAS1:1;\r
+ unsigned char AAS0:1;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TDRE:1;\r
+ unsigned char TEND:1;\r
+ unsigned char RDRF:1;\r
+ unsigned char NACKF:1;\r
+ unsigned char STOP:1;\r
+ unsigned char START:1;\r
+ unsigned char AL:1;\r
+ unsigned char TMOF:1;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTL;\r
+ };\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTH;\r
+ };\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRL:5;\r
+ } BIT;\r
+ } ICBRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRH:5;\r
+ } BIT;\r
+ } ICBRH;\r
+ unsigned char ICDRT;\r
+ unsigned char ICDRR;\r
+};\r
+\r
+struct st_rspi {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPRIE:1;\r
+ unsigned char SPE:1;\r
+ unsigned char SPTIE:1;\r
+ unsigned char SPEIE:1;\r
+ unsigned char MSTR:1;\r
+ unsigned char MODFEN:1;\r
+ unsigned char TXMD:1;\r
+ unsigned char SPMS:1;\r
+ } BIT;\r
+ } SPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char SSL3P:1;\r
+ unsigned char SSL2P:1;\r
+ unsigned char SSL1P:1;\r
+ unsigned char SSL0P:1;\r
+ } BIT;\r
+ } SSLP;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char MOIFE:1;\r
+ unsigned char MOIFV:1;\r
+ unsigned char :2;\r
+ unsigned char SPLP2:1;\r
+ unsigned char SPLP:1;\r
+ } BIT;\r
+ } SPPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PERF:1;\r
+ unsigned char MODF:1;\r
+ unsigned char IDLNF:1;\r
+ unsigned char OVRF:1;\r
+ } BIT;\r
+ } SPSR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ } WORD;\r
+ } SPDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPSLN:3;\r
+ } BIT;\r
+ } SPSCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SPECM:3;\r
+ unsigned char :1;\r
+ unsigned char SPCP:3;\r
+ } BIT;\r
+ } SPSSR;\r
+ unsigned char SPBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char SPLW:1;\r
+ unsigned char SPRDTD:1;\r
+ unsigned char :2;\r
+ unsigned char SPFC:2;\r
+ } BIT;\r
+ } SPDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SCKDL:3;\r
+ } BIT;\r
+ } SPCKD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SLNDL:3;\r
+ } BIT;\r
+ } SSLND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPNDL:3;\r
+ } BIT;\r
+ } SPND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PTE:1;\r
+ unsigned char SPIIE:1;\r
+ unsigned char SPOE:1;\r
+ unsigned char SPPE:1;\r
+ } BIT;\r
+ } SPCR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD5;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD6;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD7;\r
+};\r
+\r
+struct st_rtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char F1HZ:1;\r
+ unsigned char F2HZ:1;\r
+ unsigned char F4HZ:1;\r
+ unsigned char F8HZ:1;\r
+ unsigned char F16HZ:1;\r
+ unsigned char F32HZ:1;\r
+ unsigned char F64HZ:1;\r
+ } BIT;\r
+ } R64CNT;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECCNT;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINCNT;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRCNT;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char DAYW:3;\r
+ } BIT;\r
+ } RWKCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char DATE10:2;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYCNT;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONCNT;\r
+ char wk6[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short YR10:4;\r
+ unsigned short YR1:4;\r
+ } BIT;\r
+ } RYRCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECAR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINAR;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRAR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :4;\r
+ unsigned char DAYW:3;\r
+ } BIT;\r
+ } RWKAR;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :1;\r
+ unsigned char DATE10:2;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYAR;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :2;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONAR;\r
+ char wk12[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short YR10:4;\r
+ unsigned short YR1:4;\r
+ } BIT;\r
+ } RYRAR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RYRAREN;\r
+ char wk13[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PES:4;\r
+ unsigned char RTCOS:1;\r
+ unsigned char PIE:1;\r
+ unsigned char CIE:1;\r
+ unsigned char AIE:1;\r
+ } BIT;\r
+ } RCR1;\r
+ char wk14[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CNTMD:1;\r
+ unsigned char HR24:1;\r
+ unsigned char AADJP:1;\r
+ unsigned char AADJE:1;\r
+ unsigned char RTCOE:1;\r
+ unsigned char ADJ30:1;\r
+ unsigned char RESET:1;\r
+ unsigned char START:1;\r
+ } BIT;\r
+ } RCR2;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char RTCDV:2;\r
+ unsigned char RTCEN:1;\r
+ } BIT;\r
+ } RCR3;\r
+ char wk16[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PMADJ:2;\r
+ unsigned char ADJ:6;\r
+ } BIT;\r
+ } RADJ;\r
+};\r
+\r
+struct st_rtcb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT0;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT1;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT3;\r
+ char wk3[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT0AR;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT1AR;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT2AR;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT3AR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT0AER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT1AER;\r
+ char wk9[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short ENB:8;\r
+ } BIT;\r
+ } BCNT2AER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT3AER;\r
+};\r
+\r
+struct st_s12ad {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADST:1;\r
+ unsigned short ADCS:2;\r
+ unsigned short ADIE:1;\r
+ unsigned short :1;\r
+ unsigned short ADHSC:1;\r
+ unsigned short TRGE:1;\r
+ unsigned short EXTRG:1;\r
+ unsigned short DBLE:1;\r
+ unsigned short GBADIE:1;\r
+ unsigned short :1;\r
+ unsigned short DBLANS:5;\r
+ } BIT;\r
+ } ADCSR;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ANSA15:1;\r
+ unsigned short ANSA14:1;\r
+ unsigned short ANSA13:1;\r
+ unsigned short ANSA12:1;\r
+ unsigned short ANSA11:1;\r
+ unsigned short ANSA10:1;\r
+ unsigned short ANSA9:1;\r
+ unsigned short ANSA8:1;\r
+ unsigned short :1;\r
+ unsigned short ANSA6:1;\r
+ unsigned short :1;\r
+ unsigned short ANSA4:1;\r
+ unsigned short ANSA3:1;\r
+ unsigned short ANSA2:1;\r
+ unsigned short ANSA1:1;\r
+ unsigned short ANSA0:1;\r
+ } BIT;\r
+ } ADANSA;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADS15:1;\r
+ unsigned short ADS14:1;\r
+ unsigned short ADS13:1;\r
+ unsigned short ADS12:1;\r
+ unsigned short ADS11:1;\r
+ unsigned short ADS10:1;\r
+ unsigned short ADS9:1;\r
+ unsigned short ADS8:1;\r
+ unsigned short :1;\r
+ unsigned short ADS6:1;\r
+ unsigned short :1;\r
+ unsigned short ADS4:1;\r
+ unsigned short ADS3:1;\r
+ unsigned short ADS2:1;\r
+ unsigned short ADS1:1;\r
+ unsigned short ADS0:1;\r
+ } BIT;\r
+ } ADADS;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char ADC:2;\r
+ } BIT;\r
+ } ADADC;\r
+ char wk3[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADRFMT:1;\r
+ unsigned short :9;\r
+ unsigned short ACE:1;\r
+ } BIT;\r
+ } ADCER;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short TRSA:4;\r
+ unsigned short :4;\r
+ unsigned short TRSB:4;\r
+ } BIT;\r
+ } ADSTRGR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short OCS:1;\r
+ unsigned short TSS:1;\r
+ unsigned short :6;\r
+ unsigned short OCSAD:1;\r
+ } BIT;\r
+ } ADEXICR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ANSB15:1;\r
+ unsigned short ANSB14:1;\r
+ unsigned short ANSB13:1;\r
+ unsigned short ANSB12:1;\r
+ unsigned short ANSB11:1;\r
+ unsigned short ANSB10:1;\r
+ unsigned short ANSB9:1;\r
+ unsigned short ANSB8:1;\r
+ unsigned short :1;\r
+ unsigned short ANSB6:1;\r
+ unsigned short :1;\r
+ unsigned short ANSB4:1;\r
+ unsigned short ANSB3:1;\r
+ unsigned short ANSB2:1;\r
+ unsigned short ANSB1:1;\r
+ unsigned short ANSB0:1;\r
+ } BIT;\r
+ } ADANSB;\r
+ char wk4[2];\r
+ unsigned short ADDBLDR;\r
+ unsigned short ADTSDR;\r
+ unsigned short ADOCDR;\r
+ char wk5[2];\r
+ unsigned short ADDR0;\r
+ unsigned short ADDR1;\r
+ unsigned short ADDR2;\r
+ unsigned short ADDR3;\r
+ unsigned short ADDR4;\r
+ char wk6[2];\r
+ unsigned short ADDR6;\r
+ char wk7[2];\r
+ unsigned short ADDR8;\r
+ unsigned short ADDR9;\r
+ unsigned short ADDR10;\r
+ unsigned short ADDR11;\r
+ unsigned short ADDR12;\r
+ unsigned short ADDR13;\r
+ unsigned short ADDR14;\r
+ unsigned short ADDR15;\r
+ char wk8[32];\r
+ unsigned char ADSSTR0;\r
+ unsigned char ADSSTRL;\r
+ char wk9[14];\r
+ unsigned char ADSSTRT;\r
+ unsigned char ADSSTRO;\r
+ char wk10[1];\r
+ unsigned char ADSSTR1;\r
+ unsigned char ADSSTR2;\r
+ unsigned char ADSSTR3;\r
+ unsigned char ADSSTR4;\r
+ char wk11[1];\r
+ unsigned char ADSSTR6;\r
+};\r
+\r
+struct st_sci1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RXDESEL:1;\r
+ unsigned char :1;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+};\r
+\r
+struct st_sci12 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RXDESEL:1;\r
+ unsigned char :1;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+ char wk0[18];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ESME:1;\r
+ } BIT;\r
+ } ESMER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char BRME:1;\r
+ unsigned char RXDSF:1;\r
+ unsigned char SFSF:1;\r
+ } BIT;\r
+ } CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PIBS:3;\r
+ unsigned char PIBE:1;\r
+ unsigned char CF1DS:2;\r
+ unsigned char CF0RE:1;\r
+ unsigned char BFE:1;\r
+ } BIT;\r
+ } CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RTS:2;\r
+ unsigned char BCCS:2;\r
+ unsigned char :1;\r
+ unsigned char DFCS:3;\r
+ } BIT;\r
+ } CR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SDST:1;\r
+ } BIT;\r
+ } CR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SHARPS:1;\r
+ unsigned char :2;\r
+ unsigned char RXDXPS:1;\r
+ unsigned char TXDXPS:1;\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDIE:1;\r
+ unsigned char BCDIE:1;\r
+ unsigned char PIBDIE:1;\r
+ unsigned char CF1MIE:1;\r
+ unsigned char CF0MIE:1;\r
+ unsigned char BFDIE:1;\r
+ } BIT;\r
+ } ICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDF:1;\r
+ unsigned char BCDF:1;\r
+ unsigned char PIBDF:1;\r
+ unsigned char CF1MF:1;\r
+ unsigned char CF0MF:1;\r
+ unsigned char BFDF:1;\r
+ } BIT;\r
+ } STR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDCL:1;\r
+ unsigned char BCDCL:1;\r
+ unsigned char PIBDCL:1;\r
+ unsigned char CF1MCL:1;\r
+ unsigned char CF0MCL:1;\r
+ unsigned char BFDCL:1;\r
+ } BIT;\r
+ } STCR;\r
+ unsigned char CF0DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF0CE7:1;\r
+ unsigned char CF0CE6:1;\r
+ unsigned char CF0CE5:1;\r
+ unsigned char CF0CE4:1;\r
+ unsigned char CF0CE3:1;\r
+ unsigned char CF0CE2:1;\r
+ unsigned char CF0CE1:1;\r
+ unsigned char CF0CE0:1;\r
+ } BIT;\r
+ } CF0CR;\r
+ unsigned char CF0RR;\r
+ unsigned char PCF1DR;\r
+ unsigned char SCF1DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF1CE7:1;\r
+ unsigned char CF1CE6:1;\r
+ unsigned char CF1CE5:1;\r
+ unsigned char CF1CE4:1;\r
+ unsigned char CF1CE3:1;\r
+ unsigned char CF1CE2:1;\r
+ unsigned char CF1CE1:1;\r
+ unsigned char CF1CE0:1;\r
+ } BIT;\r
+ } CF1CR;\r
+ unsigned char CF1RR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TCST:1;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char TCSS:3;\r
+ unsigned char TWRC:1;\r
+ unsigned char :1;\r
+ unsigned char TOMS:2;\r
+ } BIT;\r
+ } TMR;\r
+ unsigned char TPRE;\r
+ unsigned char TCNT;\r
+};\r
+\r
+struct st_smci {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char GM:1;\r
+ unsigned char BLK:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char BCP:2;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char ERS:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+};\r
+\r
+struct st_system {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short MD:1;\r
+ } BIT;\r
+ } MDMONR;\r
+ char wk0[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short RAME:1;\r
+ } BIT;\r
+ } SYSCR1;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SSBY:1;\r
+ } BIT;\r
+ } SBYCR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long MSTPA28:1;\r
+ unsigned long :8;\r
+ unsigned long MSTPA19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA17:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA15:1;\r
+ unsigned long :5;\r
+ unsigned long MSTPA9:1;\r
+ } BIT;\r
+ } MSTPCRA;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long MSTPB30:1;\r
+ unsigned long :3;\r
+ unsigned long MSTPB26:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPB23:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB21:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB17:1;\r
+ unsigned long :7;\r
+ unsigned long MSTPB9:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPB6:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB4:1;\r
+ } BIT;\r
+ } MSTPCRB;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long DSLPE:1;\r
+ unsigned long :11;\r
+ unsigned long MSTPC19:1;\r
+ unsigned long :18;\r
+ unsigned long MSTPC0:1;\r
+ } BIT;\r
+ } MSTPCRC;\r
+ char wk3[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long FCK:4;\r
+ unsigned long ICK:4;\r
+ unsigned long :12;\r
+ unsigned long PCKB:4;\r
+ unsigned long :4;\r
+ unsigned long PCKD:4;\r
+ } BIT;\r
+ } SCKCR;\r
+ char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short CKSEL:3;\r
+ } BIT;\r
+ } SCKCR3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short STC:6;\r
+ unsigned short :6;\r
+ unsigned short PLIDIV:2;\r
+ } BIT;\r
+ } PLLCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char PLLEN:1;\r
+ } BIT;\r
+ } PLLCR2;\r
+ char wk5[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char MOSTP:1;\r
+ } BIT;\r
+ } MOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SOSTP:1;\r
+ } BIT;\r
+ } SOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char LCSTP:1;\r
+ } BIT;\r
+ } LOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ILCSTP:1;\r
+ } BIT;\r
+ } ILOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char HCSTP:1;\r
+ } BIT;\r
+ } HOCOCR;\r
+ char wk6[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char HCOVF:1;\r
+ unsigned char PLOVF:1;\r
+ unsigned char :1;\r
+ unsigned char MOOVF:1;\r
+ } BIT;\r
+ } OSCOVFSR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CKOSTP:1;\r
+ unsigned short CKODIV:3;\r
+ unsigned short :1;\r
+ unsigned short CKOSEL:3;\r
+ } BIT;\r
+ } CKOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OSTDE:1;\r
+ unsigned char :6;\r
+ unsigned char OSTDIE:1;\r
+ } BIT;\r
+ } OSTDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char OSTDF:1;\r
+ } BIT;\r
+ } OSTDSR;\r
+ char wk8[94];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char OPCMTSF:1;\r
+ unsigned char :1;\r
+ unsigned char OPCM:3;\r
+ } BIT;\r
+ } OPCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTCKEN:1;\r
+ unsigned char :4;\r
+ unsigned char RSTCKSEL:3;\r
+ } BIT;\r
+ } RSTCKCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MSTS:5;\r
+ } BIT;\r
+ } MOSCWTCR;\r
+ char wk9[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SOPCMTSF:1;\r
+ unsigned char :3;\r
+ unsigned char SOPCM:1;\r
+ } BIT;\r
+ } SOPCCR;\r
+ char wk10[21];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SWRF:1;\r
+ unsigned char :1;\r
+ unsigned char IWDTRF:1;\r
+ } BIT;\r
+ } RSTSR2;\r
+ char wk11[1];\r
+ unsigned short SWRR;\r
+ char wk12[28];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char LVD1IRQSEL:1;\r
+ unsigned char LVD1IDTSEL:2;\r
+ } BIT;\r
+ } LVD1CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD1MON:1;\r
+ unsigned char LVD1DET:1;\r
+ } BIT;\r
+ } LVD1SR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char LVD2IRQSEL:1;\r
+ unsigned char LVD2IDTSEL:2;\r
+ } BIT;\r
+ } LVD2CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD2MON:1;\r
+ unsigned char LVD2DET:1;\r
+ } BIT;\r
+ } LVD2SR;\r
+ char wk13[794];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRKEY:8;\r
+ unsigned short :4;\r
+ unsigned short PRC3:1;\r
+ unsigned short :1;\r
+ unsigned short PRC1:1;\r
+ unsigned short PRC0:1;\r
+ } BIT;\r
+ } PRCR;\r
+ char wk14[48784];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char LVD2RF:1;\r
+ unsigned char LVD1RF:1;\r
+ unsigned char :1;\r
+ unsigned char PORF:1;\r
+ } BIT;\r
+ } RSTSR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CWSF:1;\r
+ } BIT;\r
+ } RSTSR1;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MOSEL:1;\r
+ unsigned char MODRV21:1;\r
+ } BIT;\r
+ } MOFCR;\r
+ char wk16[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char LVD2E:1;\r
+ unsigned char LVD1E:1;\r
+ unsigned char :1;\r
+ unsigned char EXVCCINP2:1;\r
+ } BIT;\r
+ } LVCMPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2LVL:2;\r
+ unsigned char LVD1LVL:4;\r
+ } BIT;\r
+ } LVDLVLR;\r
+ char wk17[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD1RN:1;\r
+ unsigned char LVD1RI:1;\r
+ unsigned char :3;\r
+ unsigned char LVD1CMPE:1;\r
+ unsigned char :1;\r
+ unsigned char LVD1RIE:1;\r
+ } BIT;\r
+ } LVD1CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD2RN:1;\r
+ unsigned char LVD2RI:1;\r
+ unsigned char :3;\r
+ unsigned char LVD2CMPE:1;\r
+ unsigned char :1;\r
+ unsigned char LVD2RIE:1;\r
+ } BIT;\r
+ } LVD2CR0;\r
+};\r
+\r
+struct st_usb {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short SCKE:1;\r
+ unsigned short :1;\r
+ unsigned short CNEN:1;\r
+ unsigned short :1;\r
+ unsigned short DCFM:1;\r
+ unsigned short DRPD:1;\r
+ unsigned short DPRPU:1;\r
+ unsigned short :3;\r
+ unsigned short USBE:1;\r
+ } BIT;\r
+ } SYSCFG;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVCMON:2;\r
+ unsigned short :7;\r
+ unsigned short HTACT:1;\r
+ unsigned short :3;\r
+ unsigned short IDMON:1;\r
+ unsigned short LNST:2;\r
+ } BIT;\r
+ } SYSSTS0;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short HNPBTOA:1;\r
+ unsigned short EXICEN:1;\r
+ unsigned short VBUSEN:1;\r
+ unsigned short WKUP:1;\r
+ unsigned short RWUPE:1;\r
+ unsigned short USBRST:1;\r
+ unsigned short RESUME:1;\r
+ unsigned short UACT:1;\r
+ unsigned short :1;\r
+ unsigned short RHST:3;\r
+ } BIT;\r
+ } DVSTCTR0;\r
+ char wk2[10];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } CFIFO;\r
+ char wk3[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D0FIFO;\r
+ char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D1FIFO;\r
+ char wk5[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short :3;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :2;\r
+ unsigned short ISEL:1;\r
+ unsigned short :1;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } CFIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } CFIFOCTR;\r
+ char wk6[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D0FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } D0FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D1FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } D1FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBSE:1;\r
+ unsigned short RSME:1;\r
+ unsigned short SOFE:1;\r
+ unsigned short DVSE:1;\r
+ unsigned short CTRE:1;\r
+ unsigned short BEMPE:1;\r
+ unsigned short NRDYE:1;\r
+ unsigned short BRDYE:1;\r
+ } BIT;\r
+ } INTENB0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRCRE:1;\r
+ unsigned short BCHGE:1;\r
+ unsigned short :1;\r
+ unsigned short DTCHE:1;\r
+ unsigned short ATTCHE:1;\r
+ unsigned short :4;\r
+ unsigned short EOFERRE:1;\r
+ unsigned short SIGNE:1;\r
+ unsigned short SACKE:1;\r
+ unsigned short :3;\r
+ unsigned short PDDETINTE0:1;\r
+ } BIT;\r
+ } INTENB1;\r
+ char wk7[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDYE:1;\r
+ unsigned short PIPE8BRDYE:1;\r
+ unsigned short PIPE7BRDYE:1;\r
+ unsigned short PIPE6BRDYE:1;\r
+ unsigned short PIPE5BRDYE:1;\r
+ unsigned short PIPE4BRDYE:1;\r
+ unsigned short PIPE3BRDYE:1;\r
+ unsigned short PIPE2BRDYE:1;\r
+ unsigned short PIPE1BRDYE:1;\r
+ unsigned short PIPE0BRDYE:1;\r
+ } BIT;\r
+ } BRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9NRDYE:1;\r
+ unsigned short PIPE8NRDYE:1;\r
+ unsigned short PIPE7NRDYE:1;\r
+ unsigned short PIPE6NRDYE:1;\r
+ unsigned short PIPE5NRDYE:1;\r
+ unsigned short PIPE4NRDYE:1;\r
+ unsigned short PIPE3NRDYE:1;\r
+ unsigned short PIPE2NRDYE:1;\r
+ unsigned short PIPE1NRDYE:1;\r
+ unsigned short PIPE0NRDYE:1;\r
+ } BIT;\r
+ } NRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMPE:1;\r
+ unsigned short PIPE8BEMPE:1;\r
+ unsigned short PIPE7BEMPE:1;\r
+ unsigned short PIPE6BEMPE:1;\r
+ unsigned short PIPE5BEMPE:1;\r
+ unsigned short PIPE4BEMPE:1;\r
+ unsigned short PIPE3BEMPE:1;\r
+ unsigned short PIPE2BEMPE:1;\r
+ unsigned short PIPE1BEMPE:1;\r
+ unsigned short PIPE0BEMPE:1;\r
+ } BIT;\r
+ } BEMPENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short TRNENSEL:1;\r
+ unsigned short :1;\r
+ unsigned short BRDYM:1;\r
+ unsigned short :1;\r
+ unsigned short EDGESTS:1;\r
+ } BIT;\r
+ } SOFCFG;\r
+ char wk8[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBINT:1;\r
+ unsigned short RESM:1;\r
+ unsigned short SOFR:1;\r
+ unsigned short DVST:1;\r
+ unsigned short CTRT:1;\r
+ unsigned short BEMP:1;\r
+ unsigned short NRDY:1;\r
+ unsigned short BRDY:1;\r
+ unsigned short VBSTS:1;\r
+ unsigned short DVSQ:3;\r
+ unsigned short VALID:1;\r
+ unsigned short CTSQ:3;\r
+ } BIT;\r
+ } INTSTS0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRCR:1;\r
+ unsigned short BCHG:1;\r
+ unsigned short :1;\r
+ unsigned short DTCH:1;\r
+ unsigned short ATTCH:1;\r
+ unsigned short :4;\r
+ unsigned short EOFERR:1;\r
+ unsigned short SIGN:1;\r
+ unsigned short SACK:1;\r
+ unsigned short :3;\r
+ unsigned short PDDETINT0:1;\r
+ } BIT;\r
+ } INTSTS1;\r
+ char wk9[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDY:1;\r
+ unsigned short PIPE8BRDY:1;\r
+ unsigned short PIPE7BRDY:1;\r
+ unsigned short PIPE6BRDY:1;\r
+ unsigned short PIPE5BRDY:1;\r
+ unsigned short PIPE4BRDY:1;\r
+ unsigned short PIPE3BRDY:1;\r
+ unsigned short PIPE2BRDY:1;\r
+ unsigned short PIPE1BRDY:1;\r
+ unsigned short PIPE0BRDY:1;\r
+ } BIT;\r
+ } BRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9NRDY:1;\r
+ unsigned short PIPE8NRDY:1;\r
+ unsigned short PIPE7NRDY:1;\r
+ unsigned short PIPE6NRDY:1;\r
+ unsigned short PIPE5NRDY:1;\r
+ unsigned short PIPE4NRDY:1;\r
+ unsigned short PIPE3NRDY:1;\r
+ unsigned short PIPE2NRDY:1;\r
+ unsigned short PIPE1NRDY:1;\r
+ unsigned short PIPE0NRDY:1;\r
+ } BIT;\r
+ } NRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMP:1;\r
+ unsigned short PIPE8BEMP:1;\r
+ unsigned short PIPE7BEMP:1;\r
+ unsigned short PIPE6BEMP:1;\r
+ unsigned short PIPE5BEMP:1;\r
+ unsigned short PIPE4BEMP:1;\r
+ unsigned short PIPE3BEMP:1;\r
+ unsigned short PIPE2BEMP:1;\r
+ unsigned short PIPE1BEMP:1;\r
+ unsigned short PIPE0BEMP:1;\r
+ } BIT;\r
+ } BEMPSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRN:1;\r
+ unsigned short CRCE:1;\r
+ unsigned short :3;\r
+ unsigned short FRNM:11;\r
+ } BIT;\r
+ } FRMNUM;\r
+ char wk10[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BREQUEST:8;\r
+ unsigned short BMREQUESTTYPE:8;\r
+ } BIT;\r
+ } USBREQ;\r
+ unsigned short USBVAL;\r
+ unsigned short USBINDX;\r
+ unsigned short USBLENG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ } BIT;\r
+ } DCPCFG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DEVSEL:4;\r
+ unsigned short :5;\r
+ unsigned short MXPS:7;\r
+ } BIT;\r
+ } DCPMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short SUREQ:1;\r
+ unsigned short :2;\r
+ unsigned short SUREQCLR:1;\r
+ unsigned short :2;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :2;\r
+ unsigned short CCPL:1;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } DCPCTR;\r
+ char wk11[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :12;\r
+ unsigned short PIPESEL:4;\r
+ } BIT;\r
+ } PIPESEL;\r
+ char wk12[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TYPE:2;\r
+ unsigned short :3;\r
+ unsigned short BFRE:1;\r
+ unsigned short DBLB:1;\r
+ unsigned short :1;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ unsigned short EPNUM:4;\r
+ } BIT;\r
+ } PIPECFG;\r
+ char wk13[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DEVSEL:4;\r
+ unsigned short :3;\r
+ unsigned short MXPS:9;\r
+ } BIT;\r
+ } PIPEMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short IFIS:1;\r
+ unsigned short :9;\r
+ unsigned short IITV:3;\r
+ } BIT;\r
+ } PIPEPERI;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE1CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE2CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE3CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE4CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE5CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE6CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE7CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE8CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE9CTR;\r
+ char wk14[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE1TRE;\r
+ unsigned short PIPE1TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE2TRE;\r
+ unsigned short PIPE2TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE3TRE;\r
+ unsigned short PIPE3TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE4TRE;\r
+ unsigned short PIPE4TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE5TRE;\r
+ unsigned short PIPE5TRN;\r
+ char wk15[12];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PDDETSTS0:1;\r
+ unsigned short CHGDETSTS0:1;\r
+ unsigned short BATCHGE0:1;\r
+ unsigned short DCPMODE0:1;\r
+ unsigned short VDMSRCE0:1;\r
+ unsigned short IDPSINKE0:1;\r
+ unsigned short VDPSRCE0:1;\r
+ unsigned short IDMSINKE0:1;\r
+ unsigned short IDPSRCE0:1;\r
+ unsigned short RPDME0:1;\r
+ } BIT;\r
+ } USBBCCTRL0;\r
+ char wk16[26];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short VBRPDCUT:1;\r
+ unsigned short :6;\r
+ unsigned short VDDUSBE:1;\r
+ } BIT;\r
+ } USBMC;\r
+ char wk17[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD5;\r
+};\r
+\r
+enum enum_ir {\r
+IR_BSC_BUSERR=16,IR_ICU_SWINT=27,\r
+IR_CMT0_CMI0,\r
+IR_CMT1_CMI1,\r
+IR_CAC_FERRF=32,IR_CAC_MENDF,IR_CAC_OVFF,\r
+IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,\r
+IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,\r
+IR_DOC_DOPCF=57,\r
+IR_RTC_CUP=63,\r
+IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,\r
+IR_LVD_LVD1=88,IR_LVD_LVD2,\r
+IR_USB0_USBR0,\r
+IR_RTC_ALM=92,IR_RTC_PRD,\r
+IR_S12AD_S12ADI0=102,IR_S12AD_GBADI,\r
+IR_ELC_ELSR18I=106,\r
+IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,\r
+IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,\r
+IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,\r
+IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,\r
+IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,\r
+IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,\r
+IR_POE_OEI1=170,IR_POE_OEI2,\r
+IR_SCI1_ERI1=218,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,\r
+IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,\r
+IR_SCI12_ERI12=238,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3,\r
+IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0\r
+};\r
+\r
+enum enum_dtce {\r
+DTCE_ICU_SWINT=27,\r
+DTCE_CMT0_CMI0,\r
+DTCE_CMT1_CMI1,\r
+DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,\r
+DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,\r
+DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,\r
+DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI,\r
+DTCE_ELC_ELSR18I=106,\r
+DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,\r
+DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,\r
+DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,\r
+DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,\r
+DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,\r
+DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,\r
+DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,\r
+DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5,\r
+DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12,\r
+DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0\r
+};\r
+\r
+enum enum_ier {\r
+IER_BSC_BUSERR=0x02,\r
+IER_ICU_SWINT=0x03,\r
+IER_CMT0_CMI0=0x03,\r
+IER_CMT1_CMI1=0x03,\r
+IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04,\r
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,\r
+IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,\r
+IER_DOC_DOPCF=0x07,\r
+IER_RTC_CUP=0x07,\r
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,\r
+IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B,\r
+IER_USB0_USBR0=0x0B,\r
+IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,\r
+IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C,\r
+IER_ELC_ELSR18I=0x0D,\r
+IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,\r
+IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,\r
+IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,\r
+IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,\r
+IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,\r
+IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11,\r
+IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,\r
+IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,\r
+IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,\r
+IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E,\r
+IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F\r
+};\r
+\r
+enum enum_ipr {\r
+IPR_BSC_BUSERR=0,\r
+IPR_ICU_SWINT=3,\r
+IPR_CMT0_CMI0=4,\r
+IPR_CMT1_CMI1=5,\r
+IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34,\r
+IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38,\r
+IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44,\r
+IPR_DOC_DOPCF=57,\r
+IPR_RTC_CUP=63,\r
+IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,\r
+IPR_LVD_LVD1=88,IPR_LVD_LVD2=89,\r
+IPR_USB0_USBR0=90,\r
+IPR_RTC_ALM=92,IPR_RTC_PRD=93,\r
+IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103,\r
+IPR_ELC_ELSR18I=106,\r
+IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118,\r
+IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123,\r
+IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127,\r
+IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133,\r
+IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138,\r
+IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139,\r
+IPR_POE_OEI1=170,IPR_POE_OEI2=171,\r
+IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218,\r
+IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222,\r
+IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245,\r
+IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249,\r
+IPR_BSC_=0,\r
+IPR_CMT0_=4,\r
+IPR_CMT1_=5,\r
+IPR_RSPI0_=44,\r
+IPR_DOC_=57,\r
+IPR_ELC_=106,\r
+IPR_MTU1_TGI=121,\r
+IPR_MTU1_TCI=123,\r
+IPR_MTU2_TGI=125,\r
+IPR_MTU2_TCI=127,\r
+IPR_MTU3_TGI=129,\r
+IPR_MTU4_TGI=134,\r
+IPR_MTU5_=139,\r
+IPR_MTU5_TGI=139,\r
+IPR_SCI1_=218,\r
+IPR_SCI5_=222\r
+};\r
+\r
+#define IEN_BSC_BUSERR IEN0\r
+#define IEN_ICU_SWINT IEN3\r
+#define IEN_CMT0_CMI0 IEN4\r
+#define IEN_CMT1_CMI1 IEN5\r
+#define IEN_CAC_FERRF IEN0\r
+#define IEN_CAC_MENDF IEN1\r
+#define IEN_CAC_OVFF IEN2\r
+#define IEN_USB0_D0FIFO0 IEN4\r
+#define IEN_USB0_D1FIFO0 IEN5\r
+#define IEN_USB0_USBI0 IEN6\r
+#define IEN_RSPI0_SPEI0 IEN4\r
+#define IEN_RSPI0_SPRI0 IEN5\r
+#define IEN_RSPI0_SPTI0 IEN6\r
+#define IEN_RSPI0_SPII0 IEN7\r
+#define IEN_DOC_DOPCF IEN1\r
+#define IEN_RTC_CUP IEN7\r
+#define IEN_ICU_IRQ0 IEN0\r
+#define IEN_ICU_IRQ1 IEN1\r
+#define IEN_ICU_IRQ2 IEN2\r
+#define IEN_ICU_IRQ3 IEN3\r
+#define IEN_ICU_IRQ4 IEN4\r
+#define IEN_ICU_IRQ5 IEN5\r
+#define IEN_ICU_IRQ6 IEN6\r
+#define IEN_ICU_IRQ7 IEN7\r
+#define IEN_LVD_LVD1 IEN0\r
+#define IEN_LVD_LVD2 IEN1\r
+#define IEN_USB0_USBR0 IEN2\r
+#define IEN_RTC_ALM IEN4\r
+#define IEN_RTC_PRD IEN5\r
+#define IEN_S12AD_S12ADI0 IEN6\r
+#define IEN_S12AD_GBADI IEN7\r
+#define IEN_ELC_ELSR18I IEN2\r
+#define IEN_MTU0_TGIA0 IEN2\r
+#define IEN_MTU0_TGIB0 IEN3\r
+#define IEN_MTU0_TGIC0 IEN4\r
+#define IEN_MTU0_TGID0 IEN5\r
+#define IEN_MTU0_TCIV0 IEN6\r
+#define IEN_MTU0_TGIE0 IEN7\r
+#define IEN_MTU0_TGIF0 IEN0\r
+#define IEN_MTU1_TGIA1 IEN1\r
+#define IEN_MTU1_TGIB1 IEN2\r
+#define IEN_MTU1_TCIV1 IEN3\r
+#define IEN_MTU1_TCIU1 IEN4\r
+#define IEN_MTU2_TGIA2 IEN5\r
+#define IEN_MTU2_TGIB2 IEN6\r
+#define IEN_MTU2_TCIV2 IEN7\r
+#define IEN_MTU2_TCIU2 IEN0\r
+#define IEN_MTU3_TGIA3 IEN1\r
+#define IEN_MTU3_TGIB3 IEN2\r
+#define IEN_MTU3_TGIC3 IEN3\r
+#define IEN_MTU3_TGID3 IEN4\r
+#define IEN_MTU3_TCIV3 IEN5\r
+#define IEN_MTU4_TGIA4 IEN6\r
+#define IEN_MTU4_TGIB4 IEN7\r
+#define IEN_MTU4_TGIC4 IEN0\r
+#define IEN_MTU4_TGID4 IEN1\r
+#define IEN_MTU4_TCIV4 IEN2\r
+#define IEN_MTU5_TGIU5 IEN3\r
+#define IEN_MTU5_TGIV5 IEN4\r
+#define IEN_MTU5_TGIW5 IEN5\r
+#define IEN_POE_OEI1 IEN2\r
+#define IEN_POE_OEI2 IEN3\r
+#define IEN_SCI1_ERI1 IEN2\r
+#define IEN_SCI1_RXI1 IEN3\r
+#define IEN_SCI1_TXI1 IEN4\r
+#define IEN_SCI1_TEI1 IEN5\r
+#define IEN_SCI5_ERI5 IEN6\r
+#define IEN_SCI5_RXI5 IEN7\r
+#define IEN_SCI5_TXI5 IEN0\r
+#define IEN_SCI5_TEI5 IEN1\r
+#define IEN_SCI12_ERI12 IEN6\r
+#define IEN_SCI12_RXI12 IEN7\r
+#define IEN_SCI12_TXI12 IEN0\r
+#define IEN_SCI12_TEI12 IEN1\r
+#define IEN_SCI12_SCIX0 IEN2\r
+#define IEN_SCI12_SCIX1 IEN3\r
+#define IEN_SCI12_SCIX2 IEN4\r
+#define IEN_SCI12_SCIX3 IEN5\r
+#define IEN_RIIC0_EEI0 IEN6\r
+#define IEN_RIIC0_RXI0 IEN7\r
+#define IEN_RIIC0_TXI0 IEN0\r
+#define IEN_RIIC0_TEI0 IEN1\r
+\r
+#define VECT_BSC_BUSERR 16\r
+#define VECT_ICU_SWINT 27\r
+#define VECT_CMT0_CMI0 28\r
+#define VECT_CMT1_CMI1 29\r
+#define VECT_CAC_FERRF 32\r
+#define VECT_CAC_MENDF 33\r
+#define VECT_CAC_OVFF 34\r
+#define VECT_USB0_D0FIFO0 36\r
+#define VECT_USB0_D1FIFO0 37\r
+#define VECT_USB0_USBI0 38\r
+#define VECT_RSPI0_SPEI0 44\r
+#define VECT_RSPI0_SPRI0 45\r
+#define VECT_RSPI0_SPTI0 46\r
+#define VECT_RSPI0_SPII0 47\r
+#define VECT_DOC_DOPCF 57\r
+#define VECT_RTC_CUP 63\r
+#define VECT_ICU_IRQ0 64\r
+#define VECT_ICU_IRQ1 65\r
+#define VECT_ICU_IRQ2 66\r
+#define VECT_ICU_IRQ3 67\r
+#define VECT_ICU_IRQ4 68\r
+#define VECT_ICU_IRQ5 69\r
+#define VECT_ICU_IRQ6 70\r
+#define VECT_ICU_IRQ7 71\r
+#define VECT_LVD_LVD1 88\r
+#define VECT_LVD_LVD2 89\r
+#define VECT_USB0_USBR0 90\r
+#define VECT_RTC_ALM 92\r
+#define VECT_RTC_PRD 93\r
+#define VECT_S12AD_S12ADI0 102\r
+#define VECT_S12AD_GBADI 103\r
+#define VECT_ELC_ELSR18I 106\r
+#define VECT_MTU0_TGIA0 114\r
+#define VECT_MTU0_TGIB0 115\r
+#define VECT_MTU0_TGIC0 116\r
+#define VECT_MTU0_TGID0 117\r
+#define VECT_MTU0_TCIV0 118\r
+#define VECT_MTU0_TGIE0 119\r
+#define VECT_MTU0_TGIF0 120\r
+#define VECT_MTU1_TGIA1 121\r
+#define VECT_MTU1_TGIB1 122\r
+#define VECT_MTU1_TCIV1 123\r
+#define VECT_MTU1_TCIU1 124\r
+#define VECT_MTU2_TGIA2 125\r
+#define VECT_MTU2_TGIB2 126\r
+#define VECT_MTU2_TCIV2 127\r
+#define VECT_MTU2_TCIU2 128\r
+#define VECT_MTU3_TGIA3 129\r
+#define VECT_MTU3_TGIB3 130\r
+#define VECT_MTU3_TGIC3 131\r
+#define VECT_MTU3_TGID3 132\r
+#define VECT_MTU3_TCIV3 133\r
+#define VECT_MTU4_TGIA4 134\r
+#define VECT_MTU4_TGIB4 135\r
+#define VECT_MTU4_TGIC4 136\r
+#define VECT_MTU4_TGID4 137\r
+#define VECT_MTU4_TCIV4 138\r
+#define VECT_MTU5_TGIU5 139\r
+#define VECT_MTU5_TGIV5 140\r
+#define VECT_MTU5_TGIW5 141\r
+#define VECT_POE_OEI1 170\r
+#define VECT_POE_OEI2 171\r
+#define VECT_SCI1_ERI1 218\r
+#define VECT_SCI1_RXI1 219\r
+#define VECT_SCI1_TXI1 220\r
+#define VECT_SCI1_TEI1 221\r
+#define VECT_SCI5_ERI5 222\r
+#define VECT_SCI5_RXI5 223\r
+#define VECT_SCI5_TXI5 224\r
+#define VECT_SCI5_TEI5 225\r
+#define VECT_SCI12_ERI12 238\r
+#define VECT_SCI12_RXI12 239\r
+#define VECT_SCI12_TXI12 240\r
+#define VECT_SCI12_TEI12 241\r
+#define VECT_SCI12_SCIX0 242\r
+#define VECT_SCI12_SCIX1 243\r
+#define VECT_SCI12_SCIX2 244\r
+#define VECT_SCI12_SCIX3 245\r
+#define VECT_RIIC0_EEI0 246\r
+#define VECT_RIIC0_RXI0 247\r
+#define VECT_RIIC0_TXI0 248\r
+#define VECT_RIIC0_TEI0 249\r
+\r
+#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19\r
+#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17\r
+#define MSTP_CMT SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23\r
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21\r
+#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19\r
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17\r
+#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9\r
+#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6\r
+#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19\r
+#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0\r
+\r
+#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR\r
+#define _IR( x ) __IR( x )\r
+#define IR( x , y ) _IR( _ ## x ## _ ## y )\r
+#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE\r
+#define _DTCE( x ) __DTCE( x )\r
+#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )\r
+#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x\r
+#define _IEN( x ) __IEN( x )\r
+#define IEN( x , y ) _IEN( _ ## x ## _ ## y )\r
+#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR\r
+#define _IPR( x ) __IPR( x )\r
+#define IPR( x , y ) _IPR( _ ## x ## _ ## y )\r
+#define __VECT( x ) VECT ## x\r
+#define _VECT( x ) __VECT( x )\r
+#define VECT( x , y ) _VECT( _ ## x ## _ ## y )\r
+#define __MSTP( x ) MSTP ## x\r
+#define _MSTP( x ) __MSTP( x )\r
+#define MSTP( x ) _MSTP( _ ## x )\r
+\r
+#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300)\r
+#define CAC (*(volatile struct st_cac __evenaccess *)0x8B000)\r
+#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000)\r
+#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002)\r
+#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008)\r
+#define CRC (*(volatile struct st_crc __evenaccess *)0x88280)\r
+#define DA (*(volatile struct st_da __evenaccess *)0x880C0)\r
+#define DOC (*(volatile struct st_doc __evenaccess *)0x8B080)\r
+#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400)\r
+#define ELC (*(volatile struct st_elc __evenaccess *)0x8B100)\r
+#define FLASH (*(volatile struct st_flash __evenaccess *)0x7FC090)\r
+#define ICU (*(volatile struct st_icu __evenaccess *)0x87000)\r
+#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030)\r
+#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C11F)\r
+#define MTU (*(volatile struct st_mtu __evenaccess *)0x8860A)\r
+#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0x88690)\r
+#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0x88690)\r
+#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0x88692)\r
+#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0x88600)\r
+#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0x88600)\r
+#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0x88694)\r
+#define POE (*(volatile struct st_poe __evenaccess *)0x88900)\r
+#define PORT (*(volatile struct st_port __evenaccess *)0x8C120)\r
+#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000)\r
+#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001)\r
+#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002)\r
+#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003)\r
+#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004)\r
+#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005)\r
+#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A)\r
+#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B)\r
+#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C)\r
+#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E)\r
+#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300)\r
+#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380)\r
+#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400)\r
+#define RTCB (*(volatile struct st_rtcb __evenaccess *)0x8C402)\r
+#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000)\r
+#define SCI1 (*(volatile struct st_sci1 __evenaccess *)0x8A020)\r
+#define SCI5 (*(volatile struct st_sci1 __evenaccess *)0x8A0A0)\r
+#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300)\r
+#define SMCI1 (*(volatile struct st_smci __evenaccess *)0x8A020)\r
+#define SMCI5 (*(volatile struct st_smci __evenaccess *)0x8A0A0)\r
+#define SMCI12 (*(volatile struct st_smci __evenaccess *)0x8B300)\r
+#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000)\r
+#define USB0 (*(volatile struct st_usb __evenaccess *)0xA0000)\r
+#pragma bit_order\r
+#pragma packoption\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : mcu_info.h\r
+* Device(s) : RX111\r
+* Description : Information about the MCU on this board (RSKRX111).\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 08.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+\r
+#ifndef _MCU_INFO\r
+#define _MCU_INFO\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Gets MCU configuration information. */\r
+#include "r_bsp_config.h"\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* MCU Series. */\r
+#if MCU_PART_SERIES == 0x0\r
+ #define MCU_SERIES_RX100 (1)\r
+#else\r
+ #error "ERROR - MCU_PART_SERIES - Unknown MCU Series chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* MCU Group name. */\r
+#if MCU_PART_GROUP == 0x1\r
+ #define MCU_RX111 (1)\r
+ #define MCU_RX11x (1)\r
+#else\r
+ #error "ERROR - MCU_PART_GROUP - Unknown MCU Group chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* Package. */\r
+#if MCU_PART_PACKAGE == 0x0\r
+ #define PACKAGE_LFQFP64 (1)\r
+#elif MCU_PART_PACKAGE == 0x1\r
+ #define PACKAGE_LQFP64 (1)\r
+#elif MCU_PART_PACKAGE == 0x2\r
+ #define PACKAGE_TFLGA64 (1)\r
+#elif MCU_PART_PACKAGE == 0x3\r
+ #define PACKAGE_LFQFP48 (1)\r
+#elif MCU_PART_PACKAGE == 0x4\r
+ #define PACKAGE_VQFN48 (1)\r
+#elif MCU_PART_PACKAGE == 0x5\r
+ #define PACKAGE_HWQFN36 (1)\r
+#elif MCU_PART_PACKAGE == 0x6\r
+ #define PACKAGE_WFLGA36 (1)\r
+#elif MCU_PART_PACKAGE == 0x7\r
+ #define PACKAGE_SSOP36 (1)\r
+#else\r
+ #error "ERROR - MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* Memory size of your MCU. */\r
+#if MCU_PART_MEMORY_SIZE == 0x0 // "J" parts\r
+ #define ROM_SIZE_BYTES (16384)\r
+ #define RAM_SIZE_BYTES (8192)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x1\r
+ #define ROM_SIZE_BYTES (32768)\r
+ #define RAM_SIZE_BYTES (10240)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x3\r
+ #define ROM_SIZE_BYTES (65536)\r
+ #define RAM_SIZE_BYTES (10240)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x4\r
+ #define ROM_SIZE_BYTES (98304)\r
+ #define RAM_SIZE_BYTES (16384)\r
+ #define DF_SIZE_BYTES (8192)\r
+#elif MCU_PART_MEMORY_SIZE == 0x5\r
+ #define ROM_SIZE_BYTES (131072)\r
+ #define RAM_SIZE_BYTES (16384)\r
+ #define DF_SIZE_BYTES (8192)\r
+#else\r
+ #error "ERROR - MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h"\r
+#endif\r
+\r
+/* System clock speed in Hz. */\r
+#define ICLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV)\r
+/* Peripheral Module Clock B speed in Hz. */\r
+#define PCLKB_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV)\r
+/* Peripheral Module Clock D speed in Hz. */\r
+#define PCLKD_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV)\r
+/* FlashIF clock speed in Hz. */\r
+#define FCLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV)\r
+\r
+#endif /* _MCU_INFO */\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : platform.h\r
+* Description : The user chooses which MCU and board they are developing for in this file. If the board you are using\r
+* is not listed below, please add your own or use the default 'User Board'.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 30.11.2011 1.00 First Release\r
+* : 13.01.2012 1.10 Moved from having platform defined using macro defintion, to having platform defined\r
+* by choosing an include path. This makes this file simpler and cleans up the issue\r
+* where HEW shows all header files for all platforms under 'Dependencies'.\r
+* : 14.02.2012 1.20 Added RX210 BSP.\r
+* : 18.04.2012 1.30 Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding\r
+* locking.c and locking.h in board folders. Also, r_bsp can now be configured through\r
+* r_bsp_config.h.\r
+* : 26.06.2012 1.40 Added new options such as exception callbacks and the ability to choose your MCU using\r
+* its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort\r
+* to remove any extra files that the user would need to touch. Removed the flash_options.c\r
+* file and put its contents in vecttbl.c.\r
+* : 17.07.2012 1.50 Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT \r
+* macro options in r_bsp_config.h. Added some extra code to handle exceptions in\r
+* vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks.\r
+* : 08.11.2012 1.60 Added RX111 BSP\r
+***********************************************************************************************************************/\r
+\r
+#ifndef _PLATFORM_H_\r
+#define _PLATFORM_H_\r
+\r
+/***********************************************************************************************************************\r
+DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING.\r
+***********************************************************************************************************************/\r
+/* RSKRX610 */\r
+//#include "./board/rskrx610/r_bsp.h"\r
+\r
+/* RSKRX62N */\r
+//#include "./board/rskrx62n/r_bsp.h"\r
+\r
+/* RSKRX62T */\r
+//#include "./board/rskrx62t/r_bsp.h"\r
+\r
+/* RDKRX62N */\r
+//#include "./board/rdkrx62n/r_bsp.h"\r
+\r
+/* RSKRX630 */\r
+//#include "./board/rskrx630/r_bsp.h"\r
+\r
+/* RSKRX63N */\r
+//#include "./board/rskrx63n/r_bsp.h"\r
+\r
+/* RDKRX63N */\r
+//#include "./board/rdkrx63n/r_bsp.h"\r
+\r
+/* RSKRX210 */\r
+//#include "./board/rskrx210/r_bsp.h"\r
+\r
+/* RSKRX111 */\r
+#include "./board/rskrx111/r_bsp.h"\r
+\r
+/* User Board - Define your own board here. */\r
+//#include "./board/user/r_bsp.h"\r
+\r
+/***********************************************************************************************************************\r
+MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT\r
+***********************************************************************************************************************/\r
+#ifndef PLATFORM_DEFINED\r
+#error "Error - No platform defined in platform.h!"\r
+#endif\r
+\r
+#endif /* _PLATFORM_H_ */\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_bsp_config_reference.c\r
+* Device(s) : RX111\r
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included\r
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)\r
+* is just a reference file that the user can use to make their own r_bsp_config.h file.\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 07.11.2012 0.01 Beta Release\r
+***********************************************************************************************************************/\r
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE\r
+#define R_BSP_CONFIG_REF_HEADER_FILE\r
+\r
+/***********************************************************************************************************************\r
+Configuration Options\r
+***********************************************************************************************************************/\r
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such\r
+ as package and memory size.\r
+ To help parse this information, the part number will be defined using multiple macros.\r
+ R 5 F 51 11 5 A D FM\r
+ | | | | | | | | | Macro Name Description\r
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch\r
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)\r
+ | | | | | | |______not used = Blank\r
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity\r
+ | | | | |___________MCU_PART_GROUP = Group name\r
+ | | | |______________MCU_PART_SERIES = Series name\r
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)\r
+ | |__________________not used = Renesas MCU\r
+ |____________________not used = Renesas semiconductor product.\r
+ */\r
+\r
+/* Package type. Set the macro definition based on values below:\r
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch\r
+ FM = 0x0 = LFQFP/64/0.50\r
+ FK = 0x1 = LQFP/64/0.80\r
+ LF = 0x2 = TFLGA/64/0.50\r
+ FL = 0x3 = LFQFP/48/0.50\r
+ NE = 0x4 = VQFN/48/0.50\r
+ NC = 0x5 = HWQFN/36/0.50\r
+ LM = 0x6 = WFLGA/36/0.50\r
+ SB = 0x7 = SSOP/36/0.80\r
+*/\r
+#define MCU_PART_PACKAGE (0x0)\r
+\r
+/* ROM, RAM, and Data Flash Capacity.\r
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size\r
+ 5 = 0x5 = 128KB/16KB/8KB\r
+ 4 = 0x4 = 96KB/16KB/8KB\r
+ 3 = 0x3 = 64KB/10KB/8KB\r
+ 1 = 0x1 = 32KB/10KB/8KB\r
+ J = 0x0 = 16KB/8KB/8KB\r
+*/\r
+#define MCU_PART_MEMORY_SIZE (0x5)\r
+\r
+/* Group name.\r
+ Character(s) = Value for macro = Description\r
+ 10 = 0x0 = RX110 Group\r
+ 11 = 0x1 = RX111 Group\r
+*/\r
+#define MCU_PART_GROUP (0x1)\r
+\r
+/* Series name.\r
+ Character(s) = Value for macro = Description\r
+ 51 = 0x0 = RX100 Series\r
+*/\r
+#define MCU_PART_SERIES (0x0)\r
+\r
+/* Memory type.\r
+ Character(s) = Value for macro = Description\r
+ F = 0x0 = Flash memory version\r
+*/\r
+#define MCU_PART_MEMORY_TYPE (0x0)\r
+\r
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a\r
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */\r
+#if defined(BSP_DECLARE_STACK)\r
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize su=0x400\r
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */\r
+#pragma stacksize si=0x100\r
+#endif\r
+\r
+/* Heap size in bytes. */\r
+#define HEAP_BYTES (0x001)\r
+\r
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information\r
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.\r
+ 0 = Stay in Supervisor mode.\r
+ 1 = Switch to User mode.\r
+*/\r
+#define RUN_IN_USER_MODE (0)\r
+\r
+\r
+/* This macro lets other modules no if a RTOS is being used.\r
+ 0 = RTOS is not used.\r
+ 1 = RTOS is used.\r
+*/\r
+#define RTOS_USED (0)\r
+\r
+/* Clock source select (CKSEL).\r
+ 0 = Low Speed On-Chip Oscillator (LOCO)\r
+ 1 = High Speed On-Chip Oscillator (HOCO)\r
+ 2 = Main Clock Oscillator\r
+ 3 = Sub-Clock Oscillator\r
+ 4 = PLL Circuit\r
+*/\r
+#define CLOCK_SOURCE (4) // GI org 4\r
+\r
+/* Clock configuration options.\r
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The\r
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the\r
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the\r
+ settings would be:\r
+\r
+ XTAL_HZ = 16000000\r
+ PLL_DIV = 2\r
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)\r
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz\r
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz\r
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz\r
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz\r
+*/\r
+/* XTAL - Input clock frequency in Hz */\r
+#define XTAL_HZ (16000000)\r
+/* PLL Input Frequency Divider Select (PLIDIV).\r
+ Available divisors = /1 (no division), /2, /4\r
+*/\r
+#define PLL_DIV (2) // GI org 2\r
+/* PLL Frequency Multiplication Factor Select (STC).\r
+ Available multipliers = x6, x8\r
+*/\r
+#define PLL_MUL (6) // GI org 6\r
+/* System Clock Divider (ICK).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define ICK_DIV (2) // NOTE: ICLK CANNOT BE SLOWER THAN PCLK!\r
+/* Peripheral Module Clock B Divider (PCKB).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKB_DIV (2) // GI org 2\r
+/* Peripheral Module Clock D Divider (PCKD).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define PCKD_DIV (2)\r
+/* Flash IF Clock Divider (FCK).\r
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64\r
+*/\r
+#define FCK_DIV (2)\r
+\r
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and\r
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a\r
+ function to be called when the event occurs. For example, if the user wanted the function\r
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would\r
+ do the following:\r
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+ If the user does not wish to be alerted of these events then they should comment out the macros.\r
+\r
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function\r
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it\r
+ is executing. For this reason, it is recommended to keep these callback functions short as to not\r
+ decrease the real-time response of your system.\r
+*/\r
+/* Callback for Supervisor Instruction Violation Exception. */\r
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb\r
+\r
+/* Callback for Undefined Instruction Exception. */\r
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb\r
+\r
+/* Callback for Non-maskable Interrupt. */\r
+//#define NMI_ISR_CALLBACK nmi_cb\r
+\r
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source\r
+ is creating unwanted interrupts. */\r
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb\r
+\r
+/* Callback for Bus Error Interrupt. */\r
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb\r
+\r
+/* The user has the option of separately choosing little or big endian for the User Application Area */\r
+\r
+/* Endian mode for User Application.\r
+ 0 = Big Endian\r
+ Else = Little Endian (Default)\r
+*/\r
+#define USER_APP_ENDIAN (1)\r
+\r
+\r
+/* Configure WDT and IWDT settings.\r
+ OFS0 - Option Function Select Register 0\r
+ OFS0 - Option Function Select Register 0\r
+ b31:b15 Reserved (set to 1)\r
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)\r
+ b13 Reserved (set to 1)\r
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)\r
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)\r
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)\r
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)\r
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)\r
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)\r
+ b0 Reserved (set to 1) */\r
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.\r
+ OFS1 - Option Function Select Register 1\r
+ b31:b9 Reserved (set to 1)\r
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)\r
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select\r
+ 0 1 0 0: 3.10 V\r
+ 0 1 0 1: 3.00 V\r
+ 0 1 1 0: 2.90 V\r
+ 0 1 1 1: 2.79 V\r
+ 1 0 0 0: 2.68 V\r
+ 1 0 0 1: 2.58 V\r
+ 1 0 1 0: 2.48 V\r
+ 1 0 1 1: 2.06 V\r
+ 1 1 0 0: 1.96 V\r
+ 1 1 0 1: 1.86 V\r
+ b3:b2 Reserved (set to 1)\r
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)\r
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */\r
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default\r
+\r
+/* Initializes C input & output library functions.\r
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.\r
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */\r
+#define IO_LIB_ENABLE (0)\r
+\r
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */\r
+\r
+\r
+\r
--- /dev/null
+r_bsp Package\r
+=============\r
+\r
+Document Number\r
+---------------\r
+N/A\r
+\r
+Version\r
+-------\r
+v1.60\r
+\r
+Overview\r
+--------\r
+The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU\r
+information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder has iodefine\r
+files and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board\r
+and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help \r
+configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each \r
+supported board. Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which \r
+board they are using by uncommenting the include path that applies to their board. For example, if you are using the \r
+RSK+RX62N then you would uncomment the #include "./board/rskrx62n/r_bsp.h" include path. Users are encouraged to add \r
+their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a \r
+reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it \r
+to r_bsp_config.h, and use the options inside the file to configure the BSP for their project.\r
+\r
+Features\r
+--------\r
+* Provides foundation to build code on top of.\r
+* Provides MCU startup code.\r
+* Provides SFR access through iodefine.h\r
+* Stores details of MCU in 'mcu_info.h' to help configure Renesas middleware.\r
+* Easily configure BSP through r_bsp_config.h.\r
+* Choose MCU easily by inputting part number details in r_bsp_config.h.\r
+* Provides callbacks for MCU exceptions and the bus error interrupt.\r
+ \r
+Limitations\r
+-----------\r
+N/A\r
+\r
+Peripherals Used Directly\r
+-------------------------\r
+N/A\r
+\r
+Required Packages\r
+-----------------\r
+* r_glyph [required if you want to use LCD for RDK boards]\r
+* r_rspi_rx [required if you want to use LCD for RDK boards]\r
+\r
+How to add to your project\r
+--------------------------\r
+* Copy the r_bsp folder to your project.\r
+* Add an include path to the 'r_bsp' directory. \r
+* Add all of the source files for your board from the 'r_bsp\board\--YOUR_BOARD--' directory to your project. \r
+* Uncomment the include path for your board in 'platform.h' which is located in the 'r_bsp' directory.\r
+* Copy the file r_bsp_config_reference.h from the 'r_bsp\board\--YOUR_BOARD--' directory and copy it to your project's\r
+ source code directory. Rename the file r_bsp_config.h.\r
+* Open r_bsp_config.h and use the macros to configure the BSP for your project.\r
+\r
+File Structure\r
+--------------\r
+r_bsp\r
+| platform.h (choose which board is being used)\r
+| readme.txt\r
+|\r
++---board (contains supported boards)\r
+| +---rdkrx62n (contains BSP source and header files)\r
+| |\r
+| +---rdkrx63n\r
+| |\r
+| +---rskrx111\r
+| |\r
+| +---rskrx210\r
+| |\r
+| +---rskrx610\r
+| |\r
+| +---rskrx62n\r
+| |\r
+| +---rskrx62t\r
+| |\r
+| +---rskrx630\r
+| |\r
+| +---rskrx63n\r
+| |\r
+| \---user\r
+|\r
+\---mcu\r
+ +---rx111 (contains common files to this MCU group, e.g. iodefine.h)\r
+ |\r
+ +---rx210 \r
+ |\r
+ +---rx610\r
+ |\r
+ +---rx62n\r
+ |\r
+ +---rx62t\r
+ |\r
+ +---rx630\r
+ |\r
+ \---rx63n\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_switches_config.c\r
+* Description : Configures the switches code\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 17.01.2012 1.00 First Release\r
+* : 17.02.2012 1.10 Added RSKRX210 support.\r
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).\r
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.\r
+***********************************************************************************************************************/\r
+#ifndef SWITCHES_CONFIG_HEADER_FILE\r
+#define SWITCHES_CONFIG_HEADER_FILE\r
+\r
+/***********************************************************************************************************************\r
+Configuration Options\r
+***********************************************************************************************************************/\r
+/* This macro sets whether interrupts or polling is used for detecting switch presses. The benefit of using interrupts\r
+ is that no extra processing is used for polling and the use of a system timer tick is not a requirement. The downside\r
+ of using interrupts is that callback functions are called from within an interrupt so if your ISR is long then it can\r
+ degrade the real-time response of your system. The benefit of polling is that functions are called at the application\r
+ level and debouncing is supported. The downside to polling is that your system must call the R_SWITCHES_Update() on a\r
+ regular basis which requires extra processing.\r
+\r
+ 0 = Use interrupts\r
+ 1 = Use polling\r
+ */\r
+#define SWITCHES_DETECTION_MODE (0)\r
+\r
+/* The definition for these macros should be the name of the function that you want called when a switch is\r
+ pressed. It is very important that the user recognize that this function will be called from the interrupt service\r
+ routine. This means that code inside of the function should be kept short to ensure it does not hold up the rest of\r
+ the system.\r
+\r
+ Example: If SW1_CALLBACK_FUNCTION is defined to be sw1_callback then the sw1_callback function will be called when\r
+ switch 1 is pressed.\r
+*/\r
+#define SW1_CALLBACK_FUNCTION (vButtonInterruptCallback)\r
+#define SW2_CALLBACK_FUNCTION (vButtonInterruptCallback)\r
+#define SW3_CALLBACK_FUNCTION (vButtonInterruptCallback)\r
+\r
+#endif /* SWITCHES_CONFIG_HEADER_FILE */\r
--- /dev/null
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches_if.h
+* Description : Functions for using switches with callback functions.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+***********************************************************************************************************************/
+
+#ifndef SWITCHES_API_HEADER_FILE
+#define SWITCHES_API_HEADER_FILE
+
+/***********************************************************************************************************************
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/
+/* Fixed width integer support. */\r
+#include <stdint.h>\r
+/* bool support */\r
+#include <stdbool.h>\r
+/* Used for configuring the code */
+#include "r_switches_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Version Number of API. */
+#define SWITCHES_VERSION_MAJOR (1)
+#define SWITCHES_VERSION_MINOR (0)
+/* The process of getting the version number is done through the macro below. The version number is encoded where the
+ top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example,
+ Version 4.25 would be returned as 0x00040019. */
+#define R_SWITCHES_GetVersion() ((((uint32_t)SWITCHES_VERSION_MAJOR) << 16) | (uint32_t)SWITCHES_VERSION_MINOR)
+
+/***********************************************************************************************************************
+Public Functions
+***********************************************************************************************************************/
+void R_SWITCHES_Init(uint32_t detection_hz, uint32_t debounce_counts);
+void R_SWITCHES_Update(void);
+
+/* Callback prototypes. */
+#if defined(SW1_CALLBACK_FUNCTION)
+void SW1_CALLBACK_FUNCTION(void);
+#endif
+
+#if defined(SW2_CALLBACK_FUNCTION)
+void SW2_CALLBACK_FUNCTION(void);
+#endif
+
+#if defined(SW3_CALLBACK_FUNCTION)
+void SW3_CALLBACK_FUNCTION(void);
+#endif
+
+#endif /* SWITCHES_API_HEADER_FILE */
+
--- /dev/null
+PLEASE REFER TO THE APPLICATION NOTE FOR THIS MIDDLEWARE FOR MORE INFORMATION\r
+\r
+Switches\r
+========\r
+\r
+Document Number \r
+---------------\r
+N/A\r
+\r
+Version\r
+-------\r
+v1.40\r
+\r
+Overview\r
+--------\r
+Configures port pins for switches and calls user defined function on switch press. Switch presses can be detected using \r
+IRQ interrupts or by polling. The benefit of using interrupts is that no extra processing is used for polling and the \r
+use of a system timer tick is not a requirement. The downside of using interrupts is that callback functions are called \r
+from within an interrupt so if your ISR is long then it can degrade the real-time response of your system. The benefit \r
+of polling is that functions are called at the application level and debouncing is supported. The downside to polling is \r
+that your system must call the R_SWITCHES_Update() on a regular basis which requires extra processing.\r
+\r
+Features\r
+--------\r
+* Call one function to setup switches.\r
+* Define function to call when switch is pressed.\r
+* Can be configured to be interrupt or poll driven.\r
+\r
+Supported MCUs\r
+--------------\r
+* RX610 Group\r
+* RX621, RX62N Group\r
+* RX62T Group\r
+* RX630 Group\r
+* RX631, RX63N Group\r
+* RX210 Group\r
+* RX111 Group\r
+\r
+Boards Tested On\r
+----------------\r
+* RSKRX610\r
+* RSK+RX62N\r
+* RSKRX62T\r
+* RDKRX62N\r
+* RSKRX630\r
+* RSKRX63N\r
+* RDKRX63N\r
+* RSKRX111\r
+\r
+Limitations\r
+-----------\r
+* None\r
+\r
+Peripherals Used Directly\r
+-------------------------\r
+* None\r
+\r
+Required Packages\r
+-----------------\r
+* None\r
+\r
+How to add to your project\r
+--------------------------\r
+* Add src\r_switches.c to your project.\r
+* Add an include path to the 'r_switches' directory. \r
+* Add an include path to the 'r_switches\src' directory.\r
+* Configure middleware through r_switches_config.h.\r
+* Add a #include for r_switches_if.h to files that need to use this package. \r
+\r
+Toolchain(s) Used\r
+-----------------\r
+* Renesas RX v1.02\r
+\r
+File Structure\r
+--------------\r
+r_switches\r
+| readme.txt\r
+| r_switches_config.h\r
+| r_switches_if.h\r
+|\r
+\---src\r
+ r_switches.c\r
+ \r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No\r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,\r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM\r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES\r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS\r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of\r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : r_switches.c\r
+* Description : Functions for using switches with callback functions.\r
+************************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 17.01.2012 1.00 First Release\r
+* : 17.02.2012 1.10 Added RSKRX210 support.\r
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).\r
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.\r
+* : 07.11.2012 1.40 Added support for RSKRX111\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+***********************************************************************************************************************/\r
+/* Board and MCU support. */\r
+#include "platform.h"\r
+/* Switches prototypes. */\r
+#include "r_switches_if.h"\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+/* This helps reduce the amount of unique code for each supported board. */\r
+#define X_IRQ( x ) XX_IRQ( x )\r
+#define XX_IRQ( x ) _ICU_IRQ##x\r
+\r
+/* These macros define which IRQ pins are used for the switches. Note that these defintions cannot have parentheses\r
+ around them. */\r
+#if defined(PLATFORM_BOARD_RDKRX63N)\r
+ #define SW1_IRQ_NUMBER 8\r
+ #define SW2_IRQ_NUMBER 9\r
+ #define SW3_IRQ_NUMBER 12\r
+#elif defined(PLATFORM_BOARD_RSKRX63N)\r
+ #define SW1_IRQ_NUMBER 2\r
+ #define SW2_IRQ_NUMBER 8\r
+ #define SW3_IRQ_NUMBER 15\r
+#elif defined(PLATFORM_BOARD_RSKRX630)\r
+ #define SW1_IRQ_NUMBER 2\r
+ #define SW2_IRQ_NUMBER 12\r
+ #define SW3_IRQ_NUMBER 15\r
+#elif defined(PLATFORM_BOARD_RSKRX62N)\r
+ #define SW1_IRQ_NUMBER 8\r
+ #define SW2_IRQ_NUMBER 9\r
+ #define SW3_IRQ_NUMBER 15\r
+#elif defined(PLATFORM_BOARD_RDKRX62N)\r
+ #define SW1_IRQ_NUMBER 8\r
+ #define SW2_IRQ_NUMBER 9\r
+ #define SW3_IRQ_NUMBER 10\r
+#elif defined(PLATFORM_BOARD_RSKRX62T)\r
+ #define SW1_IRQ_NUMBER 0\r
+ #define SW2_IRQ_NUMBER 1\r
+ #define SW3_IRQ_NUMBER 3\r
+#elif defined(PLATFORM_BOARD_RSKRX610)\r
+ #define SW1_IRQ_NUMBER 8\r
+ #define SW2_IRQ_NUMBER 9\r
+ #define SW3_IRQ_NUMBER 3\r
+#elif defined(PLATFORM_BOARD_RSKRX210)\r
+ #define SW1_IRQ_NUMBER 1\r
+ #define SW2_IRQ_NUMBER 3\r
+ #define SW3_IRQ_NUMBER 4\r
+#elif defined(PLATFORM_BOARD_RSKRX111)\r
+ #define SW1_IRQ_NUMBER 0\r
+ #define SW2_IRQ_NUMBER 1\r
+ #define SW3_IRQ_NUMBER 4\r
+#endif\r
+\r
+/* Number of switches on this board. */\r
+#define SWITCHES_NUM (3)\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+typedef struct\r
+{\r
+ bool active;\r
+ int32_t debounce_cnt;\r
+} switch_t;\r
+\r
+/***********************************************************************************************************************\r
+Private global variables and functions\r
+***********************************************************************************************************************/\r
+#if SWITCHES_DETECTION_MODE == 1\r
+/* Update Hz */\r
+static uint32_t g_sw_debounce_cnts;\r
+/* Used for debounce. */\r
+switch_t g_switches[SWITCHES_NUM];\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_SWITCHES_Init\r
+* Description : Initializes pins to be input and interrupt on switch presses.\r
+* Arguments : detection_hz -\r
+* The times per second that the user will call R_SWITCHES_Update(). NOTE: this is only when using\r
+* polling mode. If you are using interrupt mode, then this argument will be ignored.\r
+* debouce_counts -\r
+* The number of times to check the port value before accepting the change. The slower the rate at\r
+* which R_SWITCHES_Update() will likely lower this number.\r
+* Return Value : none\r
+***********************************************************************************************************************/\r
+void R_SWITCHES_Init (uint32_t detection_hz, uint32_t debounce_counts)\r
+{\r
+ uint32_t i;\r
+\r
+ /* The SW#_XXX defintions are common macros amongst different boards. To see the definitions for these macros\r
+ see the board defintion file. For example, this file for the RSKRX63N is rskrx63n.h. */\r
+\r
+#if defined(MCU_RX62N) || defined(MCU_RX62T) || defined(MCU_RX621) || defined(MCU_RX610)\r
+\r
+ /* Make switch pins inputs. */\r
+ SW1_DDR = 0;\r
+ SW2_DDR = 0;\r
+ SW3_DDR = 0;\r
+\r
+ /* Enable input buffer control registers. */\r
+ SW1_ICR = 1;\r
+ SW2_ICR = 1;\r
+ SW3_ICR = 1;\r
+\r
+#elif defined(MCU_RX63N) || defined(MCU_RX630) || defined(MCU_RX631) || defined(MCU_RX210) || defined(MCU_RX111)\r
+\r
+ /* Unlock protection register */\r
+ MPC.PWPR.BIT.B0WI = 0 ;\r
+ /* Unlock MPC registers */\r
+ MPC.PWPR.BIT.PFSWE = 1 ;\r
+\r
+ /* Make switch pins inputs. */\r
+ SW1_PDR = 0;\r
+ SW2_PDR = 0;\r
+ SW3_PDR = 0;\r
+\r
+ /* Set port mode registers for switches. */\r
+ SW1_PMR = 0;\r
+ SW2_PMR = 0;\r
+ SW3_PMR = 0;\r
+\r
+#endif\r
+\r
+#if SWITCHES_DETECTION_MODE == 0\r
+\r
+ #if defined(PLATFORM_BOARD_RDKRX63N)\r
+\r
+ /* The switches on the RDKRX63N are connected to the following pins/IRQ's\r
+ Switch Port IRQ\r
+ ------ ---- ----\r
+ SW1 P4.0 IRQ8\r
+ SW2 P4.1 IRQ9\r
+ SW3 P4.4 IRQ12\r
+ */\r
+\r
+ MPC.P40PFS.BYTE = 0x40; /* P40 is used as IRQ pin */\r
+ MPC.P41PFS.BYTE = 0x40; /* P40 is used as IRQ pin */\r
+ MPC.P44PFS.BYTE = 0x40; /* P40 is used as IRQ pin */\r
+\r
+ #elif defined(PLATFORM_BOARD_RSKRX63N)\r
+\r
+ /* The switches on the RSKRX63N are connected to the following pins/IRQ's\r
+ Switch Port IRQ\r
+ ------ ---- ----\r
+ SW1 P3.2 IRQ2\r
+ SW2 P0.0 IRQ8\r
+ SW3 P0.7 IRQ15\r
+ */\r
+\r
+ MPC.P32PFS.BYTE = 0x40; /* P32 is used as IRQ pin */\r
+ MPC.P00PFS.BYTE = 0x40; /* P00 is used as IRQ pin */\r
+ MPC.P07PFS.BYTE = 0x40; /* P07 is used as IRQ pin */\r
+\r
+ #elif defined(PLATFORM_BOARD_RSKRX630)\r
+\r
+ /* The switches on the RSKRX630 are connected to the following pins/IRQ's\r
+ Switch Port IRQ\r
+ ------ ---- ----\r
+ SW1 P3.2 IRQ2\r
+ SW2 P4.4 IRQ12\r
+ SW3 P0.7 IRQ15\r
+ */\r
+\r
+ MPC.P32PFS.BYTE = 0x40; /* P32 is used as IRQ pin */\r
+ MPC.P44PFS.BYTE = 0x40; /* P44 is used as IRQ pin */\r
+ MPC.P07PFS.BYTE = 0x40; /* P07 is used as IRQ pin */\r
+\r
+ #elif defined(PLATFORM_BOARD_RSKRX62N)\r
+\r
+ /* The switches on the RSKRX62N are connected to the following pins/IRQ's\r
+ Switch Port IRQ\r
+ ------ ---- ----\r
+ SW1 P0.0 IRQ8-A\r
+ SW2 P0.1 IRQ9-A\r
+ SW3 P0.7 IRQ15-A\r
+ */\r
+\r
+ IOPORT.PF8IRQ.BIT.ITS8 = 0; /* IRQ8-A pin is used. */\r
+ IOPORT.PF8IRQ.BIT.ITS9 = 0; /* IRQ9-A pin is used. */\r
+ IOPORT.PF8IRQ.BIT.ITS15 = 0; /* IRQ15-A pin is used. */\r
+\r
+ #elif defined(PLATFORM_BOARD_RDKRX62N)\r
+\r
+ /* The switches on the RDKRX62N are connected to the following pins/IRQ's\r
+ Switch Port IRQ\r
+ ------ ---- ----\r
+ SW1 P4.0 IRQ8\r
+ SW2 P4.1 IRQ9\r
+ SW3 P4.2 IRQ10\r
+ */\r
+\r
+ /* Nothing else needed to do here since RDK has 100-pin package and there are no alternate pins to choose. */\r
+\r
+ #elif defined(PLATFORM_BOARD_RSKRX62T)\r
+\r
+ /* The switches on the RSKRX62T are connected to the following pins/IRQ's\r
+ Switch Port IRQ\r
+ ------ ---- ----\r
+ SW1 PE.5 IRQ0-B\r
+ SW2 PE.4 IRQ1-B\r
+ SW3 PB.4 IRQ3\r
+ */\r
+\r
+ IOPORT.PF8IRQ.BIT.ITS0 = 1; /* IRQ0-B pin is used. */\r
+ IOPORT.PF8IRQ.BIT.ITS1 = 1; /* IRQ1-B pin is used. */\r
+ /* IRQ3 is only on 1 pin. */\r
+\r
+ #elif defined(PLATFORM_BOARD_RSKRX610)\r
+\r
+ /* The switches on the RSKRX610 are connected to the following pins/IRQ's\r
+ Switch Port IRQ\r
+ ------ ---- ----\r
+ SW1 P0.0 IRQ8-A\r
+ SW2 P0.1 IRQ9-A\r
+ SW3 P1.3 IRQ3-B\r
+ */\r
+\r
+ IOPORT.PFCR8.BIT.ITS8 = 0; /* IRQ8-A pin is used. */\r
+ IOPORT.PFCR8.BIT.ITS9 = 0; /* IRQ9-A pin is used. */\r
+ IOPORT.PFCR9.BIT.ITS3 = 1; /* IRQ3-B pin is used. */\r
+\r
+ /* Enable IRQ detection. */\r
+ ICU.IRQER[SW1_IRQ_NUMBER].BIT.IRQEN = 1;\r
+ ICU.IRQER[SW2_IRQ_NUMBER].BIT.IRQEN = 1;\r
+ ICU.IRQER[SW3_IRQ_NUMBER].BIT.IRQEN = 1;\r
+\r
+ #elif defined(PLATFORM_BOARD_RSKRX210)\r
+\r
+ /* The switches on the RSKRX210 are connected to the following pins/IRQ's\r
+ Switch Port IRQ\r
+ ------ ---- ----\r
+ SW1 P3.1 IRQ1\r
+ SW2 P3.3 IRQ3\r
+ SW3 P3.4 IRQ4\r
+ */\r
+\r
+ MPC.P31PFS.BYTE = 0x40; /* P31 is used as IRQ pin */\r
+ MPC.P33PFS.BYTE = 0x40; /* P33 is used as IRQ pin */\r
+ MPC.P34PFS.BYTE = 0x40; /* P34 is used as IRQ pin */\r
+\r
+#elif defined(PLATFORM_BOARD_RSKRX111)\r
+\r
+ /* The switches on the RSKRX210 are connected to the following pins/IRQ's\r
+ Switch Port IRQ\r
+ ------ ---- ----\r
+ SW1 P3.0 IRQ0\r
+ SW2 P3.1 IRQ1\r
+ SW3 PE.4 IRQ4\r
+ */\r
+\r
+ MPC.P30PFS.BYTE = 0x40; /* P30 is used as IRQ pin */\r
+ MPC.P31PFS.BYTE = 0x40; /* P31 is used as IRQ pin */\r
+ MPC.PE4PFS.BYTE = 0x40; /* PE4 is used as IRQ pin */\r
+\r
+ #endif\r
+\r
+\r
+ /* Set IRQ type (falling edge) */\r
+ ICU.IRQCR[SW1_IRQ_NUMBER].BIT.IRQMD = 0x01;\r
+ ICU.IRQCR[SW2_IRQ_NUMBER].BIT.IRQMD = 0x01;\r
+ ICU.IRQCR[SW3_IRQ_NUMBER].BIT.IRQMD = 0x01;\r
+\r
+ /* Set interrupt priorities which muse be below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ _IPR( X_IRQ(SW1_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;\r
+ _IPR( X_IRQ(SW2_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;\r
+ _IPR( X_IRQ(SW3_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;\r
+\r
+ /* Clear any pending interrupts */\r
+ _IR( X_IRQ(SW1_IRQ_NUMBER) ) = 0;\r
+ _IR( X_IRQ(SW2_IRQ_NUMBER) ) = 0;\r
+ _IR( X_IRQ(SW3_IRQ_NUMBER) ) = 0;\r
+\r
+ /* Enable the interrupts */\r
+ _IEN( X_IRQ(SW1_IRQ_NUMBER) ) = 1;\r
+ _IEN( X_IRQ(SW2_IRQ_NUMBER) ) = 1;\r
+ _IEN( X_IRQ(SW3_IRQ_NUMBER) ) = 1;\r
+\r
+#else\r
+\r
+ /* This is based upon having 3 counts at 10Hz. */\r
+ g_sw_debounce_cnts = debounce_counts;\r
+\r
+ /* Init debounce structures. */\r
+ for (i = 0; i < SWITCHES_NUM; i++)\r
+ {\r
+ g_switches[i].active = false;\r
+ g_switches[i].debounce_cnt = 0;\r
+ }\r
+\r
+#endif /* SWITCHES_DETECTION_MODE */\r
+\r
+}\r
+\r
+/* Only define interrupts in interrupt detection mode. */\r
+#if SWITCHES_DETECTION_MODE == 0\r
+\r
+ #if defined(SW1_CALLBACK_FUNCTION)\r
+/***********************************************************************************************************************\r
+* Function name: sw1_isr\r
+* Description : Sample ISR for switch 1 input (must do hardware setup first!)\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+#pragma interrupt (sw1_isr (vect=_VECT(X_IRQ(SW1_IRQ_NUMBER))))\r
+static void sw1_isr (void)\r
+{\r
+ /* TODO: Add some debouncing! */\r
+\r
+ /* Call callback function. */\r
+ SW1_CALLBACK_FUNCTION();\r
+}\r
+ #endif /* SW1_CALLBACK_FUNCTION */\r
+\r
+ #if defined(SW2_CALLBACK_FUNCTION)\r
+/***********************************************************************************************************************\r
+* Function name: sw2_isr\r
+* Description : Sample ISR for switch 2 input (must do hardware setup first!)\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+#pragma interrupt (sw2_isr (vect=_VECT(X_IRQ(SW2_IRQ_NUMBER))))\r
+static void sw2_isr (void)\r
+{\r
+ /* TODO: Add some debouncing! */\r
+\r
+ /* Call callback function. */\r
+ SW2_CALLBACK_FUNCTION();\r
+}\r
+ #endif /* SW2_CALLBACK_FUNCTION */\r
+\r
+ #if defined(SW3_CALLBACK_FUNCTION)\r
+/***********************************************************************************************************************\r
+* Function name: sw3_isr\r
+* Description : Sample ISR for switch 3 input (must do hardware setup first!)\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+#pragma interrupt (sw3_isr (vect=_VECT(X_IRQ(SW3_IRQ_NUMBER))))\r
+static void sw3_isr (void)\r
+{\r
+ /* TODO: Add some debouncing! */\r
+\r
+ /* Call callback function. */\r
+ SW3_CALLBACK_FUNCTION();\r
+}\r
+ #endif /* SW3_CALLBACK_FUNCTION */\r
+\r
+#endif\r
+\r
+/* If using polling then the user must call the update function. */\r
+\r
+/***********************************************************************************************************************\r
+* Function name: R_SWITCHES_Update\r
+* Description : Polls switches and calls callback functions as needed. If you are using IRQ mode then this function\r
+* is not needed and can be removed if desired. It is left in so that code will not fail when switching\r
+* between polling or IRQ mode.\r
+* Arguments : none\r
+* Return value : none\r
+***********************************************************************************************************************/\r
+void R_SWITCHES_Update (void)\r
+{\r
+#if SWITCHES_DETECTION_MODE == 1\r
+ /* This code is only needed for polling mode. */\r
+ /* Check switch 1. */\r
+ if (SW1 == SW_ACTIVE)\r
+ {\r
+ if (g_switches[0].active != true)\r
+ {\r
+ if (++g_switches[0].debounce_cnt >= g_sw_debounce_cnts)\r
+ {\r
+ /* Set this to true so we only call the callback function once per press. */\r
+ g_switches[0].active = true;\r
+\r
+ /* Call callback function. */\r
+ SW1_CALLBACK_FUNCTION();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (0 == g_switches[0].debounce_cnt)\r
+ {\r
+ g_switches[0].active = false;\r
+ }\r
+ else\r
+ {\r
+ g_switches[0].debounce_cnt--;\r
+ }\r
+ }\r
+\r
+ /* Check switch 2. */\r
+ if (SW2 == SW_ACTIVE)\r
+ {\r
+ if (g_switches[1].active != true)\r
+ {\r
+ if (++g_switches[1].debounce_cnt >= g_sw_debounce_cnts)\r
+ {\r
+ /* Set this to true so we only call the callback function once per press. */\r
+ g_switches[1].active = true;\r
+\r
+ /* Call callback function. */\r
+ SW2_CALLBACK_FUNCTION();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (0 == g_switches[1].debounce_cnt)\r
+ {\r
+ g_switches[1].active = false;\r
+ }\r
+ else\r
+ {\r
+ g_switches[1].debounce_cnt--;\r
+ }\r
+ }\r
+\r
+ /* Check switch 3. */\r
+ if (SW3 == SW_ACTIVE)\r
+ {\r
+ if (g_switches[2].active != true)\r
+ {\r
+ if (++g_switches[2].debounce_cnt >= g_sw_debounce_cnts)\r
+ {\r
+ /* Set this to true so we only call the callback function once per press. */\r
+ g_switches[2].active = true;\r
+\r
+ /* Call callback function. */\r
+ SW3_CALLBACK_FUNCTION();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (0 == g_switches[2].debounce_cnt)\r
+ {\r
+ g_switches[2].active = false;\r
+ }\r
+ else\r
+ {\r
+ g_switches[2].debounce_cnt--;\r
+ }\r
+ }\r
+#endif /* SWITCHES_DETECTION_MODE */\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A low power project that\r
+ * demonstrates the FreeRTOS tickless mode, and a more comprehensive test and\r
+ * demo application. The configCREATE_LOW_POWER_DEMO setting (defined at the\r
+ * top of FreeRTOSConfig.h) is used to select between the two. The low power\r
+ * demo is implemented and described in main_low_power.c. The more\r
+ * comprehensive test and demo application is implemented and described in\r
+ * main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Platform includes. */\r
+#include "lcd.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1.\r
+ * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0.\r
+ */\r
+extern void main_low_power( void );\r
+extern void main_full( void );\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the documentation page for this demo on the FreeRTOS.org web site for\r
+full information - including hardware setup requirements. */\r
+\r
+void main( void )\r
+{\r
+ lcd_initialize();\r
+ lcd_display( LCD_LINE1, "FreeRTOS" );\r
+\r
+ /* The configCREATE_LOW_POWER_DEMO setting is described in FreeRTOSConfig.h. */\r
+ #if configCREATE_LOW_POWER_DEMO == 1\r
+ {\r
+ lcd_display( LCD_LINE2, "LP Demo" );\r
+ main_low_power();\r
+ }\r
+ #else\r
+ {\r
+ lcd_display( LCD_LINE2, "Ful Demo" );\r
+ main_full();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the size\r
+ of the heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE\r
+ in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is\r
+ called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if\r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAssertCalled( void )\r
+{\r
+volatile unsigned long ul = 0;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Set ul to a non-zero value using the debugger to step out of this\r
+ function. */\r
+ while( ul == 0 )\r
+ {\r
+ nop();\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/* ****************************************************************************\r
+ * This project includes a lot of tasks and tests and is therefore complex.\r
+ * If you would prefer a much simpler project to get started with then select\r
+ * the 'low power' demo by setting configCREATE_LOW_POWER_DEMO to 1 in\r
+ * FreeRTOSConfig.h. When configCREATE_LOW_POWER_DEMO is set to 1 main() will\r
+ * call main_low_power() instead of main_full().\r
+ * ****************************************************************************\r
+ *\r
+ * Creates all the demo application tasks, then starts the scheduler. The web\r
+ * documentation provides more details of the standard demo application tasks,\r
+ * which provide no particular functionality but do provide a good example of\r
+ * how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then\r
+ * repeatedly check that each register still contains its expected value for\r
+ * the lifetime of the tasks. Each task uses different values. The tasks run\r
+ * with very low priority so get preempted very frequently. A check variable\r
+ * is incremented on each iteration of the test loop. A register containing an\r
+ * unexpected value is indicative of an error in the context switching\r
+ * mechanism and will result in a branch to a null loop - which in turn will\r
+ * prevent the check variable from incrementing any further and allow the check\r
+ * timer (described below) to determine that an error has occurred. The nature\r
+ * of the reg test tasks necessitates that they are written in assembly code.\r
+ *\r
+ * "Check Timer" and Callback Function - The check timer period is initially\r
+ * set to three seconds. The check timer callback function checks that all the\r
+ * standard demo tasks are not only still executing, but are executing without\r
+ * reporting any errors. If the check timer discovers that a task has either\r
+ * stalled, or reported an error, then it changes its own period from the\r
+ * initial three seconds, to just 200ms. The check timer callback function\r
+ * also toggles LED 0 each time it is called. This provides a visual\r
+ * indication of the system status: If the LED toggles every three seconds,\r
+ * then no issues have been discovered. If the LED toggles every 200ms, then\r
+ * an issue has been discovered with at least one task.\r
+ *\r
+ * *NOTE 1* The CPU must be in Supervisor mode when the scheduler is started.\r
+ * The PowerON_Reset_PC() supplied in resetprg.c with this demo has\r
+ * Change_PSW_PM_to_UserMode() commented out to ensure this is the case.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Hardware specific includes. */\r
+#include "iodefine.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+#include "death.h"\r
+#include "blocktim.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+\r
+/* The code in this file is only built when configCREATE_LOW_POWER_DEMO is set\r
+to 0, otherwise the code in main_low_power.c is used. */\r
+#if configCREATE_LOW_POWER_DEMO == 0\r
+\r
+\r
+/* Values that are passed into the reg test tasks using the task parameter.\r
+The tasks check that the values are passed in correctly. */\r
+#define mainREG_TEST_1_PARAMETER ( 0x12121212UL )\r
+#define mainREG_TEST_2_PARAMETER ( 0x12345678UL )\r
+\r
+/* Priorities at which the standard demo tasks are created. */\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+\r
+/* The LED toggled by the check timer. */\r
+#define mainCHECK_LED ( 0 )\r
+\r
+/* The period at which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/* A block time of zero simple means "Don't Block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/*\r
+ * The reg test tasks as described at the top of this file.\r
+ */\r
+static void prvRegTest1Task( void *pvParameters );\r
+static void prvRegTest2Task( void *pvParameters );\r
+\r
+/*\r
+ * The actual implementation of the reg test functionality, which, because of\r
+ * the direct register access, have to be in assembly.\r
+ */\r
+static void prvRegTest1Implementation( void );\r
+static void prvRegTest2Implementation( void );\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Variables that are incremented on each iteration of the reg test tasks -\r
+provided the tasks have not reported any errors. The check timer inspects these\r
+variables to ensure they are still incrementing as expected. If a variable\r
+stops incrementing then it is likely that its associated task has stalled. */\r
+unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;\r
+\r
+/* The check timer. This uses prvCheckTimerCallback() as its callback\r
+function. */\r
+static xTimerHandle xCheckTimer = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* Start the reg test tasks which test the context switching mechanism. */\r
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the standard demo tasks. */\r
+ vCreateBlockTimeTasks();\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ );\r
+\r
+ configASSERT( xCheckTimer );\r
+\r
+ /* Start the check timer. It will actually start when the scheduler is\r
+ started. */\r
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+\r
+ /* Start the tasks running. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well execution will never reach here as the scheduler will be\r
+ running. If this null loop is reached then it is likely there was\r
+ insufficient FreeRTOS heap available for the idle task and/or timer task to\r
+ be created. See http://www.freertos.org/a00111.html. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE, lErrorStatus = pdPASS;\r
+static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL;\r
+\r
+ /* Remove compiler warnings about unused parameters. */\r
+ ( void ) xTimer;\r
+\r
+ /* Check the standard demo tasks are running without error. */\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+\r
+ /* Check the reg test tasks are still cycling. They will stop incrementing\r
+ their loop counters if they encounter an error. */\r
+ if( ulRegTest1CycleCount == ulLastRegTest1CycleCount )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+\r
+ if( ulRegTest2CycleCount == ulLastRegTest2CycleCount )\r
+ {\r
+ lErrorStatus = pdFAIL;\r
+ }\r
+\r
+ /* Remember the loop counter values this time around so they can be checked\r
+ again the next time this callback function executes. */\r
+ ulLastRegTest1CycleCount = ulRegTest1CycleCount;\r
+ ulLastRegTest2CycleCount = ulRegTest2CycleCount;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every three seconds then everything is ok. A faster toggle\r
+ indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+\r
+ /* Was an error detected this time through the callback execution? */\r
+ if( lErrorStatus != pdPASS )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+\r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ prvRegTest1Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ prvRegTest2Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+#pragma inline_asm prvRegTest1Implementation\r
+static void prvRegTest1Implementation( void )\r
+{\r
+ ; Put a known value in each register.\r
+ MOV.L #11111111H, R15\r
+ MVTACHI R15\r
+ MOV.L #22222222H, R15\r
+ MVTACLO R15\r
+ MOV.L #1, R1\r
+ MOV.L #2, R2\r
+ MOV.L #3, R3\r
+ MOV.L #4, R4\r
+ MOV.L #5, R5\r
+ MOV.L #6, R6\r
+ MOV.L #7, R7\r
+ MOV.L #8, R8\r
+ MOV.L #9, R9\r
+ MOV.L #10, R10\r
+ MOV.L #11, R11\r
+ MOV.L #12, R12\r
+ MOV.L #13, R13\r
+ MOV.L #14, R14\r
+ MOV.L #15, R15\r
+\r
+ ; Loop, checking each iteration that each register still contains the\r
+ ; expected value.\r
+TestLoop1:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest1CycleCount, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register.\r
+ MOV.L #1, R14\r
+ MOV.L #0872E0H, R15\r
+ MOV.B R14, [R15]\r
+ NOP\r
+ NOP\r
+\r
+ ;Check the accumulator value.\r
+ MVFACHI R15\r
+ CMP #11111111H, R15\r
+ BNE RegTest2Error\r
+ MVFACMI R15\r
+ CMP #11112222H, R15\r
+ BNE RegTest2Error\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ ; Now compare each register to ensure it still contains the value that was\r
+ ; set before this loop was entered.\r
+ CMP #1, R1\r
+ BNE RegTest1Error\r
+ CMP #2, R2\r
+ BNE RegTest1Error\r
+ CMP #3, R3\r
+ BNE RegTest1Error\r
+ CMP #4, R4\r
+ BNE RegTest1Error\r
+ CMP #5, R5\r
+ BNE RegTest1Error\r
+ CMP #6, R6\r
+ BNE RegTest1Error\r
+ CMP #7, R7\r
+ BNE RegTest1Error\r
+ CMP #8, R8\r
+ BNE RegTest1Error\r
+ CMP #9, R9\r
+ BNE RegTest1Error\r
+ CMP #10, R10\r
+ BNE RegTest1Error\r
+ CMP #11, R11\r
+ BNE RegTest1Error\r
+ CMP #12, R12\r
+ BNE RegTest1Error\r
+ CMP #13, R13\r
+ BNE RegTest1Error\r
+ CMP #14, R14\r
+ BNE RegTest1Error\r
+ CMP #15, R15\r
+ BNE RegTest1Error\r
+\r
+ ; All comparisons passed, start a new iteration of this loop.\r
+ BRA TestLoop1\r
+\r
+RegTest1Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; causing the check timer to indicate the error.\r
+ BRA RegTest1Error\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+#pragma inline_asm prvRegTest2Implementation\r
+static void prvRegTest2Implementation( void )\r
+{\r
+ ; Put a known value in each register.\r
+ MOV.L #33333333H, R15\r
+ MVTACHI R15\r
+ MOV.L #44444444H, R15\r
+ MVTACLO R15\r
+ MOV.L #10, R1\r
+ MOV.L #20, R2\r
+ MOV.L #30, R3\r
+ MOV.L #40, R4\r
+ MOV.L #50, R5\r
+ MOV.L #60, R6\r
+ MOV.L #70, R7\r
+ MOV.L #80, R8\r
+ MOV.L #90, R9\r
+ MOV.L #100, R10\r
+ MOV.L #110, R11\r
+ MOV.L #120, R12\r
+ MOV.L #130, R13\r
+ MOV.L #140, R14\r
+ MOV.L #150, R15\r
+\r
+ ; Loop, checking on each iteration that each register still contains the\r
+ ; expected value.\r
+TestLoop2:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest2CycleCount, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ;Check the accumulator value.\r
+ MVFACHI R15\r
+ CMP #33333333H, R15\r
+ BNE RegTest2Error\r
+ MVFACMI R15\r
+ CMP #33334444H, R15\r
+ BNE RegTest2Error\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ CMP #10, R1\r
+ BNE RegTest2Error\r
+ CMP #20, R2\r
+ BNE RegTest2Error\r
+ CMP #30, R3\r
+ BNE RegTest2Error\r
+ CMP #40, R4\r
+ BNE RegTest2Error\r
+ CMP #50, R5\r
+ BNE RegTest2Error\r
+ CMP #60, R6\r
+ BNE RegTest2Error\r
+ CMP #70, R7\r
+ BNE RegTest2Error\r
+ CMP #80, R8\r
+ BNE RegTest2Error\r
+ CMP #90, R9\r
+ BNE RegTest2Error\r
+ CMP #100, R10\r
+ BNE RegTest2Error\r
+ CMP #110, R11\r
+ BNE RegTest2Error\r
+ CMP #120, R12\r
+ BNE RegTest2Error\r
+ CMP #130, R13\r
+ BNE RegTest2Error\r
+ CMP #140, R14\r
+ BNE RegTest2Error\r
+ CMP #150, R15\r
+ BNE RegTest2Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop2\r
+\r
+RegTest2Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; - causing the check timer to indicate the error.\r
+ BRA RegTest2Error\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#endif /* configCREATE_LOW_POWER_DEMO */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/* ****************************************************************************\r
+ * When configCREATE_LOW_POWER_DEMO is set to 1 in FreeRTOSConfig.h main() will\r
+ * call main_low_power(), which is defined in this file. main_low_power()\r
+ * demonstrates FreeRTOS tick suppression being used to allow the MCU to be\r
+ * placed into both the low power deep sleep mode and the low power software\r
+ * standby mode. When configCREATE_LOW_POWER_DEMO is set to 0 main will\r
+ * instead call main_full(), which is a more comprehensive RTOS demonstration.\r
+ * ****************************************************************************\r
+ *\r
+ * This application demonstrates the FreeRTOS tickless idle mode (tick\r
+ * suppression). See http://www.freertos.org/low-power-tickless-rtos.html\r
+ * The demo is configured to execute on the Renesas RX100 RSK.\r
+ *\r
+ * Functionality:\r
+ *\r
+ * + Two tasks are created, an Rx task and a Tx task.\r
+ *\r
+ * + The Rx task repeatedly blocks on a queue to wait for data. The Rx task\r
+ * toggles LED 0 each time is receives a value from the queue.\r
+ *\r
+ * + The Tx task repeatedly enters the Blocked state for an amount of time\r
+ * that is set by the position of the potentiometer. On exiting the blocked\r
+ * state the Tx task sends a value through the queue to the Rx task (causing\r
+ * the Rx task to exit the blocked state and toggle LED 0).\r
+ *\r
+ * If the value read from the potentiometer is less than or equal to\r
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks for the equivalent\r
+ * number of milliseconds. For example, if the sampled analog value is\r
+ * 2000, then the Tx task blocks for 2000ms. Blocking for a finite period\r
+ * allows the kernel to stop the tick interrupt and place the RX100 into\r
+ * deep sleep mode.\r
+ *\r
+ * If the value read form the potentiometer is greater than\r
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks on a semaphore with\r
+ * an infinite timeout. Blocking with an infinite timeout allows the kernel\r
+ * to stop the tick interrupt and place the RX100 into software standby\r
+ * mode. Pressing a button will generate an interrupt that causes the RX100\r
+ * to exit software standby mode. The interrupt service routine 'gives' the\r
+ * semaphore to unblock the Tx task.\r
+ *\r
+ *\r
+ * Using the Demo and Observed Behaviour:\r
+ *\r
+ * 1) Turn the potentiometer completely counter clockwise.\r
+ *\r
+ * 2) Program the RX100 with the application, then disconnect the programming/\r
+ * debugging hardware to ensure power readings are not effected by any\r
+ * connected interfaces.\r
+ *\r
+ * 3) Start the application running. LED 0 will toggle quickly because the\r
+ * potentiometer is turned to its lowest value. LED 1 will be illuminated\r
+ * when the RX100 is not in a power saving mode, but will appear to be off\r
+ * because most execution time is spent in a sleep mode. Led 2 will be\r
+ * illuminated when the RX100 is in deep sleep mode, and will appear to be\r
+ * always on, again because most execution time is spent in deep sleep mode.\r
+ * The LEDs are turned on and off by the application defined pre and post\r
+ * sleep macros (see the definitions of configPRE_SLEEP_PROCESSING() and\r
+ * configPOST_SLEEP_PROCESSING() in FreeRTOSConfig.h).\r
+ *\r
+ * 4) Slowly turn the potentiometer in the clockwise direction. This will\r
+ * increase the value read from the potentiometer, which will increase the\r
+ * time the Tx task spends in the Blocked state, which will therefore\r
+ * decrease the frequency at which the Tx task sends data to the queue (and\r
+ * the rate at which LED 0 is toggled).\r
+ *\r
+ * 5) Keep turning the potentiometer in the clockwise direction. Eventually\r
+ * the value read from the potentiometer will go above\r
+ * mainSOFTWARE_STANDBY_DELAY, causing the Tx task to block on the semaphore\r
+ * with an infinite timeout. LED 0 will stop toggling because the Tx task is\r
+ * no longer sending to the queue. LED 1 and LED 2 will both be off because\r
+ * the RX100 is neither running or in deep sleep mode (it is in software\r
+ * standby mode).\r
+ *\r
+ * 6) Turn the potentiometer counter clockwise again to ensure its value goes\r
+ * back below mainSOFTWARE_STANDBY_DELAY.\r
+ *\r
+ * 7) Press any of the three buttons to generate an interrupt. The interrupt\r
+ * will take the RX100 out of software standby mode, and the interrupt\r
+ * service routine will unblock the Tx task by 'giving' the semaphore. LED 0\r
+ * will then start to toggle again.\r
+ *\r
+ */\r
+\r
+\r
+/* Hardware specific includes. */\r
+#include "platform.h"\r
+#include "r_switches_if.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Common demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the Rx and Tx tasks are created. */\r
+#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* The number of items the queue can hold. This is 1 as the Rx task will\r
+remove items as they are added so the Tx task should always find the queue\r
+empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* The LED used to indicate that a value has been received on the queue. */\r
+#define mainQUEUE_LED ( 0 )\r
+\r
+/* The LED used to indicate that full power is being used (the MCU is not in\r
+deep sleep or software standby mode). */\r
+#define mainFULL_POWER_LED ( 1 )\r
+\r
+/* The LED used to indicate that deep sleep mode is being used. */\r
+#define mainDEEP_SLEEP_LED ( 2 )\r
+\r
+/* The Tx task sends to the queue with a frequency that is set by the value\r
+read from the potentiometer until the value goes above that set by the\r
+mainSOFTWARE_STANDBY_DELAY constant - at which time the Tx task instead blocks\r
+indefinitely on a semaphore. */\r
+#define mainSOFTWARE_STANDBY_DELAY ( 3000UL )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0 )\r
+\r
+/* The value that is sent from the Tx task to the Rx task on the queue. */\r
+#define mainQUEUED_VALUE ( 100UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The Rx and Tx tasks as described at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Reads and returns the value of the ADC connected to the potentiometer built\r
+ * onto the RSK.\r
+ */\r
+static unsigned short prvReadPOT( void );\r
+\r
+/*\r
+ * The handler for the interrupt generated when any of the buttons are pressed.\r
+ */\r
+void vButtonInterruptCallback( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue to pass data from the Tx task to the Rx task. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/* The semaphore that is 'given' by interrupts generated from button pushes. */\r
+static xSemaphoreHandle xSemaphore = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_low_power( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+ configASSERT( xQueue );\r
+\r
+ /* Create the semaphore that is 'given' by an interrupt generated from a\r
+ button push. */\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ configASSERT( xSemaphore );\r
+\r
+ /* Make sure the semaphore starts in the expected state - no button pushes\r
+ have yet occurred. A block time of zero can be used as it is guaranteed\r
+ that the semaphore will be available because it has just been created. */\r
+ xSemaphoreTake( xSemaphore, mainDONT_BLOCK );\r
+\r
+ /* Start the two tasks as described at the top of this file. */\r
+ xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* The CPU is currently running, not sleeping, so turn on the LED that\r
+ shows the CPU is not in a sleep mode. */\r
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );\r
+\r
+ /* Start the scheduler running running. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well the next line of code will not be reached as the\r
+ scheduler will be running. If the next line is reached then it is likely\r
+ there was insufficient FreeRTOS heap available for the idle task and/or\r
+ timer task to be created. See http://www.freertos.org/a00111.html. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xDelay;\r
+const unsigned long ulValueToSend = mainQUEUED_VALUE;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* The delay period between successive sends to the queue is set by\r
+ the potentiometer reading. */\r
+ xDelay = ( portTickType ) prvReadPOT();\r
+\r
+ /* If the block time is greater than 3000 milliseconds then block\r
+ indefinitely waiting for a button push. */\r
+ if( xDelay > mainSOFTWARE_STANDBY_DELAY )\r
+ {\r
+ /* As this is an indefinite delay the kernel will place the CPU\r
+ into software standby mode the next time the idle task runs. */\r
+ xSemaphoreTake( xSemaphore, portMAX_DELAY );\r
+ }\r
+ else\r
+ {\r
+ /* Convert a time in milliseconds to a time in ticks. */\r
+ xDelay /= portTICK_RATE_MS;\r
+\r
+ /* Place this task in the blocked state until it is time to run\r
+ again. As this is not an indefinite sleep the kernel will place\r
+ the CPU into the deep sleep state when the idle task next runs. */\r
+ vTaskDelay( xDelay );\r
+ }\r
+\r
+ /* Send to the queue - causing the queue receive task to flash its LED.\r
+ It should not be necessary to block on the queue send because the Rx\r
+ task will have removed the last queued item. */\r
+ xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have arrived, but is it the expected\r
+ value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == mainQUEUED_VALUE )\r
+ {\r
+ vParTestToggleLED( mainQUEUE_LED );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPreSleepProcessing( unsigned long ulExpectedIdleTime )\r
+{\r
+ /* Called by the kernel before it places the MCU into a sleep mode because\r
+ configPRE_SLEEP_PROCESSING() is #defined to vPreSleepProcessing().\r
+\r
+ NOTE: Additional actions can be taken here to get the power consumption\r
+ even lower. For example, the ADC input used by this demo could be turned\r
+ off here, and then back on again in the power sleep processing function.\r
+ For maximum power saving ensure all unused pins are in their lowest power\r
+ state. */\r
+\r
+ /* Avoid compiler warnings about the unused parameter. */\r
+ ( void ) ulExpectedIdleTime;\r
+\r
+ /* Is the MCU about to enter deep sleep mode or software standby mode? */\r
+ if( SYSTEM.SBYCR.BIT.SSBY == 0 )\r
+ {\r
+ /* Turn on the LED that indicates deep sleep mode is being entered. */\r
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdTRUE );\r
+ }\r
+ else\r
+ {\r
+ /* Software standby mode is being used, so no LEDs are illuminated to\r
+ ensure minimum power readings are obtained. Ensure the Queue LED is\r
+ also off. */\r
+ vParTestSetLED( mainQUEUE_LED, pdFALSE );\r
+ }\r
+\r
+ /* Turn off the LED that indicates full power is being used. */\r
+ vParTestSetLED( mainFULL_POWER_LED, pdFALSE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPostSleepProcessing( unsigned long ulExpectedIdleTime )\r
+{\r
+ /* Called by the kernel when the MCU exits a sleep mode because\r
+ configPOST_SLEEP_PROCESSING is #defined to vPostSleepProcessing(). */\r
+\r
+ /* Avoid compiler warnings about the unused parameter. */\r
+ ( void ) ulExpectedIdleTime;\r
+\r
+ /* Turn off the LED that indicates deep sleep mode, and turn on the LED\r
+ that indicates full power is being used. */\r
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdFALSE );\r
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static unsigned short prvReadPOT( void )\r
+{\r
+unsigned short usADCValue;\r
+const unsigned short usMinADCValue = 128;\r
+\r
+ /* Start an ADC scan. */\r
+ S12AD.ADCSR.BIT.ADST = 1;\r
+ while( S12AD.ADCSR.BIT.ADST == 1 )\r
+ {\r
+ /* Just waiting for the ADC scan to complete. Inefficient\r
+ polling! */\r
+ }\r
+\r
+ usADCValue = S12AD.ADDR4;\r
+\r
+ /* Don't let the ADC value get too small as the LED behaviour will look\r
+ erratic. */\r
+ if( usADCValue < usMinADCValue )\r
+ {\r
+ usADCValue = usMinADCValue;\r
+ }\r
+\r
+ return usADCValue;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vButtonInterruptCallback( void )\r
+{\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* The semaphore is only created when the build is configured to create the\r
+ low power demo. */\r
+ if( xSemaphore != NULL )\r
+ {\r
+ /* This interrupt will bring the CPU out of deep sleep and software\r
+ standby modes. Give the semaphore that was used to place the Tx task\r
+ into an indefinite sleep. */\r
+ if( uxQueueMessagesWaitingFromISR( xSemaphore ) == 0 )\r
+ {\r
+ xSemaphoreGiveFromISR( xSemaphore, &lHigherPriorityTaskWoken );\r
+ }\r
+ else\r
+ {\r
+ /* The semaphore was already available, so the task is not blocked\r
+ on it and there is no point giving it. */\r
+ }\r
+\r
+ /* If giving the semaphore caused a task to leave the Blocked state,\r
+ and the task that left the Blocked state has a priority equal to or\r
+ above the priority of the task that this interrupt interrupted, then\r
+ lHigherPriorityTaskWoken will have been set to pdTRUE inside the call\r
+ to xSemaphoreGiveFromISR(), and calling portYIELD_FROM_ISR() will cause\r
+ a context switch to the unblocked task. */\r
+ portYIELD_FROM_ISR( lHigherPriorityTaskWoken );\r
+ }\r
+}\r
+\r
projects / freertos / commitdiff