+;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************\r
+;* File Name : startup_stm32l475xx.s\r
+;* Author : MCD Application Team\r
+;* Description : STM32L475xx Ultra Low Power Devices vector\r
+;* This module performs:\r
+;* - Set the initial SP\r
+;* - Set the initial PC == _iar_program_start,\r
+;* - Set the vector table entries with the exceptions ISR\r
+;* address.\r
+;* - Branches to main in the C library (which eventually\r
+;* calls main()).\r
+;* After Reset the Cortex-M4 processor is in Thread mode,\r
+;* priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;*\r
+;* Redistribution and use in source and binary forms, with or without modification,\r
+;* are permitted provided that the following conditions are met:\r
+;* 1. Redistributions of source code must retain the above copyright notice,\r
+;* this list of conditions and the following disclaimer.\r
+;* 2. Redistributions in binary form must reproduce the above copyright notice,\r
+;* this list of conditions and the following disclaimer in the documentation\r
+;* and/or other materials provided with the distribution.\r
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+;* may be used to endorse or promote products derived from this software\r
+;* without specific prior written permission.\r
+;*\r
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+;*\r
+;*******************************************************************************\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ EXTERN __iar_program_start\r
+ EXTERN SystemInit\r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler ; Reset Handler\r
+\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WWDG_IRQHandler ; Window WatchDog\r
+ DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection\r
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line\r
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line\r
+ DCD FLASH_IRQHandler ; FLASH\r
+ DCD RCC_IRQHandler ; RCC\r
+ DCD EXTI0_IRQHandler ; EXTI Line0\r
+ DCD EXTI1_IRQHandler ; EXTI Line1\r
+ DCD EXTI2_IRQHandler ; EXTI Line2\r
+ DCD EXTI3_IRQHandler ; EXTI Line3\r
+ DCD EXTI4_IRQHandler ; EXTI Line4\r
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1\r
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2\r
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3\r
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4\r
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5\r
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6\r
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7\r
+ DCD ADC1_2_IRQHandler ; ADC1, ADC2\r
+ DCD CAN1_TX_IRQHandler ; CAN1 TX\r
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0\r
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1\r
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE\r
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s\r
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15\r
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16\r
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17\r
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare\r
+ DCD TIM2_IRQHandler ; TIM2\r
+ DCD TIM3_IRQHandler ; TIM3\r
+ DCD TIM4_IRQHandler ; TIM4\r
+ DCD I2C1_EV_IRQHandler ; I2C1 Event\r
+ DCD I2C1_ER_IRQHandler ; I2C1 Error\r
+ DCD I2C2_EV_IRQHandler ; I2C2 Event\r
+ DCD I2C2_ER_IRQHandler ; I2C2 Error\r
+ DCD SPI1_IRQHandler ; SPI1\r
+ DCD SPI2_IRQHandler ; SPI2\r
+ DCD USART1_IRQHandler ; USART1\r
+ DCD USART2_IRQHandler ; USART2\r
+ DCD USART3_IRQHandler ; USART3\r
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]\r
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line\r
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt\r
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt\r
+ DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt\r
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt\r
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt\r
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt\r
+ DCD FMC_IRQHandler ; FMC\r
+ DCD SDMMC1_IRQHandler ; SDMMC1\r
+ DCD TIM5_IRQHandler ; TIM5\r
+ DCD SPI3_IRQHandler ; SPI3\r
+ DCD UART4_IRQHandler ; UART4\r
+ DCD UART5_IRQHandler ; UART5\r
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors\r
+ DCD TIM7_IRQHandler ; TIM7\r
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1\r
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2\r
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3\r
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4\r
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5\r
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt\r
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt\r
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt\r
+ DCD COMP_IRQHandler ; COMP Interrupt\r
+ DCD LPTIM1_IRQHandler ; LP TIM1 interrupt\r
+ DCD LPTIM2_IRQHandler ; LP TIM2 interrupt\r
+ DCD OTG_FS_IRQHandler ; USB OTG FS\r
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6\r
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7\r
+ DCD LPUART1_IRQHandler ; LP UART 1 interrupt\r
+ DCD QUADSPI_IRQHandler ; Quad SPI global interrupt\r
+ DCD I2C3_EV_IRQHandler ; I2C3 event\r
+ DCD I2C3_ER_IRQHandler ; I2C3 error\r
+ DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt\r
+ DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt\r
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt\r
+ DCD TSC_IRQHandler ; Touch Sense Controller global interrupt\r
+ DCD 0 ; Reserved \r
+ DCD 0 ; Reserved \r
+ DCD RNG_IRQHandler ; RNG global interrupt\r
+ DCD FPU_IRQHandler ; FPU\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ THUMB\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(2)\r
+Reset_Handler\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+\r
+ PUBWEAK NMI_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+NMI_Handler\r
+ B NMI_Handler\r
+\r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+\r
+ PUBWEAK MemManage_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+MemManage_Handler\r
+ B MemManage_Handler\r
+\r
+ PUBWEAK BusFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+BusFault_Handler\r
+ B BusFault_Handler\r
+\r
+ PUBWEAK UsageFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+UsageFault_Handler\r
+ B UsageFault_Handler\r
+\r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+\r
+ PUBWEAK DebugMon_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DebugMon_Handler\r
+ B DebugMon_Handler\r
+\r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+\r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+\r
+ PUBWEAK WWDG_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+WWDG_IRQHandler\r
+ B WWDG_IRQHandler\r
+\r
+ PUBWEAK PVD_PVM_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+PVD_PVM_IRQHandler\r
+ B PVD_PVM_IRQHandler\r
+\r
+ PUBWEAK TAMP_STAMP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TAMP_STAMP_IRQHandler\r
+ B TAMP_STAMP_IRQHandler\r
+\r
+ PUBWEAK RTC_WKUP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+RTC_WKUP_IRQHandler\r
+ B RTC_WKUP_IRQHandler\r
+\r
+ PUBWEAK FLASH_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+FLASH_IRQHandler\r
+ B FLASH_IRQHandler\r
+\r
+ PUBWEAK RCC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+RCC_IRQHandler\r
+ B RCC_IRQHandler\r
+\r
+ PUBWEAK EXTI0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI0_IRQHandler\r
+ B EXTI0_IRQHandler\r
+\r
+ PUBWEAK EXTI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI1_IRQHandler\r
+ B EXTI1_IRQHandler\r
+\r
+ PUBWEAK EXTI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI2_IRQHandler\r
+ B EXTI2_IRQHandler\r
+\r
+ PUBWEAK EXTI3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI3_IRQHandler\r
+ B EXTI3_IRQHandler\r
+\r
+ PUBWEAK EXTI4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI4_IRQHandler\r
+ B EXTI4_IRQHandler\r
+\r
+ PUBWEAK DMA1_Channel1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel1_IRQHandler\r
+ B DMA1_Channel1_IRQHandler\r
+\r
+ PUBWEAK DMA1_Channel2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel2_IRQHandler\r
+ B DMA1_Channel2_IRQHandler\r
+\r
+ PUBWEAK DMA1_Channel3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel3_IRQHandler\r
+ B DMA1_Channel3_IRQHandler\r
+\r
+ PUBWEAK DMA1_Channel4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel4_IRQHandler\r
+ B DMA1_Channel4_IRQHandler\r
+\r
+ PUBWEAK DMA1_Channel5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel5_IRQHandler\r
+ B DMA1_Channel5_IRQHandler\r
+\r
+ PUBWEAK DMA1_Channel6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel6_IRQHandler\r
+ B DMA1_Channel6_IRQHandler\r
+\r
+ PUBWEAK DMA1_Channel7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel7_IRQHandler\r
+ B DMA1_Channel7_IRQHandler\r
+\r
+ PUBWEAK ADC1_2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+ADC1_2_IRQHandler\r
+ B ADC1_2_IRQHandler\r
+\r
+ PUBWEAK CAN1_TX_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+CAN1_TX_IRQHandler\r
+ B CAN1_TX_IRQHandler\r
+\r
+ PUBWEAK CAN1_RX0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+CAN1_RX0_IRQHandler\r
+ B CAN1_RX0_IRQHandler\r
+\r
+ PUBWEAK CAN1_RX1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+CAN1_RX1_IRQHandler\r
+ B CAN1_RX1_IRQHandler\r
+\r
+ PUBWEAK CAN1_SCE_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+CAN1_SCE_IRQHandler\r
+ B CAN1_SCE_IRQHandler\r
+\r
+ PUBWEAK EXTI9_5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI9_5_IRQHandler\r
+ B EXTI9_5_IRQHandler\r
+\r
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_BRK_TIM15_IRQHandler\r
+ B TIM1_BRK_TIM15_IRQHandler\r
+\r
+ PUBWEAK TIM1_UP_TIM16_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_UP_TIM16_IRQHandler\r
+ B TIM1_UP_TIM16_IRQHandler\r
+\r
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_TRG_COM_TIM17_IRQHandler\r
+ B TIM1_TRG_COM_TIM17_IRQHandler\r
+\r
+ PUBWEAK TIM1_CC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_CC_IRQHandler\r
+ B TIM1_CC_IRQHandler\r
+\r
+ PUBWEAK TIM2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM2_IRQHandler\r
+ B TIM2_IRQHandler\r
+\r
+ PUBWEAK TIM3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM3_IRQHandler\r
+ B TIM3_IRQHandler\r
+\r
+ PUBWEAK TIM4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM4_IRQHandler\r
+ B TIM4_IRQHandler\r
+\r
+ PUBWEAK I2C1_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C1_EV_IRQHandler\r
+ B I2C1_EV_IRQHandler\r
+\r
+ PUBWEAK I2C1_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C1_ER_IRQHandler\r
+ B I2C1_ER_IRQHandler\r
+\r
+ PUBWEAK I2C2_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C2_EV_IRQHandler\r
+ B I2C2_EV_IRQHandler\r
+\r
+ PUBWEAK I2C2_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C2_ER_IRQHandler\r
+ B I2C2_ER_IRQHandler\r
+\r
+ PUBWEAK SPI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI1_IRQHandler\r
+ B SPI1_IRQHandler\r
+\r
+ PUBWEAK SPI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI2_IRQHandler\r
+ B SPI2_IRQHandler\r
+\r
+ PUBWEAK USART1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART1_IRQHandler\r
+ B USART1_IRQHandler\r
+\r
+ PUBWEAK USART2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART2_IRQHandler\r
+ B USART2_IRQHandler\r
+\r
+ PUBWEAK USART3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART3_IRQHandler\r
+ B USART3_IRQHandler\r
+\r
+ PUBWEAK EXTI15_10_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI15_10_IRQHandler\r
+ B EXTI15_10_IRQHandler\r
+\r
+ PUBWEAK RTC_Alarm_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+RTC_Alarm_IRQHandler\r
+ B RTC_Alarm_IRQHandler\r
+\r
+ PUBWEAK DFSDM1_FLT3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DFSDM1_FLT3_IRQHandler\r
+ B DFSDM1_FLT3_IRQHandler\r
+\r
+ PUBWEAK TIM8_BRK_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM8_BRK_IRQHandler\r
+ B TIM8_BRK_IRQHandler\r
+\r
+ PUBWEAK TIM8_UP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM8_UP_IRQHandler\r
+ B TIM8_UP_IRQHandler\r
+\r
+ PUBWEAK TIM8_TRG_COM_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM8_TRG_COM_IRQHandler\r
+ B TIM8_TRG_COM_IRQHandler\r
+\r
+ PUBWEAK TIM8_CC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM8_CC_IRQHandler\r
+ B TIM8_CC_IRQHandler\r
+\r
+ PUBWEAK ADC3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+ADC3_IRQHandler\r
+ B ADC3_IRQHandler\r
+\r
+ PUBWEAK FMC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+FMC_IRQHandler\r
+ B FMC_IRQHandler\r
+\r
+ PUBWEAK SDMMC1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SDMMC1_IRQHandler\r
+ B SDMMC1_IRQHandler\r
+\r
+ PUBWEAK TIM5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM5_IRQHandler\r
+ B TIM5_IRQHandler\r
+\r
+ PUBWEAK SPI3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI3_IRQHandler\r
+ B SPI3_IRQHandler\r
+\r
+ PUBWEAK UART4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+UART4_IRQHandler\r
+ B UART4_IRQHandler\r
+\r
+ PUBWEAK UART5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+UART5_IRQHandler\r
+ B UART5_IRQHandler\r
+\r
+ PUBWEAK TIM6_DAC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM6_DAC_IRQHandler\r
+ B TIM6_DAC_IRQHandler\r
+\r
+ PUBWEAK TIM7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM7_IRQHandler\r
+ B TIM7_IRQHandler\r
+\r
+ PUBWEAK DMA2_Channel1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel1_IRQHandler\r
+ B DMA2_Channel1_IRQHandler\r
+\r
+ PUBWEAK DMA2_Channel2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel2_IRQHandler\r
+ B DMA2_Channel2_IRQHandler\r
+\r
+ PUBWEAK DMA2_Channel3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel3_IRQHandler\r
+ B DMA2_Channel3_IRQHandler\r
+\r
+ PUBWEAK DMA2_Channel4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel4_IRQHandler\r
+ B DMA2_Channel4_IRQHandler\r
+\r
+ PUBWEAK DMA2_Channel5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel5_IRQHandler\r
+ B DMA2_Channel5_IRQHandler\r
+\r
+ PUBWEAK DFSDM1_FLT0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DFSDM1_FLT0_IRQHandler\r
+ B DFSDM1_FLT0_IRQHandler\r
+\r
+ PUBWEAK DFSDM1_FLT1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DFSDM1_FLT1_IRQHandler\r
+ B DFSDM1_FLT1_IRQHandler\r
+\r
+ PUBWEAK DFSDM1_FLT2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DFSDM1_FLT2_IRQHandler\r
+ B DFSDM1_FLT2_IRQHandler\r
+\r
+ PUBWEAK COMP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+COMP_IRQHandler\r
+ B COMP_IRQHandler\r
+\r
+ PUBWEAK LPTIM1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+LPTIM1_IRQHandler\r
+ B LPTIM1_IRQHandler\r
+\r
+ PUBWEAK LPTIM2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+LPTIM2_IRQHandler\r
+ B LPTIM2_IRQHandler\r
+\r
+ PUBWEAK OTG_FS_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+OTG_FS_IRQHandler\r
+ B OTG_FS_IRQHandler\r
+\r
+ PUBWEAK DMA2_Channel6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel6_IRQHandler\r
+ B DMA2_Channel6_IRQHandler\r
+\r
+ PUBWEAK DMA2_Channel7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA2_Channel7_IRQHandler\r
+ B DMA2_Channel7_IRQHandler\r
+\r
+ PUBWEAK LPUART1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+LPUART1_IRQHandler\r
+ B LPUART1_IRQHandler\r
+\r
+ PUBWEAK QUADSPI_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+QUADSPI_IRQHandler\r
+ B QUADSPI_IRQHandler\r
+\r
+ PUBWEAK I2C3_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C3_EV_IRQHandler\r
+ B I2C3_EV_IRQHandler\r
+\r
+ PUBWEAK I2C3_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C3_ER_IRQHandler\r
+ B I2C3_ER_IRQHandler\r
+\r
+ PUBWEAK SAI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SAI1_IRQHandler\r
+ B SAI1_IRQHandler\r
+\r
+ PUBWEAK SAI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SAI2_IRQHandler\r
+ B SAI2_IRQHandler\r
+\r
+ PUBWEAK SWPMI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SWPMI1_IRQHandler\r
+ B SWPMI1_IRQHandler\r
+\r
+ PUBWEAK TSC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TSC_IRQHandler\r
+ B TSC_IRQHandler\r
+\r
+ PUBWEAK RNG_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+RNG_IRQHandler\r
+ B RNG_IRQHandler\r
+\r
+ PUBWEAK FPU_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+FPU_IRQHandler\r
+ B FPU_IRQHandler\r
+\r
+ END\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r