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<listOptionValue builtIn="false" value=""${TCINSTALL}/rx-elf/optlibinc""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/Main_Full/Standard_Demo_Tasks/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/Main_Full}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/Full_Demo/Standard_Demo_Tasks/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/Full_Demo}""/>\r
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/Renesas_Code}""/>\r
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+ <tool id="com.renesas.cdt.rx.hardwaredebug.win32.tool.compiler.Id.2005862425" name="Compiler" superClass="com.renesas.cdt.rx.hardwaredebug.win32.tool.compiler.Id.2031381723"/>\r
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</storageModule>\r
<locationURI>FREERTOS_ROOT/FreeRTOS/Source</locationURI>\r
</link>\r
<link>\r
- <name>src/Main_Full/Standard_Demo_Tasks</name>\r
+ <name>src/Full_Demo/Standard_Demo_Tasks</name>\r
<type>2</type>\r
<locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal</locationURI>\r
</link>\r
<link>\r
- <name>src/Main_Full/Standard_Demo_Tasks/include</name>\r
+ <name>src/Full_Demo/Standard_Demo_Tasks/include</name>\r
<type>2</type>\r
<locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/include</locationURI>\r
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#include "task.h"\r
#include "semphr.h"\r
\r
+/* Renesas includes. */\r
+#include "rskrx231def.h"\r
+\r
/* Priorities at which the tasks are created. */\r
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
is it the expected value? If it is, toggle the LED. */\r
if( ulReceivedValue == ulExpectedValue )\r
{\r
-//_RB_ LED0 = !LED0;\r
+ LED0 = !LED0;\r
ulReceivedValue = 0U;\r
}\r
}\r
#define configUSE_PREEMPTION 1\r
#define configUSE_IDLE_HOOK 1\r
#define configUSE_TICK_HOOK 1\r
-#define configCPU_CLOCK_HZ ( 52000000UL ) /*_RB_ guess*/\r
-#define configPERIPHERAL_CLOCK_HZ ( 26000000UL ) /*_RB_ guess*/\r
+#define configCPU_CLOCK_HZ ( 52000000UL )\r
+#define configPERIPHERAL_CLOCK_HZ ( 26000000UL )\r
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 )\r
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) )\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * This file contains the non-portable and therefore RX62N specific parts of\r
+ * the IntQueue standard demo task - namely the configuration of the timers\r
+ * that generate the interrupts and the interrupt entry points.\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueue.h"\r
+#include "IntQueueTimer.h"\r
+\r
+#define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_2_3_FREQUENCY ( 2111UL )\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+ /* Ensure interrupts do not start until full configuration is complete. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Give write access. */\r
+ SYSTEM.PRCR.WORD = 0xa502;\r
+\r
+ /* Cascade two 8bit timer channels to generate the interrupts.\r
+ 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
+ utilised for this test. */\r
+\r
+ /* Enable the timers. */\r
+ SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;\r
+ SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;\r
+\r
+ /* Enable compare match A interrupt request. */\r
+ TMR0.TCR.BIT.CMIEA = 1;\r
+ TMR2.TCR.BIT.CMIEA = 1;\r
+\r
+ /* Clear the timer on compare match A. */\r
+ TMR0.TCR.BIT.CCLR = 1;\r
+ TMR2.TCR.BIT.CCLR = 1;\r
+\r
+ /* Set the compare match value. */\r
+ TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
+ TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
+\r
+ /* 16 bit operation ( count from timer 1,2 ). */\r
+ TMR0.TCCR.BIT.CSS = 3;\r
+ TMR2.TCCR.BIT.CSS = 3;\r
+\r
+ /* Use PCLK as the input. */\r
+ TMR1.TCCR.BIT.CSS = 1;\r
+ TMR3.TCCR.BIT.CSS = 1;\r
+\r
+ /* Divide PCLK by 8. */\r
+ TMR1.TCCR.BIT.CKS = 2;\r
+ TMR3.TCCR.BIT.CKS = 2;\r
+\r
+ /* Enable TMR 0, 2 interrupts. */\r
+ TMR0.TCR.BIT.CMIEA = 1;\r
+ TMR2.TCR.BIT.CMIEA = 1;\r
+\r
+ /* Set interrupt priority and enable. */\r
+ IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
+ IR( TMR0, CMIA0 ) = 0U;\r
+ IEN( TMR0, CMIA0 ) = 1U;\r
+\r
+ /* Do the same for TMR2, but to vector 129. */\r
+ IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;\r
+ IR( TMR2, CMIA2 ) = 0U;\r
+ IEN( TMR2, CMIA2 ) = 1U;\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __GNUC__\r
+\r
+ void vIntQTimerISR0( void ) __attribute__ ((interrupt));\r
+ void vIntQTimerISR1( void ) __attribute__ ((interrupt));\r
+\r
+ void vIntQTimerISR0( void )\r
+ {\r
+ /* Enable interrupts to allow interrupt nesting. */\r
+ __asm volatile( "setpsw i" );\r
+\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vIntQTimerISR1( void )\r
+ {\r
+ /* Enable interrupts to allow interrupt nesting. */\r
+ __asm volatile( "setpsw i" );\r
+\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+ }\r
+\r
+#endif /* __GNUC__ */\r
+\r
+#ifdef __ICCRX__\r
+\r
+#pragma vector = VECT_TMR0_CMIA0\r
+__interrupt void vT0_1InterruptHandler( void )\r
+{\r
+ __enable_interrupt();\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma vector = VECT_TMR2_CMIA2\r
+__interrupt void vT2_3InterruptHandler( void )\r
+{\r
+ __enable_interrupt();\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+}\r
+\r
+#endif /* __ICCRX__ */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+BaseType_t xTimer0Handler( void );\r
+BaseType_t xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+;/*\r
+; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+; All rights reserved\r
+;\r
+; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * FreeRTOS provides completely free yet professionally developed, *\r
+; * robust, strictly quality controlled, supported, and cross *\r
+; * platform software that has become a de facto standard. *\r
+; * *\r
+; * Help yourself get started quickly and support the FreeRTOS *\r
+; * project by purchasing a FreeRTOS tutorial book, reference *\r
+; * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+; * *\r
+; * Thank you! *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify it under\r
+; the terms of the GNU General Public License (version 2) as published by the\r
+; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+;\r
+; >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+; >>! a combined work that includes FreeRTOS without being obliged to provide\r
+; >>! the source code for proprietary components outside of the FreeRTOS\r
+; >>! kernel.\r
+;\r
+; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+; FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+; link: http://www.freertos.org/a00114.html\r
+;\r
+; 1 tab == 4 spaces!\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * Having a problem? Start by reading the FAQ "My application does *\r
+; * not run, what could be wrong?" *\r
+; * *\r
+; * http://www.FreeRTOS.org/FAQHelp.html *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+; http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+; license and Real Time Engineers Ltd. contact details.;\r
+;\r
+; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+; including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+; compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+;\r
+; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+; licenses offer ticketed support, indemnification and middleware.\r
+;\r
+; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+; engineered and independently SIL3 certified version for use in safety and\r
+; mission critical applications that require provable dependability.\r
+;\r
+; 1 tab == 4 spaces!\r
+;*/\r
+\r
+ .global _vRegTest1Implementation\r
+ .global _vRegTest2Implementation\r
+\r
+ .extern _ulRegTest1LoopCounter\r
+ .extern _ulRegTest2LoopCounter\r
+\r
+ .text\r
+\r
+\r
+;/* This function is explained in the comments at the top of main.c. */\r
+_vRegTest1Implementation:\r
+\r
+ ; Put a known value in each register.\r
+ MOV.L #1, R1\r
+ MOV.L #2, R2\r
+ MOV.L #3, R3\r
+ MOV.L #4, R4\r
+ MOV.L #5, R5\r
+ MOV.L #6, R6\r
+ MOV.L #7, R7\r
+ MOV.L #8, R8\r
+ MOV.L #9, R9\r
+ MOV.L #10, R10\r
+ MOV.L #11, R11\r
+ MOV.L #12, R12\r
+ MOV.L #13, R13\r
+ MOV.L #14, R14\r
+ MOV.L #15, R15\r
+\r
+ ; Loop, checking each itteration that each register still contains the\r
+ ; expected value.\r
+TestLoop1:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest1LoopCounter, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register.\r
+ MOV.L #1, R14\r
+ MOV.L #0872E0H, R15\r
+ MOV.B R14, [R15]\r
+ NOP\r
+ NOP\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ ; Now compare each register to ensure it still contains the value that was\r
+ ; set before this loop was entered.\r
+ CMP #1, R1\r
+ BNE RegTest1Error\r
+ CMP #2, R2\r
+ BNE RegTest1Error\r
+ CMP #3, R3\r
+ BNE RegTest1Error\r
+ CMP #4, R4\r
+ BNE RegTest1Error\r
+ CMP #5, R5\r
+ BNE RegTest1Error\r
+ CMP #6, R6\r
+ BNE RegTest1Error\r
+ CMP #7, R7\r
+ BNE RegTest1Error\r
+ CMP #8, R8\r
+ BNE RegTest1Error\r
+ CMP #9, R9\r
+ BNE RegTest1Error\r
+ CMP #10, R10\r
+ BNE RegTest1Error\r
+ CMP #11, R11\r
+ BNE RegTest1Error\r
+ CMP #12, R12\r
+ BNE RegTest1Error\r
+ CMP #13, R13\r
+ BNE RegTest1Error\r
+ CMP #14, R14\r
+ BNE RegTest1Error\r
+ CMP #15, R15\r
+ BNE RegTest1Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop1\r
+\r
+RegTest1Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; causing the check task to indicate the error.\r
+ BRA RegTest1Error\r
+;/*-----------------------------------------------------------*/\r
+\r
+;/* This function is explained in the comments at the top of main.c. */\r
+_vRegTest2Implementation:\r
+\r
+ ; Put a known value in each register.\r
+ MOV.L #10, R1\r
+ MOV.L #20, R2\r
+ MOV.L #30, R3\r
+ MOV.L #40, R4\r
+ MOV.L #50, R5\r
+ MOV.L #60, R6\r
+ MOV.L #70, R7\r
+ MOV.L #80, R8\r
+ MOV.L #90, R9\r
+ MOV.L #100, R10\r
+ MOV.L #110, R11\r
+ MOV.L #120, R12\r
+ MOV.L #130, R13\r
+ MOV.L #140, R14\r
+ MOV.L #150, R15\r
+\r
+ ; Loop, checking on each itteration that each register still contains the\r
+ ; expected value.\r
+TestLoop2:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest2LoopCounter, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ CMP #10, R1\r
+ BNE RegTest2Error\r
+ CMP #20, R2\r
+ BNE RegTest2Error\r
+ CMP #30, R3\r
+ BNE RegTest2Error\r
+ CMP #40, R4\r
+ BNE RegTest2Error\r
+ CMP #50, R5\r
+ BNE RegTest2Error\r
+ CMP #60, R6\r
+ BNE RegTest2Error\r
+ CMP #70, R7\r
+ BNE RegTest2Error\r
+ CMP #80, R8\r
+ BNE RegTest2Error\r
+ CMP #90, R9\r
+ BNE RegTest2Error\r
+ CMP #100, R10\r
+ BNE RegTest2Error\r
+ CMP #110, R11\r
+ BNE RegTest2Error\r
+ CMP #120, R12\r
+ BNE RegTest2Error\r
+ CMP #130, R13\r
+ BNE RegTest2Error\r
+ CMP #140, R14\r
+ BNE RegTest2Error\r
+ CMP #150, R15\r
+ BNE RegTest2Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop2\r
+\r
+RegTest2Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; - causing the check task to indicate the error.\r
+ BRA RegTest2Error\r
+ \r
+ .END\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+ PUBLIC _vRegTest1Implementation\r
+ PUBLIC _vRegTest2Implementation\r
+ \r
+ EXTERN _ulRegTest1LoopCounter\r
+ EXTERN _ulRegTest2LoopCounter\r
+\r
+ RSEG CODE:CODE(4)\r
+\r
+/* This function is explained in the comments at the top of main.c. */\r
+_vRegTest1Implementation:\r
+\r
+ ;/* Put a known value in the guard byte of the accumulators. */\r
+ MOV.L #10, R1\r
+ MVTACGU R1, A0\r
+ MOV.L #20, R1\r
+ MVTACGU R1, A1\r
+\r
+ /* Put a known value in each register. */\r
+ MOV #1, R1 \r
+ MOV #2, R2 \r
+ MOV #3, R3 \r
+ MOV #4, R4 \r
+ MOV #5, R5 \r
+ MOV #6, R6 \r
+ MOV #7, R7 \r
+ MOV #8, R8 \r
+ MOV #9, R9 \r
+ MOV #10, R10 \r
+ MOV #11, R11 \r
+ MOV #12, R12 \r
+ MOV #13, R13 \r
+ MOV #14, R14 \r
+ MOV #15, R15 \r
+ \r
+ ;/* Put a known value in the hi and low of the accumulators. */\r
+ MVTACHI R1, A0\r
+ MVTACLO R2, A0\r
+ MVTACHI R3, A1\r
+ MVTACLO R4, A1\r
+ /* Loop, checking each itteration that each register still contains the\r
+ expected value. */\r
+TestLoop1: \r
+\r
+ /* Push the registers that are going to get clobbered. */\r
+ PUSHM R14-R15 \r
+ \r
+ /* Increment the loop counter to show this task is still getting CPU time. */\r
+ MOV #_ulRegTest1LoopCounter, R14 \r
+ MOV [ R14 ], R15 \r
+ ADD #1, R15 \r
+ MOV R15, [ R14 ] \r
+ \r
+ /* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */\r
+ MOV #1, R14 \r
+ MOV #0872E0H, R15 \r
+ MOV.B R14, [R15] \r
+ NOP \r
+ NOP \r
+ \r
+ ;/* Check accumulators. */\r
+ MVFACHI #0, A0, R15\r
+ CMP #1, R15\r
+ BNE RegTest1Error\r
+ MVFACLO #0, A0, R15\r
+ CMP #2, R15\r
+ BNE RegTest1Error\r
+ MVFACGU #0, A0, R15\r
+ CMP #10, R15\r
+ BNE RegTest1Error\r
+ MVFACHI #0, A1, R15\r
+ CMP #3, R15\r
+ BNE RegTest1Error\r
+ MVFACLO #0, A1, R15\r
+ CMP #4, R15\r
+ BNE RegTest1Error\r
+ MVFACGU #0, A1, R15\r
+ CMP #20, R15\r
+ BNE RegTest1Error\r
+\r
+ /* Restore the clobbered registers. */\r
+ POPM R14-R15 \r
+ \r
+ /* Now compare each register to ensure it still contains the value that was\r
+ set before this loop was entered. */\r
+ CMP #1, R1 \r
+ BNE RegTest1Error \r
+ CMP #2, R2 \r
+ BNE RegTest1Error \r
+ CMP #3, R3 \r
+ BNE RegTest1Error \r
+ CMP #4, R4 \r
+ BNE RegTest1Error \r
+ CMP #5, R5 \r
+ BNE RegTest1Error \r
+ CMP #6, R6 \r
+ BNE RegTest1Error \r
+ CMP #7, R7 \r
+ BNE RegTest1Error \r
+ CMP #8, R8 \r
+ BNE RegTest1Error \r
+ CMP #9, R9 \r
+ BNE RegTest1Error \r
+ CMP #10, R10 \r
+ BNE RegTest1Error \r
+ CMP #11, R11 \r
+ BNE RegTest1Error \r
+ CMP #12, R12 \r
+ BNE RegTest1Error \r
+ CMP #13, R13 \r
+ BNE RegTest1Error \r
+ CMP #14, R14 \r
+ BNE RegTest1Error \r
+ CMP #15, R15 \r
+ BNE RegTest1Error \r
+\r
+ /* All comparisons passed, start a new itteratio of this loop. */\r
+ BRA TestLoop1 \r
+ \r
+RegTest1Error: \r
+ /* A compare failed, just loop here so the loop counter stops incrementing\r
+ - causing the check task to indicate the error. */\r
+ BRA RegTest1Error \r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of main.c. */\r
+_vRegTest2Implementation:\r
+\r
+ ;/* Put a known value in the guard byte of the accumulators. */\r
+ MOV.L #1H, R1\r
+ MVTACGU R1, A0\r
+ MOV.L #2H, R1\r
+ MVTACGU R1, A1\r
+\r
+ /* Put a known value in each register. */\r
+ MOV #10H, R1 \r
+ MOV #20H, R2 \r
+ MOV #30H, R3 \r
+ MOV #40H, R4 \r
+ MOV #50H, R5 \r
+ MOV #60H, R6 \r
+ MOV #70H, R7 \r
+ MOV #80H, R8 \r
+ MOV #90H, R9 \r
+ MOV #100H, R10 \r
+ MOV #110H, R11 \r
+ MOV #120H, R12 \r
+ MOV #130H, R13 \r
+ MOV #140H, R14 \r
+ MOV #150H, R15 \r
+\r
+ ;/* Put a known value in the hi and low of the accumulators. */\r
+ MVTACHI R1, A0\r
+ MVTACLO R2, A0\r
+ MVTACHI R3, A1\r
+ MVTACLO R4, A1\r
+\r
+ /* Loop, checking each itteration that each register still contains the\r
+ expected value. */\r
+TestLoop2: \r
+\r
+ /* Push the registers that are going to get clobbered. */\r
+ PUSHM R14-R15 \r
+ \r
+ /* Increment the loop counter to show this task is still getting CPU time. */\r
+ MOV #_ulRegTest2LoopCounter, R14 \r
+ MOV [ R14 ], R15 \r
+ ADD #1, R15 \r
+ MOV R15, [ R14 ] \r
+ \r
+ ;/* Check accumulators. */\r
+ MVFACHI #0, A0, R15\r
+ CMP #10H, R15\r
+ BNE RegTest1Error\r
+ MVFACLO #0, A0, R15\r
+ CMP #20H, R15\r
+ BNE RegTest1Error\r
+ MVFACGU #0, A0, R15\r
+ CMP #1H, R15\r
+ BNE RegTest1Error\r
+ MVFACHI #0, A1, R15\r
+ CMP #30H, R15\r
+ BNE RegTest1Error\r
+ MVFACLO #0, A1, R15\r
+ CMP #40H, R15\r
+ BNE RegTest1Error\r
+ MVFACGU #0, A1, R15\r
+ CMP #2H, R15\r
+ BNE RegTest1Error\r
+\r
+ /* Restore the clobbered registers. */\r
+ POPM R14-R15 \r
+ \r
+ /* Now compare each register to ensure it still contains the value that was\r
+ set before this loop was entered. */\r
+ CMP #10H, R1 \r
+ BNE RegTest2Error \r
+ CMP #20H, R2 \r
+ BNE RegTest2Error \r
+ CMP #30H, R3 \r
+ BNE RegTest2Error \r
+ CMP #40H, R4 \r
+ BNE RegTest2Error \r
+ CMP #50H, R5 \r
+ BNE RegTest2Error \r
+ CMP #60H, R6 \r
+ BNE RegTest2Error \r
+ CMP #70H, R7 \r
+ BNE RegTest2Error \r
+ CMP #80H, R8 \r
+ BNE RegTest2Error \r
+ CMP #90H, R9 \r
+ BNE RegTest2Error \r
+ CMP #100H, R10 \r
+ BNE RegTest2Error \r
+ CMP #110H, R11 \r
+ BNE RegTest2Error \r
+ CMP #120H, R12 \r
+ BNE RegTest2Error \r
+ CMP #130H, R13 \r
+ BNE RegTest2Error \r
+ CMP #140H, R14 \r
+ BNE RegTest2Error \r
+ CMP #150H, R15 \r
+ BNE RegTest2Error \r
+\r
+ /* All comparisons passed, start a new itteratio of this loop. */\r
+ BRA TestLoop2 \r
+ \r
+RegTest2Error: \r
+ /* A compare failed, just loop here so the loop counter stops incrementing\r
+ - causing the check task to indicate the error. */\r
+ BRA RegTest2Error \r
+\r
+ \r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky\r
+ * style project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to\r
+ * select between the two. See the notes on using\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the\r
+ * comprehensive version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ *\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and software timers, then\r
+ * starts the scheduler. The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" task - The check task period is initially set to three seconds. The\r
+ * task checks that all the standard demo tasks, and the register check tasks,\r
+ * are not only still executing, but are executing without reporting any errors.\r
+ * If the check task discovers that a task has either stalled, or reported an\r
+ * error, then it changes its own execution period from the initial three\r
+ * seconds, to just 200ms. The check task also toggles an LED each time it is\r
+ * called. This provides a visual indication of the system status: If the LED\r
+ * toggles every three seconds, then no issues have been discovered. If the LED\r
+ * toggles every 200ms, then an issue has been discovered with at least one\r
+ * task.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "flop.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+#include "serial.h"\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "IntQueue.h"\r
+#include "EventGroupsDemo.h"\r
+#include "TaskNotify.h"\r
+#include "IntSemTest.h"\r
+\r
+/* Renesas includes. */\r
+#include "rskrx231def.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )\r
+#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The priority used by the UART command console task. */\r
+#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )\r
+\r
+/* Parameters that are passed into the register check tasks solely for the\r
+purpose of ensuring parameters are passed into tasks correctly. */\r
+#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL )\r
+#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL )\r
+\r
+/* The base period used by the timer test tasks. */\r
+#define mainTIMER_TEST_PERIOD ( 50 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Entry point for the comprehensive demo (as opposed to the simple blinky\r
+ * demo).\r
+ */\r
+void main_full( void );\r
+\r
+/*\r
+ * The full demo includes some functionality called from the tick hook.\r
+ */\r
+void vFullDemoTickHook( void );\r
+\r
+ /*\r
+ * The check task, as described at the top of this file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the registers, as described at the top of this file. The nature of these\r
+ * files necessitates that they are written in assembly, but the entry points\r
+ * are kept in the C file for the convenience of checking the task parameter.\r
+ */\r
+static void prvRegTest1Task( void *pvParameters );\r
+static void prvRegTest2Task( void *pvParameters );\r
+void vRegTest1Implementation( void );\r
+void vRegTest2Implementation( void );\r
+\r
+/*\r
+ * A high priority task that does nothing other than execute at a pseudo random\r
+ * time to ensure the other test tasks don't just execute in a repeating\r
+ * pattern.\r
+ */\r
+static void prvPseudoRandomiser( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check task. If the variables keep incrementing,\r
+then the register check tasks have not discovered any errors. If a variable\r
+stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/* String for display in the web server. It is set to an error message if the\r
+check task detects an error. */\r
+const char *pcStatusMessage = "All tasks running without error";\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* Start all the other standard demo/test tasks. They have no particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartInterruptQueueTasks();\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+ vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );\r
+ vStartEventGroupTasks();\r
+ vStartTaskNotifyTask();\r
+ vStartInterruptSemaphoreTasks();\r
+\r
+ /* Create the register check tasks, as described at the top of this file */\r
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the task that just adds a little random behaviour. */\r
+ xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
+\r
+ /* Create the task that performs the 'check' functionality, as described at\r
+ the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* The set of tasks created by the following function call have to be\r
+ created last as they keep account of the number of tasks they expect to see\r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
+TickType_t xLastExecutionTime;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. The onboard LED is toggled on each iteration.\r
+ If an error is detected then the delay period is decreased from\r
+ mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
+ effect of increasing the rate at which the onboard LED toggles, and in so\r
+ doing gives visual feedback of the system status. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+ if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 0UL;\r
+ }\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 1UL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 2UL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 3UL;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 4UL;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 5UL;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 6UL;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 7UL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 8UL;\r
+ }\r
+\r
+ if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )\r
+ {\r
+ ulErrorFound |= 1UL << 9UL;\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 10UL;\r
+ }\r
+\r
+ if( xIsQueueOverwriteTaskStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= 1UL << 11UL;\r
+ }\r
+\r
+ if( xAreEventGroupTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= 1UL << 12UL;\r
+ }\r
+\r
+ if( xAreTaskNotificationTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 13UL;\r
+ }\r
+\r
+ if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 14UL;\r
+ }\r
+\r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound |= 1UL << 15UL;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound |= 1UL << 16UL;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ LED0 = !LED0;\r
+\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash the LED\r
+ at a higher frequency to give visible feedback that something has\r
+ gone wrong (it might just be that the loop back connector required\r
+ by the comtest tasks has not been fitted). */\r
+ xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
+ pcStatusMessage = "Error found in at least one task.";\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPseudoRandomiser( void *pvParameters )\r
+{\r
+const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );\r
+volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;\r
+\r
+ /* This task does nothing other than ensure there is a little bit of\r
+ disruption in the scheduling pattern of the other tasks. Normally this is\r
+ done by generating interrupts at pseudo random times. */\r
+ for( ;; )\r
+ {\r
+ ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;\r
+ ulValue = ( ulNextRand >> 16UL ) & 0xffUL;\r
+\r
+ if( ulValue < ulMinDelay )\r
+ {\r
+ ulValue = ulMinDelay;\r
+ }\r
+\r
+ vTaskDelay( ulValue );\r
+\r
+ while( ulValue > 0 )\r
+ {\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+\r
+ ulValue--;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vFullDemoTickHook( void )\r
+{\r
+ /* The full demo includes a software timer demo/test that requires\r
+ prodding periodically from the tick interrupt. */\r
+ vTimerPeriodicISRTests();\r
+\r
+ /* Call the periodic queue overwrite from ISR demo. */\r
+ vQueueOverwritePeriodicISRDemo();\r
+\r
+ /* Call the periodic event group from ISR demo. */\r
+ vPeriodicEventGroupsProcessing();\r
+\r
+ /* Use task notifications from an interrupt. */\r
+ xNotifyTaskFromISR();\r
+\r
+ /* Use mutexes from interrupts. */\r
+ vInterruptSemaphorePeriodicTest();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+ if( pvParameters != mainREG_TEST_1_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ vRegTest1Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+ if( pvParameters != mainREG_TEST_2_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ vRegTest2Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*\r
- * This file contains the non-portable and therefore RX62N specific parts of\r
- * the IntQueue standard demo task - namely the configuration of the timers\r
- * that generate the interrupts and the interrupt entry points.\r
- */\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Demo includes. */\r
-#include "IntQueueTimer.h"\r
-#include "IntQueue.h"\r
-\r
-#define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
-#define tmrTIMER_2_3_FREQUENCY ( 2111UL )\r
-\r
-void vInitialiseTimerForIntQueueTest( void )\r
-{\r
- /* Ensure interrupts do not start until full configuration is complete. */\r
- portENTER_CRITICAL();\r
- {\r
- /* Give write access. */\r
- SYSTEM.PRCR.WORD = 0xa502;\r
-\r
- /* Cascade two 8bit timer channels to generate the interrupts.\r
- 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
- utilised for this test. */\r
-\r
- /* Enable the timers. */\r
- SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;\r
- SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;\r
-\r
- /* Enable compare match A interrupt request. */\r
- TMR0.TCR.BIT.CMIEA = 1;\r
- TMR2.TCR.BIT.CMIEA = 1;\r
-\r
- /* Clear the timer on compare match A. */\r
- TMR0.TCR.BIT.CCLR = 1;\r
- TMR2.TCR.BIT.CCLR = 1;\r
-\r
- /* Set the compare match value. */\r
- TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
- TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
-\r
- /* 16 bit operation ( count from timer 1,2 ). */\r
- TMR0.TCCR.BIT.CSS = 3;\r
- TMR2.TCCR.BIT.CSS = 3;\r
-\r
- /* Use PCLK as the input. */\r
- TMR1.TCCR.BIT.CSS = 1;\r
- TMR3.TCCR.BIT.CSS = 1;\r
-\r
- /* Divide PCLK by 8. */\r
- TMR1.TCCR.BIT.CKS = 2;\r
- TMR3.TCCR.BIT.CKS = 2;\r
-\r
- /* Enable TMR 0, 2 interrupts. */\r
- TMR0.TCR.BIT.CMIEA = 1;\r
- TMR2.TCR.BIT.CMIEA = 1;\r
-\r
- /* Set interrupt priority and enable. */\r
- IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
- IR( TMR0, CMIA0 ) = 0U;\r
- IEN( TMR0, CMIA0 ) = 1U;\r
-\r
- /* Do the same for TMR2, but to vector 129. */\r
- IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;\r
- IR( TMR2, CMIA2 ) = 0U;\r
- IEN( TMR2, CMIA2 ) = 1U;\r
- }\r
- portEXIT_CRITICAL();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#ifdef __GNUC__\r
-\r
- void vIntQTimerISR0( void ) __attribute__ ((interrupt));\r
- void vIntQTimerISR1( void ) __attribute__ ((interrupt));\r
-\r
- void vIntQTimerISR0( void )\r
- {\r
- /* Enable interrupts to allow interrupt nesting. */\r
- __asm volatile( "setpsw i" );\r
-\r
- portYIELD_FROM_ISR( xFirstTimerHandler() );\r
- }\r
- /*-----------------------------------------------------------*/\r
-\r
- void vIntQTimerISR1( void )\r
- {\r
- /* Enable interrupts to allow interrupt nesting. */\r
- __asm volatile( "setpsw i" );\r
-\r
- portYIELD_FROM_ISR( xSecondTimerHandler() );\r
- }\r
-\r
-#endif /* __GNUC__ */\r
-\r
-#ifdef __ICCRX__\r
-\r
-#pragma vector = VECT_TMR0_CMIA0\r
-__interrupt void vT0_1InterruptHandler( void )\r
-{\r
- __enable_interrupt();\r
- portYIELD_FROM_ISR( xFirstTimerHandler() );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#pragma vector = VECT_TMR2_CMIA2\r
-__interrupt void vT2_3InterruptHandler( void )\r
-{\r
- __enable_interrupt();\r
- portYIELD_FROM_ISR( xSecondTimerHandler() );\r
-}\r
-\r
-#endif /* __ICCRX__ */\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-#ifndef INT_QUEUE_TIMER_H\r
-#define INT_QUEUE_TIMER_H\r
-\r
-void vInitialiseTimerForIntQueueTest( void );\r
-portBASE_TYPE xTimer0Handler( void );\r
-portBASE_TYPE xTimer1Handler( void );\r
-\r
-#endif\r
-\r
+++ /dev/null
-;/*\r
-; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
-; All rights reserved\r
-;\r
-; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-;\r
-; ***************************************************************************\r
-; * *\r
-; * FreeRTOS provides completely free yet professionally developed, *\r
-; * robust, strictly quality controlled, supported, and cross *\r
-; * platform software that has become a de facto standard. *\r
-; * *\r
-; * Help yourself get started quickly and support the FreeRTOS *\r
-; * project by purchasing a FreeRTOS tutorial book, reference *\r
-; * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
-; * *\r
-; * Thank you! *\r
-; * *\r
-; ***************************************************************************\r
-;\r
-; This file is part of the FreeRTOS distribution.\r
-;\r
-; FreeRTOS is free software; you can redistribute it and/or modify it under\r
-; the terms of the GNU General Public License (version 2) as published by the\r
-; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-;\r
-; >>! NOTE: The modification to the GPL is included to allow you to distribute\r
-; >>! a combined work that includes FreeRTOS without being obliged to provide\r
-; >>! the source code for proprietary components outside of the FreeRTOS\r
-; >>! kernel.\r
-;\r
-; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
-; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
-; FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
-; link: http://www.freertos.org/a00114.html\r
-;\r
-; 1 tab == 4 spaces!\r
-;\r
-; ***************************************************************************\r
-; * *\r
-; * Having a problem? Start by reading the FAQ "My application does *\r
-; * not run, what could be wrong?" *\r
-; * *\r
-; * http://www.FreeRTOS.org/FAQHelp.html *\r
-; * *\r
-; ***************************************************************************\r
-;\r
-; http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
-; license and Real Time Engineers Ltd. contact details.;\r
-;\r
-; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
-; including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
-; compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-;\r
-; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
-; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
-; licenses offer ticketed support, indemnification and middleware.\r
-;\r
-; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
-; engineered and independently SIL3 certified version for use in safety and\r
-; mission critical applications that require provable dependability.\r
-;\r
-; 1 tab == 4 spaces!\r
-;*/\r
-\r
- .global _vRegTest1Implementation\r
- .global _vRegTest2Implementation\r
-\r
- .extern _ulRegTest1LoopCounter\r
- .extern _ulRegTest2LoopCounter\r
-\r
- .text\r
-\r
-\r
-;/* This function is explained in the comments at the top of main.c. */\r
-_vRegTest1Implementation:\r
-\r
- ; Put a known value in each register.\r
- MOV.L #1, R1\r
- MOV.L #2, R2\r
- MOV.L #3, R3\r
- MOV.L #4, R4\r
- MOV.L #5, R5\r
- MOV.L #6, R6\r
- MOV.L #7, R7\r
- MOV.L #8, R8\r
- MOV.L #9, R9\r
- MOV.L #10, R10\r
- MOV.L #11, R11\r
- MOV.L #12, R12\r
- MOV.L #13, R13\r
- MOV.L #14, R14\r
- MOV.L #15, R15\r
-\r
- ; Loop, checking each itteration that each register still contains the\r
- ; expected value.\r
-TestLoop1:\r
-\r
- ; Push the registers that are going to get clobbered.\r
- PUSHM R14-R15\r
-\r
- ; Increment the loop counter to show this task is still getting CPU time.\r
- MOV.L #_ulRegTest1LoopCounter, R14\r
- MOV.L [ R14 ], R15\r
- ADD #1, R15\r
- MOV.L R15, [ R14 ]\r
-\r
- ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register.\r
- MOV.L #1, R14\r
- MOV.L #0872E0H, R15\r
- MOV.B R14, [R15]\r
- NOP\r
- NOP\r
-\r
- ; Restore the clobbered registers.\r
- POPM R14-R15\r
-\r
- ; Now compare each register to ensure it still contains the value that was\r
- ; set before this loop was entered.\r
- CMP #1, R1\r
- BNE RegTest1Error\r
- CMP #2, R2\r
- BNE RegTest1Error\r
- CMP #3, R3\r
- BNE RegTest1Error\r
- CMP #4, R4\r
- BNE RegTest1Error\r
- CMP #5, R5\r
- BNE RegTest1Error\r
- CMP #6, R6\r
- BNE RegTest1Error\r
- CMP #7, R7\r
- BNE RegTest1Error\r
- CMP #8, R8\r
- BNE RegTest1Error\r
- CMP #9, R9\r
- BNE RegTest1Error\r
- CMP #10, R10\r
- BNE RegTest1Error\r
- CMP #11, R11\r
- BNE RegTest1Error\r
- CMP #12, R12\r
- BNE RegTest1Error\r
- CMP #13, R13\r
- BNE RegTest1Error\r
- CMP #14, R14\r
- BNE RegTest1Error\r
- CMP #15, R15\r
- BNE RegTest1Error\r
-\r
- ; All comparisons passed, start a new itteratio of this loop.\r
- BRA TestLoop1\r
-\r
-RegTest1Error:\r
- ; A compare failed, just loop here so the loop counter stops incrementing\r
- ; causing the check task to indicate the error.\r
- BRA RegTest1Error\r
-;/*-----------------------------------------------------------*/\r
-\r
-;/* This function is explained in the comments at the top of main.c. */\r
-_vRegTest2Implementation:\r
-\r
- ; Put a known value in each register.\r
- MOV.L #10, R1\r
- MOV.L #20, R2\r
- MOV.L #30, R3\r
- MOV.L #40, R4\r
- MOV.L #50, R5\r
- MOV.L #60, R6\r
- MOV.L #70, R7\r
- MOV.L #80, R8\r
- MOV.L #90, R9\r
- MOV.L #100, R10\r
- MOV.L #110, R11\r
- MOV.L #120, R12\r
- MOV.L #130, R13\r
- MOV.L #140, R14\r
- MOV.L #150, R15\r
-\r
- ; Loop, checking on each itteration that each register still contains the\r
- ; expected value.\r
-TestLoop2:\r
-\r
- ; Push the registers that are going to get clobbered.\r
- PUSHM R14-R15\r
-\r
- ; Increment the loop counter to show this task is still getting CPU time.\r
- MOV.L #_ulRegTest2LoopCounter, R14\r
- MOV.L [ R14 ], R15\r
- ADD #1, R15\r
- MOV.L R15, [ R14 ]\r
-\r
- ; Restore the clobbered registers.\r
- POPM R14-R15\r
-\r
- CMP #10, R1\r
- BNE RegTest2Error\r
- CMP #20, R2\r
- BNE RegTest2Error\r
- CMP #30, R3\r
- BNE RegTest2Error\r
- CMP #40, R4\r
- BNE RegTest2Error\r
- CMP #50, R5\r
- BNE RegTest2Error\r
- CMP #60, R6\r
- BNE RegTest2Error\r
- CMP #70, R7\r
- BNE RegTest2Error\r
- CMP #80, R8\r
- BNE RegTest2Error\r
- CMP #90, R9\r
- BNE RegTest2Error\r
- CMP #100, R10\r
- BNE RegTest2Error\r
- CMP #110, R11\r
- BNE RegTest2Error\r
- CMP #120, R12\r
- BNE RegTest2Error\r
- CMP #130, R13\r
- BNE RegTest2Error\r
- CMP #140, R14\r
- BNE RegTest2Error\r
- CMP #150, R15\r
- BNE RegTest2Error\r
-\r
- ; All comparisons passed, start a new itteratio of this loop.\r
- BRA TestLoop2\r
-\r
-RegTest2Error:\r
- ; A compare failed, just loop here so the loop counter stops incrementing\r
- ; - causing the check task to indicate the error.\r
- BRA RegTest2Error\r
- \r
- .END\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
- PUBLIC _vRegTest1Implementation\r
- PUBLIC _vRegTest2Implementation\r
- \r
- EXTERN _ulRegTest1LoopCounter\r
- EXTERN _ulRegTest2LoopCounter\r
-\r
- RSEG CODE:CODE(4)\r
-\r
-/* This function is explained in the comments at the top of main.c. */\r
-_vRegTest1Implementation:\r
-\r
- ;/* Put a known value in the guard byte of the accumulators. */\r
- MOV.L #10, R1\r
- MVTACGU R1, A0\r
- MOV.L #20, R1\r
- MVTACGU R1, A1\r
-\r
- /* Put a known value in each register. */\r
- MOV #1, R1 \r
- MOV #2, R2 \r
- MOV #3, R3 \r
- MOV #4, R4 \r
- MOV #5, R5 \r
- MOV #6, R6 \r
- MOV #7, R7 \r
- MOV #8, R8 \r
- MOV #9, R9 \r
- MOV #10, R10 \r
- MOV #11, R11 \r
- MOV #12, R12 \r
- MOV #13, R13 \r
- MOV #14, R14 \r
- MOV #15, R15 \r
- \r
- ;/* Put a known value in the hi and low of the accumulators. */\r
- MVTACHI R1, A0\r
- MVTACLO R2, A0\r
- MVTACHI R3, A1\r
- MVTACLO R4, A1\r
- /* Loop, checking each itteration that each register still contains the\r
- expected value. */\r
-TestLoop1: \r
-\r
- /* Push the registers that are going to get clobbered. */\r
- PUSHM R14-R15 \r
- \r
- /* Increment the loop counter to show this task is still getting CPU time. */\r
- MOV #_ulRegTest1LoopCounter, R14 \r
- MOV [ R14 ], R15 \r
- ADD #1, R15 \r
- MOV R15, [ R14 ] \r
- \r
- /* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */\r
- MOV #1, R14 \r
- MOV #0872E0H, R15 \r
- MOV.B R14, [R15] \r
- NOP \r
- NOP \r
- \r
- ;/* Check accumulators. */\r
- MVFACHI #0, A0, R15\r
- CMP #1, R15\r
- BNE RegTest1Error\r
- MVFACLO #0, A0, R15\r
- CMP #2, R15\r
- BNE RegTest1Error\r
- MVFACGU #0, A0, R15\r
- CMP #10, R15\r
- BNE RegTest1Error\r
- MVFACHI #0, A1, R15\r
- CMP #3, R15\r
- BNE RegTest1Error\r
- MVFACLO #0, A1, R15\r
- CMP #4, R15\r
- BNE RegTest1Error\r
- MVFACGU #0, A1, R15\r
- CMP #20, R15\r
- BNE RegTest1Error\r
-\r
- /* Restore the clobbered registers. */\r
- POPM R14-R15 \r
- \r
- /* Now compare each register to ensure it still contains the value that was\r
- set before this loop was entered. */\r
- CMP #1, R1 \r
- BNE RegTest1Error \r
- CMP #2, R2 \r
- BNE RegTest1Error \r
- CMP #3, R3 \r
- BNE RegTest1Error \r
- CMP #4, R4 \r
- BNE RegTest1Error \r
- CMP #5, R5 \r
- BNE RegTest1Error \r
- CMP #6, R6 \r
- BNE RegTest1Error \r
- CMP #7, R7 \r
- BNE RegTest1Error \r
- CMP #8, R8 \r
- BNE RegTest1Error \r
- CMP #9, R9 \r
- BNE RegTest1Error \r
- CMP #10, R10 \r
- BNE RegTest1Error \r
- CMP #11, R11 \r
- BNE RegTest1Error \r
- CMP #12, R12 \r
- BNE RegTest1Error \r
- CMP #13, R13 \r
- BNE RegTest1Error \r
- CMP #14, R14 \r
- BNE RegTest1Error \r
- CMP #15, R15 \r
- BNE RegTest1Error \r
-\r
- /* All comparisons passed, start a new itteratio of this loop. */\r
- BRA TestLoop1 \r
- \r
-RegTest1Error: \r
- /* A compare failed, just loop here so the loop counter stops incrementing\r
- - causing the check task to indicate the error. */\r
- BRA RegTest1Error \r
-/*-----------------------------------------------------------*/\r
-\r
-/* This function is explained in the comments at the top of main.c. */\r
-_vRegTest2Implementation:\r
-\r
- ;/* Put a known value in the guard byte of the accumulators. */\r
- MOV.L #1H, R1\r
- MVTACGU R1, A0\r
- MOV.L #2H, R1\r
- MVTACGU R1, A1\r
-\r
- /* Put a known value in each register. */\r
- MOV #10H, R1 \r
- MOV #20H, R2 \r
- MOV #30H, R3 \r
- MOV #40H, R4 \r
- MOV #50H, R5 \r
- MOV #60H, R6 \r
- MOV #70H, R7 \r
- MOV #80H, R8 \r
- MOV #90H, R9 \r
- MOV #100H, R10 \r
- MOV #110H, R11 \r
- MOV #120H, R12 \r
- MOV #130H, R13 \r
- MOV #140H, R14 \r
- MOV #150H, R15 \r
-\r
- ;/* Put a known value in the hi and low of the accumulators. */\r
- MVTACHI R1, A0\r
- MVTACLO R2, A0\r
- MVTACHI R3, A1\r
- MVTACLO R4, A1\r
-\r
- /* Loop, checking each itteration that each register still contains the\r
- expected value. */\r
-TestLoop2: \r
-\r
- /* Push the registers that are going to get clobbered. */\r
- PUSHM R14-R15 \r
- \r
- /* Increment the loop counter to show this task is still getting CPU time. */\r
- MOV #_ulRegTest2LoopCounter, R14 \r
- MOV [ R14 ], R15 \r
- ADD #1, R15 \r
- MOV R15, [ R14 ] \r
- \r
- ;/* Check accumulators. */\r
- MVFACHI #0, A0, R15\r
- CMP #10H, R15\r
- BNE RegTest1Error\r
- MVFACLO #0, A0, R15\r
- CMP #20H, R15\r
- BNE RegTest1Error\r
- MVFACGU #0, A0, R15\r
- CMP #1H, R15\r
- BNE RegTest1Error\r
- MVFACHI #0, A1, R15\r
- CMP #30H, R15\r
- BNE RegTest1Error\r
- MVFACLO #0, A1, R15\r
- CMP #40H, R15\r
- BNE RegTest1Error\r
- MVFACGU #0, A1, R15\r
- CMP #2H, R15\r
- BNE RegTest1Error\r
-\r
- /* Restore the clobbered registers. */\r
- POPM R14-R15 \r
- \r
- /* Now compare each register to ensure it still contains the value that was\r
- set before this loop was entered. */\r
- CMP #10H, R1 \r
- BNE RegTest2Error \r
- CMP #20H, R2 \r
- BNE RegTest2Error \r
- CMP #30H, R3 \r
- BNE RegTest2Error \r
- CMP #40H, R4 \r
- BNE RegTest2Error \r
- CMP #50H, R5 \r
- BNE RegTest2Error \r
- CMP #60H, R6 \r
- BNE RegTest2Error \r
- CMP #70H, R7 \r
- BNE RegTest2Error \r
- CMP #80H, R8 \r
- BNE RegTest2Error \r
- CMP #90H, R9 \r
- BNE RegTest2Error \r
- CMP #100H, R10 \r
- BNE RegTest2Error \r
- CMP #110H, R11 \r
- BNE RegTest2Error \r
- CMP #120H, R12 \r
- BNE RegTest2Error \r
- CMP #130H, R13 \r
- BNE RegTest2Error \r
- CMP #140H, R14 \r
- BNE RegTest2Error \r
- CMP #150H, R15 \r
- BNE RegTest2Error \r
-\r
- /* All comparisons passed, start a new itteratio of this loop. */\r
- BRA TestLoop2 \r
- \r
-RegTest2Error: \r
- /* A compare failed, just loop here so the loop counter stops incrementing\r
- - causing the check task to indicate the error. */\r
- BRA RegTest2Error \r
-\r
- \r
- END\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * NOTE 1: This project provides two demo applications. A simple blinky\r
- * style project, and a more comprehensive test and demo application. The\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to\r
- * select between the two. See the notes on using\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the\r
- * comprehensive version.\r
- *\r
- * NOTE 2: This file only contains the source code that is specific to the\r
- * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
- * required to configure the hardware, are defined in main.c.\r
- *\r
- ******************************************************************************\r
- *\r
- * main_full() creates all the demo application tasks and software timers, then\r
- * starts the scheduler. The web documentation provides more details of the\r
- * standard demo application tasks, which provide no particular functionality,\r
- * but do provide a good example of how to use the FreeRTOS API.\r
- *\r
- * In addition to the standard demo tasks, the following tasks and tests are\r
- * defined and/or created within this file:\r
- *\r
- * "Reg test" tasks - These fill both the core and floating point registers with\r
- * known values, then check that each register maintains its expected value for\r
- * the lifetime of the task. Each task uses a different set of values. The reg\r
- * test tasks execute with a very low priority, so get preempted very\r
- * frequently. A register containing an unexpected value is indicative of an\r
- * error in the context switching mechanism.\r
- *\r
- * "Check" task - The check task period is initially set to three seconds. The\r
- * task checks that all the standard demo tasks, and the register check tasks,\r
- * are not only still executing, but are executing without reporting any errors.\r
- * If the check task discovers that a task has either stalled, or reported an\r
- * error, then it changes its own execution period from the initial three\r
- * seconds, to just 200ms. The check task also toggles an LED each time it is\r
- * called. This provides a visual indication of the system status: If the LED\r
- * toggles every three seconds, then no issues have been discovered. If the LED\r
- * toggles every 200ms, then an issue has been discovered with at least one\r
- * task.\r
- */\r
-\r
-/* Standard includes. */\r
-#include <stdio.h>\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "timers.h"\r
-#include "semphr.h"\r
-\r
-/* Standard demo application includes. */\r
-#include "flop.h"\r
-#include "semtest.h"\r
-#include "dynamic.h"\r
-#include "BlockQ.h"\r
-#include "blocktim.h"\r
-#include "countsem.h"\r
-#include "GenQTest.h"\r
-#include "recmutex.h"\r
-#include "death.h"\r
-#include "partest.h"\r
-#include "comtest2.h"\r
-#include "serial.h"\r
-#include "TimerDemo.h"\r
-#include "QueueOverwrite.h"\r
-#include "IntQueue.h"\r
-#include "EventGroupsDemo.h"\r
-#include "TaskNotify.h"\r
-#include "IntSemTest.h"\r
-\r
-/* Priorities for the demo application tasks. */\r
-#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
-#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
-#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
-#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
-#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )\r
-#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
-#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
-\r
-/* The priority used by the UART command console task. */\r
-#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
-\r
-/* A block time of zero simply means "don't block". */\r
-#define mainDONT_BLOCK ( 0UL )\r
-\r
-/* The period after which the check timer will expire, in ms, provided no errors\r
-have been reported by any of the standard demo tasks. ms are converted to the\r
-equivalent in ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )\r
-\r
-/* The period at which the check timer will expire, in ms, if an error has been\r
-reported in one of the standard demo tasks. ms are converted to the equivalent\r
-in ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )\r
-\r
-/* Parameters that are passed into the register check tasks solely for the\r
-purpose of ensuring parameters are passed into tasks correctly. */\r
-#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL )\r
-#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL )\r
-\r
-/* The base period used by the timer test tasks. */\r
-#define mainTIMER_TEST_PERIOD ( 50 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Entry point for the comprehensive demo (as opposed to the simple blinky\r
- * demo).\r
- */\r
-void main_full( void );\r
-\r
-/*\r
- * The full demo includes some functionality called from the tick hook.\r
- */\r
-void vFullDemoTickHook( void );\r
-\r
- /*\r
- * The check task, as described at the top of this file.\r
- */\r
-static void prvCheckTask( void *pvParameters );\r
-\r
-/*\r
- * Register check tasks, and the tasks used to write over and check the contents\r
- * of the registers, as described at the top of this file. The nature of these\r
- * files necessitates that they are written in assembly, but the entry points\r
- * are kept in the C file for the convenience of checking the task parameter.\r
- */\r
-static void prvRegTest1Task( void *pvParameters );\r
-static void prvRegTest2Task( void *pvParameters );\r
-void vRegTest1Implementation( void );\r
-void vRegTest2Implementation( void );\r
-\r
-/*\r
- * A high priority task that does nothing other than execute at a pseudo random\r
- * time to ensure the other test tasks don't just execute in a repeating\r
- * pattern.\r
- */\r
-static void prvPseudoRandomiser( void *pvParameters );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The following two variables are used to communicate the status of the\r
-register check tasks to the check task. If the variables keep incrementing,\r
-then the register check tasks have not discovered any errors. If a variable\r
-stops incrementing, then an error has been found. */\r
-volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
-\r
-/* String for display in the web server. It is set to an error message if the\r
-check task detects an error. */\r
-const char *pcStatusMessage = "All tasks running without error";\r
-/*-----------------------------------------------------------*/\r
-\r
-void main_full( void )\r
-{\r
- /* Start all the other standard demo/test tasks. They have no particular\r
- functionality, but do demonstrate how to use the FreeRTOS API and test the\r
- kernel port. */\r
- vStartInterruptQueueTasks();\r
- vStartDynamicPriorityTasks();\r
- vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
- vCreateBlockTimeTasks();\r
- vStartCountingSemaphoreTasks();\r
- vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
- vStartRecursiveMutexTasks();\r
- vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
- vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
- vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
- vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );\r
- vStartEventGroupTasks();\r
- vStartTaskNotifyTask();\r
- vStartInterruptSemaphoreTasks();\r
-\r
- /* Create the register check tasks, as described at the top of this file */\r
- xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
-\r
- /* Create the task that just adds a little random behaviour. */\r
- xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
-\r
- /* Create the task that performs the 'check' functionality, as described at\r
- the top of this file. */\r
- xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
-\r
- /* The set of tasks created by the following function call have to be\r
- created last as they keep account of the number of tasks they expect to see\r
- running. */\r
- vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
-\r
- /* Start the scheduler. */\r
- vTaskStartScheduler();\r
-\r
- /* If all is well, the scheduler will now be running, and the following\r
- line will never be reached. If the following line does execute, then\r
- there was either insufficient FreeRTOS heap memory available for the idle\r
- and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
- User mode. See the memory management section on the FreeRTOS web site for\r
- more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
- mode from which main() is called is set in the C start up code and must be\r
- a privileged mode (not user mode). */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvCheckTask( void *pvParameters )\r
-{\r
-TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
-TickType_t xLastExecutionTime;\r
-static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
-unsigned long ulErrorFound = pdFALSE;\r
-\r
- /* Just to stop compiler warnings. */\r
- ( void ) pvParameters;\r
-\r
- /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
- works correctly. */\r
- xLastExecutionTime = xTaskGetTickCount();\r
-\r
- /* Cycle for ever, delaying then checking all the other tasks are still\r
- operating without error. The onboard LED is toggled on each iteration.\r
- If an error is detected then the delay period is decreased from\r
- mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
- effect of increasing the rate at which the onboard LED toggles, and in so\r
- doing gives visual feedback of the system status. */\r
- for( ;; )\r
- {\r
- /* Delay until it is time to execute again. */\r
- vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
-\r
- /* Check all the demo tasks (other than the flash tasks) to ensure\r
- that they are all still running, and that none have detected an error. */\r
- if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 0UL;\r
- }\r
-\r
- if( xAreMathsTaskStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 1UL;\r
- }\r
-\r
- if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 2UL;\r
- }\r
-\r
- if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 3UL;\r
- }\r
-\r
- if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 4UL;\r
- }\r
-\r
- if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 5UL;\r
- }\r
-\r
- if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 6UL;\r
- }\r
-\r
- if( xIsCreateTaskStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 7UL;\r
- }\r
-\r
- if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 8UL;\r
- }\r
-\r
- if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )\r
- {\r
- ulErrorFound |= 1UL << 9UL;\r
- }\r
-\r
- if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 10UL;\r
- }\r
-\r
- if( xIsQueueOverwriteTaskStillRunning() != pdPASS )\r
- {\r
- ulErrorFound |= 1UL << 11UL;\r
- }\r
-\r
- if( xAreEventGroupTasksStillRunning() != pdPASS )\r
- {\r
- ulErrorFound |= 1UL << 12UL;\r
- }\r
-\r
- if( xAreTaskNotificationTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 13UL;\r
- }\r
-\r
- if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 14UL;\r
- }\r
-\r
- /* Check that the register test 1 task is still running. */\r
- if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
- {\r
- ulErrorFound |= 1UL << 15UL;\r
- }\r
- ulLastRegTest1Value = ulRegTest1LoopCounter;\r
-\r
- /* Check that the register test 2 task is still running. */\r
- if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
- {\r
- ulErrorFound |= 1UL << 16UL;\r
- }\r
- ulLastRegTest2Value = ulRegTest2LoopCounter;\r
-\r
- /* Toggle the check LED to give an indication of the system status. If\r
- the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
- everything is ok. A faster toggle indicates an error. */\r
-//_RB_ LED0 = !LED0;\r
-\r
- if( ulErrorFound != pdFALSE )\r
- {\r
- /* An error has been detected in one of the tasks - flash the LED\r
- at a higher frequency to give visible feedback that something has\r
- gone wrong (it might just be that the loop back connector required\r
- by the comtest tasks has not been fitted). */\r
- xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
- pcStatusMessage = "Error found in at least one task.";\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvPseudoRandomiser( void *pvParameters )\r
-{\r
-const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );\r
-volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;\r
-\r
- /* This task does nothing other than ensure there is a little bit of\r
- disruption in the scheduling pattern of the other tasks. Normally this is\r
- done by generating interrupts at pseudo random times. */\r
- for( ;; )\r
- {\r
- ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;\r
- ulValue = ( ulNextRand >> 16UL ) & 0xffUL;\r
-\r
- if( ulValue < ulMinDelay )\r
- {\r
- ulValue = ulMinDelay;\r
- }\r
-\r
- vTaskDelay( ulValue );\r
-\r
- while( ulValue > 0 )\r
- {\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
-\r
- ulValue--;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vFullDemoTickHook( void )\r
-{\r
- /* The full demo includes a software timer demo/test that requires\r
- prodding periodically from the tick interrupt. */\r
- vTimerPeriodicISRTests();\r
-\r
- /* Call the periodic queue overwrite from ISR demo. */\r
- vQueueOverwritePeriodicISRDemo();\r
-\r
- /* Call the periodic event group from ISR demo. */\r
- vPeriodicEventGroupsProcessing();\r
-\r
- /* Use task notifications from an interrupt. */\r
- xNotifyTaskFromISR();\r
-\r
- /* Use mutexes from interrupts. */\r
- vInterruptSemaphorePeriodicTest();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This function is explained in the comments at the top of this file. */\r
-static void prvRegTest1Task( void *pvParameters )\r
-{\r
- if( pvParameters != mainREG_TEST_1_PARAMETER )\r
- {\r
- /* The parameter did not contain the expected value. */\r
- for( ;; )\r
- {\r
- /* Stop the tick interrupt so its obvious something has gone wrong. */\r
- taskDISABLE_INTERRUPTS();\r
- }\r
- }\r
-\r
- /* This is an inline asm function that never returns. */\r
- vRegTest1Implementation();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This function is explained in the comments at the top of this file. */\r
-static void prvRegTest2Task( void *pvParameters )\r
-{\r
- if( pvParameters != mainREG_TEST_2_PARAMETER )\r
- {\r
- /* The parameter did not contain the expected value. */\r
- for( ;; )\r
- {\r
- /* Stop the tick interrupt so its obvious something has gone wrong. */\r
- taskDISABLE_INTERRUPTS();\r
- }\r
- }\r
-\r
- /* This is an inline asm function that never returns. */\r
- vRegTest2Implementation();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
* File Name : r_cg_cgc.c\r
* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
* Device(s) : R5F52318AxFP\r
-* Tool-Chain : GCCRX\r
+* Tool-Chain : CCRX\r
* Description : This file implements device driver for CGC module.\r
-* Creation Date: 23/09/2015\r
+* Creation Date: 2015/08/17\r
***********************************************************************************************************************/\r
\r
/***********************************************************************************************************************\r
void R_CGC_Create(void)\r
{\r
uint32_t sckcr_dummy;\r
+ uint32_t w_count;\r
volatile uint32_t memorywaitcycle;\r
\r
/* Set main clock control registers */\r
SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _00_CGC_MAINOSC_UNDER10M;\r
- SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768;\r
+ SYSTEM.MOSCWTCR.BYTE = _04_CGC_OSC_WAIT_CYCLE_8192;\r
\r
/* Set main clock operation */\r
SYSTEM.MOSCCR.BIT.MOSTP = 0U;\r
while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF);\r
\r
/* Set system clock */\r
- sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000100_CGC_PCLKB_DIV_2 | _00001000_CGC_PCLKA_DIV_2 | \r
+ sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000100_CGC_PCLKB_DIV_2 | _00000000_CGC_PCLKA_DIV_1 | \r
_00010000_CGC_BCLK_DIV_2 | _00000000_CGC_ICLK_DIV_1 | _10000000_CGC_FCLK_DIV_2;\r
SYSTEM.SCKCR.LONG = sckcr_dummy;\r
\r
while (SYSTEM.SCKCR.LONG != sckcr_dummy);\r
\r
/* Set PLL circuit */\r
- SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 | _0C00_CGC_PLL_FREQ_MUL_6_5;\r
+ SYSTEM.PLLCR.WORD = _0001_CGC_PLL_FREQ_DIV_2 | _1A00_CGC_PLL_FREQ_MUL_13_5;\r
SYSTEM.PLLCR2.BIT.PLLEN = 0U;\r
\r
/* Wait for PLL wait counter overflow */\r
while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF);\r
\r
- /* Disable sub-clock */\r
+ /* Stop sub-clock */\r
SYSTEM.SOSCCR.BIT.SOSTP = 1U;\r
\r
/* Wait for the register modification to complete */\r
while (1U != SYSTEM.SOSCCR.BIT.SOSTP);\r
\r
- /* Disable sub-clock */\r
+ /* Stop sub-clock */\r
RTC.RCR3.BIT.RTCEN = 0U;\r
\r
/* Wait for the register modification to complete */\r
while (0U != RTC.RCR3.BIT.RTCEN);\r
\r
+ /* Wait for 5 sub-clock cycles */\r
+ for (w_count = 0U; w_count < _007B_CGC_SUBSTPWT_WAIT; w_count++)\r
+ {\r
+ nop();\r
+ }\r
+\r
+ /* Set sub-clock drive capacity */\r
+ RTC.RCR3.BIT.RTCDV = 1U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (1U != RTC.RCR3.BIT.RTCDV);\r
+\r
+ /* Set sub-clock */\r
+ SYSTEM.SOSCCR.BIT.SOSTP = 0U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (0U != SYSTEM.SOSCCR.BIT.SOSTP);\r
+\r
+ /* Wait for sub-clock to be stable */\r
+ for (w_count = 0U; w_count < _00061A81_CGC_SUBOSCWT_WAIT; w_count++)\r
+ {\r
+ nop();\r
+ }\r
+\r
/* Set BCLK */\r
SYSTEM.SCKCR.BIT.PSTOP1 = 1U;\r
\r
* File Name : r_cg_cgc.h\r
* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
* Device(s) : R5F52318AxFP\r
-* Tool-Chain : GCCRX\r
+* Tool-Chain : CCRX\r
* Description : This file implements device driver for CGC module.\r
-* Creation Date: 23/09/2015\r
+* Creation Date: 2015/08/17\r
***********************************************************************************************************************/\r
#ifndef CGC_H\r
#define CGC_H\r
/***********************************************************************************************************************\r
Macro definitions\r
***********************************************************************************************************************/\r
+#define _007B_CGC_SUBSTPWT_WAIT (0x007BU) /* Wait time for 5 sub clock cycles */\r
+#define _00061A81_CGC_SUBOSCWT_WAIT (0x00061A81U) /* Wait time for sub clock stable */\r
\r
/***********************************************************************************************************************\r
Typedef definitions\r
* File Name : r_cg_cgc_user.c\r
* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
* Device(s) : R5F52318AxFP\r
-* Tool-Chain : GCCRX\r
+* Tool-Chain : CCRX\r
* Description : This file implements device driver for CGC module.\r
-* Creation Date: 23/09/2015\r
+* Creation Date: 2015/08/17\r
***********************************************************************************************************************/\r
\r
/***********************************************************************************************************************\r
***********************************************************************************************************************/\r
#include "r_cg_macrodriver.h"\r
#include "r_cg_cgc.h"\r
+#include "r_cg_icu.h"\r
+#include "r_cg_port.h"\r
+\r
/* Start user code for include. Do not edit comment generated here */\r
/* End user code. Do not edit comment generated here */\r
#include "r_cg_userdefine.h"\r
\r
/* Set peripheral settings */\r
R_CGC_Create();\r
+ R_ICU_Create();\r
+ R_PORT_Create();\r
\r
/* Disable writing to MPC pin function control registers */\r
MPC.PWPR.BIT.PFSWE = 0U; \r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_icu.c\r
+* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for ICU module.\r
+* Creation Date: 2015/08/17\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_icu.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_ICU_Create\r
+* Description : This function initializes ICU module.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_ICU_Create(void)\r
+{\r
+ /* Disable IRQ0~7 interrupts */\r
+ ICU.IER[0x08].BYTE = _00_ICU_IRQ0_DISABLE | _00_ICU_IRQ1_DISABLE | _00_ICU_IRQ2_DISABLE | _00_ICU_IRQ3_DISABLE | \r
+ _00_ICU_IRQ4_DISABLE | _00_ICU_IRQ5_DISABLE | _00_ICU_IRQ6_DISABLE | _00_ICU_IRQ7_DISABLE;\r
+\r
+ /* Set IRQ settings */\r
+ ICU.IRQCR[1].BYTE = _04_ICU_IRQ_EDGE_FALLING;\r
+ ICU.IRQCR[4].BYTE = _04_ICU_IRQ_EDGE_FALLING;\r
+\r
+ /* Set IRQ1 priority level */\r
+ IPR(ICU,IRQ1) = _0F_ICU_PRIORITY_LEVEL15;\r
+\r
+ /* Set IRQ4 priority level */\r
+ IPR(ICU,IRQ4) = _0F_ICU_PRIORITY_LEVEL15;\r
+\r
+ /* Set IRQ1 pin */\r
+ MPC.P31PFS.BYTE = 0x40U;\r
+ PORT3.PDR.BYTE &= 0xFDU;\r
+ PORT3.PMR.BYTE &= 0xFDU;\r
+\r
+ /* Set IRQ4 pin */\r
+ MPC.P34PFS.BYTE = 0x40U;\r
+ PORT3.PDR.BYTE &= 0xEFU;\r
+ PORT3.PMR.BYTE &= 0xEFU;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_ICU_IRQ1_Start\r
+* Description : This function enables IRQ1 interrupt.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_ICU_IRQ1_Start(void)\r
+{\r
+ /* Enable IRQ1 interrupt */\r
+ IEN(ICU,IRQ1) = 1U; \r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_ICU_IRQ1_Stop\r
+* Description : This function disables IRQ1 interrupt.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_ICU_IRQ1_Stop(void)\r
+{\r
+ /* Disable IRQ1 interrupt */\r
+ IEN(ICU,IRQ1) = 0U; \r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_ICU_IRQ4_Start\r
+* Description : This function enables IRQ4 interrupt.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_ICU_IRQ4_Start(void)\r
+{\r
+ /* Enable IRQ4 interrupt */\r
+ IEN(ICU,IRQ4) = 1U; \r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_ICU_IRQ4_Stop\r
+* Description : This function disables IRQ4 interrupt.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_ICU_IRQ4_Stop(void)\r
+{\r
+ /* Disable IRQ4 interrupt */\r
+ IEN(ICU,IRQ4) = 0U; \r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+\r
+/*******************************************************************************\r
+* Function Name: R_ICU_IRQIsFallingEdge\r
+* Description : This function returns 1 if the specified ICU_IRQ is set to\r
+* falling edge triggered, otherwise 0.\r
+* Arguments : uint8_t irq_no\r
+* Return Value : 1 if falling edge triggered, 0 if not\r
+*******************************************************************************/\r
+uint8_t R_ICU_IRQIsFallingEdge (const uint8_t irq_no)\r
+{\r
+ uint8_t falling_edge_trig = 0x0;\r
+\r
+ if (ICU.IRQCR[irq_no].BYTE & _04_ICU_IRQ_EDGE_FALLING)\r
+ {\r
+ falling_edge_trig = 1;\r
+ }\r
+\r
+ return falling_edge_trig;\r
+\r
+}\r
+\r
+/*******************************************************************************\r
+* End of function R_ICU_IRQIsFallingEdge\r
+*******************************************************************************/\r
+\r
+/*******************************************************************************\r
+* Function Name: R_ICU_IRQSetFallingEdge\r
+* Description : This function sets/clears the falling edge trigger for the\r
+* specified ICU_IRQ.\r
+* Arguments : uint8_t irq_no\r
+* uint8_t set_f_edge, 1 if setting falling edge triggered, 0 if\r
+* clearing\r
+* Return Value : None\r
+*******************************************************************************/\r
+void R_ICU_IRQSetFallingEdge (const uint8_t irq_no, const uint8_t set_f_edge)\r
+{\r
+ if (1 == set_f_edge)\r
+ {\r
+ ICU.IRQCR[irq_no].BYTE |= _04_ICU_IRQ_EDGE_FALLING;\r
+ }\r
+ else\r
+ {\r
+ ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_04_ICU_IRQ_EDGE_FALLING;\r
+ }\r
+}\r
+\r
+/******************************************************************************\r
+* End of function R_ICU_IRQSetFallingEdge\r
+*******************************************************************************/\r
+\r
+/*******************************************************************************\r
+* Function Name: R_ICU_IRQSetRisingEdge\r
+* Description : This function sets/clear the rising edge trigger for the\r
+* specified ICU_IRQ.\r
+* Arguments : uint8_t irq_no\r
+* uint8_t set_r_edge, 1 if setting rising edge triggered, 0 if\r
+* clearing\r
+* Return Value : None\r
+*******************************************************************************/\r
+void R_ICU_IRQSetRisingEdge (const uint8_t irq_no, const uint8_t set_r_edge)\r
+{\r
+ if (1 == set_r_edge)\r
+ {\r
+ ICU.IRQCR[irq_no].BYTE |= _08_ICU_IRQ_EDGE_RISING;\r
+ }\r
+ else\r
+ {\r
+ ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_08_ICU_IRQ_EDGE_RISING;\r
+ }\r
+}\r
+\r
+/******************************************************************************\r
+* End of function R_ICU_IRQSetRisingEdge\r
+*******************************************************************************/\r
+\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_icu.h\r
+* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for ICU module.\r
+* Creation Date: 2015/08/17\r
+***********************************************************************************************************************/\r
+#ifndef ICU_H\r
+#define ICU_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+/*\r
+ Interrupt Request Enable Register 08 (IER08)\r
+*/\r
+/*Interrupt Request Enable/Disable(IENn) */\r
+#define _00_ICU_IRQ0_DISABLE (0x00U) /* IRQ0 interrupt request is disabled */\r
+#define _01_ICU_IRQ0_ENABLE (0x01U) /* IRQ0 interrupt request is enabled */\r
+#define _00_ICU_IRQ1_DISABLE (0x00U) /* IRQ1 interrupt request is disabled */\r
+#define _02_ICU_IRQ1_ENABLE (0x02U) /* IRQ1 interrupt request is enabled */\r
+#define _00_ICU_IRQ2_DISABLE (0x00U) /* IRQ2 interrupt request is disabled */\r
+#define _04_ICU_IRQ2_ENABLE (0x04U) /* IRQ2 interrupt request is enabled */\r
+#define _00_ICU_IRQ3_DISABLE (0x00U) /* IRQ3 interrupt request is disabled */\r
+#define _08_ICU_IRQ3_ENABLE (0x08U) /* IRQ3 interrupt request is enabled */\r
+#define _00_ICU_IRQ4_DISABLE (0x00U) /* IRQ4 interrupt request is disabled */\r
+#define _10_ICU_IRQ4_ENABLE (0x10U) /* IRQ4 interrupt request is enabled */\r
+#define _00_ICU_IRQ5_DISABLE (0x00U) /* IRQ5 interrupt request is disabled */\r
+#define _20_ICU_IRQ5_ENABLE (0x20U) /* IRQ5 interrupt request is enabled */\r
+#define _00_ICU_IRQ6_DISABLE (0x00U) /* IRQ6 interrupt request is disabled */\r
+#define _40_ICU_IRQ6_ENABLE (0x40U) /* IRQ6 interrupt request is enabled */\r
+#define _00_ICU_IRQ7_DISABLE (0x00U) /* IRQ7 interrupt request is disabled */\r
+#define _80_ICU_IRQ7_ENABLE (0x80U) /* IRQ7 interrupt request is enabled */\r
+\r
+/*\r
+ Interrupt Source Priority Register n (IPRn)\r
+*/\r
+/* Interrupt Priority Level Select (IPR[3:0]) */\r
+#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */\r
+#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */\r
+#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */\r
+#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */\r
+#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */\r
+#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */\r
+#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */\r
+#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */\r
+#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */\r
+#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */\r
+#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */\r
+#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */\r
+#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */\r
+#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */\r
+#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */\r
+#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */\r
+\r
+/*\r
+ Fast Interrupt Set Register (FIR)\r
+*/\r
+/* Fast Interrupt Enable (FIEN) */\r
+#define _0000_ICU_FAST_INTERRUPT_DISABLE (0x0000U) /* Fast interrupt is disabled */\r
+#define _8000_ICU_FAST_INTERRUPT_ENABLE (0x8000U) /* Fast interrupt is enabled */\r
+\r
+/*\r
+ IRQ Control Register i (IRQCRi) (i = 0 to 7)\r
+*/\r
+/* IRQ Detection Sense Select (IRQMD[1:0]) */\r
+#define _00_ICU_IRQ_EDGE_LOW_LEVEL (0x00U) /* Low level */\r
+#define _04_ICU_IRQ_EDGE_FALLING (0x04U) /* Falling edge */\r
+#define _08_ICU_IRQ_EDGE_RISING (0x08U) /* Rising edge */\r
+#define _0C_ICU_IRQ_EDGE_BOTH (0x0CU) /* Rising and falling edge */\r
+\r
+/*\r
+ IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0)\r
+*/\r
+/* Digital Filter Enable (FLTEN0n) */\r
+#define _00_ICU_IRQn_FILTER_DISABLE (0x00U) /* IRQn digital filter is disabled */\r
+#define _01_ICU_IRQ0_FILTER_ENABLE (0x01U) /* IRQ0 digital filter is enabled */\r
+#define _02_ICU_IRQ1_FILTER_ENABLE (0x02U) /* IRQ1 digital filter is enabled */\r
+#define _04_ICU_IRQ2_FILTER_ENABLE (0x04U) /* IRQ2 digital filter is enabled */\r
+#define _08_ICU_IRQ3_FILTER_ENABLE (0x08U) /* IRQ3 digital filter is enabled */\r
+#define _10_ICU_IRQ4_FILTER_ENABLE (0x10U) /* IRQ4 digital filter is enabled */\r
+#define _20_ICU_IRQ5_FILTER_ENABLE (0x20U) /* IRQ5 digital filter is enabled */\r
+#define _40_ICU_IRQ6_FILTER_ENABLE (0x40U) /* IRQ6 digital filter is enabled */\r
+#define _80_ICU_IRQ7_FILTER_ENABLE (0x80U) /* IRQ7 digital filter is enabled */\r
+\r
+/*\r
+ IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0)\r
+*/\r
+/* IRQn Digital Filter Sampling Clock (FCLKSELn) */\r
+#define _0000_ICU_IRQ0_FILTER_PCLK (0x0000U) /* IRQ0 sample clock is run at every PCLK cycle */\r
+#define _0001_ICU_IRQ0_FILTER_PCLK_8 (0x0001U) /* IRQ0 sample clock is run at every PCLK/8 cycle */\r
+#define _0002_ICU_IRQ0_FILTER_PCLK_32 (0x0002U) /* IRQ0 sample clock is run at every PCLK/32 cycle */\r
+#define _0003_ICU_IRQ0_FILTER_PCLK_64 (0x0003U) /* IRQ0 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ1_FILTER_PCLK (0x0000U) /* IRQ1 sample clock is run at every PCLK cycle */\r
+#define _0004_ICU_IRQ1_FILTER_PCLK_8 (0x0004U) /* IRQ1 sample clock is run at every PCLK/8 cycle */\r
+#define _0008_ICU_IRQ1_FILTER_PCLK_32 (0x0008U) /* IRQ1 sample clock is run at every PCLK/32 cycle */\r
+#define _000C_ICU_IRQ1_FILTER_PCLK_64 (0x000CU) /* IRQ1 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ2_FILTER_PCLK (0x0000U) /* IRQ2 sample clock is run at every PCLK cycle */\r
+#define _0010_ICU_IRQ2_FILTER_PCLK_8 (0x0010U) /* IRQ2 sample clock is run at every PCLK/8 cycle */\r
+#define _0020_ICU_IRQ2_FILTER_PCLK_32 (0x0020U) /* IRQ2 sample clock is run at every PCLK/32 cycle */\r
+#define _0030_ICU_IRQ2_FILTER_PCLK_64 (0x0030U) /* IRQ2 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ3_FILTER_PCLK (0x0000U) /* IRQ3 sample clock is run at every PCLK cycle */\r
+#define _0040_ICU_IRQ3_FILTER_PCLK_8 (0x0040U) /* IRQ3 sample clock is run at every PCLK/8 cycle */\r
+#define _0080_ICU_IRQ3_FILTER_PCLK_32 (0x0080U) /* IRQ3 sample clock is run at every PCLK/32 cycle */\r
+#define _00C0_ICU_IRQ3_FILTER_PCLK_64 (0x00C0U) /* IRQ3 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ4_FILTER_PCLK (0x0000U) /* IRQ4 sample clock is run at every PCLK cycle */\r
+#define _0100_ICU_IRQ4_FILTER_PCLK_8 (0x0100U) /* IRQ4 sample clock is run at every PCLK/8 cycle */\r
+#define _0200_ICU_IRQ4_FILTER_PCLK_32 (0x0200U) /* IRQ4 sample clock is run at every PCLK/32 cycle */\r
+#define _0300_ICU_IRQ4_FILTER_PCLK_64 (0x0300U) /* IRQ4 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ5_FILTER_PCLK (0x0000U) /* IRQ5 sample clock is run at every PCLK cycle */\r
+#define _0400_ICU_IRQ5_FILTER_PCLK_8 (0x0400U) /* IRQ5 sample clock is run at every PCLK/8 cycle */\r
+#define _0800_ICU_IRQ5_FILTER_PCLK_32 (0x0800U) /* IRQ5 sample clock is run at every PCLK/32 cycle */\r
+#define _0C00_ICU_IRQ5_FILTER_PCLK_64 (0x0C00U) /* IRQ5 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ6_FILTER_PCLK (0x0000U) /* IRQ6 sample clock is run at every PCLK cycle */\r
+#define _1000_ICU_IRQ6_FILTER_PCLK_8 (0x1000U) /* IRQ6 sample clock is run at every PCLK/8 cycle */\r
+#define _2000_ICU_IRQ6_FILTER_PCLK_32 (0x2000U) /* IRQ6 sample clock is run at every PCLK/32 cycle */\r
+#define _3000_ICU_IRQ6_FILTER_PCLK_64 (0x3000U) /* IRQ6 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ7_FILTER_PCLK (0x0000U) /* IRQ7 sample clock is run at every PCLK cycle */\r
+#define _4000_ICU_IRQ7_FILTER_PCLK_8 (0x4000U) /* IRQ7 sample clock is run at every PCLK/8 cycle */\r
+#define _8000_ICU_IRQ7_FILTER_PCLK_32 (0x8000U) /* IRQ7 sample clock is run at every PCLK/32 cycle */\r
+#define _C000_ICU_IRQ7_FILTER_PCLK_64 (0xC000U) /* IRQ7 sample clock is run at every PCLK/64 cycle */\r
+\r
+/*\r
+ NMI Pin Interrupt Control Register (NMICR)\r
+*/\r
+/* NMI Digital Filter Sampling Clock (NMIMD) */\r
+#define _00_ICU_NMI_EDGE_FALLING (0x00U) /* Falling edge */\r
+#define _08_ICU_NMI_EDGE_RISING (0x08U) /* Rising edge */\r
+\r
+/*\r
+ NMI Pin Digital Filter Setting Register (NMIFLTC)\r
+*/\r
+/* NMI Digital Filter Sampling Clock (NFCLKSEL[1:0]) */\r
+#define _00_ICU_NMI_FILTER_PCLK (0x00U) /* NMI sample clock is run at every PCLK cycle */\r
+#define _01_ICU_NMI_FILTER_PCLK_8 (0x01U) /* NMI sample clock is run at every PCLK/8 cycle */\r
+#define _02_ICU_NMI_FILTER_PCLK_32 (0x02U) /* NMI sample clock is run at every PCLK/32 cycle */\r
+#define _03_ICU_NMI_FILTER_PCLK_64 (0x03U) /* NMI sample clock is run at every PCLK/64 cycle */\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_ICU_Create(void);\r
+void R_ICU_IRQ1_Start(void);\r
+void R_ICU_IRQ1_Stop(void);\r
+void R_ICU_IRQ4_Start(void);\r
+void R_ICU_IRQ4_Stop(void);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+\r
+/* Function prototypes for detecting and setting the edge trigger of ICU_IRQ */\r
+uint8_t R_ICU_IRQIsFallingEdge(const uint8_t irq_no);\r
+void R_ICU_IRQSetFallingEdge(const uint8_t irq_no, const uint8_t set_f_edge);\r
+void R_ICU_IRQSetRisingEdge(const uint8_t irq_no, const uint8_t set_r_edge);\r
+\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_port.c\r
+* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for Port module.\r
+* Creation Date: 2015/08/17\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_port.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_PORT_Create\r
+* Description : This function initializes the Port I/O.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_PORT_Create(void)\r
+{\r
+ PORT1.PODR.BYTE = _80_Pm7_OUTPUT_1;\r
+ PORT3.PODR.BYTE = _08_Pm3_OUTPUT_1;\r
+ PORT5.PODR.BYTE = _01_Pm0_OUTPUT_1 | _02_Pm1_OUTPUT_1 | _04_Pm2_OUTPUT_1;\r
+ PORTE.PODR.BYTE = _08_Pm3_OUTPUT_1 | _80_Pm7_OUTPUT_1;\r
+ PORT1.PDR.BYTE = _80_Pm7_MODE_OUTPUT;\r
+ PORT3.PDR.BYTE = _08_Pm3_MODE_OUTPUT;\r
+ PORT5.PDR.BYTE = _01_Pm0_MODE_OUTPUT | _02_Pm1_MODE_OUTPUT | _04_Pm2_MODE_OUTPUT;\r
+ PORTE.PDR.BYTE = _08_Pm3_MODE_OUTPUT | _10_Pm4_MODE_OUTPUT | _80_Pm7_MODE_OUTPUT;\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_port.h\r
+* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for Port module.\r
+* Creation Date: 2015/08/17\r
+***********************************************************************************************************************/\r
+#ifndef PORT_H\r
+#define PORT_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+/*\r
+ Port Direction Register (PDR)\r
+*/\r
+/* Pmn Direction Control (B7 - B0) */\r
+#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */\r
+#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */\r
+#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */\r
+#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */\r
+#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */\r
+#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */\r
+#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */\r
+#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */\r
+#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */\r
+#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */\r
+#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */\r
+#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */\r
+#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */\r
+#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */\r
+#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */\r
+#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */\r
+#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */\r
+#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */\r
+#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */\r
+#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */\r
+#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */\r
+#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */\r
+#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */\r
+#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */\r
+\r
+/*\r
+ Port Output Data Register (PODR)\r
+*/\r
+/* Pmn Output Data Store (B7 - B0) */\r
+#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */\r
+#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */\r
+#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */\r
+#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */\r
+#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */\r
+#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */\r
+#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */\r
+#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */\r
+#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */\r
+#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */\r
+#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */\r
+#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */\r
+#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */\r
+#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */\r
+#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */\r
+#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */\r
+\r
+/*\r
+ Open Drain Control Register 0 (ODR0)\r
+*/\r
+/* Pmn Output Type Select (Pm0 to Pm3) */\r
+#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
+#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
+#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* PMOS open-drain output, for PE1 only*/\r
+#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
+#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
+\r
+/*\r
+ Open Drain Control Register 1 (ODR1)\r
+*/\r
+/* Pmn Output Type Select (Pm4 to Pm7) */\r
+#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
+#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
+#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
+#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
+\r
+/*\r
+ Pull-Up Control Register (PCR)\r
+*/\r
+/* Pmn Input Pull-Up Resistor Control (B7 - B0) */\r
+#define _00_Pm0_PULLUP_OFF (0x00U) /* Pm0 pull-up resistor not connected */\r
+#define _01_Pm0_PULLUP_ON (0x01U) /* Pm0 pull-up resistor connected */\r
+#define _00_Pm1_PULLUP_OFF (0x00U) /* Pm1 pull-up resistor not connected */\r
+#define _02_Pm1_PULLUP_ON (0x02U) /* Pm1 pull-up resistor connected */\r
+#define _00_Pm2_PULLUP_OFF (0x00U) /* Pm2 Pull-up resistor not connected */\r
+#define _04_Pm2_PULLUP_ON (0x04U) /* Pm2 pull-up resistor connected */\r
+#define _00_Pm3_PULLUP_OFF (0x00U) /* Pm3 pull-up resistor not connected */\r
+#define _08_Pm3_PULLUP_ON (0x08U) /* Pm3 pull-up resistor connected */\r
+#define _00_Pm4_PULLUP_OFF (0x00U) /* Pm4 pull-up resistor not connected */\r
+#define _10_Pm4_PULLUP_ON (0x10U) /* Pm4 pull-up resistor connected */\r
+#define _00_Pm5_PULLUP_OFF (0x00U) /* Pm5 pull-up resistor not connected */\r
+#define _20_Pm5_PULLUP_ON (0x20U) /* Pm5 pull-up resistor connected */\r
+#define _00_Pm6_PULLUP_OFF (0x00U) /* Pm6 pull-up resistor not connected */\r
+#define _40_Pm6_PULLUP_ON (0x40U) /* Pm6 pull-up resistor connected */\r
+#define _00_Pm7_PULLUP_OFF (0x00U) /* Pm7 pull-up resistor not connected */\r
+#define _80_Pm7_PULLUP_ON (0x80U) /* Pm7 pull-up resistor connected */\r
+\r
+/*\r
+ Drive Capacity Control Register (DSCR)\r
+*/\r
+/* Pmn Drive Capacity Control (B7 - B0) */\r
+#define _00_Pm0_HIDRV_OFF (0x00U) /* Pm0 Normal drive output */\r
+#define _01_Pm0_HIDRV_ON (0x01U) /* Pm0 High-drive output */\r
+#define _00_Pm1_HIDRV_OFF (0x00U) /* Pm1 Normal drive output */\r
+#define _02_Pm1_HIDRV_ON (0x02U) /* Pm1 High-drive output */\r
+#define _00_Pm2_HIDRV_OFF (0x00U) /* Pm2 Normal drive output */\r
+#define _04_Pm2_HIDRV_ON (0x04U) /* Pm2 High-drive output */\r
+#define _00_Pm3_HIDRV_OFF (0x00U) /* Pm3 Normal drive output */\r
+#define _08_Pm3_HIDRV_ON (0x08U) /* Pm3 High-drive output */\r
+#define _00_Pm4_HIDRV_OFF (0x00U) /* Pm4 Normal drive output */\r
+#define _10_Pm4_HIDRV_ON (0x10U) /* Pm4 High-drive output */\r
+#define _00_Pm5_HIDRV_OFF (0x00U) /* Pm5 Normal drive output */\r
+#define _20_Pm5_HIDRV_ON (0x20U) /* Pm5 High-drive output */\r
+#define _00_Pm6_HIDRV_OFF (0x00U) /* Pm6 Normal drive output */\r
+#define _40_Pm6_HIDRV_ON (0x40U) /* Pm6 High-drive output */\r
+#define _00_Pm7_HIDRV_OFF (0x00U) /* Pm7 Normal drive output */\r
+#define _80_Pm7_HIDRV_ON (0x80U) /* Pm7 High-drive output */\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_PORT_Create(void);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
* File Name : r_cg_userdefine.h\r
* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
* Device(s) : R5F52318AxFP\r
-* Tool-Chain : GCCRX\r
+* Tool-Chain : CCRX\r
* Description : This file includes user definition.\r
-* Creation Date: 23/09/2015\r
+* Creation Date: 2015/08/17\r
***********************************************************************************************************************/\r
#ifndef _USER_DEF_H\r
#define _USER_DEF_H\r
/***********************************************************************************************************************\r
User definitions\r
***********************************************************************************************************************/\r
+#define FAST_INTERRUPT_VECTOR 0\r
\r
/* Start user code for function. Do not edit comment generated here */\r
+\r
+#define TRUE (1)\r
+#define FALSE (0)\r
+\r
+extern volatile uint8_t g_adc_trigger;\r
+\r
/* End user code. Do not edit comment generated here */\r
#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : rskrx231def.h\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : CCRX\r
+* H/W Platform : RSKRX231\r
+* Description : Defines macros relating to the RSKRX231 user LEDs and switches\r
+***********************************************************************************************************************/\r
+/**********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 01.06.2015 1.00 First Release\r
+***********************************************************************************************************************/\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+#ifndef RSKRX231_H\r
+#define RSKRX231_H\r
+\r
+\r
+/* General Values */\r
+#define LED_ON (0)\r
+#define LED_OFF (1)\r
+#define SET_BIT_HIGH (1)\r
+#define SET_BIT_LOW (0)\r
+#define SET_BYTE_HIGH (0xFF)\r
+#define SET_BYTE_LOW (0x00)\r
+\r
+/* Switches */\r
+#define SW1 (PORT3.PIDR.BIT.B1)\r
+#define SW2 (PORT3.PIDR.BIT.B4)\r
+#define SW3 (PORT0.PIDR.BIT.B7)\r
+\r
+/* LED port settings */\r
+#define LED0 (PORT1.PODR.BIT.B7)\r
+#define LED1 (PORT5.PODR.BIT.B0)\r
+#define LED2 (PORT5.PODR.BIT.B1)\r
+#define LED3 (PORT5.PODR.BIT.B2)\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Exported global variables\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Exported global functions (to be accessed by other files)\r
+***********************************************************************************************************************/\r
+\r
+#endif\r
+\r
#include "task.h"\r
#include "semphr.h"\r
\r
+/* Renesas includes. */\r
+#include "rskrx231def.h"\r
+\r
/* Priorities at which the tasks are created. */\r
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
is it the expected value? If it is, toggle the LED. */\r
if( ulReceivedValue == ulExpectedValue )\r
{\r
-//_RB_ LED0 = !LED0;\r
+ LED0 = !LED0;\r
ulReceivedValue = 0U;\r
}\r
}\r
#define configUSE_PREEMPTION 1\r
#define configUSE_IDLE_HOOK 1\r
#define configUSE_TICK_HOOK 1\r
-#define configCPU_CLOCK_HZ ( 52000000UL ) /*_RB_ guess*/\r
-#define configPERIPHERAL_CLOCK_HZ ( 26000000UL ) /*_RB_ guess*/\r
+#define configCPU_CLOCK_HZ ( 52000000UL )\r
+#define configPERIPHERAL_CLOCK_HZ ( 26000000UL )\r
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 )\r
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) )\r
#include "TaskNotify.h"\r
#include "IntSemTest.h"\r
\r
+/* Renesas includes. */\r
+#include "rskrx231def.h"\r
+\r
/* Priorities for the demo application tasks. */\r
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
/* Toggle the check LED to give an indication of the system status. If\r
the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
everything is ok. A faster toggle indicates an error. */\r
-//_RB_ LED0 = !LED0;\r
+ LED0 = !LED0;\r
\r
if( ulErrorFound != pdFALSE )\r
{\r
* Device(s) : R5F52318AxFP\r
* Tool-Chain : CCRX\r
* Description : This file implements device driver for CGC module.\r
-* Creation Date: 23/09/2015\r
+* Creation Date: 2015/08/17\r
***********************************************************************************************************************/\r
\r
/***********************************************************************************************************************\r
void R_CGC_Create(void)\r
{\r
uint32_t sckcr_dummy;\r
+ uint32_t w_count;\r
volatile uint32_t memorywaitcycle;\r
\r
/* Set main clock control registers */\r
SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _00_CGC_MAINOSC_UNDER10M;\r
- SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768;\r
+ SYSTEM.MOSCWTCR.BYTE = _04_CGC_OSC_WAIT_CYCLE_8192;\r
\r
/* Set main clock operation */\r
SYSTEM.MOSCCR.BIT.MOSTP = 0U;\r
while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF);\r
\r
/* Set system clock */\r
- sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000100_CGC_PCLKB_DIV_2 | _00001000_CGC_PCLKA_DIV_2 | \r
+ sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000100_CGC_PCLKB_DIV_2 | _00000000_CGC_PCLKA_DIV_1 | \r
_00010000_CGC_BCLK_DIV_2 | _00000000_CGC_ICLK_DIV_1 | _10000000_CGC_FCLK_DIV_2;\r
SYSTEM.SCKCR.LONG = sckcr_dummy;\r
\r
while (SYSTEM.SCKCR.LONG != sckcr_dummy);\r
\r
/* Set PLL circuit */\r
- SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 | _0C00_CGC_PLL_FREQ_MUL_6_5;\r
+ SYSTEM.PLLCR.WORD = _0001_CGC_PLL_FREQ_DIV_2 | _1A00_CGC_PLL_FREQ_MUL_13_5;\r
SYSTEM.PLLCR2.BIT.PLLEN = 0U;\r
\r
/* Wait for PLL wait counter overflow */\r
while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF);\r
\r
- /* Disable sub-clock */\r
+ /* Stop sub-clock */\r
SYSTEM.SOSCCR.BIT.SOSTP = 1U;\r
\r
/* Wait for the register modification to complete */\r
while (1U != SYSTEM.SOSCCR.BIT.SOSTP);\r
\r
- /* Disable sub-clock */\r
+ /* Stop sub-clock */\r
RTC.RCR3.BIT.RTCEN = 0U;\r
\r
/* Wait for the register modification to complete */\r
while (0U != RTC.RCR3.BIT.RTCEN);\r
\r
+ /* Wait for 5 sub-clock cycles */\r
+ for (w_count = 0U; w_count < _007B_CGC_SUBSTPWT_WAIT; w_count++)\r
+ {\r
+ nop();\r
+ }\r
+\r
+ /* Set sub-clock drive capacity */\r
+ RTC.RCR3.BIT.RTCDV = 1U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (1U != RTC.RCR3.BIT.RTCDV);\r
+\r
+ /* Set sub-clock */\r
+ SYSTEM.SOSCCR.BIT.SOSTP = 0U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (0U != SYSTEM.SOSCCR.BIT.SOSTP);\r
+\r
+ /* Wait for sub-clock to be stable */\r
+ for (w_count = 0U; w_count < _00061A81_CGC_SUBOSCWT_WAIT; w_count++)\r
+ {\r
+ nop();\r
+ }\r
+\r
/* Set BCLK */\r
SYSTEM.SCKCR.BIT.PSTOP1 = 1U;\r
\r
* Device(s) : R5F52318AxFP\r
* Tool-Chain : CCRX\r
* Description : This file implements device driver for CGC module.\r
-* Creation Date: 23/09/2015\r
+* Creation Date: 2015/08/17\r
***********************************************************************************************************************/\r
#ifndef CGC_H\r
#define CGC_H\r
/***********************************************************************************************************************\r
Macro definitions\r
***********************************************************************************************************************/\r
+#define _007B_CGC_SUBSTPWT_WAIT (0x007BU) /* Wait time for 5 sub clock cycles */\r
+#define _00061A81_CGC_SUBOSCWT_WAIT (0x00061A81U) /* Wait time for sub clock stable */\r
\r
/***********************************************************************************************************************\r
Typedef definitions\r
* Device(s) : R5F52318AxFP\r
* Tool-Chain : CCRX\r
* Description : This file implements device driver for CGC module.\r
-* Creation Date: 23/09/2015\r
+* Creation Date: 2015/08/17\r
***********************************************************************************************************************/\r
\r
/***********************************************************************************************************************\r
* File Name : r_cg_hardware_setup.c\r
* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
* Device(s) : R5F52318AxFP\r
-* Tool-Chain : CCRX\r
+* Tool-Chain : GCCRX\r
* Description : This file implements system initializing function.\r
* Creation Date: 23/09/2015\r
***********************************************************************************************************************/\r
***********************************************************************************************************************/\r
#include "r_cg_macrodriver.h"\r
#include "r_cg_cgc.h"\r
+#include "r_cg_icu.h"\r
+#include "r_cg_port.h"\r
+\r
/* Start user code for include. Do not edit comment generated here */\r
/* End user code. Do not edit comment generated here */\r
#include "r_cg_userdefine.h"\r
/* Start user code for global. Do not edit comment generated here */\r
/* End user code. Do not edit comment generated here */\r
\r
+int HardwareSetup(void);\r
+void R_Systeminit(void);\r
+\r
/***********************************************************************************************************************\r
* Function Name: R_Systeminit\r
* Description : This function initializes every macro.\r
\r
/* Set peripheral settings */\r
R_CGC_Create();\r
+ R_ICU_Create();\r
+ R_PORT_Create();\r
\r
/* Disable writing to MPC pin function control registers */\r
MPC.PWPR.BIT.PFSWE = 0U; \r
* Arguments : None\r
* Return Value : None\r
***********************************************************************************************************************/\r
-void HardwareSetup(void)\r
+int HardwareSetup(void)\r
{\r
R_Systeminit();\r
+\r
+ return (1U);\r
}\r
\r
/* Start user code for adding. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_icu.c\r
+* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for ICU module.\r
+* Creation Date: 2015/08/17\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_icu.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_ICU_Create\r
+* Description : This function initializes ICU module.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_ICU_Create(void)\r
+{\r
+ /* Disable IRQ0~7 interrupts */\r
+ ICU.IER[0x08].BYTE = _00_ICU_IRQ0_DISABLE | _00_ICU_IRQ1_DISABLE | _00_ICU_IRQ2_DISABLE | _00_ICU_IRQ3_DISABLE | \r
+ _00_ICU_IRQ4_DISABLE | _00_ICU_IRQ5_DISABLE | _00_ICU_IRQ6_DISABLE | _00_ICU_IRQ7_DISABLE;\r
+\r
+ /* Set IRQ settings */\r
+ ICU.IRQCR[1].BYTE = _04_ICU_IRQ_EDGE_FALLING;\r
+ ICU.IRQCR[4].BYTE = _04_ICU_IRQ_EDGE_FALLING;\r
+\r
+ /* Set IRQ1 priority level */\r
+ IPR(ICU,IRQ1) = _0F_ICU_PRIORITY_LEVEL15;\r
+\r
+ /* Set IRQ4 priority level */\r
+ IPR(ICU,IRQ4) = _0F_ICU_PRIORITY_LEVEL15;\r
+\r
+ /* Set IRQ1 pin */\r
+ MPC.P31PFS.BYTE = 0x40U;\r
+ PORT3.PDR.BYTE &= 0xFDU;\r
+ PORT3.PMR.BYTE &= 0xFDU;\r
+\r
+ /* Set IRQ4 pin */\r
+ MPC.P34PFS.BYTE = 0x40U;\r
+ PORT3.PDR.BYTE &= 0xEFU;\r
+ PORT3.PMR.BYTE &= 0xEFU;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_ICU_IRQ1_Start\r
+* Description : This function enables IRQ1 interrupt.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_ICU_IRQ1_Start(void)\r
+{\r
+ /* Enable IRQ1 interrupt */\r
+ IEN(ICU,IRQ1) = 1U; \r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_ICU_IRQ1_Stop\r
+* Description : This function disables IRQ1 interrupt.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_ICU_IRQ1_Stop(void)\r
+{\r
+ /* Disable IRQ1 interrupt */\r
+ IEN(ICU,IRQ1) = 0U; \r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_ICU_IRQ4_Start\r
+* Description : This function enables IRQ4 interrupt.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_ICU_IRQ4_Start(void)\r
+{\r
+ /* Enable IRQ4 interrupt */\r
+ IEN(ICU,IRQ4) = 1U; \r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_ICU_IRQ4_Stop\r
+* Description : This function disables IRQ4 interrupt.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_ICU_IRQ4_Stop(void)\r
+{\r
+ /* Disable IRQ4 interrupt */\r
+ IEN(ICU,IRQ4) = 0U; \r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+\r
+/*******************************************************************************\r
+* Function Name: R_ICU_IRQIsFallingEdge\r
+* Description : This function returns 1 if the specified ICU_IRQ is set to\r
+* falling edge triggered, otherwise 0.\r
+* Arguments : uint8_t irq_no\r
+* Return Value : 1 if falling edge triggered, 0 if not\r
+*******************************************************************************/\r
+uint8_t R_ICU_IRQIsFallingEdge (const uint8_t irq_no)\r
+{\r
+ uint8_t falling_edge_trig = 0x0;\r
+\r
+ if (ICU.IRQCR[irq_no].BYTE & _04_ICU_IRQ_EDGE_FALLING)\r
+ {\r
+ falling_edge_trig = 1;\r
+ }\r
+\r
+ return falling_edge_trig;\r
+\r
+}\r
+\r
+/*******************************************************************************\r
+* End of function R_ICU_IRQIsFallingEdge\r
+*******************************************************************************/\r
+\r
+/*******************************************************************************\r
+* Function Name: R_ICU_IRQSetFallingEdge\r
+* Description : This function sets/clears the falling edge trigger for the\r
+* specified ICU_IRQ.\r
+* Arguments : uint8_t irq_no\r
+* uint8_t set_f_edge, 1 if setting falling edge triggered, 0 if\r
+* clearing\r
+* Return Value : None\r
+*******************************************************************************/\r
+void R_ICU_IRQSetFallingEdge (const uint8_t irq_no, const uint8_t set_f_edge)\r
+{\r
+ if (1 == set_f_edge)\r
+ {\r
+ ICU.IRQCR[irq_no].BYTE |= _04_ICU_IRQ_EDGE_FALLING;\r
+ }\r
+ else\r
+ {\r
+ ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_04_ICU_IRQ_EDGE_FALLING;\r
+ }\r
+}\r
+\r
+/******************************************************************************\r
+* End of function R_ICU_IRQSetFallingEdge\r
+*******************************************************************************/\r
+\r
+/*******************************************************************************\r
+* Function Name: R_ICU_IRQSetRisingEdge\r
+* Description : This function sets/clear the rising edge trigger for the\r
+* specified ICU_IRQ.\r
+* Arguments : uint8_t irq_no\r
+* uint8_t set_r_edge, 1 if setting rising edge triggered, 0 if\r
+* clearing\r
+* Return Value : None\r
+*******************************************************************************/\r
+void R_ICU_IRQSetRisingEdge (const uint8_t irq_no, const uint8_t set_r_edge)\r
+{\r
+ if (1 == set_r_edge)\r
+ {\r
+ ICU.IRQCR[irq_no].BYTE |= _08_ICU_IRQ_EDGE_RISING;\r
+ }\r
+ else\r
+ {\r
+ ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_08_ICU_IRQ_EDGE_RISING;\r
+ }\r
+}\r
+\r
+/******************************************************************************\r
+* End of function R_ICU_IRQSetRisingEdge\r
+*******************************************************************************/\r
+\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_icu.h\r
+* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for ICU module.\r
+* Creation Date: 2015/08/17\r
+***********************************************************************************************************************/\r
+#ifndef ICU_H\r
+#define ICU_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+/*\r
+ Interrupt Request Enable Register 08 (IER08)\r
+*/\r
+/*Interrupt Request Enable/Disable(IENn) */\r
+#define _00_ICU_IRQ0_DISABLE (0x00U) /* IRQ0 interrupt request is disabled */\r
+#define _01_ICU_IRQ0_ENABLE (0x01U) /* IRQ0 interrupt request is enabled */\r
+#define _00_ICU_IRQ1_DISABLE (0x00U) /* IRQ1 interrupt request is disabled */\r
+#define _02_ICU_IRQ1_ENABLE (0x02U) /* IRQ1 interrupt request is enabled */\r
+#define _00_ICU_IRQ2_DISABLE (0x00U) /* IRQ2 interrupt request is disabled */\r
+#define _04_ICU_IRQ2_ENABLE (0x04U) /* IRQ2 interrupt request is enabled */\r
+#define _00_ICU_IRQ3_DISABLE (0x00U) /* IRQ3 interrupt request is disabled */\r
+#define _08_ICU_IRQ3_ENABLE (0x08U) /* IRQ3 interrupt request is enabled */\r
+#define _00_ICU_IRQ4_DISABLE (0x00U) /* IRQ4 interrupt request is disabled */\r
+#define _10_ICU_IRQ4_ENABLE (0x10U) /* IRQ4 interrupt request is enabled */\r
+#define _00_ICU_IRQ5_DISABLE (0x00U) /* IRQ5 interrupt request is disabled */\r
+#define _20_ICU_IRQ5_ENABLE (0x20U) /* IRQ5 interrupt request is enabled */\r
+#define _00_ICU_IRQ6_DISABLE (0x00U) /* IRQ6 interrupt request is disabled */\r
+#define _40_ICU_IRQ6_ENABLE (0x40U) /* IRQ6 interrupt request is enabled */\r
+#define _00_ICU_IRQ7_DISABLE (0x00U) /* IRQ7 interrupt request is disabled */\r
+#define _80_ICU_IRQ7_ENABLE (0x80U) /* IRQ7 interrupt request is enabled */\r
+\r
+/*\r
+ Interrupt Source Priority Register n (IPRn)\r
+*/\r
+/* Interrupt Priority Level Select (IPR[3:0]) */\r
+#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */\r
+#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */\r
+#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */\r
+#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */\r
+#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */\r
+#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */\r
+#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */\r
+#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */\r
+#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */\r
+#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */\r
+#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */\r
+#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */\r
+#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */\r
+#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */\r
+#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */\r
+#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */\r
+\r
+/*\r
+ Fast Interrupt Set Register (FIR)\r
+*/\r
+/* Fast Interrupt Enable (FIEN) */\r
+#define _0000_ICU_FAST_INTERRUPT_DISABLE (0x0000U) /* Fast interrupt is disabled */\r
+#define _8000_ICU_FAST_INTERRUPT_ENABLE (0x8000U) /* Fast interrupt is enabled */\r
+\r
+/*\r
+ IRQ Control Register i (IRQCRi) (i = 0 to 7)\r
+*/\r
+/* IRQ Detection Sense Select (IRQMD[1:0]) */\r
+#define _00_ICU_IRQ_EDGE_LOW_LEVEL (0x00U) /* Low level */\r
+#define _04_ICU_IRQ_EDGE_FALLING (0x04U) /* Falling edge */\r
+#define _08_ICU_IRQ_EDGE_RISING (0x08U) /* Rising edge */\r
+#define _0C_ICU_IRQ_EDGE_BOTH (0x0CU) /* Rising and falling edge */\r
+\r
+/*\r
+ IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0)\r
+*/\r
+/* Digital Filter Enable (FLTEN0n) */\r
+#define _00_ICU_IRQn_FILTER_DISABLE (0x00U) /* IRQn digital filter is disabled */\r
+#define _01_ICU_IRQ0_FILTER_ENABLE (0x01U) /* IRQ0 digital filter is enabled */\r
+#define _02_ICU_IRQ1_FILTER_ENABLE (0x02U) /* IRQ1 digital filter is enabled */\r
+#define _04_ICU_IRQ2_FILTER_ENABLE (0x04U) /* IRQ2 digital filter is enabled */\r
+#define _08_ICU_IRQ3_FILTER_ENABLE (0x08U) /* IRQ3 digital filter is enabled */\r
+#define _10_ICU_IRQ4_FILTER_ENABLE (0x10U) /* IRQ4 digital filter is enabled */\r
+#define _20_ICU_IRQ5_FILTER_ENABLE (0x20U) /* IRQ5 digital filter is enabled */\r
+#define _40_ICU_IRQ6_FILTER_ENABLE (0x40U) /* IRQ6 digital filter is enabled */\r
+#define _80_ICU_IRQ7_FILTER_ENABLE (0x80U) /* IRQ7 digital filter is enabled */\r
+\r
+/*\r
+ IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0)\r
+*/\r
+/* IRQn Digital Filter Sampling Clock (FCLKSELn) */\r
+#define _0000_ICU_IRQ0_FILTER_PCLK (0x0000U) /* IRQ0 sample clock is run at every PCLK cycle */\r
+#define _0001_ICU_IRQ0_FILTER_PCLK_8 (0x0001U) /* IRQ0 sample clock is run at every PCLK/8 cycle */\r
+#define _0002_ICU_IRQ0_FILTER_PCLK_32 (0x0002U) /* IRQ0 sample clock is run at every PCLK/32 cycle */\r
+#define _0003_ICU_IRQ0_FILTER_PCLK_64 (0x0003U) /* IRQ0 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ1_FILTER_PCLK (0x0000U) /* IRQ1 sample clock is run at every PCLK cycle */\r
+#define _0004_ICU_IRQ1_FILTER_PCLK_8 (0x0004U) /* IRQ1 sample clock is run at every PCLK/8 cycle */\r
+#define _0008_ICU_IRQ1_FILTER_PCLK_32 (0x0008U) /* IRQ1 sample clock is run at every PCLK/32 cycle */\r
+#define _000C_ICU_IRQ1_FILTER_PCLK_64 (0x000CU) /* IRQ1 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ2_FILTER_PCLK (0x0000U) /* IRQ2 sample clock is run at every PCLK cycle */\r
+#define _0010_ICU_IRQ2_FILTER_PCLK_8 (0x0010U) /* IRQ2 sample clock is run at every PCLK/8 cycle */\r
+#define _0020_ICU_IRQ2_FILTER_PCLK_32 (0x0020U) /* IRQ2 sample clock is run at every PCLK/32 cycle */\r
+#define _0030_ICU_IRQ2_FILTER_PCLK_64 (0x0030U) /* IRQ2 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ3_FILTER_PCLK (0x0000U) /* IRQ3 sample clock is run at every PCLK cycle */\r
+#define _0040_ICU_IRQ3_FILTER_PCLK_8 (0x0040U) /* IRQ3 sample clock is run at every PCLK/8 cycle */\r
+#define _0080_ICU_IRQ3_FILTER_PCLK_32 (0x0080U) /* IRQ3 sample clock is run at every PCLK/32 cycle */\r
+#define _00C0_ICU_IRQ3_FILTER_PCLK_64 (0x00C0U) /* IRQ3 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ4_FILTER_PCLK (0x0000U) /* IRQ4 sample clock is run at every PCLK cycle */\r
+#define _0100_ICU_IRQ4_FILTER_PCLK_8 (0x0100U) /* IRQ4 sample clock is run at every PCLK/8 cycle */\r
+#define _0200_ICU_IRQ4_FILTER_PCLK_32 (0x0200U) /* IRQ4 sample clock is run at every PCLK/32 cycle */\r
+#define _0300_ICU_IRQ4_FILTER_PCLK_64 (0x0300U) /* IRQ4 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ5_FILTER_PCLK (0x0000U) /* IRQ5 sample clock is run at every PCLK cycle */\r
+#define _0400_ICU_IRQ5_FILTER_PCLK_8 (0x0400U) /* IRQ5 sample clock is run at every PCLK/8 cycle */\r
+#define _0800_ICU_IRQ5_FILTER_PCLK_32 (0x0800U) /* IRQ5 sample clock is run at every PCLK/32 cycle */\r
+#define _0C00_ICU_IRQ5_FILTER_PCLK_64 (0x0C00U) /* IRQ5 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ6_FILTER_PCLK (0x0000U) /* IRQ6 sample clock is run at every PCLK cycle */\r
+#define _1000_ICU_IRQ6_FILTER_PCLK_8 (0x1000U) /* IRQ6 sample clock is run at every PCLK/8 cycle */\r
+#define _2000_ICU_IRQ6_FILTER_PCLK_32 (0x2000U) /* IRQ6 sample clock is run at every PCLK/32 cycle */\r
+#define _3000_ICU_IRQ6_FILTER_PCLK_64 (0x3000U) /* IRQ6 sample clock is run at every PCLK/64 cycle */\r
+#define _0000_ICU_IRQ7_FILTER_PCLK (0x0000U) /* IRQ7 sample clock is run at every PCLK cycle */\r
+#define _4000_ICU_IRQ7_FILTER_PCLK_8 (0x4000U) /* IRQ7 sample clock is run at every PCLK/8 cycle */\r
+#define _8000_ICU_IRQ7_FILTER_PCLK_32 (0x8000U) /* IRQ7 sample clock is run at every PCLK/32 cycle */\r
+#define _C000_ICU_IRQ7_FILTER_PCLK_64 (0xC000U) /* IRQ7 sample clock is run at every PCLK/64 cycle */\r
+\r
+/*\r
+ NMI Pin Interrupt Control Register (NMICR)\r
+*/\r
+/* NMI Digital Filter Sampling Clock (NMIMD) */\r
+#define _00_ICU_NMI_EDGE_FALLING (0x00U) /* Falling edge */\r
+#define _08_ICU_NMI_EDGE_RISING (0x08U) /* Rising edge */\r
+\r
+/*\r
+ NMI Pin Digital Filter Setting Register (NMIFLTC)\r
+*/\r
+/* NMI Digital Filter Sampling Clock (NFCLKSEL[1:0]) */\r
+#define _00_ICU_NMI_FILTER_PCLK (0x00U) /* NMI sample clock is run at every PCLK cycle */\r
+#define _01_ICU_NMI_FILTER_PCLK_8 (0x01U) /* NMI sample clock is run at every PCLK/8 cycle */\r
+#define _02_ICU_NMI_FILTER_PCLK_32 (0x02U) /* NMI sample clock is run at every PCLK/32 cycle */\r
+#define _03_ICU_NMI_FILTER_PCLK_64 (0x03U) /* NMI sample clock is run at every PCLK/64 cycle */\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_ICU_Create(void);\r
+void R_ICU_IRQ1_Start(void);\r
+void R_ICU_IRQ1_Stop(void);\r
+void R_ICU_IRQ4_Start(void);\r
+void R_ICU_IRQ4_Stop(void);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+\r
+/* Function prototypes for detecting and setting the edge trigger of ICU_IRQ */\r
+uint8_t R_ICU_IRQIsFallingEdge(const uint8_t irq_no);\r
+void R_ICU_IRQSetFallingEdge(const uint8_t irq_no, const uint8_t set_f_edge);\r
+void R_ICU_IRQSetRisingEdge(const uint8_t irq_no, const uint8_t set_r_edge);\r
+\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_interrupt_handlers.h\r
+* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : GCCRX\r
+* Description : This file declares interrupt handlers.\r
+* Creation Date: 23/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef INTERRUPT_HANDLERS_H\r
+#define INTERRUPT_HANDLERS_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+\r
+/* Undefined */\r
+void r_undefined_exception(void) __attribute__ ((interrupt));\r
+\r
+/* Access Exception */\r
+void r_access_exception(void) __attribute__ ((interrupt));\r
+\r
+/* Privileged Instruction Exception */\r
+void r_privileged_exception(void) __attribute__ ((interrupt));\r
+\r
+/* Floating Point Exception */\r
+void r_floatingpoint_exception(void) __attribute__ ((interrupt));\r
+\r
+/* NMI */\r
+void r_nmi_exception(void) __attribute__ ((interrupt));\r
+\r
+/* BRK */\r
+void r_brk_exception(void) __attribute__ ((interrupt));\r
+\r
+/* Hardware Vectors */\r
+void PowerON_Reset(void) __attribute__ ((interrupt));\r
+\r
+/* Idle Vectors */\r
+void r_undefined_exception(void) __attribute__ ((interrupt));\r
+void r_reserved_exception(void) __attribute__ ((interrupt));\r
+\r
+#endif
\ No newline at end of file
* DISCLAIMER\r
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
+* applicable laws, including copyright laws.\r
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability\r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
* following link:\r
* http://www.renesas.com/disclaimer\r
*\r
* File Name : r_cg_macrodriver.h\r
* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
* Device(s) : R5F52318AxFP\r
-* Tool-Chain : CCRX\r
+* Tool-Chain : GCCRX\r
* Description : This file implements general head file.\r
* Creation Date: 23/09/2015\r
***********************************************************************************************************************/\r
typedef signed long int32_t;\r
typedef unsigned long uint32_t;\r
\r
- typedef signed char int_least8_t;\r
- typedef signed short int_least16_t;\r
- typedef signed long int_least32_t;\r
- typedef unsigned char uint_least8_t;\r
- typedef unsigned short uint_least16_t;\r
- typedef unsigned long uint_least32_t;\r
+ typedef signed char int_least8_t;\r
+ typedef signed short int_least16_t;\r
+ typedef signed long int_least32_t;\r
+ typedef unsigned char uint_least8_t;\r
+ typedef unsigned short uint_least16_t;\r
+ typedef unsigned long uint_least32_t;\r
#endif\r
\r
typedef unsigned short MD_STATUS;\r
#define __TYPEDEF__\r
#endif\r
\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-void HardwareSetup(void);\r
-void R_Systeminit(void);\r
\r
-#endif
\ No newline at end of file
+\r
+#endif\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_port.c\r
+* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for Port module.\r
+* Creation Date: 2015/08/17\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_port.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_PORT_Create\r
+* Description : This function initializes the Port I/O.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_PORT_Create(void)\r
+{\r
+ PORT1.PODR.BYTE = _80_Pm7_OUTPUT_1;\r
+ PORT3.PODR.BYTE = _08_Pm3_OUTPUT_1;\r
+ PORT5.PODR.BYTE = _01_Pm0_OUTPUT_1 | _02_Pm1_OUTPUT_1 | _04_Pm2_OUTPUT_1;\r
+ PORTE.PODR.BYTE = _08_Pm3_OUTPUT_1 | _80_Pm7_OUTPUT_1;\r
+ PORT1.PDR.BYTE = _80_Pm7_MODE_OUTPUT;\r
+ PORT3.PDR.BYTE = _08_Pm3_MODE_OUTPUT;\r
+ PORT5.PDR.BYTE = _01_Pm0_MODE_OUTPUT | _02_Pm1_MODE_OUTPUT | _04_Pm2_MODE_OUTPUT;\r
+ PORTE.PDR.BYTE = _08_Pm3_MODE_OUTPUT | _10_Pm4_MODE_OUTPUT | _80_Pm7_MODE_OUTPUT;\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_port.h\r
+* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015]\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for Port module.\r
+* Creation Date: 2015/08/17\r
+***********************************************************************************************************************/\r
+#ifndef PORT_H\r
+#define PORT_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+/*\r
+ Port Direction Register (PDR)\r
+*/\r
+/* Pmn Direction Control (B7 - B0) */\r
+#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */\r
+#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */\r
+#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */\r
+#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */\r
+#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */\r
+#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */\r
+#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */\r
+#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */\r
+#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */\r
+#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */\r
+#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */\r
+#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */\r
+#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */\r
+#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */\r
+#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */\r
+#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */\r
+#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */\r
+#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */\r
+#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */\r
+#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */\r
+#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */\r
+#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */\r
+#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */\r
+#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */\r
+\r
+/*\r
+ Port Output Data Register (PODR)\r
+*/\r
+/* Pmn Output Data Store (B7 - B0) */\r
+#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */\r
+#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */\r
+#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */\r
+#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */\r
+#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */\r
+#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */\r
+#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */\r
+#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */\r
+#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */\r
+#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */\r
+#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */\r
+#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */\r
+#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */\r
+#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */\r
+#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */\r
+#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */\r
+\r
+/*\r
+ Open Drain Control Register 0 (ODR0)\r
+*/\r
+/* Pmn Output Type Select (Pm0 to Pm3) */\r
+#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
+#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
+#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* PMOS open-drain output, for PE1 only*/\r
+#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
+#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
+\r
+/*\r
+ Open Drain Control Register 1 (ODR1)\r
+*/\r
+/* Pmn Output Type Select (Pm4 to Pm7) */\r
+#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
+#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
+#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
+#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
+\r
+/*\r
+ Pull-Up Control Register (PCR)\r
+*/\r
+/* Pmn Input Pull-Up Resistor Control (B7 - B0) */\r
+#define _00_Pm0_PULLUP_OFF (0x00U) /* Pm0 pull-up resistor not connected */\r
+#define _01_Pm0_PULLUP_ON (0x01U) /* Pm0 pull-up resistor connected */\r
+#define _00_Pm1_PULLUP_OFF (0x00U) /* Pm1 pull-up resistor not connected */\r
+#define _02_Pm1_PULLUP_ON (0x02U) /* Pm1 pull-up resistor connected */\r
+#define _00_Pm2_PULLUP_OFF (0x00U) /* Pm2 Pull-up resistor not connected */\r
+#define _04_Pm2_PULLUP_ON (0x04U) /* Pm2 pull-up resistor connected */\r
+#define _00_Pm3_PULLUP_OFF (0x00U) /* Pm3 pull-up resistor not connected */\r
+#define _08_Pm3_PULLUP_ON (0x08U) /* Pm3 pull-up resistor connected */\r
+#define _00_Pm4_PULLUP_OFF (0x00U) /* Pm4 pull-up resistor not connected */\r
+#define _10_Pm4_PULLUP_ON (0x10U) /* Pm4 pull-up resistor connected */\r
+#define _00_Pm5_PULLUP_OFF (0x00U) /* Pm5 pull-up resistor not connected */\r
+#define _20_Pm5_PULLUP_ON (0x20U) /* Pm5 pull-up resistor connected */\r
+#define _00_Pm6_PULLUP_OFF (0x00U) /* Pm6 pull-up resistor not connected */\r
+#define _40_Pm6_PULLUP_ON (0x40U) /* Pm6 pull-up resistor connected */\r
+#define _00_Pm7_PULLUP_OFF (0x00U) /* Pm7 pull-up resistor not connected */\r
+#define _80_Pm7_PULLUP_ON (0x80U) /* Pm7 pull-up resistor connected */\r
+\r
+/*\r
+ Drive Capacity Control Register (DSCR)\r
+*/\r
+/* Pmn Drive Capacity Control (B7 - B0) */\r
+#define _00_Pm0_HIDRV_OFF (0x00U) /* Pm0 Normal drive output */\r
+#define _01_Pm0_HIDRV_ON (0x01U) /* Pm0 High-drive output */\r
+#define _00_Pm1_HIDRV_OFF (0x00U) /* Pm1 Normal drive output */\r
+#define _02_Pm1_HIDRV_ON (0x02U) /* Pm1 High-drive output */\r
+#define _00_Pm2_HIDRV_OFF (0x00U) /* Pm2 Normal drive output */\r
+#define _04_Pm2_HIDRV_ON (0x04U) /* Pm2 High-drive output */\r
+#define _00_Pm3_HIDRV_OFF (0x00U) /* Pm3 Normal drive output */\r
+#define _08_Pm3_HIDRV_ON (0x08U) /* Pm3 High-drive output */\r
+#define _00_Pm4_HIDRV_OFF (0x00U) /* Pm4 Normal drive output */\r
+#define _10_Pm4_HIDRV_ON (0x10U) /* Pm4 High-drive output */\r
+#define _00_Pm5_HIDRV_OFF (0x00U) /* Pm5 Normal drive output */\r
+#define _20_Pm5_HIDRV_ON (0x20U) /* Pm5 High-drive output */\r
+#define _00_Pm6_HIDRV_OFF (0x00U) /* Pm6 Normal drive output */\r
+#define _40_Pm6_HIDRV_ON (0x40U) /* Pm6 High-drive output */\r
+#define _00_Pm7_HIDRV_OFF (0x00U) /* Pm7 Normal drive output */\r
+#define _80_Pm7_HIDRV_ON (0x80U) /* Pm7 High-drive output */\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_PORT_Create(void);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
* Device(s) : R5F52318AxFP\r
* Tool-Chain : CCRX\r
* Description : This file includes user definition.\r
-* Creation Date: 23/09/2015\r
+* Creation Date: 2015/08/17\r
***********************************************************************************************************************/\r
#ifndef _USER_DEF_H\r
#define _USER_DEF_H\r
#define FAST_INTERRUPT_VECTOR 0\r
\r
/* Start user code for function. Do not edit comment generated here */\r
+\r
+#define TRUE (1)\r
+#define FALSE (0)\r
+\r
+extern volatile uint8_t g_adc_trigger;\r
+\r
/* End user code. Do not edit comment generated here */\r
#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No \r
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all \r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, \r
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM \r
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES \r
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS \r
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of \r
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer \r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. \r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : rskrx231def.h\r
+* Device(s) : R5F52318AxFP\r
+* Tool-Chain : CCRX\r
+* H/W Platform : RSKRX231\r
+* Description : Defines macros relating to the RSKRX231 user LEDs and switches\r
+***********************************************************************************************************************/\r
+/**********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 01.06.2015 1.00 First Release\r
+***********************************************************************************************************************/\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+#ifndef RSKRX231_H\r
+#define RSKRX231_H\r
+\r
+\r
+/* General Values */\r
+#define LED_ON (0)\r
+#define LED_OFF (1)\r
+#define SET_BIT_HIGH (1)\r
+#define SET_BIT_LOW (0)\r
+#define SET_BYTE_HIGH (0xFF)\r
+#define SET_BYTE_LOW (0x00)\r
+\r
+/* Switches */\r
+#define SW1 (PORT3.PIDR.BIT.B1)\r
+#define SW2 (PORT3.PIDR.BIT.B4)\r
+#define SW3 (PORT0.PIDR.BIT.B7)\r
+\r
+/* LED port settings */\r
+#define LED0 (PORT1.PODR.BIT.B7)\r
+#define LED1 (PORT5.PODR.BIT.B0)\r
+#define LED2 (PORT5.PODR.BIT.B1)\r
+#define LED3 (PORT5.PODR.BIT.B2)\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Exported global variables\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Exported global functions (to be accessed by other files)\r
+***********************************************************************************************************************/\r
+\r
+#endif\r
+\r
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