git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77
  78 #define DRVNAME "it87"
  79
  80 /* Necessary API not (yet) exported in upstream kernel */
  81 /* #define __IT87_USE_ACPI_MUTEX */
  82
  83 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  84              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  85              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  86              it8655, it8665, it8686 };
  87
  88 static unsigned short force_id;
  89 module_param(force_id, ushort, 0);
  90 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  91
  92 static struct platform_device *it87_pdev[2];
  93 #ifdef __IT87_USE_ACPI_MUTEX
  94 static acpi_handle it87_acpi_sio_handle;
  95 static char *it87_acpi_sio_mutex;
  96 #endif
  97
  98 #define REG_2E  0x2e    /* The register to read/write */
  99 #define REG_4E  0x4e    /* Secondary register to read/write */
 100
 101 #define DEV     0x07    /* Register: Logical device select */
 102 #define PME     0x04    /* The device with the fan registers in it */
 103
 104 /* The device with the IT8718F/IT8720F VID value in it */
 105 #define GPIO    0x07
 106
 107 #define DEVID   0x20    /* Register: Device ID */
 108 #define DEVREV  0x22    /* Register: Device Revision */
 109
 110 static inline void __superio_enter(int ioreg)
 111 {
 112         outb(0x87, ioreg);
 113         outb(0x01, ioreg);
 114         outb(0x55, ioreg);
 115         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 116 }
 117
 118 static inline int superio_inb(int ioreg, int reg)
 119 {
 120         int val;
 121
 122         outb(reg, ioreg);
 123         val = inb(ioreg + 1);
 124
 125         return val;
 126 }
 127
 128 static inline void superio_outb(int ioreg, int reg, int val)
 129 {
 130         outb(reg, ioreg);
 131         outb(val, ioreg + 1);
 132 }
 133
 134 static int superio_inw(int ioreg, int reg)
 135 {
 136         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 137 }
 138
 139 static inline void superio_select(int ioreg, int ldn)
 140 {
 141         outb(DEV, ioreg);
 142         outb(ldn, ioreg + 1);
 143 }
 144
 145 static inline int superio_enter(int ioreg)
 146 {
 147 #ifdef __IT87_USE_ACPI_MUTEX
 148         if (it87_acpi_sio_mutex) {
 149                 acpi_status status;
 150
 151                 status = acpi_acquire_mutex(NULL, it87_acpi_sio_mutex, 0x10);
 152                 if (ACPI_FAILURE(status)) {
 153                         pr_err("Failed to acquire ACPI mutex\n");
 154                         return -EBUSY;
 155                 }
 156         }
 157 #endif
 158         /*
 159          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 160          */
 161         if (!request_muxed_region(ioreg, 2, DRVNAME))
 162                 goto error;
 163
 164         __superio_enter(ioreg);
 165         return 0;
 166
 167 error:
 168 #ifdef __IT87_USE_ACPI_MUTEX
 169         if (it87_acpi_sio_mutex)
 170                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 171 #endif
 172         return -EBUSY;
 173 }
 174
 175 static inline void superio_exit(int ioreg, bool doexit)
 176 {
 177         if (doexit) {
 178                 outb(0x02, ioreg);
 179                 outb(0x02, ioreg + 1);
 180         }
 181         release_region(ioreg, 2);
 182 #ifdef __IT87_USE_ACPI_MUTEX
 183         if (it87_acpi_sio_mutex)
 184                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 185 #endif
 186 }
 187
 188 /* Logical device 4 registers */
 189 #define IT8712F_DEVID 0x8712
 190 #define IT8705F_DEVID 0x8705
 191 #define IT8716F_DEVID 0x8716
 192 #define IT8718F_DEVID 0x8718
 193 #define IT8720F_DEVID 0x8720
 194 #define IT8721F_DEVID 0x8721
 195 #define IT8726F_DEVID 0x8726
 196 #define IT8728F_DEVID 0x8728
 197 #define IT8732F_DEVID 0x8732
 198 #define IT8792E_DEVID 0x8733
 199 #define IT8771E_DEVID 0x8771
 200 #define IT8772E_DEVID 0x8772
 201 #define IT8781F_DEVID 0x8781
 202 #define IT8782F_DEVID 0x8782
 203 #define IT8783E_DEVID 0x8783
 204 #define IT8786E_DEVID 0x8786
 205 #define IT8790E_DEVID 0x8790
 206 #define IT8603E_DEVID 0x8603
 207 #define IT8607E_DEVID 0x8607
 208 #define IT8613E_DEVID 0x8613
 209 #define IT8620E_DEVID 0x8620
 210 #define IT8622E_DEVID 0x8622
 211 #define IT8623E_DEVID 0x8623
 212 #define IT8625E_DEVID 0x8625
 213 #define IT8628E_DEVID 0x8628
 214 #define IT8655E_DEVID 0x8655
 215 #define IT8665E_DEVID 0x8665
 216 #define IT8686E_DEVID 0x8686
 217 #define IT87_ACT_REG  0x30
 218 #define IT87_BASE_REG 0x60
 219
 220 /* Logical device 7 registers (IT8712F and later) */
 221 #define IT87_SIO_GPIO1_REG      0x25
 222 #define IT87_SIO_GPIO2_REG      0x26
 223 #define IT87_SIO_GPIO3_REG      0x27
 224 #define IT87_SIO_GPIO4_REG      0x28
 225 #define IT87_SIO_GPIO5_REG      0x29
 226 #define IT87_SIO_GPIO9_REG      0xd3
 227 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 228 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 229 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 230 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 231 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 232 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 233
 234 /* Update battery voltage after every reading if true */
 235 static bool update_vbat;
 236
 237 /* Not all BIOSes properly configure the PWM registers */
 238 static bool fix_pwm_polarity;
 239
 240 /* Many IT87 constants specified below */
 241
 242 /* Length of ISA address segment */
 243 #define IT87_EXTENT 8
 244
 245 /* Length of ISA address segment for Environmental Controller */
 246 #define IT87_EC_EXTENT 2
 247
 248 /* Offset of EC registers from ISA base address */
 249 #define IT87_EC_OFFSET 5
 250
 251 /* Where are the ISA address/data registers relative to the EC base address */
 252 #define IT87_ADDR_REG_OFFSET 0
 253 #define IT87_DATA_REG_OFFSET 1
 254
 255 /*----- The IT87 registers -----*/
 256
 257 #define IT87_REG_CONFIG        0x00
 258
 259 #define IT87_REG_ALARM1        0x01
 260 #define IT87_REG_ALARM2        0x02
 261 #define IT87_REG_ALARM3        0x03
 262
 263 #define IT87_REG_BANK           0x06
 264
 265 /*
 266  * The IT8718F and IT8720F have the VID value in a different register, in
 267  * Super-I/O configuration space.
 268  */
 269 #define IT87_REG_VID           0x0a
 270 /*
 271  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 272  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 273  * mode.
 274  */
 275 #define IT87_REG_FAN_DIV       0x0b
 276 #define IT87_REG_FAN_16BIT     0x0c
 277
 278 /*
 279  * Monitors:
 280  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 281  * - up to 6 temp (1 to 6)
 282  * - up to 6 fan (1 to 6)
 283  */
 284
 285 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 286 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 287 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 288 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 289
 290 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 291 static const u8 IT87_REG_FAN_MIN_8665[] =
 292                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 293 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 294 static const u8 IT87_REG_FANX_MIN_8665[] =
 295                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 296
 297 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 298
 299 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 300
 301 #define IT87_REG_FAN_MAIN_CTRL 0x13
 302 #define IT87_REG_FAN_CTL       0x14
 303
 304 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 305 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 306
 307 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 308
 309 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 310                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 311
 312 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 313
 314 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 315 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 316
 317 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 318 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 319
 320 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 321                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 322 static const u8 IT87_REG_TEMP_LOW_8686[] =
 323                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 324
 325 #define IT87_REG_VIN_ENABLE    0x50
 326 #define IT87_REG_TEMP_ENABLE   0x51
 327 #define IT87_REG_TEMP_EXTRA    0x55
 328 #define IT87_REG_BEEP_ENABLE   0x5c
 329
 330 #define IT87_REG_CHIPID        0x58
 331
 332 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 333
 334 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 335 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 336
 337 #define IT87_REG_TEMP456_ENABLE 0x77
 338
 339 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 340 #define IT87_REG_TEMP_SRC2      0x23d
 341
 342 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 343 #define NUM_VIN_LIMIT           8
 344 #define NUM_TEMP                6
 345 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 346 #define NUM_FAN_DIV             3
 347 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 348 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 349
 350 struct it87_devices {
 351         const char *name;
 352         const char * const suffix;
 353         u32 features;
 354         u8 num_temp_limit;
 355         u8 num_temp_offset;
 356         u8 peci_mask;
 357         u8 old_peci_mask;
 358 };
 359
 360 #define FEAT_12MV_ADC           BIT(0)
 361 #define FEAT_NEWER_AUTOPWM      BIT(1)
 362 #define FEAT_OLD_AUTOPWM        BIT(2)
 363 #define FEAT_16BIT_FANS         BIT(3)
 364 #define FEAT_TEMP_PECI          BIT(5)
 365 #define FEAT_TEMP_OLD_PECI      BIT(6)
 366 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 367 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 368 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 369 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 370 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 371 #define FEAT_10_9MV_ADC         BIT(12)
 372 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 373 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 374 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 375 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 376 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 377 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 378 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 379 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 380 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 381 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 382 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 383 #define FEAT_11MV_ADC           BIT(24)
 384 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 385
 386 static const struct it87_devices it87_devices[] = {
 387         [it87] = {
 388                 .name = "it87",
 389                 .suffix = "F",
 390                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 391                                                 /* may need to overwrite */
 392                 .num_temp_limit = 3,
 393                 .num_temp_offset = 0,
 394         },
 395         [it8712] = {
 396                 .name = "it8712",
 397                 .suffix = "F",
 398                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 399                                                 /* may need to overwrite */
 400                 .num_temp_limit = 3,
 401                 .num_temp_offset = 0,
 402         },
 403         [it8716] = {
 404                 .name = "it8716",
 405                 .suffix = "F",
 406                 .features = FEAT_16BIT_FANS | FEAT_VID
 407                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 408                   | FEAT_FANCTL_ONOFF,
 409                 .num_temp_limit = 3,
 410                 .num_temp_offset = 3,
 411         },
 412         [it8718] = {
 413                 .name = "it8718",
 414                 .suffix = "F",
 415                 .features = FEAT_16BIT_FANS | FEAT_VID
 416                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 417                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 418                 .num_temp_limit = 3,
 419                 .num_temp_offset = 3,
 420                 .old_peci_mask = 0x4,
 421         },
 422         [it8720] = {
 423                 .name = "it8720",
 424                 .suffix = "F",
 425                 .features = FEAT_16BIT_FANS | FEAT_VID
 426                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 427                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 428                 .num_temp_limit = 3,
 429                 .num_temp_offset = 3,
 430                 .old_peci_mask = 0x4,
 431         },
 432         [it8721] = {
 433                 .name = "it8721",
 434                 .suffix = "F",
 435                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 436                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 437                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 438                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 439                 .num_temp_limit = 3,
 440                 .num_temp_offset = 3,
 441                 .peci_mask = 0x05,
 442                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 443         },
 444         [it8728] = {
 445                 .name = "it8728",
 446                 .suffix = "F",
 447                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 448                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 449                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 450                   | FEAT_FANCTL_ONOFF,
 451                 .num_temp_limit = 6,
 452                 .num_temp_offset = 3,
 453                 .peci_mask = 0x07,
 454         },
 455         [it8732] = {
 456                 .name = "it8732",
 457                 .suffix = "F",
 458                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 459                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 460                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 461                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 462                 .num_temp_limit = 3,
 463                 .num_temp_offset = 3,
 464                 .peci_mask = 0x07,
 465                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 466         },
 467         [it8771] = {
 468                 .name = "it8771",
 469                 .suffix = "E",
 470                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 471                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 472                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 473                                 /* PECI: guesswork */
 474                                 /* 12mV ADC (OHM) */
 475                                 /* 16 bit fans (OHM) */
 476                                 /* three fans, always 16 bit (guesswork) */
 477                 .num_temp_limit = 3,
 478                 .num_temp_offset = 3,
 479                 .peci_mask = 0x07,
 480         },
 481         [it8772] = {
 482                 .name = "it8772",
 483                 .suffix = "E",
 484                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 485                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 486                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 487                                 /* PECI (coreboot) */
 488                                 /* 12mV ADC (HWSensors4, OHM) */
 489                                 /* 16 bit fans (HWSensors4, OHM) */
 490                                 /* three fans, always 16 bit (datasheet) */
 491                 .num_temp_limit = 3,
 492                 .num_temp_offset = 3,
 493                 .peci_mask = 0x07,
 494         },
 495         [it8781] = {
 496                 .name = "it8781",
 497                 .suffix = "F",
 498                 .features = FEAT_16BIT_FANS
 499                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 500                   | FEAT_FANCTL_ONOFF,
 501                 .num_temp_limit = 3,
 502                 .num_temp_offset = 3,
 503                 .old_peci_mask = 0x4,
 504         },
 505         [it8782] = {
 506                 .name = "it8782",
 507                 .suffix = "F",
 508                 .features = FEAT_16BIT_FANS
 509                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 510                   | FEAT_FANCTL_ONOFF,
 511                 .num_temp_limit = 3,
 512                 .num_temp_offset = 3,
 513                 .old_peci_mask = 0x4,
 514         },
 515         [it8783] = {
 516                 .name = "it8783",
 517                 .suffix = "E/F",
 518                 .features = FEAT_16BIT_FANS
 519                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 520                   | FEAT_FANCTL_ONOFF,
 521                 .num_temp_limit = 3,
 522                 .num_temp_offset = 3,
 523                 .old_peci_mask = 0x4,
 524         },
 525         [it8786] = {
 526                 .name = "it8786",
 527                 .suffix = "E",
 528                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 529                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 530                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 531                 .num_temp_limit = 3,
 532                 .num_temp_offset = 3,
 533                 .peci_mask = 0x07,
 534         },
 535         [it8790] = {
 536                 .name = "it8790",
 537                 .suffix = "E",
 538                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 539                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 540                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 541                 .num_temp_limit = 3,
 542                 .num_temp_offset = 3,
 543                 .peci_mask = 0x07,
 544         },
 545         [it8792] = {
 546                 .name = "it8792",
 547                 .suffix = "E",
 548                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 549                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 550                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 551                 .num_temp_limit = 3,
 552                 .num_temp_offset = 3,
 553                 .peci_mask = 0x07,
 554         },
 555         [it8603] = {
 556                 .name = "it8603",
 557                 .suffix = "E",
 558                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 559                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 560                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 561                 .num_temp_limit = 3,
 562                 .num_temp_offset = 3,
 563                 .peci_mask = 0x07,
 564         },
 565         [it8607] = {
 566                 .name = "it8607",
 567                 .suffix = "E",
 568                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 569                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 570                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 571                   | FEAT_FANCTL_ONOFF,
 572                 .num_temp_limit = 3,
 573                 .num_temp_offset = 3,
 574                 .peci_mask = 0x07,
 575         },
 576         [it8613] = {
 577                 .name = "it8613",
 578                 .suffix = "E",
 579                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 580                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 581                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 582                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 583                 .num_temp_limit = 6,
 584                 .num_temp_offset = 6,
 585                 .peci_mask = 0x07,
 586         },
 587         [it8620] = {
 588                 .name = "it8620",
 589                 .suffix = "E",
 590                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 591                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 592                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 593                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 594                   | FEAT_FANCTL_ONOFF,
 595                 .num_temp_limit = 3,
 596                 .num_temp_offset = 3,
 597                 .peci_mask = 0x07,
 598         },
 599         [it8622] = {
 600                 .name = "it8622",
 601                 .suffix = "E",
 602                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 603                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 604                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 605                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 606                 .num_temp_limit = 3,
 607                 .num_temp_offset = 3,
 608                 .peci_mask = 0x07,
 609         },
 610         [it8625] = {
 611                 .name = "it8625",
 612                 .suffix = "E",
 613                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 614                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 615                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 616                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 617                 .num_temp_limit = 6,
 618                 .num_temp_offset = 6,
 619         },
 620         [it8628] = {
 621                 .name = "it8628",
 622                 .suffix = "E",
 623                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 624                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 625                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 626                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 627                   | FEAT_FANCTL_ONOFF,
 628                 .num_temp_limit = 6,
 629                 .num_temp_offset = 3,
 630                 .peci_mask = 0x07,
 631         },
 632         [it8655] = {
 633                 .name = "it8655",
 634                 .suffix = "E",
 635                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 636                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 637                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 638                 .num_temp_limit = 6,
 639                 .num_temp_offset = 6,
 640         },
 641         [it8665] = {
 642                 .name = "it8665",
 643                 .suffix = "E",
 644                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 645                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 646                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 647                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 648                 .num_temp_limit = 6,
 649                 .num_temp_offset = 6,
 650         },
 651         [it8686] = {
 652                 .name = "it8686",
 653                 .suffix = "E",
 654                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 655                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 656                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 657                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 658                 .num_temp_limit = 6,
 659                 .num_temp_offset = 6,
 660         },
 661 };
 662
 663 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 664 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 665 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 666 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 667 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 668 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 669                                  ((data)->peci_mask & BIT(nr)))
 670 #define has_temp_old_peci(data, nr) \
 671                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 672                                  ((data)->old_peci_mask & BIT(nr)))
 673 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 674 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 675                                                      FEAT_SIX_FANS))
 676 #define has_vid(data)           ((data)->features & FEAT_VID)
 677 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 678 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 679 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 680 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 681                                                      | FEAT_SIX_PWM))
 682 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 683 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 684 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 685 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 686 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 687                                                      FEAT_FIVE_FANS | \
 688                                                      FEAT_SIX_FANS))
 689 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 690                                                      FEAT_FIVE_PWM \
 691                                                      | FEAT_SIX_PWM))
 692 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 693 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 694 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 695 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 696 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 697
 698 struct it87_sio_data {
 699         enum chips type;
 700         /* Values read from Super-I/O config space */
 701         u8 revision;
 702         u8 vid_value;
 703         u8 beep_pin;
 704         u8 internal;    /* Internal sensors can be labeled */
 705         /* Features skipped based on config or DMI */
 706         u16 skip_in;
 707         u8 skip_vid;
 708         u8 skip_fan;
 709         u8 skip_pwm;
 710         u8 skip_temp;
 711 };
 712
 713 /*
 714  * For each registered chip, we need to keep some data in memory.
 715  * The structure is dynamically allocated.
 716  */
 717 struct it87_data {
 718         const struct attribute_group *groups[7];
 719         enum chips type;
 720         u32 features;
 721         u8 bank;
 722         u8 peci_mask;
 723         u8 old_peci_mask;
 724
 725         const u8 *REG_FAN;
 726         const u8 *REG_FANX;
 727         const u8 *REG_FAN_MIN;
 728         const u8 *REG_FANX_MIN;
 729
 730         const u8 *REG_PWM;
 731
 732         const u8 *REG_TEMP_OFFSET;
 733         const u8 *REG_TEMP_LOW;
 734         const u8 *REG_TEMP_HIGH;
 735
 736         unsigned short addr;
 737         const char *name;
 738         struct mutex update_lock;
 739         char valid;             /* !=0 if following fields are valid */
 740         unsigned long last_updated;     /* In jiffies */
 741
 742         u16 in_scaled;          /* Internal voltage sensors are scaled */
 743         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 744         u16 has_in;             /* Bitfield, voltage sensors enabled */
 745         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 746         u8 has_fan;             /* Bitfield, fans enabled */
 747         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 748         u8 has_temp;            /* Bitfield, temp sensors enabled */
 749         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 750         u8 num_temp_limit;      /* Number of temperature limit registers */
 751         u8 num_temp_offset;     /* Number of temperature offset registers */
 752         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 753         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 754         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 755         bool has_vid;           /* True if VID supported */
 756         u8 vid;                 /* Register encoding, combined */
 757         u8 vrm;
 758         u32 alarms;             /* Register encoding, combined */
 759         bool has_beep;          /* true if beep supported */
 760         u8 beeps;               /* Register encoding */
 761         u8 fan_main_ctrl;       /* Register value */
 762         u8 fan_ctl;             /* Register value */
 763
 764         /*
 765          * The following 3 arrays correspond to the same registers up to
 766          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 767          * 7, and we want to preserve settings on mode changes, so we have
 768          * to track all values separately.
 769          * Starting with the IT8721F, the manual PWM duty cycles are stored
 770          * in separate registers (8-bit values), so the separate tracking
 771          * is no longer needed, but it is still done to keep the driver
 772          * simple.
 773          */
 774         u8 has_pwm;             /* Bitfield, pwm control enabled */
 775         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 776         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 777         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 778
 779         /* Automatic fan speed control registers */
 780         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 781         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 782 };
 783
 784 static int adc_lsb(const struct it87_data *data, int nr)
 785 {
 786         int lsb;
 787
 788         if (has_12mv_adc(data))
 789                 lsb = 120;
 790         else if (has_10_9mv_adc(data))
 791                 lsb = 109;
 792         else if (has_11mv_adc(data))
 793                 lsb = 110;
 794         else
 795                 lsb = 160;
 796         if (data->in_scaled & BIT(nr))
 797                 lsb <<= 1;
 798         return lsb;
 799 }
 800
 801 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 802 {
 803         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 804         return clamp_val(val, 0, 255);
 805 }
 806
 807 static int in_from_reg(const struct it87_data *data, int nr, int val)
 808 {
 809         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 810 }
 811
 812 static inline u8 FAN_TO_REG(long rpm, int div)
 813 {
 814         if (rpm == 0)
 815                 return 255;
 816         rpm = clamp_val(rpm, 1, 1000000);
 817         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 818 }
 819
 820 static inline u16 FAN16_TO_REG(long rpm)
 821 {
 822         if (rpm == 0)
 823                 return 0xffff;
 824         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 825 }
 826
 827 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 828                                 1350000 / ((val) * (div)))
 829 /* The divider is fixed to 2 in 16-bit mode */
 830 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 831                              1350000 / ((val) * 2))
 832
 833 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 834                                     ((val) + 500) / 1000), -128, 127))
 835 #define TEMP_FROM_REG(val) ((val) * 1000)
 836
 837 static u8 pwm_to_reg(const struct it87_data *data, long val)
 838 {
 839         if (has_newer_autopwm(data))
 840                 return val;
 841         else
 842                 return val >> 1;
 843 }
 844
 845 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 846 {
 847         if (has_newer_autopwm(data))
 848                 return reg;
 849         else
 850                 return (reg & 0x7f) << 1;
 851 }
 852
 853 static int DIV_TO_REG(int val)
 854 {
 855         int answer = 0;
 856
 857         while (answer < 7 && (val >>= 1))
 858                 answer++;
 859         return answer;
 860 }
 861
 862 #define DIV_FROM_REG(val) BIT(val)
 863
 864 /*
 865  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 866  * depending on the chip type, to calculate the actual PWM frequency.
 867  *
 868  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 869  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 870  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 871  * sometimes just one. It is unknown if this is a datasheet error or real,
 872  * so this is ignored for now.
 873  */
 874 static const unsigned int pwm_freq[8] = {
 875         48000000,
 876         24000000,
 877         12000000,
 878         8000000,
 879         6000000,
 880         3000000,
 881         1500000,
 882         750000,
 883 };
 884
 885 static int _it87_read_value(struct it87_data *data, u8 reg)
 886 {
 887         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 888         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 889 }
 890
 891 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 892 {
 893         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 894         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 895 }
 896
 897 static void it87_set_bank(struct it87_data *data, u8 bank)
 898 {
 899         if (has_bank_sel(data) && bank != data->bank) {
 900                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 901
 902                 breg &= 0x1f;
 903                 breg |= (bank << 5);
 904                 data->bank = bank;
 905                 _it87_write_value(data, IT87_REG_BANK, breg);
 906         }
 907 }
 908
 909 /*
 910  * Must be called with data->update_lock held, except during initialization.
 911  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 912  * would slow down the IT87 access and should not be necessary.
 913  */
 914 static int it87_read_value(struct it87_data *data, u16 reg)
 915 {
 916         it87_set_bank(data, reg >> 8);
 917         return _it87_read_value(data, reg & 0xff);
 918 }
 919
 920 /*
 921  * Must be called with data->update_lock held, except during initialization.
 922  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 923  * would slow down the IT87 access and should not be necessary.
 924  */
 925 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
 926 {
 927         it87_set_bank(data, reg >> 8);
 928         _it87_write_value(data, reg & 0xff, value);
 929 }
 930
 931 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 932 {
 933         data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]);
 934         if (has_newer_autopwm(data)) {
 935                 if (has_new_tempmap(data))
 936                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x38;
 937                 else
 938                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 939                 data->pwm_duty[nr] = it87_read_value(data,
 940                                                      IT87_REG_PWM_DUTY[nr]);
 941         } else {
 942                 if (data->pwm_ctrl[nr] & 0x80)  /* Automatic mode */
 943                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 944                 else                            /* Manual mode */
 945                         data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
 946         }
 947
 948         if (has_old_autopwm(data)) {
 949                 int i;
 950
 951                 for (i = 0; i < 5 ; i++)
 952                         data->auto_temp[nr][i] = it87_read_value(data,
 953                                                 IT87_REG_AUTO_TEMP(nr, i));
 954                 for (i = 0; i < 3 ; i++)
 955                         data->auto_pwm[nr][i] = it87_read_value(data,
 956                                                 IT87_REG_AUTO_PWM(nr, i));
 957         } else if (has_newer_autopwm(data)) {
 958                 int i;
 959
 960                 /*
 961                  * 0: temperature hysteresis (base + 5)
 962                  * 1: fan off temperature (base + 0)
 963                  * 2: fan start temperature (base + 1)
 964                  * 3: fan max temperature (base + 2)
 965                  */
 966                 data->auto_temp[nr][0] =
 967                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
 968
 969                 for (i = 0; i < 3 ; i++)
 970                         data->auto_temp[nr][i + 1] =
 971                                 it87_read_value(data,
 972                                                 IT87_REG_AUTO_TEMP(nr, i));
 973                 /*
 974                  * 0: start pwm value (base + 3)
 975                  * 1: pwm slope (base + 4, 1/8th pwm)
 976                  */
 977                 data->auto_pwm[nr][0] =
 978                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
 979                 data->auto_pwm[nr][1] =
 980                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
 981         }
 982 }
 983
 984 static struct it87_data *it87_update_device(struct device *dev)
 985 {
 986         struct it87_data *data = dev_get_drvdata(dev);
 987         int i;
 988
 989         mutex_lock(&data->update_lock);
 990
 991         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
 992             !data->valid) {
 993                 if (update_vbat) {
 994                         /*
 995                          * Cleared after each update, so reenable.  Value
 996                          * returned by this read will be previous value
 997                          */
 998                         it87_write_value(data, IT87_REG_CONFIG,
 999                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1000                 }
1001                 for (i = 0; i < NUM_VIN; i++) {
1002                         if (!(data->has_in & BIT(i)))
1003                                 continue;
1004
1005                         data->in[i][0] =
1006                                 it87_read_value(data, IT87_REG_VIN[i]);
1007
1008                         /* VBAT and AVCC don't have limit registers */
1009                         if (i >= NUM_VIN_LIMIT)
1010                                 continue;
1011
1012                         data->in[i][1] =
1013                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
1014                         data->in[i][2] =
1015                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
1016                 }
1017
1018                 for (i = 0; i < NUM_FAN; i++) {
1019                         /* Skip disabled fans */
1020                         if (!(data->has_fan & BIT(i)))
1021                                 continue;
1022
1023                         data->fan[i][1] =
1024                                 it87_read_value(data, data->REG_FAN_MIN[i]);
1025                         data->fan[i][0] = it87_read_value(data,
1026                                        data->REG_FAN[i]);
1027                         /* Add high byte if in 16-bit mode */
1028                         if (has_16bit_fans(data)) {
1029                                 data->fan[i][0] |= it87_read_value(data,
1030                                                 data->REG_FANX[i]) << 8;
1031                                 data->fan[i][1] |= it87_read_value(data,
1032                                                 data->REG_FANX_MIN[i]) << 8;
1033                         }
1034                 }
1035                 for (i = 0; i < NUM_TEMP; i++) {
1036                         if (!(data->has_temp & BIT(i)))
1037                                 continue;
1038                         data->temp[i][0] =
1039                                 it87_read_value(data, IT87_REG_TEMP(i));
1040
1041                         if (i >= data->num_temp_limit)
1042                                 continue;
1043
1044                         if (i < data->num_temp_offset)
1045                                 data->temp[i][3] =
1046                                   it87_read_value(data,
1047                                                   data->REG_TEMP_OFFSET[i]);
1048
1049                         data->temp[i][1] =
1050                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1051                         data->temp[i][2] =
1052                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1053                 }
1054
1055                 /* Newer chips don't have clock dividers */
1056                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1057                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1058                         data->fan_div[0] = i & 0x07;
1059                         data->fan_div[1] = (i >> 3) & 0x07;
1060                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1061                 }
1062
1063                 data->alarms =
1064                         it87_read_value(data, IT87_REG_ALARM1) |
1065                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1066                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1067                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1068
1069                 data->fan_main_ctrl = it87_read_value(data,
1070                                 IT87_REG_FAN_MAIN_CTRL);
1071                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1072                 for (i = 0; i < NUM_PWM; i++) {
1073                         if (!(data->has_pwm & BIT(i)))
1074                                 continue;
1075                         it87_update_pwm_ctrl(data, i);
1076                 }
1077
1078                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1079                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1080                 /*
1081                  * The IT8705F does not have VID capability.
1082                  * The IT8718F and later don't use IT87_REG_VID for the
1083                  * same purpose.
1084                  */
1085                 if (data->type == it8712 || data->type == it8716) {
1086                         data->vid = it87_read_value(data, IT87_REG_VID);
1087                         /*
1088                          * The older IT8712F revisions had only 5 VID pins,
1089                          * but we assume it is always safe to read 6 bits.
1090                          */
1091                         data->vid &= 0x3f;
1092                 }
1093                 data->last_updated = jiffies;
1094                 data->valid = 1;
1095         }
1096
1097         mutex_unlock(&data->update_lock);
1098
1099         return data;
1100 }
1101
1102 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1103                        char *buf)
1104 {
1105         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1106         struct it87_data *data = it87_update_device(dev);
1107         int index = sattr->index;
1108         int nr = sattr->nr;
1109
1110         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1111 }
1112
1113 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1114                       const char *buf, size_t count)
1115 {
1116         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1117         struct it87_data *data = dev_get_drvdata(dev);
1118         int index = sattr->index;
1119         int nr = sattr->nr;
1120         unsigned long val;
1121
1122         if (kstrtoul(buf, 10, &val) < 0)
1123                 return -EINVAL;
1124
1125         mutex_lock(&data->update_lock);
1126         data->in[nr][index] = in_to_reg(data, nr, val);
1127         it87_write_value(data,
1128                          index == 1 ? IT87_REG_VIN_MIN(nr)
1129                                     : IT87_REG_VIN_MAX(nr),
1130                          data->in[nr][index]);
1131         mutex_unlock(&data->update_lock);
1132         return count;
1133 }
1134
1135 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1136 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1137                             0, 1);
1138 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1139                             0, 2);
1140
1141 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1142 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1143                             1, 1);
1144 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1145                             1, 2);
1146
1147 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1148 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1149                             2, 1);
1150 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1151                             2, 2);
1152
1153 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1154 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1155                             3, 1);
1156 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1157                             3, 2);
1158
1159 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1160 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1161                             4, 1);
1162 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1163                             4, 2);
1164
1165 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1166 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1167                             5, 1);
1168 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1169                             5, 2);
1170
1171 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1172 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1173                             6, 1);
1174 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1175                             6, 2);
1176
1177 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1178 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1179                             7, 1);
1180 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1181                             7, 2);
1182
1183 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1184 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1185 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1186 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1187 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1188
1189 /* Up to 6 temperatures */
1190 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1191                          char *buf)
1192 {
1193         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1194         int nr = sattr->nr;
1195         int index = sattr->index;
1196         struct it87_data *data = it87_update_device(dev);
1197
1198         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1199 }
1200
1201 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1202                         const char *buf, size_t count)
1203 {
1204         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1205         int nr = sattr->nr;
1206         int index = sattr->index;
1207         struct it87_data *data = dev_get_drvdata(dev);
1208         long val;
1209         u8 reg, regval;
1210
1211         if (kstrtol(buf, 10, &val) < 0)
1212                 return -EINVAL;
1213
1214         mutex_lock(&data->update_lock);
1215
1216         switch (index) {
1217         default:
1218         case 1:
1219                 reg = data->REG_TEMP_LOW[nr];
1220                 break;
1221         case 2:
1222                 reg = data->REG_TEMP_HIGH[nr];
1223                 break;
1224         case 3:
1225                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1226                 if (!(regval & 0x80)) {
1227                         regval |= 0x80;
1228                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1229                 }
1230                 data->valid = 0;
1231                 reg = data->REG_TEMP_OFFSET[nr];
1232                 break;
1233         }
1234
1235         data->temp[nr][index] = TEMP_TO_REG(val);
1236         it87_write_value(data, reg, data->temp[nr][index]);
1237         mutex_unlock(&data->update_lock);
1238         return count;
1239 }
1240
1241 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1242 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1243                             0, 1);
1244 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1245                             0, 2);
1246 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1247                             set_temp, 0, 3);
1248 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1249 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1250                             1, 1);
1251 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1252                             1, 2);
1253 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1254                             set_temp, 1, 3);
1255 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1256 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1257                             2, 1);
1258 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1259                             2, 2);
1260 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1261                             set_temp, 2, 3);
1262 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1263 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1264                             3, 1);
1265 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1266                             3, 2);
1267 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1268                             set_temp, 3, 3);
1269 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1270 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1271                             4, 1);
1272 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1273                             4, 2);
1274 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1275                             set_temp, 4, 3);
1276 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1277 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1278                             5, 1);
1279 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1280                             5, 2);
1281 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1282                             set_temp, 5, 3);
1283
1284 static int get_temp_type(struct it87_data *data, int index)
1285 {
1286         u8 reg, extra;
1287         int type = 0;
1288
1289         if (has_bank_sel(data)) {
1290                 int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
1291                 u8 src1, src2;
1292
1293                 src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
1294                 src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
1295
1296                 switch (data->type) {
1297                 case it8686:
1298                         switch (src1) {
1299                         case 0:
1300                                 if (index >= 3)
1301                                         return 4;
1302                                 break;
1303                         case 1:
1304                                 if (index == 1 || index == 2 ||
1305                                           index == 4 || index == 5)
1306                                         return 6;
1307                                 break;
1308                         case 2:
1309                                 if (index == 2 || index == 6)
1310                                         return 5;
1311                                 break;
1312                         default:
1313                                 break;
1314                         }
1315                         break;
1316                 case it8625:
1317                         if (index < 3)
1318                                 break;
1319                 case it8655:
1320                 case it8665:
1321                         if (src1 < 3) {
1322                                 index = src1;
1323                                 break;
1324                         }
1325                         switch(src1) {
1326                         case 3:
1327                                 type = (src2 & BIT(index)) ? 6 : 5;
1328                                 break;
1329                         case 4 ... 8:
1330                                 type = (src2 & BIT(index)) ? 4 : 6;
1331                                 break;
1332                         case 9:
1333                                 type = (src2 & BIT(index)) ? 5 : 0;
1334                                 break;
1335                         default:
1336                                 break;
1337                         }
1338                         return type;
1339                 default:
1340                         return 0;
1341                 }
1342         }
1343         if (index >= 3)
1344                 return 0;
1345
1346         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1347         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1348
1349         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1350             (has_temp_old_peci(data, index) && (extra & 0x80)))
1351                 type = 6;               /* Intel PECI */
1352         if (reg & BIT(index))
1353                 type = 3;               /* thermal diode */
1354         else if (reg & BIT(index + 3))
1355                 type = 4;               /* thermistor */
1356
1357         return type;
1358 }
1359
1360 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1361                               char *buf)
1362 {
1363         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1364         struct it87_data *data = it87_update_device(dev);
1365         int type = get_temp_type(data, sensor_attr->index);
1366
1367         return sprintf(buf, "%d\n", type);
1368 }
1369
1370 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1371                              const char *buf, size_t count)
1372 {
1373         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1374         int nr = sensor_attr->index;
1375
1376         struct it87_data *data = dev_get_drvdata(dev);
1377         long val;
1378         u8 reg, extra;
1379
1380         if (kstrtol(buf, 10, &val) < 0)
1381                 return -EINVAL;
1382
1383         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1384         reg &= ~(1 << nr);
1385         reg &= ~(8 << nr);
1386         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1387                 reg &= 0x3f;
1388         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1389         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1390                 extra &= 0x7f;
1391         if (val == 2) { /* backwards compatibility */
1392                 dev_warn(dev,
1393                          "Sensor type 2 is deprecated, please use 4 instead\n");
1394                 val = 4;
1395         }
1396         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1397         if (val == 3)
1398                 reg |= 1 << nr;
1399         else if (val == 4)
1400                 reg |= 8 << nr;
1401         else if (has_temp_peci(data, nr) && val == 6)
1402                 reg |= (nr + 1) << 6;
1403         else if (has_temp_old_peci(data, nr) && val == 6)
1404                 extra |= 0x80;
1405         else if (val != 0)
1406                 return -EINVAL;
1407
1408         mutex_lock(&data->update_lock);
1409         data->sensor = reg;
1410         data->extra = extra;
1411         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1412         if (has_temp_old_peci(data, nr))
1413                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1414         data->valid = 0;        /* Force cache refresh */
1415         mutex_unlock(&data->update_lock);
1416         return count;
1417 }
1418
1419 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1420                           set_temp_type, 0);
1421 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1422                           set_temp_type, 1);
1423 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1424                           set_temp_type, 2);
1425 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1426                           set_temp_type, 3);
1427 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1428                           set_temp_type, 4);
1429 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1430                           set_temp_type, 5);
1431
1432 /* 6 Fans */
1433
1434 static int pwm_mode(const struct it87_data *data, int nr)
1435 {
1436         if (has_fanctl_onoff(data) && nr < 3 &&
1437             !(data->fan_main_ctrl & BIT(nr)))
1438                 return 0;                               /* Full speed */
1439         if (data->pwm_ctrl[nr] & 0x80)
1440                 return 2;                               /* Automatic mode */
1441         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1442             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1443                 return 0;                       /* Full speed */
1444
1445         return 1;                               /* Manual mode */
1446 }
1447
1448 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1449                         char *buf)
1450 {
1451         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1452         int nr = sattr->nr;
1453         int index = sattr->index;
1454         int speed;
1455         struct it87_data *data = it87_update_device(dev);
1456
1457         speed = has_16bit_fans(data) ?
1458                 FAN16_FROM_REG(data->fan[nr][index]) :
1459                 FAN_FROM_REG(data->fan[nr][index],
1460                              DIV_FROM_REG(data->fan_div[nr]));
1461         return sprintf(buf, "%d\n", speed);
1462 }
1463
1464 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1465                             char *buf)
1466 {
1467         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1468         struct it87_data *data = it87_update_device(dev);
1469         int nr = sensor_attr->index;
1470
1471         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1472 }
1473
1474 static ssize_t show_pwm_enable(struct device *dev,
1475                                struct device_attribute *attr, char *buf)
1476 {
1477         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1478         struct it87_data *data = it87_update_device(dev);
1479         int nr = sensor_attr->index;
1480
1481         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1482 }
1483
1484 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1485                         char *buf)
1486 {
1487         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1488         struct it87_data *data = it87_update_device(dev);
1489         int nr = sensor_attr->index;
1490
1491         return sprintf(buf, "%d\n",
1492                        pwm_from_reg(data, data->pwm_duty[nr]));
1493 }
1494
1495 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1496                              char *buf)
1497 {
1498         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1499         struct it87_data *data = it87_update_device(dev);
1500         int nr = sensor_attr->index;
1501         unsigned int freq;
1502         int index;
1503
1504         if (has_pwm_freq2(data) && nr == 1)
1505                 index = (data->extra >> 4) & 0x07;
1506         else
1507                 index = (data->fan_ctl >> 4) & 0x07;
1508
1509         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1510
1511         return sprintf(buf, "%u\n", freq);
1512 }
1513
1514 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1515                        const char *buf, size_t count)
1516 {
1517         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1518         int nr = sattr->nr;
1519         int index = sattr->index;
1520
1521         struct it87_data *data = dev_get_drvdata(dev);
1522         long val;
1523         u8 reg;
1524
1525         if (kstrtol(buf, 10, &val) < 0)
1526                 return -EINVAL;
1527
1528         mutex_lock(&data->update_lock);
1529
1530         if (has_16bit_fans(data)) {
1531                 data->fan[nr][index] = FAN16_TO_REG(val);
1532                 it87_write_value(data, data->REG_FAN_MIN[nr],
1533                                  data->fan[nr][index] & 0xff);
1534                 it87_write_value(data, data->REG_FANX_MIN[nr],
1535                                  data->fan[nr][index] >> 8);
1536         } else {
1537                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1538                 switch (nr) {
1539                 case 0:
1540                         data->fan_div[nr] = reg & 0x07;
1541                         break;
1542                 case 1:
1543                         data->fan_div[nr] = (reg >> 3) & 0x07;
1544                         break;
1545                 case 2:
1546                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1547                         break;
1548                 }
1549                 data->fan[nr][index] =
1550                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1551                 it87_write_value(data, data->REG_FAN_MIN[nr],
1552                                  data->fan[nr][index]);
1553         }
1554
1555         mutex_unlock(&data->update_lock);
1556         return count;
1557 }
1558
1559 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1560                            const char *buf, size_t count)
1561 {
1562         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1563         struct it87_data *data = dev_get_drvdata(dev);
1564         int nr = sensor_attr->index;
1565         unsigned long val;
1566         int min;
1567         u8 old;
1568
1569         if (kstrtoul(buf, 10, &val) < 0)
1570                 return -EINVAL;
1571
1572         mutex_lock(&data->update_lock);
1573         old = it87_read_value(data, IT87_REG_FAN_DIV);
1574
1575         /* Save fan min limit */
1576         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1577
1578         switch (nr) {
1579         case 0:
1580         case 1:
1581                 data->fan_div[nr] = DIV_TO_REG(val);
1582                 break;
1583         case 2:
1584                 if (val < 8)
1585                         data->fan_div[nr] = 1;
1586                 else
1587                         data->fan_div[nr] = 3;
1588         }
1589         val = old & 0x80;
1590         val |= (data->fan_div[0] & 0x07);
1591         val |= (data->fan_div[1] & 0x07) << 3;
1592         if (data->fan_div[2] == 3)
1593                 val |= 0x1 << 6;
1594         it87_write_value(data, IT87_REG_FAN_DIV, val);
1595
1596         /* Restore fan min limit */
1597         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1598         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1599
1600         mutex_unlock(&data->update_lock);
1601         return count;
1602 }
1603
1604 /* Returns 0 if OK, -EINVAL otherwise */
1605 static int check_trip_points(struct device *dev, int nr)
1606 {
1607         const struct it87_data *data = dev_get_drvdata(dev);
1608         int i, err = 0;
1609
1610         if (has_old_autopwm(data)) {
1611                 for (i = 0; i < 3; i++) {
1612                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1613                                 err = -EINVAL;
1614                 }
1615                 for (i = 0; i < 2; i++) {
1616                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1617                                 err = -EINVAL;
1618                 }
1619         } else if (has_newer_autopwm(data)) {
1620                 for (i = 1; i < 3; i++) {
1621                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1622                                 err = -EINVAL;
1623                 }
1624         }
1625
1626         if (err) {
1627                 dev_err(dev,
1628                         "Inconsistent trip points, not switching to automatic mode\n");
1629                 dev_err(dev, "Adjust the trip points and try again\n");
1630         }
1631         return err;
1632 }
1633
1634 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1635                               const char *buf, size_t count)
1636 {
1637         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1638         struct it87_data *data = dev_get_drvdata(dev);
1639         int nr = sensor_attr->index;
1640         long val;
1641
1642         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1643                 return -EINVAL;
1644
1645         /* Check trip points before switching to automatic mode */
1646         if (val == 2) {
1647                 if (check_trip_points(dev, nr) < 0)
1648                         return -EINVAL;
1649         }
1650
1651         mutex_lock(&data->update_lock);
1652
1653         if (val == 0) {
1654                 if (nr < 3 && has_fanctl_onoff(data)) {
1655                         int tmp;
1656                         /* make sure the fan is on when in on/off mode */
1657                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1658                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1659                         /* set on/off mode */
1660                         data->fan_main_ctrl &= ~BIT(nr);
1661                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1662                                          data->fan_main_ctrl);
1663                 } else {
1664                         u8 ctrl;
1665
1666                         /* No on/off mode, set maximum pwm value */
1667                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1668                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1669                                          data->pwm_duty[nr]);
1670                         /* and set manual mode */
1671                         if (has_newer_autopwm(data)) {
1672                                 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1673                                         data->pwm_temp_map[nr];
1674                         } else {
1675                                 ctrl = data->pwm_duty[nr];
1676                         }
1677                         data->pwm_ctrl[nr] = ctrl;
1678                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1679                 }
1680         } else {
1681                 u8 ctrl;
1682
1683                 if (has_newer_autopwm(data)) {
1684                         ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1685                                 data->pwm_temp_map[nr];
1686                         if (val != 1)
1687                                 ctrl |= 0x80;
1688                 } else {
1689                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1690                 }
1691                 data->pwm_ctrl[nr] = ctrl;
1692                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1693
1694                 if (has_fanctl_onoff(data) && nr < 3) {
1695                         /* set SmartGuardian mode */
1696                         data->fan_main_ctrl |= BIT(nr);
1697                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1698                                          data->fan_main_ctrl);
1699                 }
1700         }
1701
1702         mutex_unlock(&data->update_lock);
1703         return count;
1704 }
1705
1706 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1707                        const char *buf, size_t count)
1708 {
1709         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1710         struct it87_data *data = dev_get_drvdata(dev);
1711         int nr = sensor_attr->index;
1712         long val;
1713
1714         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1715                 return -EINVAL;
1716
1717         mutex_lock(&data->update_lock);
1718         it87_update_pwm_ctrl(data, nr);
1719         if (has_newer_autopwm(data)) {
1720                 /*
1721                  * If we are in automatic mode, the PWM duty cycle register
1722                  * is read-only so we can't write the value.
1723                  */
1724                 if (data->pwm_ctrl[nr] & 0x80) {
1725                         mutex_unlock(&data->update_lock);
1726                         return -EBUSY;
1727                 }
1728                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1729                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1730                                  data->pwm_duty[nr]);
1731         } else {
1732                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1733                 /*
1734                  * If we are in manual mode, write the duty cycle immediately;
1735                  * otherwise, just store it for later use.
1736                  */
1737                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1738                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1739                         it87_write_value(data, data->REG_PWM[nr],
1740                                          data->pwm_ctrl[nr]);
1741                 }
1742         }
1743         mutex_unlock(&data->update_lock);
1744         return count;
1745 }
1746
1747 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1748                             const char *buf, size_t count)
1749 {
1750         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1751         struct it87_data *data = dev_get_drvdata(dev);
1752         int nr = sensor_attr->index;
1753         unsigned long val;
1754         int i;
1755
1756         if (kstrtoul(buf, 10, &val) < 0)
1757                 return -EINVAL;
1758
1759         val = clamp_val(val, 0, 1000000);
1760         val *= has_newer_autopwm(data) ? 256 : 128;
1761
1762         /* Search for the nearest available frequency */
1763         for (i = 0; i < 7; i++) {
1764                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1765                         break;
1766         }
1767
1768         mutex_lock(&data->update_lock);
1769         if (nr == 0) {
1770                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1771                 data->fan_ctl |= i << 4;
1772                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1773         } else {
1774                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1775                 data->extra |= i << 4;
1776                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1777         }
1778         mutex_unlock(&data->update_lock);
1779
1780         return count;
1781 }
1782
1783 static ssize_t show_pwm_temp_map(struct device *dev,
1784                                  struct device_attribute *attr, char *buf)
1785 {
1786         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1787         struct it87_data *data = it87_update_device(dev);
1788         int nr = sensor_attr->index;
1789         int map;
1790
1791         map = data->pwm_temp_map[nr];
1792         if (has_new_tempmap(data)) {
1793                 map >>= 3;
1794                 if (map >= 6)
1795                         map = 0;        /* Should never happen */
1796         } else {
1797                 if (map >= 3)
1798                         map = 0;        /* Should never happen */
1799                 if (nr >= 3)            /* pwm channels 3..6 map to temp4..6 */
1800                         map += 3;
1801         }
1802
1803         return sprintf(buf, "%d\n", (int)BIT(map));
1804 }
1805
1806 static ssize_t set_pwm_temp_map(struct device *dev,
1807                                 struct device_attribute *attr, const char *buf,
1808                                 size_t count)
1809 {
1810         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1811         struct it87_data *data = dev_get_drvdata(dev);
1812         int nr = sensor_attr->index;
1813         long val;
1814         u8 reg;
1815
1816         if (kstrtol(buf, 10, &val) < 0)
1817                 return -EINVAL;
1818
1819         if (nr >= 3 && !has_new_tempmap(data))
1820                 val -= 3;
1821
1822         switch (val) {
1823         case BIT(0):
1824                 reg = 0x00;
1825                 break;
1826         case BIT(1):
1827                 reg = 0x01;
1828                 break;
1829         case BIT(2):
1830                 reg = 0x02;
1831                 break;
1832         case BIT(3):
1833                 reg = 0x03;
1834                 break;
1835         case BIT(4):
1836                 reg = 0x04;
1837                 break;
1838         case BIT(5):
1839                 reg = 0x05;
1840                 break;
1841         case BIT(6):
1842                 reg = 0x06;
1843                 break;
1844         default:
1845                 return -EINVAL;
1846         }
1847
1848         if (has_new_tempmap(data))
1849                 reg <<= 3;
1850         else if (reg > 0x02)
1851                 return -EINVAL;
1852
1853         mutex_lock(&data->update_lock);
1854         it87_update_pwm_ctrl(data, nr);
1855         data->pwm_temp_map[nr] = reg;
1856         /*
1857          * If we are in automatic mode, write the temp mapping immediately;
1858          * otherwise, just store it for later use.
1859          */
1860         if (data->pwm_ctrl[nr] & 0x80) {
1861                 u8 mask = has_new_tempmap(data) ? 0xc7 : 0xfc;
1862
1863                 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & mask) |
1864                                                 data->pwm_temp_map[nr];
1865                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1866         }
1867         mutex_unlock(&data->update_lock);
1868         return count;
1869 }
1870
1871 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1872                              char *buf)
1873 {
1874         struct it87_data *data = it87_update_device(dev);
1875         struct sensor_device_attribute_2 *sensor_attr =
1876                         to_sensor_dev_attr_2(attr);
1877         int nr = sensor_attr->nr;
1878         int point = sensor_attr->index;
1879
1880         return sprintf(buf, "%d\n",
1881                        pwm_from_reg(data, data->auto_pwm[nr][point]));
1882 }
1883
1884 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1885                             const char *buf, size_t count)
1886 {
1887         struct it87_data *data = dev_get_drvdata(dev);
1888         struct sensor_device_attribute_2 *sensor_attr =
1889                         to_sensor_dev_attr_2(attr);
1890         int nr = sensor_attr->nr;
1891         int point = sensor_attr->index;
1892         int regaddr;
1893         long val;
1894
1895         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1896                 return -EINVAL;
1897
1898         mutex_lock(&data->update_lock);
1899         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1900         if (has_newer_autopwm(data))
1901                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1902         else
1903                 regaddr = IT87_REG_AUTO_PWM(nr, point);
1904         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1905         mutex_unlock(&data->update_lock);
1906         return count;
1907 }
1908
1909 static ssize_t show_auto_pwm_slope(struct device *dev,
1910                                    struct device_attribute *attr, char *buf)
1911 {
1912         struct it87_data *data = it87_update_device(dev);
1913         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1914         int nr = sensor_attr->index;
1915
1916         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1917 }
1918
1919 static ssize_t set_auto_pwm_slope(struct device *dev,
1920                                   struct device_attribute *attr,
1921                                   const char *buf, size_t count)
1922 {
1923         struct it87_data *data = dev_get_drvdata(dev);
1924         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1925         int nr = sensor_attr->index;
1926         unsigned long val;
1927
1928         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1929                 return -EINVAL;
1930
1931         mutex_lock(&data->update_lock);
1932         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1933         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1934                          data->auto_pwm[nr][1]);
1935         mutex_unlock(&data->update_lock);
1936         return count;
1937 }
1938
1939 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1940                               char *buf)
1941 {
1942         struct it87_data *data = it87_update_device(dev);
1943         struct sensor_device_attribute_2 *sensor_attr =
1944                         to_sensor_dev_attr_2(attr);
1945         int nr = sensor_attr->nr;
1946         int point = sensor_attr->index;
1947         int reg;
1948
1949         if (has_old_autopwm(data) || point)
1950                 reg = data->auto_temp[nr][point];
1951         else
1952                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1953
1954         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1955 }
1956
1957 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1958                              const char *buf, size_t count)
1959 {
1960         struct it87_data *data = dev_get_drvdata(dev);
1961         struct sensor_device_attribute_2 *sensor_attr =
1962                         to_sensor_dev_attr_2(attr);
1963         int nr = sensor_attr->nr;
1964         int point = sensor_attr->index;
1965         long val;
1966         int reg;
1967
1968         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1969                 return -EINVAL;
1970
1971         mutex_lock(&data->update_lock);
1972         if (has_newer_autopwm(data) && !point) {
1973                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1974                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1975                 data->auto_temp[nr][0] = reg;
1976                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1977         } else {
1978                 reg = TEMP_TO_REG(val);
1979                 data->auto_temp[nr][point] = reg;
1980                 if (has_newer_autopwm(data))
1981                         point--;
1982                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1983         }
1984         mutex_unlock(&data->update_lock);
1985         return count;
1986 }
1987
1988 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1989 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1990                             0, 1);
1991 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1992                           set_fan_div, 0);
1993
1994 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1995 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1996                             1, 1);
1997 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1998                           set_fan_div, 1);
1999
2000 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
2001 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2002                             2, 1);
2003 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
2004                           set_fan_div, 2);
2005
2006 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2007 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2008                             3, 1);
2009
2010 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2011 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2012                             4, 1);
2013
2014 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2015 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2016                             5, 1);
2017
2018 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2019                           show_pwm_enable, set_pwm_enable, 0);
2020 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2021 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2022                           set_pwm_freq, 0);
2023 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2024                           show_pwm_temp_map, set_pwm_temp_map, 0);
2025 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2026                             show_auto_pwm, set_auto_pwm, 0, 0);
2027 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2028                             show_auto_pwm, set_auto_pwm, 0, 1);
2029 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2030                             show_auto_pwm, set_auto_pwm, 0, 2);
2031 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2032                             show_auto_pwm, NULL, 0, 3);
2033 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2034                             show_auto_temp, set_auto_temp, 0, 1);
2035 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2036                             show_auto_temp, set_auto_temp, 0, 0);
2037 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2038                             show_auto_temp, set_auto_temp, 0, 2);
2039 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2040                             show_auto_temp, set_auto_temp, 0, 3);
2041 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2042                             show_auto_temp, set_auto_temp, 0, 4);
2043 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2044                             show_auto_pwm, set_auto_pwm, 0, 0);
2045 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2046                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2047
2048 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2049                           show_pwm_enable, set_pwm_enable, 1);
2050 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2051 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2052 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2053                           show_pwm_temp_map, set_pwm_temp_map, 1);
2054 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2055                             show_auto_pwm, set_auto_pwm, 1, 0);
2056 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2057                             show_auto_pwm, set_auto_pwm, 1, 1);
2058 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2059                             show_auto_pwm, set_auto_pwm, 1, 2);
2060 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2061                             show_auto_pwm, NULL, 1, 3);
2062 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2063                             show_auto_temp, set_auto_temp, 1, 1);
2064 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2065                             show_auto_temp, set_auto_temp, 1, 0);
2066 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2067                             show_auto_temp, set_auto_temp, 1, 2);
2068 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2069                             show_auto_temp, set_auto_temp, 1, 3);
2070 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2071                             show_auto_temp, set_auto_temp, 1, 4);
2072 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2073                             show_auto_pwm, set_auto_pwm, 1, 0);
2074 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2075                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2076
2077 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2078                           show_pwm_enable, set_pwm_enable, 2);
2079 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2080 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2081 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2082                           show_pwm_temp_map, set_pwm_temp_map, 2);
2083 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2084                             show_auto_pwm, set_auto_pwm, 2, 0);
2085 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2086                             show_auto_pwm, set_auto_pwm, 2, 1);
2087 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2088                             show_auto_pwm, set_auto_pwm, 2, 2);
2089 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2090                             show_auto_pwm, NULL, 2, 3);
2091 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2092                             show_auto_temp, set_auto_temp, 2, 1);
2093 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2094                             show_auto_temp, set_auto_temp, 2, 0);
2095 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2096                             show_auto_temp, set_auto_temp, 2, 2);
2097 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2098                             show_auto_temp, set_auto_temp, 2, 3);
2099 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2100                             show_auto_temp, set_auto_temp, 2, 4);
2101 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2102                             show_auto_pwm, set_auto_pwm, 2, 0);
2103 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2104                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2105
2106 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2107                           show_pwm_enable, set_pwm_enable, 3);
2108 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2109 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2110 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2111                           show_pwm_temp_map, set_pwm_temp_map, 3);
2112 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2113                             show_auto_temp, set_auto_temp, 2, 1);
2114 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2115                             show_auto_temp, set_auto_temp, 2, 0);
2116 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2117                             show_auto_temp, set_auto_temp, 2, 2);
2118 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2119                             show_auto_temp, set_auto_temp, 2, 3);
2120 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2121                             show_auto_pwm, set_auto_pwm, 3, 0);
2122 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2123                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2124
2125 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2126                           show_pwm_enable, set_pwm_enable, 4);
2127 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2128 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2129 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2130                           show_pwm_temp_map, set_pwm_temp_map, 4);
2131 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2132                             show_auto_temp, set_auto_temp, 2, 1);
2133 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2134                             show_auto_temp, set_auto_temp, 2, 0);
2135 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2136                             show_auto_temp, set_auto_temp, 2, 2);
2137 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2138                             show_auto_temp, set_auto_temp, 2, 3);
2139 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2140                             show_auto_pwm, set_auto_pwm, 4, 0);
2141 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2142                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2143
2144 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2145                           show_pwm_enable, set_pwm_enable, 5);
2146 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2147 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2148 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2149                           show_pwm_temp_map, set_pwm_temp_map, 5);
2150 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2151                             show_auto_temp, set_auto_temp, 2, 1);
2152 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2153                             show_auto_temp, set_auto_temp, 2, 0);
2154 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2155                             show_auto_temp, set_auto_temp, 2, 2);
2156 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2157                             show_auto_temp, set_auto_temp, 2, 3);
2158 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2159                             show_auto_pwm, set_auto_pwm, 5, 0);
2160 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2161                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2162
2163 /* Alarms */
2164 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2165                            char *buf)
2166 {
2167         struct it87_data *data = it87_update_device(dev);
2168
2169         return sprintf(buf, "%u\n", data->alarms);
2170 }
2171 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2172
2173 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2174                           char *buf)
2175 {
2176         struct it87_data *data = it87_update_device(dev);
2177         int bitnr = to_sensor_dev_attr(attr)->index;
2178
2179         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2180 }
2181
2182 static ssize_t clear_intrusion(struct device *dev,
2183                                struct device_attribute *attr, const char *buf,
2184                                size_t count)
2185 {
2186         struct it87_data *data = dev_get_drvdata(dev);
2187         int config;
2188         long val;
2189
2190         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2191                 return -EINVAL;
2192
2193         mutex_lock(&data->update_lock);
2194         config = it87_read_value(data, IT87_REG_CONFIG);
2195         if (config < 0) {
2196                 count = config;
2197         } else {
2198                 config |= BIT(5);
2199                 it87_write_value(data, IT87_REG_CONFIG, config);
2200                 /* Invalidate cache to force re-read */
2201                 data->valid = 0;
2202         }
2203         mutex_unlock(&data->update_lock);
2204
2205         return count;
2206 }
2207
2208 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2209 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2210 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2211 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2212 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2213 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2214 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2215 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2216 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2217 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2218 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2219 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2220 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2221 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2222 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2223 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2224 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2225 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2226 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2227 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2228 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2229                           show_alarm, clear_intrusion, 4);
2230
2231 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2232                          char *buf)
2233 {
2234         struct it87_data *data = it87_update_device(dev);
2235         int bitnr = to_sensor_dev_attr(attr)->index;
2236
2237         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2238 }
2239
2240 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2241                         const char *buf, size_t count)
2242 {
2243         int bitnr = to_sensor_dev_attr(attr)->index;
2244         struct it87_data *data = dev_get_drvdata(dev);
2245         long val;
2246
2247         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2248                 return -EINVAL;
2249
2250         mutex_lock(&data->update_lock);
2251         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2252         if (val)
2253                 data->beeps |= BIT(bitnr);
2254         else
2255                 data->beeps &= ~BIT(bitnr);
2256         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2257         mutex_unlock(&data->update_lock);
2258         return count;
2259 }
2260
2261 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2262                           show_beep, set_beep, 1);
2263 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2264 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2265 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2266 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2267 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2268 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2269 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2270 /* fanX_beep writability is set later */
2271 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2272 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2273 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2274 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2275 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2276 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2277 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2278                           show_beep, set_beep, 2);
2279 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2280 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2281 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2282 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2283 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2284
2285 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2286                             char *buf)
2287 {
2288         struct it87_data *data = dev_get_drvdata(dev);
2289
2290         return sprintf(buf, "%u\n", data->vrm);
2291 }
2292
2293 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2294                              const char *buf, size_t count)
2295 {
2296         struct it87_data *data = dev_get_drvdata(dev);
2297         unsigned long val;
2298
2299         if (kstrtoul(buf, 10, &val) < 0)
2300                 return -EINVAL;
2301
2302         data->vrm = val;
2303
2304         return count;
2305 }
2306 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2307
2308 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2309                             char *buf)
2310 {
2311         struct it87_data *data = it87_update_device(dev);
2312
2313         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2314 }
2315 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2316
2317 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2318                           char *buf)
2319 {
2320         static const char * const labels[] = {
2321                 "+5V",
2322                 "5VSB",
2323                 "Vbat",
2324                 "AVCC",
2325         };
2326         static const char * const labels_it8721[] = {
2327                 "+3.3V",
2328                 "3VSB",
2329                 "Vbat",
2330                 "+3.3V",
2331         };
2332         struct it87_data *data = dev_get_drvdata(dev);
2333         int nr = to_sensor_dev_attr(attr)->index;
2334         const char *label;
2335
2336         if (has_vin3_5v(data) && nr == 0)
2337                 label = labels[0];
2338         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2339                  has_11mv_adc(data))
2340                 label = labels_it8721[nr];
2341         else
2342                 label = labels[nr];
2343
2344         return sprintf(buf, "%s\n", label);
2345 }
2346 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2347 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2348 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2349 /* AVCC3 */
2350 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2351
2352 static umode_t it87_in_is_visible(struct kobject *kobj,
2353                                   struct attribute *attr, int index)
2354 {
2355         struct device *dev = container_of(kobj, struct device, kobj);
2356         struct it87_data *data = dev_get_drvdata(dev);
2357         int i = index / 5;      /* voltage index */
2358         int a = index % 5;      /* attribute index */
2359
2360         if (index >= 40) {      /* in8 and higher only have input attributes */
2361                 i = index - 40 + 8;
2362                 a = 0;
2363         }
2364
2365         if (!(data->has_in & BIT(i)))
2366                 return 0;
2367
2368         if (a == 4 && !data->has_beep)
2369                 return 0;
2370
2371         return attr->mode;
2372 }
2373
2374 static struct attribute *it87_attributes_in[] = {
2375         &sensor_dev_attr_in0_input.dev_attr.attr,
2376         &sensor_dev_attr_in0_min.dev_attr.attr,
2377         &sensor_dev_attr_in0_max.dev_attr.attr,
2378         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2379         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2380
2381         &sensor_dev_attr_in1_input.dev_attr.attr,
2382         &sensor_dev_attr_in1_min.dev_attr.attr,
2383         &sensor_dev_attr_in1_max.dev_attr.attr,
2384         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2385         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2386
2387         &sensor_dev_attr_in2_input.dev_attr.attr,
2388         &sensor_dev_attr_in2_min.dev_attr.attr,
2389         &sensor_dev_attr_in2_max.dev_attr.attr,
2390         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2391         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2392
2393         &sensor_dev_attr_in3_input.dev_attr.attr,
2394         &sensor_dev_attr_in3_min.dev_attr.attr,
2395         &sensor_dev_attr_in3_max.dev_attr.attr,
2396         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2397         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2398
2399         &sensor_dev_attr_in4_input.dev_attr.attr,
2400         &sensor_dev_attr_in4_min.dev_attr.attr,
2401         &sensor_dev_attr_in4_max.dev_attr.attr,
2402         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2403         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2404
2405         &sensor_dev_attr_in5_input.dev_attr.attr,
2406         &sensor_dev_attr_in5_min.dev_attr.attr,
2407         &sensor_dev_attr_in5_max.dev_attr.attr,
2408         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2409         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2410
2411         &sensor_dev_attr_in6_input.dev_attr.attr,
2412         &sensor_dev_attr_in6_min.dev_attr.attr,
2413         &sensor_dev_attr_in6_max.dev_attr.attr,
2414         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2415         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2416
2417         &sensor_dev_attr_in7_input.dev_attr.attr,
2418         &sensor_dev_attr_in7_min.dev_attr.attr,
2419         &sensor_dev_attr_in7_max.dev_attr.attr,
2420         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2421         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2422
2423         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2424         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2425         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2426         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2427         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2428         NULL
2429 };
2430
2431 static const struct attribute_group it87_group_in = {
2432         .attrs = it87_attributes_in,
2433         .is_visible = it87_in_is_visible,
2434 };
2435
2436 static umode_t it87_temp_is_visible(struct kobject *kobj,
2437                                     struct attribute *attr, int index)
2438 {
2439         struct device *dev = container_of(kobj, struct device, kobj);
2440         struct it87_data *data = dev_get_drvdata(dev);
2441         int i = index / 7;      /* temperature index */
2442         int a = index % 7;      /* attribute index */
2443
2444         if (!(data->has_temp & BIT(i)))
2445                 return 0;
2446
2447         if (a && i >= data->num_temp_limit)
2448                 return 0;
2449
2450         if (a == 3) {
2451                 int type = get_temp_type(data, i);
2452
2453                 if (type == 0)
2454                         return 0;
2455                 if (has_bank_sel(data))
2456                         return 0444;
2457                 return attr->mode;
2458         }
2459
2460         if (a == 5 && i >= data->num_temp_offset)
2461                 return 0;
2462
2463         if (a == 6 && !data->has_beep)
2464                 return 0;
2465
2466         return attr->mode;
2467 }
2468
2469 static struct attribute *it87_attributes_temp[] = {
2470         &sensor_dev_attr_temp1_input.dev_attr.attr,
2471         &sensor_dev_attr_temp1_max.dev_attr.attr,
2472         &sensor_dev_attr_temp1_min.dev_attr.attr,
2473         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2474         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2475         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2476         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2477
2478         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2479         &sensor_dev_attr_temp2_max.dev_attr.attr,
2480         &sensor_dev_attr_temp2_min.dev_attr.attr,
2481         &sensor_dev_attr_temp2_type.dev_attr.attr,
2482         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2483         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2484         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2485
2486         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2487         &sensor_dev_attr_temp3_max.dev_attr.attr,
2488         &sensor_dev_attr_temp3_min.dev_attr.attr,
2489         &sensor_dev_attr_temp3_type.dev_attr.attr,
2490         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2491         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2492         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2493
2494         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2495         &sensor_dev_attr_temp4_max.dev_attr.attr,
2496         &sensor_dev_attr_temp4_min.dev_attr.attr,
2497         &sensor_dev_attr_temp4_type.dev_attr.attr,
2498         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2499         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2500         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2501
2502         &sensor_dev_attr_temp5_input.dev_attr.attr,
2503         &sensor_dev_attr_temp5_max.dev_attr.attr,
2504         &sensor_dev_attr_temp5_min.dev_attr.attr,
2505         &sensor_dev_attr_temp5_type.dev_attr.attr,
2506         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2507         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2508         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2509
2510         &sensor_dev_attr_temp6_input.dev_attr.attr,
2511         &sensor_dev_attr_temp6_max.dev_attr.attr,
2512         &sensor_dev_attr_temp6_min.dev_attr.attr,
2513         &sensor_dev_attr_temp6_type.dev_attr.attr,
2514         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2515         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2516         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2517         NULL
2518 };
2519
2520 static const struct attribute_group it87_group_temp = {
2521         .attrs = it87_attributes_temp,
2522         .is_visible = it87_temp_is_visible,
2523 };
2524
2525 static umode_t it87_is_visible(struct kobject *kobj,
2526                                struct attribute *attr, int index)
2527 {
2528         struct device *dev = container_of(kobj, struct device, kobj);
2529         struct it87_data *data = dev_get_drvdata(dev);
2530
2531         if ((index == 2 || index == 3) && !data->has_vid)
2532                 return 0;
2533
2534         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2535                 return 0;
2536
2537         return attr->mode;
2538 }
2539
2540 static struct attribute *it87_attributes[] = {
2541         &dev_attr_alarms.attr,
2542         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2543         &dev_attr_vrm.attr,                             /* 2 */
2544         &dev_attr_cpu0_vid.attr,                        /* 3 */
2545         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2546         &sensor_dev_attr_in7_label.dev_attr.attr,
2547         &sensor_dev_attr_in8_label.dev_attr.attr,
2548         &sensor_dev_attr_in9_label.dev_attr.attr,
2549         NULL
2550 };
2551
2552 static const struct attribute_group it87_group = {
2553         .attrs = it87_attributes,
2554         .is_visible = it87_is_visible,
2555 };
2556
2557 static umode_t it87_fan_is_visible(struct kobject *kobj,
2558                                    struct attribute *attr, int index)
2559 {
2560         struct device *dev = container_of(kobj, struct device, kobj);
2561         struct it87_data *data = dev_get_drvdata(dev);
2562         int i = index / 5;      /* fan index */
2563         int a = index % 5;      /* attribute index */
2564
2565         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2566                 i = (index - 15) / 4 + 3;
2567                 a = (index - 15) % 4;
2568         }
2569
2570         if (!(data->has_fan & BIT(i)))
2571                 return 0;
2572
2573         if (a == 3) {                           /* beep */
2574                 if (!data->has_beep)
2575                         return 0;
2576                 /* first fan beep attribute is writable */
2577                 if (i == __ffs(data->has_fan))
2578                         return attr->mode | S_IWUSR;
2579         }
2580
2581         if (a == 4 && has_16bit_fans(data))     /* divisor */
2582                 return 0;
2583
2584         return attr->mode;
2585 }
2586
2587 static struct attribute *it87_attributes_fan[] = {
2588         &sensor_dev_attr_fan1_input.dev_attr.attr,
2589         &sensor_dev_attr_fan1_min.dev_attr.attr,
2590         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2591         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2592         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2593
2594         &sensor_dev_attr_fan2_input.dev_attr.attr,
2595         &sensor_dev_attr_fan2_min.dev_attr.attr,
2596         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2597         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2598         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2599
2600         &sensor_dev_attr_fan3_input.dev_attr.attr,
2601         &sensor_dev_attr_fan3_min.dev_attr.attr,
2602         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2603         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2604         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2605
2606         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2607         &sensor_dev_attr_fan4_min.dev_attr.attr,
2608         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2609         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2610
2611         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2612         &sensor_dev_attr_fan5_min.dev_attr.attr,
2613         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2614         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2615
2616         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2617         &sensor_dev_attr_fan6_min.dev_attr.attr,
2618         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2619         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2620         NULL
2621 };
2622
2623 static const struct attribute_group it87_group_fan = {
2624         .attrs = it87_attributes_fan,
2625         .is_visible = it87_fan_is_visible,
2626 };
2627
2628 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2629                                    struct attribute *attr, int index)
2630 {
2631         struct device *dev = container_of(kobj, struct device, kobj);
2632         struct it87_data *data = dev_get_drvdata(dev);
2633         int i = index / 4;      /* pwm index */
2634         int a = index % 4;      /* attribute index */
2635
2636         if (!(data->has_pwm & BIT(i)))
2637                 return 0;
2638
2639         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2640         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2641                 return attr->mode | S_IWUSR;
2642
2643         /* pwm2_freq is writable if there are two pwm frequency selects */
2644         if (has_pwm_freq2(data) && i == 1 && a == 2)
2645                 return attr->mode | S_IWUSR;
2646
2647         return attr->mode;
2648 }
2649
2650 static struct attribute *it87_attributes_pwm[] = {
2651         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2652         &sensor_dev_attr_pwm1.dev_attr.attr,
2653         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2654         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2655
2656         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2657         &sensor_dev_attr_pwm2.dev_attr.attr,
2658         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2659         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2660
2661         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2662         &sensor_dev_attr_pwm3.dev_attr.attr,
2663         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2664         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2665
2666         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2667         &sensor_dev_attr_pwm4.dev_attr.attr,
2668         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2669         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2670
2671         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2672         &sensor_dev_attr_pwm5.dev_attr.attr,
2673         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2674         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2675
2676         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2677         &sensor_dev_attr_pwm6.dev_attr.attr,
2678         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2679         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2680
2681         NULL
2682 };
2683
2684 static const struct attribute_group it87_group_pwm = {
2685         .attrs = it87_attributes_pwm,
2686         .is_visible = it87_pwm_is_visible,
2687 };
2688
2689 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2690                                         struct attribute *attr, int index)
2691 {
2692         struct device *dev = container_of(kobj, struct device, kobj);
2693         struct it87_data *data = dev_get_drvdata(dev);
2694         int i = index / 11;     /* pwm index */
2695         int a = index % 11;     /* attribute index */
2696
2697         if (index >= 33) {      /* pwm 4..6 */
2698                 i = (index - 33) / 6 + 3;
2699                 a = (index - 33) % 6 + 4;
2700         }
2701
2702         if (!(data->has_pwm & BIT(i)))
2703                 return 0;
2704
2705         if (has_newer_autopwm(data)) {
2706                 if (a < 4)      /* no auto point pwm */
2707                         return 0;
2708                 if (a == 8)     /* no auto_point4 */
2709                         return 0;
2710         }
2711         if (has_old_autopwm(data)) {
2712                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2713                         return 0;
2714         }
2715
2716         return attr->mode;
2717 }
2718
2719 static struct attribute *it87_attributes_auto_pwm[] = {
2720         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2721         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2722         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2723         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2724         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2725         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2726         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2727         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2728         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2729         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2730         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2731
2732         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2733         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2734         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2735         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2736         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2737         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2738         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2739         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2740         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2741         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2742         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2743
2744         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2745         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2746         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2747         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2748         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2749         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2750         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2751         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2752         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2753         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2754         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2755
2756         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2757         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2758         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2759         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2760         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2761         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2762
2763         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2764         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2765         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2766         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2767         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2768         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2769
2770         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2771         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2772         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2773         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2774         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2775         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2776
2777         NULL,
2778 };
2779
2780 static const struct attribute_group it87_group_auto_pwm = {
2781         .attrs = it87_attributes_auto_pwm,
2782         .is_visible = it87_auto_pwm_is_visible,
2783 };
2784
2785 /* SuperIO detection - will change isa_address if a chip is found */
2786 static int __init it87_find(int sioaddr, unsigned short *address,
2787                             struct it87_sio_data *sio_data)
2788 {
2789         const struct it87_devices *config;
2790         bool doexit = true;
2791         u16 chip_type;
2792         int err;
2793
2794         err = superio_enter(sioaddr);
2795         if (err)
2796                 return err;
2797
2798         err = -ENODEV;
2799         chip_type = superio_inw(sioaddr, DEVID);
2800         if (chip_type == 0xffff)
2801                 goto exit;
2802
2803         if (force_id)
2804                 chip_type = force_id;
2805
2806         switch (chip_type) {
2807         case IT8705F_DEVID:
2808                 sio_data->type = it87;
2809                 break;
2810         case IT8712F_DEVID:
2811                 sio_data->type = it8712;
2812                 break;
2813         case IT8716F_DEVID:
2814         case IT8726F_DEVID:
2815                 sio_data->type = it8716;
2816                 break;
2817         case IT8718F_DEVID:
2818                 sio_data->type = it8718;
2819                 break;
2820         case IT8720F_DEVID:
2821                 sio_data->type = it8720;
2822                 break;
2823         case IT8721F_DEVID:
2824                 sio_data->type = it8721;
2825                 break;
2826         case IT8728F_DEVID:
2827                 sio_data->type = it8728;
2828                 break;
2829         case IT8732F_DEVID:
2830                 sio_data->type = it8732;
2831                 break;
2832         case IT8792E_DEVID:
2833                 sio_data->type = it8792;
2834                 /*
2835                  * Disabling configuration mode on IT8792E can result in system
2836                  * hang-ups and access failures to the Super-IO chip at the
2837                  * second SIO address. Never exit configuration mode on this
2838                  * chip to avoid the problem.
2839                  */
2840                 doexit = false;
2841                 break;
2842         case IT8771E_DEVID:
2843                 sio_data->type = it8771;
2844                 break;
2845         case IT8772E_DEVID:
2846                 sio_data->type = it8772;
2847                 break;
2848         case IT8781F_DEVID:
2849                 sio_data->type = it8781;
2850                 break;
2851         case IT8782F_DEVID:
2852                 sio_data->type = it8782;
2853                 break;
2854         case IT8783E_DEVID:
2855                 sio_data->type = it8783;
2856                 break;
2857         case IT8786E_DEVID:
2858                 sio_data->type = it8786;
2859                 break;
2860         case IT8790E_DEVID:
2861                 sio_data->type = it8790;
2862                 break;
2863         case IT8603E_DEVID:
2864         case IT8623E_DEVID:
2865                 sio_data->type = it8603;
2866                 break;
2867         case IT8607E_DEVID:
2868                 sio_data->type = it8607;
2869                 break;
2870         case IT8613E_DEVID:
2871                 sio_data->type = it8613;
2872                 break;
2873         case IT8620E_DEVID:
2874                 sio_data->type = it8620;
2875                 break;
2876         case IT8622E_DEVID:
2877                 sio_data->type = it8622;
2878                 break;
2879         case IT8625E_DEVID:
2880                 sio_data->type = it8625;
2881                 break;
2882         case IT8628E_DEVID:
2883                 sio_data->type = it8628;
2884                 break;
2885         case IT8655E_DEVID:
2886                 sio_data->type = it8655;
2887                 break;
2888         case IT8665E_DEVID:
2889                 sio_data->type = it8665;
2890                 break;
2891         case IT8686E_DEVID:
2892                 sio_data->type = it8686;
2893                 break;
2894         case 0xffff:    /* No device at all */
2895                 goto exit;
2896         default:
2897                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2898                 goto exit;
2899         }
2900
2901         superio_select(sioaddr, PME);
2902         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2903                 pr_info("Device not activated, skipping\n");
2904                 goto exit;
2905         }
2906
2907         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2908         if (*address == 0) {
2909                 pr_info("Base address not set, skipping\n");
2910                 goto exit;
2911         }
2912
2913         err = 0;
2914         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2915         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2916                 it87_devices[sio_data->type].suffix,
2917                 *address, sio_data->revision);
2918
2919         config = &it87_devices[sio_data->type];
2920
2921         /* in7 (VSB or VCCH5V) is always internal on some chips */
2922         if (has_in7_internal(config))
2923                 sio_data->internal |= BIT(1);
2924
2925         /* in8 (Vbat) is always internal */
2926         sio_data->internal |= BIT(2);
2927
2928         /* in9 (AVCC3), always internal if supported */
2929         if (has_avcc3(config))
2930                 sio_data->internal |= BIT(3); /* in9 is AVCC */
2931         else
2932                 sio_data->skip_in |= BIT(9);
2933
2934         if (!has_four_pwm(config))
2935                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2936         else if (!has_five_pwm(config))
2937                 sio_data->skip_pwm |= BIT(4) | BIT(5);
2938         else if (!has_six_pwm(config))
2939                 sio_data->skip_pwm |= BIT(5);
2940
2941         if (!has_vid(config))
2942                 sio_data->skip_vid = 1;
2943
2944         /* Read GPIO config and VID value from LDN 7 (GPIO) */
2945         if (sio_data->type == it87) {
2946                 /* The IT8705F has a different LD number for GPIO */
2947                 superio_select(sioaddr, 5);
2948                 sio_data->beep_pin = superio_inb(sioaddr,
2949                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2950         } else if (sio_data->type == it8783) {
2951                 int reg25, reg27, reg2a, reg2c, regef;
2952
2953                 superio_select(sioaddr, GPIO);
2954
2955                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2956                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2957                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2958                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2959                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2960
2961                 /* Check if fan3 is there or not */
2962                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2963                         sio_data->skip_fan |= BIT(2);
2964                 if ((reg25 & BIT(4)) ||
2965                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
2966                         sio_data->skip_pwm |= BIT(2);
2967
2968                 /* Check if fan2 is there or not */
2969                 if (reg27 & BIT(7))
2970                         sio_data->skip_fan |= BIT(1);
2971                 if (reg27 & BIT(3))
2972                         sio_data->skip_pwm |= BIT(1);
2973
2974                 /* VIN5 */
2975                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2976                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2977
2978                 /* VIN6 */
2979                 if (reg27 & BIT(1))
2980                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2981
2982                 /*
2983                  * VIN7
2984                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2985                  */
2986                 if (reg27 & BIT(2)) {
2987                         /*
2988                          * The data sheet is a bit unclear regarding the
2989                          * internal voltage divider for VCCH5V. It says
2990                          * "This bit enables and switches VIN7 (pin 91) to the
2991                          * internal voltage divider for VCCH5V".
2992                          * This is different to other chips, where the internal
2993                          * voltage divider would connect VIN7 to an internal
2994                          * voltage source. Maybe that is the case here as well.
2995                          *
2996                          * Since we don't know for sure, re-route it if that is
2997                          * not the case, and ask the user to report if the
2998                          * resulting voltage is sane.
2999                          */
3000                         if (!(reg2c & BIT(1))) {
3001                                 reg2c |= BIT(1);
3002                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3003                                              reg2c);
3004                                 pr_notice("Routing internal VCCH5V to in7.\n");
3005                         }
3006                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3007                         pr_notice("Please report if it displays a reasonable voltage.\n");
3008                 }
3009
3010                 if (reg2c & BIT(0))
3011                         sio_data->internal |= BIT(0);
3012                 if (reg2c & BIT(1))
3013                         sio_data->internal |= BIT(1);
3014
3015                 sio_data->beep_pin = superio_inb(sioaddr,
3016                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3017         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3018                 int reg27, reg29;
3019
3020                 superio_select(sioaddr, GPIO);
3021
3022                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3023
3024                 /* Check if fan3 is there or not */
3025                 if (reg27 & BIT(6))
3026                         sio_data->skip_pwm |= BIT(2);
3027                 if (reg27 & BIT(7))
3028                         sio_data->skip_fan |= BIT(2);
3029
3030                 /* Check if fan2 is there or not */
3031                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3032                 if (reg29 & BIT(1))
3033                         sio_data->skip_pwm |= BIT(1);
3034                 if (reg29 & BIT(2))
3035                         sio_data->skip_fan |= BIT(1);
3036
3037                 switch (sio_data->type) {
3038                 case it8603:
3039                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3040                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3041                         break;
3042                 case it8607:
3043                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3044                         sio_data->skip_fan |= BIT(0);
3045                 default:
3046                         break;
3047                 }
3048
3049                 sio_data->beep_pin = superio_inb(sioaddr,
3050                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3051         } else if (sio_data->type == it8613) {
3052                 int reg27, reg29, reg2a;
3053
3054                 superio_select(sioaddr, GPIO);
3055
3056                 /* Check for pwm3, fan3, pwm5, fan5 */
3057                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3058                 if (reg27 & BIT(1))
3059                         sio_data->skip_fan |= BIT(4);
3060                 if (reg27 & BIT(3))
3061                         sio_data->skip_pwm |= BIT(4);
3062                 if (reg27 & BIT(6))
3063                         sio_data->skip_pwm |= BIT(2);
3064                 if (reg27 & BIT(7))
3065                         sio_data->skip_fan |= BIT(2);
3066
3067                 /* Check for pwm2, fan2 */
3068                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3069                 if (reg29 & BIT(1))
3070                         sio_data->skip_pwm |= BIT(1);
3071                 if (reg29 & BIT(2))
3072                         sio_data->skip_fan |= BIT(1);
3073
3074                 /* Check for pwm4, fan4 */
3075                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3076                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3077                         sio_data->skip_fan |= BIT(3);
3078                         sio_data->skip_pwm |= BIT(3);
3079                 }
3080
3081                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3082                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3083                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3084                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3085
3086                 sio_data->beep_pin = superio_inb(sioaddr,
3087                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3088         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3089                    sio_data->type == it8686) {
3090                 int reg;
3091
3092                 superio_select(sioaddr, GPIO);
3093
3094                 /* Check for pwm5 */
3095                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3096                 if (reg & BIT(6))
3097                         sio_data->skip_pwm |= BIT(4);
3098
3099                 /* Check for fan4, fan5 */
3100                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3101                 if (!(reg & BIT(5)))
3102                         sio_data->skip_fan |= BIT(3);
3103                 if (!(reg & BIT(4)))
3104                         sio_data->skip_fan |= BIT(4);
3105
3106                 /* Check for pwm3, fan3 */
3107                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3108                 if (reg & BIT(6))
3109                         sio_data->skip_pwm |= BIT(2);
3110                 if (reg & BIT(7))
3111                         sio_data->skip_fan |= BIT(2);
3112
3113                 /* Check for pwm4 */
3114                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3115                 if (reg & BIT(2))
3116                         sio_data->skip_pwm |= BIT(3);
3117
3118                 /* Check for pwm2, fan2 */
3119                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3120                 if (reg & BIT(1))
3121                         sio_data->skip_pwm |= BIT(1);
3122                 if (reg & BIT(2))
3123                         sio_data->skip_fan |= BIT(1);
3124                 /* Check for pwm6, fan6 */
3125                 if (!(reg & BIT(7))) {
3126                         sio_data->skip_pwm |= BIT(5);
3127                         sio_data->skip_fan |= BIT(5);
3128                 }
3129
3130                 /* Check if AVCC is on VIN3 */
3131                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3132                 if (reg & BIT(0)) {
3133                         /* For it8686, the bit just enables AVCC3 */
3134                         if (sio_data->type != it8686)
3135                                 sio_data->internal |= BIT(0);
3136                 } else {
3137                         sio_data->internal &= ~BIT(3);
3138                         sio_data->skip_in |= BIT(9);
3139                 }
3140
3141                 sio_data->beep_pin = superio_inb(sioaddr,
3142                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3143         } else if (sio_data->type == it8622) {
3144                 int reg;
3145
3146                 superio_select(sioaddr, GPIO);
3147
3148                 /* Check for pwm4, fan4 */
3149                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3150                 if (reg & BIT(6))
3151                         sio_data->skip_fan |= BIT(3);
3152                 if (reg & BIT(5))
3153                         sio_data->skip_pwm |= BIT(3);
3154
3155                 /* Check for pwm3, fan3, pwm5, fan5 */
3156                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3157                 if (reg & BIT(6))
3158                         sio_data->skip_pwm |= BIT(2);
3159                 if (reg & BIT(7))
3160                         sio_data->skip_fan |= BIT(2);
3161                 if (reg & BIT(3))
3162                         sio_data->skip_pwm |= BIT(4);
3163                 if (reg & BIT(1))
3164                         sio_data->skip_fan |= BIT(4);
3165
3166                 /* Check for pwm2, fan2 */
3167                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3168                 if (reg & BIT(1))
3169                         sio_data->skip_pwm |= BIT(1);
3170                 if (reg & BIT(2))
3171                         sio_data->skip_fan |= BIT(1);
3172
3173                 /* Check for AVCC */
3174                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3175                 if (!(reg & BIT(0)))
3176                         sio_data->skip_in |= BIT(9);
3177
3178                 sio_data->beep_pin = superio_inb(sioaddr,
3179                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3180         } else if (sio_data->type == it8732) {
3181                 int reg;
3182
3183                 superio_select(sioaddr, GPIO);
3184
3185                 /* Check for pwm2, fan2 */
3186                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3187                 if (reg & BIT(1))
3188                         sio_data->skip_pwm |= BIT(1);
3189                 if (reg & BIT(2))
3190                         sio_data->skip_fan |= BIT(1);
3191
3192                 /* Check for pwm3, fan3, fan4 */
3193                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3194                 if (reg & BIT(6))
3195                         sio_data->skip_pwm |= BIT(2);
3196                 if (reg & BIT(7))
3197                         sio_data->skip_fan |= BIT(2);
3198                 if (reg & BIT(5))
3199                         sio_data->skip_fan |= BIT(3);
3200
3201                 /* Check if AVCC is on VIN3 */
3202                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3203                 if (reg & BIT(0))
3204                         sio_data->internal |= BIT(0);
3205
3206                 sio_data->beep_pin = superio_inb(sioaddr,
3207                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3208         } else if (sio_data->type == it8655) {
3209                 int reg;
3210
3211                 superio_select(sioaddr, GPIO);
3212
3213                 /* Check for pwm2 */
3214                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3215                 if (reg & BIT(1))
3216                         sio_data->skip_pwm |= BIT(1);
3217
3218                 /* Check for fan2 */
3219                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3220                 if (reg & BIT(4))
3221                         sio_data->skip_fan |= BIT(1);
3222
3223                 /* Check for pwm3, fan3 */
3224                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3225                 if (reg & BIT(6))
3226                         sio_data->skip_pwm |= BIT(2);
3227                 if (reg & BIT(7))
3228                         sio_data->skip_fan |= BIT(2);
3229
3230                 sio_data->beep_pin = superio_inb(sioaddr,
3231                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3232         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3233                 int reg27, reg29, reg2d, regd3;
3234
3235                 superio_select(sioaddr, GPIO);
3236
3237                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3238                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3239                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3240                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3241
3242                 /* Check for pwm2, fan2 */
3243                 if (reg29 & BIT(1))
3244                         sio_data->skip_pwm |= BIT(1);
3245                 if (reg2d & BIT(4))
3246                         sio_data->skip_fan |= BIT(1);
3247
3248                 /* Check for pwm3, fan3 */
3249                 if (reg27 & BIT(6))
3250                         sio_data->skip_pwm |= BIT(2);
3251                 if (reg27 & BIT(7))
3252                         sio_data->skip_fan |= BIT(2);
3253
3254                 /* Check for pwm4, fan4, pwm5, fan5 */
3255                 if (sio_data->type == it8625) {
3256                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3257
3258                         if (reg25 & BIT(6))
3259                                 sio_data->skip_fan |= BIT(3);
3260                         if (reg25 & BIT(5))
3261                                 sio_data->skip_pwm |= BIT(3);
3262                         if (reg27 & BIT(3))
3263                                 sio_data->skip_pwm |= BIT(4);
3264                         if (reg27 & BIT(1))
3265                                 sio_data->skip_fan |= BIT(4);
3266                 } else {
3267                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3268
3269                         if (regd3 & BIT(2))
3270                                 sio_data->skip_pwm |= BIT(3);
3271                         if (regd3 & BIT(3))
3272                                 sio_data->skip_fan |= BIT(3);
3273                         if (reg26 & BIT(5))
3274                                 sio_data->skip_pwm |= BIT(4);
3275                         if (!(reg26 & BIT(4)))
3276                                 sio_data->skip_fan |= BIT(4);
3277                 }
3278
3279                 /* Check for pwm6, fan6 */
3280                 if (regd3 & BIT(0))
3281                         sio_data->skip_pwm |= BIT(5);
3282                 if (regd3 & BIT(1))
3283                         sio_data->skip_fan |= BIT(5);
3284
3285                 sio_data->beep_pin = superio_inb(sioaddr,
3286                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3287         } else {
3288                 int reg;
3289                 bool uart6;
3290
3291                 superio_select(sioaddr, GPIO);
3292
3293                 /* Check for fan4, fan5 */
3294                 if (has_five_fans(config)) {
3295                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3296                         switch (sio_data->type) {
3297                         case it8718:
3298                                 if (reg & BIT(5))
3299                                         sio_data->skip_fan |= BIT(3);
3300                                 if (reg & BIT(4))
3301                                         sio_data->skip_fan |= BIT(4);
3302                                 break;
3303                         case it8720:
3304                         case it8721:
3305                         case it8728:
3306                                 if (!(reg & BIT(5)))
3307                                         sio_data->skip_fan |= BIT(3);
3308                                 if (!(reg & BIT(4)))
3309                                         sio_data->skip_fan |= BIT(4);
3310                                 break;
3311                         default:
3312                                 break;
3313                         }
3314                 }
3315
3316                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3317                 if (!sio_data->skip_vid) {
3318                         /* We need at least 4 VID pins */
3319                         if (reg & 0x0f) {
3320                                 pr_info("VID is disabled (pins used for GPIO)\n");
3321                                 sio_data->skip_vid = 1;
3322                         }
3323                 }
3324
3325                 /* Check if fan3 is there or not */
3326                 if (reg & BIT(6))
3327                         sio_data->skip_pwm |= BIT(2);
3328                 if (reg & BIT(7))
3329                         sio_data->skip_fan |= BIT(2);
3330
3331                 /* Check if fan2 is there or not */
3332                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3333                 if (reg & BIT(1))
3334                         sio_data->skip_pwm |= BIT(1);
3335                 if (reg & BIT(2))
3336                         sio_data->skip_fan |= BIT(1);
3337
3338                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3339                     !(sio_data->skip_vid))
3340                         sio_data->vid_value = superio_inb(sioaddr,
3341                                                           IT87_SIO_VID_REG);
3342
3343                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3344
3345                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3346
3347                 /*
3348                  * The IT8720F has no VIN7 pin, so VCCH should always be
3349                  * routed internally to VIN7 with an internal divider.
3350                  * Curiously, there still is a configuration bit to control
3351                  * this, which means it can be set incorrectly. And even
3352                  * more curiously, many boards out there are improperly
3353                  * configured, even though the IT8720F datasheet claims
3354                  * that the internal routing of VCCH to VIN7 is the default
3355                  * setting. So we force the internal routing in this case.
3356                  *
3357                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3358                  * If UART6 is enabled, re-route VIN7 to the internal divider
3359                  * if that is not already the case.
3360                  */
3361                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3362                         reg |= BIT(1);
3363                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3364                         pr_notice("Routing internal VCCH to in7\n");
3365                 }
3366                 if (reg & BIT(0))
3367                         sio_data->internal |= BIT(0);
3368                 if (reg & BIT(1))
3369                         sio_data->internal |= BIT(1);
3370
3371                 /*
3372                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3373                  * While VIN7 can be routed to the internal voltage divider,
3374                  * VIN5 and VIN6 are not available if UART6 is enabled.
3375                  *
3376                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3377                  * is the temperature source. Since we can not read the
3378                  * temperature source here, skip_temp is preliminary.
3379                  */
3380                 if (uart6) {
3381                         sio_data->skip_in |= BIT(5) | BIT(6);
3382                         sio_data->skip_temp |= BIT(2);
3383                 }
3384
3385                 sio_data->beep_pin = superio_inb(sioaddr,
3386                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3387         }
3388         if (sio_data->beep_pin)
3389                 pr_info("Beeping is supported\n");
3390
3391 exit:
3392         superio_exit(sioaddr, doexit);
3393         return err;
3394 }
3395
3396 static void it87_init_regs(struct platform_device *pdev)
3397 {
3398         struct it87_data *data = platform_get_drvdata(pdev);
3399
3400         /* Initialize chip specific register pointers */
3401         switch (data->type) {
3402         case it8628:
3403         case it8686:
3404                 data->REG_FAN = IT87_REG_FAN;
3405                 data->REG_FANX = IT87_REG_FANX;
3406                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3407                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3408                 data->REG_PWM = IT87_REG_PWM;
3409                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3410                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3411                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3412                 break;
3413         case it8625:
3414         case it8655:
3415         case it8665:
3416                 data->REG_FAN = IT87_REG_FAN_8665;
3417                 data->REG_FANX = IT87_REG_FANX_8665;
3418                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3419                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3420                 data->REG_PWM = IT87_REG_PWM_8665;
3421                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3422                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3423                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3424                 break;
3425         case it8622:
3426                 data->REG_FAN = IT87_REG_FAN;
3427                 data->REG_FANX = IT87_REG_FANX;
3428                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3429                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3430                 data->REG_PWM = IT87_REG_PWM_8665;
3431                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3432                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3433                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3434                 break;
3435         case it8613:
3436                 data->REG_FAN = IT87_REG_FAN;
3437                 data->REG_FANX = IT87_REG_FANX;
3438                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3439                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3440                 data->REG_PWM = IT87_REG_PWM_8665;
3441                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3442                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3443                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3444                 break;
3445         default:
3446                 data->REG_FAN = IT87_REG_FAN;
3447                 data->REG_FANX = IT87_REG_FANX;
3448                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3449                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3450                 data->REG_PWM = IT87_REG_PWM;
3451                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3452                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3453                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3454                 break;
3455         }
3456 }
3457
3458 /* Called when we have found a new IT87. */
3459 static void it87_init_device(struct platform_device *pdev)
3460 {
3461         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3462         struct it87_data *data = platform_get_drvdata(pdev);
3463         int tmp, i;
3464         u8 mask;
3465
3466         /*
3467          * For each PWM channel:
3468          * - If it is in automatic mode, setting to manual mode should set
3469          *   the fan to full speed by default.
3470          * - If it is in manual mode, we need a mapping to temperature
3471          *   channels to use when later setting to automatic mode later.
3472          *   Use a 1:1 mapping by default (we are clueless.)
3473          * In both cases, the value can (and should) be changed by the user
3474          * prior to switching to a different mode.
3475          * Note that this is no longer needed for the IT8721F and later, as
3476          * these have separate registers for the temperature mapping and the
3477          * manual duty cycle.
3478          */
3479         for (i = 0; i < NUM_AUTO_PWM; i++) {
3480                 data->pwm_temp_map[i] = i;
3481                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3482                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3483         }
3484
3485         /*
3486          * Some chips seem to have default value 0xff for all limit
3487          * registers. For low voltage limits it makes no sense and triggers
3488          * alarms, so change to 0 instead. For high temperature limits, it
3489          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3490          * but is still confusing, so change to 127 degrees C.
3491          */
3492         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3493                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3494                 if (tmp == 0xff)
3495                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3496         }
3497         for (i = 0; i < data->num_temp_limit; i++) {
3498                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3499                 if (tmp == 0xff)
3500                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3501         }
3502
3503         /*
3504          * Temperature channels are not forcibly enabled, as they can be
3505          * set to two different sensor types and we can't guess which one
3506          * is correct for a given system. These channels can be enabled at
3507          * run-time through the temp{1-3}_type sysfs accessors if needed.
3508          */
3509
3510         /* Check if voltage monitors are reset manually or by some reason */
3511         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3512         if ((tmp & 0xff) == 0) {
3513                 /* Enable all voltage monitors */
3514                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3515         }
3516
3517         /* Check if tachometers are reset manually or by some reason */
3518         mask = 0x70 & ~(sio_data->skip_fan << 4);
3519         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3520         if ((data->fan_main_ctrl & mask) == 0) {
3521                 /* Enable all fan tachometers */
3522                 data->fan_main_ctrl |= mask;
3523                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3524                                  data->fan_main_ctrl);
3525         }
3526         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3527
3528         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3529
3530         /* Set tachometers to 16-bit mode if needed */
3531         if (has_fan16_config(data)) {
3532                 if (~tmp & 0x07 & data->has_fan) {
3533                         dev_dbg(&pdev->dev,
3534                                 "Setting fan1-3 to 16-bit mode\n");
3535                         it87_write_value(data, IT87_REG_FAN_16BIT,
3536                                          tmp | 0x07);
3537                 }
3538         }
3539
3540         /* Check for additional fans */
3541         if (has_four_fans(data) && (tmp & BIT(4)))
3542                 data->has_fan |= BIT(3); /* fan4 enabled */
3543         if (has_five_fans(data) && (tmp & BIT(5)))
3544                 data->has_fan |= BIT(4); /* fan5 enabled */
3545         if (has_six_fans(data)) {
3546                 switch (data->type) {
3547                 case it8620:
3548                 case it8628:
3549                 case it8686:
3550                         if (tmp & BIT(2))
3551                                 data->has_fan |= BIT(5); /* fan6 enabled */
3552                         break;
3553                 case it8625:
3554                 case it8665:
3555                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3556                         if (tmp & BIT(3))
3557                                 data->has_fan |= BIT(5); /* fan6 enabled */
3558                         break;
3559                 default:
3560                         break;
3561                 }
3562         }
3563
3564         /* Fan input pins may be used for alternative functions */
3565         data->has_fan &= ~sio_data->skip_fan;
3566
3567         /* Check if pwm6 is enabled */
3568         if (has_six_pwm(data)) {
3569                 switch (data->type) {
3570                 case it8620:
3571                 case it8686:
3572                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3573                         if (!(tmp & BIT(3)))
3574                                 sio_data->skip_pwm |= BIT(5);
3575                         break;
3576                 default:
3577                         break;
3578                 }
3579         }
3580
3581         /* Start monitoring */
3582         it87_write_value(data, IT87_REG_CONFIG,
3583                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3584                          | (update_vbat ? 0x41 : 0x01));
3585 }
3586
3587 /* Return 1 if and only if the PWM interface is safe to use */
3588 static int it87_check_pwm(struct device *dev)
3589 {
3590         struct it87_data *data = dev_get_drvdata(dev);
3591         /*
3592          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3593          * and polarity set to active low is sign that this is the case so we
3594          * disable pwm control to protect the user.
3595          */
3596         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3597
3598         if ((tmp & 0x87) == 0) {
3599                 if (fix_pwm_polarity) {
3600                         /*
3601                          * The user asks us to attempt a chip reconfiguration.
3602                          * This means switching to active high polarity and
3603                          * inverting all fan speed values.
3604                          */
3605                         int i;
3606                         u8 pwm[3];
3607
3608                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3609                                 pwm[i] = it87_read_value(data,
3610                                                          data->REG_PWM[i]);
3611
3612                         /*
3613                          * If any fan is in automatic pwm mode, the polarity
3614                          * might be correct, as suspicious as it seems, so we
3615                          * better don't change anything (but still disable the
3616                          * PWM interface).
3617                          */
3618                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3619                                 dev_info(dev,
3620                                          "Reconfiguring PWM to active high polarity\n");
3621                                 it87_write_value(data, IT87_REG_FAN_CTL,
3622                                                  tmp | 0x87);
3623                                 for (i = 0; i < 3; i++)
3624                                         it87_write_value(data,
3625                                                          data->REG_PWM[i],
3626                                                          0x7f & ~pwm[i]);
3627                                 return 1;
3628                         }
3629
3630                         dev_info(dev,
3631                                  "PWM configuration is too broken to be fixed\n");
3632                 }
3633
3634                 dev_info(dev,
3635                          "Detected broken BIOS defaults, disabling PWM interface\n");
3636                 return 0;
3637         } else if (fix_pwm_polarity) {
3638                 dev_info(dev,
3639                          "PWM configuration looks sane, won't touch\n");
3640         }
3641
3642         return 1;
3643 }
3644
3645 static int it87_probe(struct platform_device *pdev)
3646 {
3647         struct it87_data *data;
3648         struct resource *res;
3649         struct device *dev = &pdev->dev;
3650         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3651         int enable_pwm_interface;
3652         struct device *hwmon_dev;
3653
3654         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3655         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3656                                  DRVNAME)) {
3657                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3658                         (unsigned long)res->start,
3659                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3660                 return -EBUSY;
3661         }
3662
3663         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3664         if (!data)
3665                 return -ENOMEM;
3666
3667         data->addr = res->start;
3668         data->type = sio_data->type;
3669         data->features = it87_devices[sio_data->type].features;
3670         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3671         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3672         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3673         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3674         data->bank = 0xff;
3675
3676         /*
3677          * IT8705F Datasheet 0.4.1, 3h == Version G.
3678          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3679          * These are the first revisions with 16-bit tachometer support.
3680          */
3681         switch (data->type) {
3682         case it87:
3683                 if (sio_data->revision >= 0x03) {
3684                         data->features &= ~FEAT_OLD_AUTOPWM;
3685                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3686                 }
3687                 break;
3688         case it8712:
3689                 if (sio_data->revision >= 0x08) {
3690                         data->features &= ~FEAT_OLD_AUTOPWM;
3691                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3692                                           FEAT_FIVE_FANS;
3693                 }
3694                 break;
3695         default:
3696                 break;
3697         }
3698
3699         /* Now, we do the remaining detection. */
3700         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3701             it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3702                 return -ENODEV;
3703
3704         platform_set_drvdata(pdev, data);
3705
3706         mutex_init(&data->update_lock);
3707
3708         /* Initialize register pointers */
3709         it87_init_regs(pdev);
3710
3711         /* Check PWM configuration */
3712         enable_pwm_interface = it87_check_pwm(dev);
3713
3714         /* Starting with IT8721F, we handle scaling of internal voltages */
3715         if (has_scaling(data)) {
3716                 if (sio_data->internal & BIT(0))
3717                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3718                 if (sio_data->internal & BIT(1))
3719                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3720                 if (sio_data->internal & BIT(2))
3721                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3722                 if (sio_data->internal & BIT(3))
3723                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3724         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3725                    sio_data->type == it8783) {
3726                 if (sio_data->internal & BIT(0))
3727                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3728                 if (sio_data->internal & BIT(1))
3729                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3730         }
3731
3732         data->has_temp = 0x07;
3733         if (sio_data->skip_temp & BIT(2)) {
3734                 if (sio_data->type == it8782 &&
3735                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3736                         data->has_temp &= ~BIT(2);
3737         }
3738
3739         data->in_internal = sio_data->internal;
3740         data->has_in = 0x3ff & ~sio_data->skip_in;
3741
3742         if (has_six_temp(data)) {
3743                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3744
3745                 /* Check for additional temperature sensors */
3746                 if ((reg & 0x03) >= 0x02)
3747                         data->has_temp |= BIT(3);
3748                 if (((reg >> 2) & 0x03) >= 0x02)
3749                         data->has_temp |= BIT(4);
3750                 if (((reg >> 4) & 0x03) >= 0x02)
3751                         data->has_temp |= BIT(5);
3752
3753                 /* Check for additional voltage sensors */
3754                 if ((reg & 0x03) == 0x01)
3755                         data->has_in |= BIT(10);
3756                 if (((reg >> 2) & 0x03) == 0x01)
3757                         data->has_in |= BIT(11);
3758                 if (((reg >> 4) & 0x03) == 0x01)
3759                         data->has_in |= BIT(12);
3760         }
3761
3762         data->has_beep = !!sio_data->beep_pin;
3763
3764         /* Initialize the IT87 chip */
3765         it87_init_device(pdev);
3766
3767         if (!sio_data->skip_vid) {
3768                 data->has_vid = true;
3769                 data->vrm = vid_which_vrm();
3770                 /* VID reading from Super-I/O config space if available */
3771                 data->vid = sio_data->vid_value;
3772         }
3773
3774         /* Prepare for sysfs hooks */
3775         data->groups[0] = &it87_group;
3776         data->groups[1] = &it87_group_in;
3777         data->groups[2] = &it87_group_temp;
3778         data->groups[3] = &it87_group_fan;
3779
3780         if (enable_pwm_interface) {
3781                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3782                 data->has_pwm &= ~sio_data->skip_pwm;
3783
3784                 data->groups[4] = &it87_group_pwm;
3785                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3786                         data->groups[5] = &it87_group_auto_pwm;
3787         }
3788
3789         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3790                                         it87_devices[sio_data->type].name,
3791                                         data, data->groups);
3792         return PTR_ERR_OR_ZERO(hwmon_dev);
3793 }
3794
3795 static struct platform_driver it87_driver = {
3796         .driver = {
3797                 .name   = DRVNAME,
3798         },
3799         .probe  = it87_probe,
3800 };
3801
3802 static int __init it87_device_add(int index, unsigned short address,
3803                                   const struct it87_sio_data *sio_data)
3804 {
3805         struct platform_device *pdev;
3806         struct resource res = {
3807                 .start  = address + IT87_EC_OFFSET,
3808                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3809                 .name   = DRVNAME,
3810                 .flags  = IORESOURCE_IO,
3811         };
3812         int err;
3813
3814         err = acpi_check_resource_conflict(&res);
3815         if (err)
3816                 return err;
3817
3818         pdev = platform_device_alloc(DRVNAME, address);
3819         if (!pdev)
3820                 return -ENOMEM;
3821
3822         err = platform_device_add_resources(pdev, &res, 1);
3823         if (err) {
3824                 pr_err("Device resource addition failed (%d)\n", err);
3825                 goto exit_device_put;
3826         }
3827
3828         err = platform_device_add_data(pdev, sio_data,
3829                                        sizeof(struct it87_sio_data));
3830         if (err) {
3831                 pr_err("Platform data allocation failed\n");
3832                 goto exit_device_put;
3833         }
3834
3835         err = platform_device_add(pdev);
3836         if (err) {
3837                 pr_err("Device addition failed (%d)\n", err);
3838                 goto exit_device_put;
3839         }
3840
3841         it87_pdev[index] = pdev;
3842         return 0;
3843
3844 exit_device_put:
3845         platform_device_put(pdev);
3846         return err;
3847 }
3848
3849 struct it87_dmi_data {
3850         char *sio_mutex;        /* SIO ACPI mutex                       */
3851         u8 skip_pwm;            /* pwm channels to skip for this board  */
3852 };
3853
3854 /*
3855  * On Gigabyte AB350 and AX370 boards, accesses to the Super-IO chip
3856  * at address 0x2e/0x2f need to be mutex protected.
3857  */
3858 static struct it87_dmi_data gigabyte_ab350_gaming = {
3859         .sio_mutex = "\\_SB.PCI0.SBRG.SIO1.MUT0",
3860 };
3861
3862 /*
3863  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3864  * connected to a fan, but to something else. One user
3865  * has reported instant system power-off when changing
3866  * the PWM2 duty cycle, so we disable it.
3867  * I use the board name string as the trigger in case
3868  * the same board is ever used in other systems.
3869  */
3870 static struct it87_dmi_data nvidia_fn68pt = {
3871         .skip_pwm = BIT(1),
3872 };
3873
3874 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3875         {
3876                 .matches = {
3877                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3878                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming-CF"),
3879                 },
3880                 .driver_data = &gigabyte_ab350_gaming,
3881         },
3882         {
3883                 .matches = {
3884                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3885                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming 3-CF"),
3886                 },
3887                 .driver_data = &gigabyte_ab350_gaming,
3888         },
3889         {
3890                 .matches = {
3891                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3892                         DMI_MATCH(DMI_BOARD_NAME, "AB350M-D3H-CF"),
3893                 },
3894                 .driver_data = &gigabyte_ab350_gaming,
3895         },
3896         {
3897                 .matches = {
3898                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3899                         DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming K7"),
3900                 },
3901                 .driver_data = &gigabyte_ab350_gaming,
3902         },
3903         {
3904                 .matches = {
3905                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3906                         DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming 5"),
3907                 },
3908                 .driver_data = &gigabyte_ab350_gaming,
3909         },
3910         {
3911                 .matches = {
3912                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3913                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3914                 },
3915                 .driver_data = &nvidia_fn68pt,
3916         },
3917         { }
3918 };
3919
3920 static int __init sm_it87_init(void)
3921 {
3922         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3923         struct it87_dmi_data *dmi_data = NULL;
3924         int sioaddr[2] = { REG_2E, REG_4E };
3925         struct it87_sio_data sio_data;
3926         unsigned short isa_address;
3927         bool found = false;
3928         int i, err;
3929
3930         if (dmi)
3931                 dmi_data = dmi->driver_data;
3932
3933         if (dmi_data) {
3934 #ifdef __IT87_USE_ACPI_MUTEX
3935                 if (dmi_data->sio_mutex) {
3936                         static acpi_status status;
3937
3938                         status = acpi_get_handle(NULL, dmi_data->sio_mutex,
3939                                                  &it87_acpi_sio_handle);
3940                         if (ACPI_SUCCESS(status)) {
3941                                 it87_acpi_sio_mutex = dmi_data->sio_mutex;
3942                                 pr_debug("Found ACPI SIO mutex %s\n",
3943                                          dmi_data->sio_mutex);
3944                         } else {
3945                                 pr_warn("ACPI SIO mutex %s not found\n",
3946                                         dmi_data->sio_mutex);
3947                         }
3948                 }
3949 #endif /* __IT87_USE_ACPI_MUTEX */
3950         }
3951
3952         err = platform_driver_register(&it87_driver);
3953         if (err)
3954                 return err;
3955
3956         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3957                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3958                 isa_address = 0;
3959                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3960                 if (err || isa_address == 0)
3961                         continue;
3962
3963                 if (dmi_data)
3964                         sio_data.skip_pwm |= dmi_data->skip_pwm;
3965                 err = it87_device_add(i, isa_address, &sio_data);
3966                 if (err)
3967                         goto exit_dev_unregister;
3968                 found = true;
3969         }
3970
3971         if (!found) {
3972                 err = -ENODEV;
3973                 goto exit_unregister;
3974         }
3975         return 0;
3976
3977 exit_dev_unregister:
3978         /* NULL check handled by platform_device_unregister */
3979         platform_device_unregister(it87_pdev[0]);
3980 exit_unregister:
3981         platform_driver_unregister(&it87_driver);
3982         return err;
3983 }
3984
3985 static void __exit sm_it87_exit(void)
3986 {
3987         /* NULL check handled by platform_device_unregister */
3988         platform_device_unregister(it87_pdev[1]);
3989         platform_device_unregister(it87_pdev[0]);
3990         platform_driver_unregister(&it87_driver);
3991 }
3992
3993 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3994 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3995 module_param(update_vbat, bool, 0);
3996 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3997 module_param(fix_pwm_polarity, bool, 0);
3998 MODULE_PARM_DESC(fix_pwm_polarity,
3999                  "Force PWM polarity to active high (DANGEROUS)");
4000 MODULE_LICENSE("GPL");
4001
4002 module_init(sm_it87_init);
4003 module_exit(sm_it87_exit);