git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77
  78 #ifndef IT87_DRIVER_VERSION
  79 #define IT87_DRIVER_VERSION     "<not provided>"
  80 #endif
  81
  82 #define DRVNAME "it87"
  83
  84 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  85              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  86              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  87              it8655, it8665, it8686 };
  88
  89 static unsigned short force_id;
  90 module_param(force_id, ushort, 0000);
  91 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  92
  93 static bool ignore_resource_conflict;
  94 module_param(ignore_resource_conflict, bool, 0000);
  95 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
  96
  97 static bool mmio;
  98 module_param(mmio, bool, 0000);
  99 MODULE_PARM_DESC(mmio, "Use MMIO if available");
 100
 101 static struct platform_device *it87_pdev[2];
 102
 103 #define REG_2E  0x2e    /* The register to read/write */
 104 #define REG_4E  0x4e    /* Secondary register to read/write */
 105
 106 #define DEV     0x07    /* Register: Logical device select */
 107 #define PME     0x04    /* The device with the fan registers in it */
 108
 109 /* The device with the IT8718F/IT8720F VID value in it */
 110 #define GPIO    0x07
 111
 112 #define DEVID   0x20    /* Register: Device ID */
 113 #define DEVREV  0x22    /* Register: Device Revision */
 114
 115 static inline void __superio_enter(int ioreg)
 116 {
 117         outb(0x87, ioreg);
 118         outb(0x01, ioreg);
 119         outb(0x55, ioreg);
 120         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 121 }
 122
 123 static inline int superio_inb(int ioreg, int reg)
 124 {
 125         int val;
 126
 127         outb(reg, ioreg);
 128         val = inb(ioreg + 1);
 129
 130         return val;
 131 }
 132
 133 static inline void superio_outb(int ioreg, int reg, int val)
 134 {
 135         outb(reg, ioreg);
 136         outb(val, ioreg + 1);
 137 }
 138
 139 static int superio_inw(int ioreg, int reg)
 140 {
 141         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 142 }
 143
 144 static inline void superio_select(int ioreg, int ldn)
 145 {
 146         outb(DEV, ioreg);
 147         outb(ldn, ioreg + 1);
 148 }
 149
 150 static inline int superio_enter(int ioreg)
 151 {
 152         /*
 153          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 154          */
 155         if (!request_muxed_region(ioreg, 2, DRVNAME))
 156                 return -EBUSY;
 157
 158         __superio_enter(ioreg);
 159         return 0;
 160 }
 161
 162 static inline void superio_exit(int ioreg, bool doexit)
 163 {
 164         if (doexit) {
 165                 outb(0x02, ioreg);
 166                 outb(0x02, ioreg + 1);
 167         }
 168         release_region(ioreg, 2);
 169 }
 170
 171 /* Logical device 4 registers */
 172 #define IT8712F_DEVID 0x8712
 173 #define IT8705F_DEVID 0x8705
 174 #define IT8716F_DEVID 0x8716
 175 #define IT8718F_DEVID 0x8718
 176 #define IT8720F_DEVID 0x8720
 177 #define IT8721F_DEVID 0x8721
 178 #define IT8726F_DEVID 0x8726
 179 #define IT8728F_DEVID 0x8728
 180 #define IT8732F_DEVID 0x8732
 181 #define IT8792E_DEVID 0x8733
 182 #define IT8771E_DEVID 0x8771
 183 #define IT8772E_DEVID 0x8772
 184 #define IT8781F_DEVID 0x8781
 185 #define IT8782F_DEVID 0x8782
 186 #define IT8783E_DEVID 0x8783
 187 #define IT8786E_DEVID 0x8786
 188 #define IT8790E_DEVID 0x8790
 189 #define IT8603E_DEVID 0x8603
 190 #define IT8607E_DEVID 0x8607
 191 #define IT8613E_DEVID 0x8613
 192 #define IT8620E_DEVID 0x8620
 193 #define IT8622E_DEVID 0x8622
 194 #define IT8623E_DEVID 0x8623
 195 #define IT8625E_DEVID 0x8625
 196 #define IT8628E_DEVID 0x8628
 197 #define IT8655E_DEVID 0x8655
 198 #define IT8665E_DEVID 0x8665
 199 #define IT8686E_DEVID 0x8686
 200
 201 /* Logical device 4 (Environmental Monitor) registers */
 202 #define IT87_ACT_REG            0x30
 203 #define IT87_BASE_REG           0x60
 204 #define IT87_SPECIAL_CFG_REG    0xf3    /* special configuration register */
 205
 206 /* Global configuration registers (IT8712F and later) */
 207 #define IT87_EC_HWM_MIO_REG     0x24    /* MMIO configuration register */
 208 #define IT87_SIO_GPIO1_REG      0x25
 209 #define IT87_SIO_GPIO2_REG      0x26
 210 #define IT87_SIO_GPIO3_REG      0x27
 211 #define IT87_SIO_GPIO4_REG      0x28
 212 #define IT87_SIO_GPIO5_REG      0x29
 213 #define IT87_SIO_GPIO9_REG      0xd3
 214 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 215 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 216 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 217
 218 /* Logical device 7 (GPIO) registers (IT8712F and later) */
 219 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 220 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 221 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 222
 223 /* Update battery voltage after every reading if true */
 224 static bool update_vbat;
 225
 226 /* Not all BIOSes properly configure the PWM registers */
 227 static bool fix_pwm_polarity;
 228
 229 /* Many IT87 constants specified below */
 230
 231 /* Length of ISA address segment */
 232 #define IT87_EXTENT 8
 233
 234 /* Length of ISA address segment for Environmental Controller */
 235 #define IT87_EC_EXTENT 2
 236
 237 /* Offset of EC registers from ISA base address */
 238 #define IT87_EC_OFFSET 5
 239
 240 /* Where are the ISA address/data registers relative to the EC base address */
 241 #define IT87_ADDR_REG_OFFSET 0
 242 #define IT87_DATA_REG_OFFSET 1
 243
 244 /*----- The IT87 registers -----*/
 245
 246 #define IT87_REG_CONFIG        0x00
 247
 248 #define IT87_REG_ALARM1        0x01
 249 #define IT87_REG_ALARM2        0x02
 250 #define IT87_REG_ALARM3        0x03
 251
 252 #define IT87_REG_BANK           0x06
 253
 254 /*
 255  * The IT8718F and IT8720F have the VID value in a different register, in
 256  * Super-I/O configuration space.
 257  */
 258 #define IT87_REG_VID           0x0a
 259 /*
 260  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 261  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 262  * mode.
 263  */
 264 #define IT87_REG_FAN_DIV       0x0b
 265 #define IT87_REG_FAN_16BIT     0x0c
 266
 267 /*
 268  * Monitors:
 269  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 270  * - up to 6 temp (1 to 6)
 271  * - up to 6 fan (1 to 6)
 272  */
 273
 274 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 275 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 276 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 277 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 278
 279 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 280 static const u8 IT87_REG_FAN_MIN_8665[] =
 281                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 282 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 283 static const u8 IT87_REG_FANX_MIN_8665[] =
 284                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 285
 286 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 287
 288 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 289
 290 #define IT87_REG_FAN_MAIN_CTRL 0x13
 291 #define IT87_REG_FAN_CTL       0x14
 292
 293 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 294 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 295
 296 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 297
 298 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 299                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 300
 301 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 302
 303 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 304 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 305
 306 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 307 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 308
 309 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 310                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 311 static const u8 IT87_REG_TEMP_LOW_8686[] =
 312                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 313
 314 #define IT87_REG_VIN_ENABLE    0x50
 315 #define IT87_REG_TEMP_ENABLE   0x51
 316 #define IT87_REG_TEMP_EXTRA    0x55
 317 #define IT87_REG_BEEP_ENABLE   0x5c
 318
 319 #define IT87_REG_CHIPID        0x58
 320
 321 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 322
 323 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 324 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 325
 326 #define IT87_REG_TEMP456_ENABLE 0x77
 327
 328 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 329 #define IT87_REG_TEMP_SRC2      0x23d
 330
 331 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 332 #define NUM_VIN_LIMIT           8
 333 #define NUM_TEMP                6
 334 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 335 #define NUM_FAN_DIV             3
 336 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 337 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 338
 339 struct it87_devices {
 340         const char *name;
 341         const char * const suffix;
 342         u32 features;
 343         u8 num_temp_limit;
 344         u8 num_temp_offset;
 345         u8 num_temp_map;        /* Number of temperature sources for pwm */
 346         u8 peci_mask;
 347         u8 old_peci_mask;
 348         u8 smbus_bitmap;        /* SMBus enable bits in extra config register */
 349         u8 ec_special_config;
 350 };
 351
 352 #define FEAT_12MV_ADC           BIT(0)
 353 #define FEAT_NEWER_AUTOPWM      BIT(1)
 354 #define FEAT_OLD_AUTOPWM        BIT(2)
 355 #define FEAT_16BIT_FANS         BIT(3)
 356 #define FEAT_TEMP_PECI          BIT(5)
 357 #define FEAT_TEMP_OLD_PECI      BIT(6)
 358 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 359 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 360 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 361 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 362 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 363 #define FEAT_10_9MV_ADC         BIT(12)
 364 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 365 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 366 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 367 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 368 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 369 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 370 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 371 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 372 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 373 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 374 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 375 #define FEAT_11MV_ADC           BIT(24)
 376 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 377 #define FEAT_MMIO               BIT(26) /* Chip supports MMIO */
 378 #define FEAT_FOUR_TEMP          BIT(27)
 379
 380 static const struct it87_devices it87_devices[] = {
 381         [it87] = {
 382                 .name = "it87",
 383                 .suffix = "F",
 384                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 385                                                 /* may need to overwrite */
 386                 .num_temp_limit = 3,
 387                 .num_temp_offset = 0,
 388                 .num_temp_map = 3,
 389         },
 390         [it8712] = {
 391                 .name = "it8712",
 392                 .suffix = "F",
 393                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 394                                                 /* may need to overwrite */
 395                 .num_temp_limit = 3,
 396                 .num_temp_offset = 0,
 397                 .num_temp_map = 3,
 398         },
 399         [it8716] = {
 400                 .name = "it8716",
 401                 .suffix = "F",
 402                 .features = FEAT_16BIT_FANS | FEAT_VID
 403                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 404                   | FEAT_FANCTL_ONOFF,
 405                 .num_temp_limit = 3,
 406                 .num_temp_offset = 3,
 407                 .num_temp_map = 3,
 408         },
 409         [it8718] = {
 410                 .name = "it8718",
 411                 .suffix = "F",
 412                 .features = FEAT_16BIT_FANS | FEAT_VID
 413                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 414                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 415                 .num_temp_limit = 3,
 416                 .num_temp_offset = 3,
 417                 .num_temp_map = 3,
 418                 .old_peci_mask = 0x4,
 419         },
 420         [it8720] = {
 421                 .name = "it8720",
 422                 .suffix = "F",
 423                 .features = FEAT_16BIT_FANS | FEAT_VID
 424                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 425                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 426                 .num_temp_limit = 3,
 427                 .num_temp_offset = 3,
 428                 .num_temp_map = 3,
 429                 .old_peci_mask = 0x4,
 430         },
 431         [it8721] = {
 432                 .name = "it8721",
 433                 .suffix = "F",
 434                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 435                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 436                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 437                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 438                 .num_temp_limit = 3,
 439                 .num_temp_offset = 3,
 440                 .num_temp_map = 3,
 441                 .peci_mask = 0x05,
 442                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 443         },
 444         [it8728] = {
 445                 .name = "it8728",
 446                 .suffix = "F",
 447                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 448                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 449                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 450                   | FEAT_FANCTL_ONOFF,
 451                 .num_temp_limit = 6,
 452                 .num_temp_offset = 3,
 453                 .num_temp_map = 3,
 454                 .peci_mask = 0x07,
 455         },
 456         [it8732] = {
 457                 .name = "it8732",
 458                 .suffix = "F",
 459                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 460                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 461                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 462                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 463                 .num_temp_limit = 3,
 464                 .num_temp_offset = 3,
 465                 .num_temp_map = 3,
 466                 .peci_mask = 0x07,
 467                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 468         },
 469         [it8771] = {
 470                 .name = "it8771",
 471                 .suffix = "E",
 472                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 473                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 474                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 475                                 /* PECI: guesswork */
 476                                 /* 12mV ADC (OHM) */
 477                                 /* 16 bit fans (OHM) */
 478                                 /* three fans, always 16 bit (guesswork) */
 479                 .num_temp_limit = 3,
 480                 .num_temp_offset = 3,
 481                 .num_temp_map = 3,
 482                 .peci_mask = 0x07,
 483         },
 484         [it8772] = {
 485                 .name = "it8772",
 486                 .suffix = "E",
 487                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 488                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 489                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 490                                 /* PECI (coreboot) */
 491                                 /* 12mV ADC (HWSensors4, OHM) */
 492                                 /* 16 bit fans (HWSensors4, OHM) */
 493                                 /* three fans, always 16 bit (datasheet) */
 494                 .num_temp_limit = 3,
 495                 .num_temp_offset = 3,
 496                 .num_temp_map = 3,
 497                 .peci_mask = 0x07,
 498         },
 499         [it8781] = {
 500                 .name = "it8781",
 501                 .suffix = "F",
 502                 .features = FEAT_16BIT_FANS
 503                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 504                   | FEAT_FANCTL_ONOFF,
 505                 .num_temp_limit = 3,
 506                 .num_temp_offset = 3,
 507                 .num_temp_map = 3,
 508                 .old_peci_mask = 0x4,
 509         },
 510         [it8782] = {
 511                 .name = "it8782",
 512                 .suffix = "F",
 513                 .features = FEAT_16BIT_FANS
 514                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 515                   | FEAT_FANCTL_ONOFF,
 516                 .num_temp_limit = 3,
 517                 .num_temp_offset = 3,
 518                 .num_temp_map = 3,
 519                 .old_peci_mask = 0x4,
 520         },
 521         [it8783] = {
 522                 .name = "it8783",
 523                 .suffix = "E/F",
 524                 .features = FEAT_16BIT_FANS
 525                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 526                   | FEAT_FANCTL_ONOFF,
 527                 .num_temp_limit = 3,
 528                 .num_temp_offset = 3,
 529                 .num_temp_map = 3,
 530                 .old_peci_mask = 0x4,
 531         },
 532         [it8786] = {
 533                 .name = "it8786",
 534                 .suffix = "E",
 535                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 536                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 537                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 538                 .num_temp_limit = 3,
 539                 .num_temp_offset = 3,
 540                 .num_temp_map = 3,
 541                 .peci_mask = 0x07,
 542         },
 543         [it8790] = {
 544                 .name = "it8790",
 545                 .suffix = "E",
 546                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 547                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 548                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 549                 .num_temp_limit = 3,
 550                 .num_temp_offset = 3,
 551                 .num_temp_map = 3,
 552                 .peci_mask = 0x07,
 553         },
 554         [it8792] = {
 555                 .name = "it8792",
 556                 .suffix = "E",
 557                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 558                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 559                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 560                 .num_temp_limit = 3,
 561                 .num_temp_offset = 3,
 562                 .num_temp_map = 3,
 563                 .peci_mask = 0x07,
 564         },
 565         [it8603] = {
 566                 .name = "it8603",
 567                 .suffix = "E",
 568                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 569                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 570                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 571                 .num_temp_limit = 3,
 572                 .num_temp_offset = 3,
 573                 .num_temp_map = 4,
 574                 .peci_mask = 0x07,
 575         },
 576         [it8607] = {
 577                 .name = "it8607",
 578                 .suffix = "E",
 579                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 580                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 581                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 582                   | FEAT_FANCTL_ONOFF,
 583                 .num_temp_limit = 3,
 584                 .num_temp_offset = 3,
 585                 .num_temp_map = 6,
 586                 .peci_mask = 0x07,
 587         },
 588         [it8613] = {
 589                 .name = "it8613",
 590                 .suffix = "E",
 591                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 592                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 593                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 594                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 595                 .num_temp_limit = 6,
 596                 .num_temp_offset = 6,
 597                 .num_temp_map = 6,
 598                 .peci_mask = 0x07,
 599         },
 600         [it8620] = {
 601                 .name = "it8620",
 602                 .suffix = "E",
 603                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 604                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 605                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 606                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 607                   | FEAT_FANCTL_ONOFF,
 608                 .num_temp_limit = 3,
 609                 .num_temp_offset = 3,
 610                 .num_temp_map = 3,
 611                 .peci_mask = 0x07,
 612         },
 613         [it8622] = {
 614                 .name = "it8622",
 615                 .suffix = "E",
 616                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 617                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
 618                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 619                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 620                 .num_temp_limit = 3,
 621                 .num_temp_offset = 3,
 622                 .num_temp_map = 4,
 623                 .peci_mask = 0x0f,
 624                 .smbus_bitmap = BIT(1) | BIT(2),
 625         },
 626         [it8625] = {
 627                 .name = "it8625",
 628                 .suffix = "E",
 629                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 630                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 631                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 632                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 633                 .num_temp_limit = 6,
 634                 .num_temp_offset = 6,
 635                 .num_temp_map = 6,
 636                 .smbus_bitmap = BIT(1) | BIT(2),
 637         },
 638         [it8628] = {
 639                 .name = "it8628",
 640                 .suffix = "E",
 641                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 642                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 643                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 644                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 645                   | FEAT_FANCTL_ONOFF,
 646                 .num_temp_limit = 6,
 647                 .num_temp_offset = 3,
 648                 .num_temp_map = 3,
 649                 .peci_mask = 0x07,
 650         },
 651         [it8655] = {
 652                 .name = "it8655",
 653                 .suffix = "E",
 654                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 655                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 656                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
 657                   | FEAT_MMIO,
 658                 .num_temp_limit = 6,
 659                 .num_temp_offset = 6,
 660                 .num_temp_map = 6,
 661                 .smbus_bitmap = BIT(2),
 662         },
 663         [it8665] = {
 664                 .name = "it8665",
 665                 .suffix = "E",
 666                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 667                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 668                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 669                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO,
 670                 .num_temp_limit = 6,
 671                 .num_temp_offset = 6,
 672                 .num_temp_map = 6,
 673                 .smbus_bitmap = BIT(2),
 674         },
 675         [it8686] = {
 676                 .name = "it8686",
 677                 .suffix = "E",
 678                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 679                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 680                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 681                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 682                 .num_temp_limit = 6,
 683                 .num_temp_offset = 6,
 684                 .num_temp_map = 7,
 685                 .smbus_bitmap = BIT(1) | BIT(2),
 686         },
 687 };
 688
 689 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 690 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 691 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 692 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 693 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 694 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 695                                  ((data)->peci_mask & BIT(nr)))
 696 #define has_temp_old_peci(data, nr) \
 697                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 698                                  ((data)->old_peci_mask & BIT(nr)))
 699 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 700 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 701                                                      FEAT_SIX_FANS))
 702 #define has_vid(data)           ((data)->features & FEAT_VID)
 703 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 704 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 705 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 706 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 707                                                      | FEAT_SIX_PWM))
 708 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 709 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 710 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 711 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 712 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 713                                                      FEAT_FIVE_FANS | \
 714                                                      FEAT_SIX_FANS))
 715 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 716                                                      FEAT_FIVE_PWM \
 717                                                      | FEAT_SIX_PWM))
 718 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 719 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 720 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 721 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 722 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 723 #define has_mmio(data)          ((data)->features & FEAT_MMIO)
 724 #define has_four_temp(data)     ((data)->features & FEAT_FOUR_TEMP)
 725
 726 struct it87_sio_data {
 727         enum chips type;
 728         u8 sioaddr;
 729         u8 doexit;
 730         /* Values read from Super-I/O config space */
 731         u8 revision;
 732         u8 vid_value;
 733         u8 beep_pin;
 734         u8 internal;    /* Internal sensors can be labeled */
 735         /* Features skipped based on config or DMI */
 736         u16 skip_in;
 737         u8 skip_vid;
 738         u8 skip_fan;
 739         u8 skip_pwm;
 740         u8 skip_temp;
 741         u8 smbus_bitmap;
 742         u8 ec_special_config;
 743 };
 744
 745 /*
 746  * For each registered chip, we need to keep some data in memory.
 747  * The structure is dynamically allocated.
 748  */
 749 struct it87_data {
 750         const struct attribute_group *groups[7];
 751         enum chips type;
 752         u32 features;
 753         u8 peci_mask;
 754         u8 old_peci_mask;
 755
 756         u8 smbus_bitmap;        /* !=0 if SMBus needs to be disabled */
 757         u8 ec_special_config;   /* EC special config register restore value */
 758         u8 sioaddr;             /* SIO port address */
 759         bool doexit;            /* true if exit from sio config is ok */
 760
 761         void __iomem *mmio;     /* Remapped MMIO address if available */
 762         int (*read)(struct it87_data *, u16);
 763         void (*write)(struct it87_data *, u16, u8);
 764
 765         const u8 *REG_FAN;
 766         const u8 *REG_FANX;
 767         const u8 *REG_FAN_MIN;
 768         const u8 *REG_FANX_MIN;
 769
 770         const u8 *REG_PWM;
 771
 772         const u8 *REG_TEMP_OFFSET;
 773         const u8 *REG_TEMP_LOW;
 774         const u8 *REG_TEMP_HIGH;
 775
 776         unsigned short addr;
 777         const char *name;
 778         struct mutex update_lock;
 779         char valid;             /* !=0 if following fields are valid */
 780         unsigned long last_updated;     /* In jiffies */
 781
 782         u16 in_scaled;          /* Internal voltage sensors are scaled */
 783         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 784         u16 has_in;             /* Bitfield, voltage sensors enabled */
 785         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 786         u8 has_fan;             /* Bitfield, fans enabled */
 787         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 788         u8 has_temp;            /* Bitfield, temp sensors enabled */
 789         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 790         u8 num_temp_limit;      /* Number of temperature limit registers */
 791         u8 num_temp_offset;     /* Number of temperature offset registers */
 792         u8 temp_src[4];         /* Up to 4 temperature source registers */
 793         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 794         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 795         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 796         bool has_vid;           /* True if VID supported */
 797         u8 vid;                 /* Register encoding, combined */
 798         u8 vrm;
 799         u32 alarms;             /* Register encoding, combined */
 800         bool has_beep;          /* true if beep supported */
 801         u8 beeps;               /* Register encoding */
 802         u8 fan_main_ctrl;       /* Register value */
 803         u8 fan_ctl;             /* Register value */
 804
 805         /*
 806          * The following 3 arrays correspond to the same registers up to
 807          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 808          * 7, and we want to preserve settings on mode changes, so we have
 809          * to track all values separately.
 810          * Starting with the IT8721F, the manual PWM duty cycles are stored
 811          * in separate registers (8-bit values), so the separate tracking
 812          * is no longer needed, but it is still done to keep the driver
 813          * simple.
 814          */
 815         u8 has_pwm;             /* Bitfield, pwm control enabled */
 816         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 817         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 818         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 819         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 820         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 821         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 822
 823         /* Automatic fan speed control registers */
 824         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 825         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 826 };
 827
 828 static int adc_lsb(const struct it87_data *data, int nr)
 829 {
 830         int lsb;
 831
 832         if (has_12mv_adc(data))
 833                 lsb = 120;
 834         else if (has_10_9mv_adc(data))
 835                 lsb = 109;
 836         else if (has_11mv_adc(data))
 837                 lsb = 110;
 838         else
 839                 lsb = 160;
 840         if (data->in_scaled & BIT(nr))
 841                 lsb <<= 1;
 842         return lsb;
 843 }
 844
 845 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 846 {
 847         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 848         return clamp_val(val, 0, 255);
 849 }
 850
 851 static int in_from_reg(const struct it87_data *data, int nr, int val)
 852 {
 853         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 854 }
 855
 856 static inline u8 FAN_TO_REG(long rpm, int div)
 857 {
 858         if (rpm == 0)
 859                 return 255;
 860         rpm = clamp_val(rpm, 1, 1000000);
 861         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 862 }
 863
 864 static inline u16 FAN16_TO_REG(long rpm)
 865 {
 866         if (rpm == 0)
 867                 return 0xffff;
 868         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 869 }
 870
 871 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 872                                 1350000 / ((val) * (div)))
 873 /* The divider is fixed to 2 in 16-bit mode */
 874 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 875                              1350000 / ((val) * 2))
 876
 877 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 878                                     ((val) + 500) / 1000), -128, 127))
 879 #define TEMP_FROM_REG(val) ((val) * 1000)
 880
 881 static u8 pwm_to_reg(const struct it87_data *data, long val)
 882 {
 883         if (has_newer_autopwm(data))
 884                 return val;
 885         else
 886                 return val >> 1;
 887 }
 888
 889 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 890 {
 891         if (has_newer_autopwm(data))
 892                 return reg;
 893         else
 894                 return (reg & 0x7f) << 1;
 895 }
 896
 897 static int DIV_TO_REG(int val)
 898 {
 899         int answer = 0;
 900
 901         while (answer < 7 && (val >>= 1))
 902                 answer++;
 903         return answer;
 904 }
 905
 906 #define DIV_FROM_REG(val) BIT(val)
 907
 908 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 909 {
 910         u8 map;
 911
 912         map  = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 913         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 914                 map = 0;
 915
 916         return map;
 917 }
 918
 919 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 920 {
 921         u8 ctrl = data->pwm_ctrl[nr];
 922
 923         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 924                (map << data->pwm_temp_map_shift);
 925 }
 926
 927 /*
 928  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 929  * depending on the chip type, to calculate the actual PWM frequency.
 930  *
 931  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 932  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 933  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 934  * sometimes just one. It is unknown if this is a datasheet error or real,
 935  * so this is ignored for now.
 936  */
 937 static const unsigned int pwm_freq[8] = {
 938         48000000,
 939         24000000,
 940         12000000,
 941         8000000,
 942         6000000,
 943         3000000,
 944         1500000,
 945         750000,
 946 };
 947
 948 static int smbus_disable(struct it87_data *data)
 949 {
 950         int err;
 951
 952         if (data->smbus_bitmap) {
 953                 err = superio_enter(data->sioaddr);
 954                 if (err)
 955                         return err;
 956                 superio_select(data->sioaddr, PME);
 957                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 958                              data->ec_special_config & ~data->smbus_bitmap);
 959                 superio_exit(data->sioaddr, data->doexit);
 960         }
 961         return 0;
 962 }
 963
 964 static int smbus_enable(struct it87_data *data)
 965 {
 966         int err;
 967
 968         if (data->smbus_bitmap) {
 969                 err = superio_enter(data->sioaddr);
 970                 if (err)
 971                         return err;
 972
 973                 superio_select(data->sioaddr, PME);
 974                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 975                              data->ec_special_config);
 976                 superio_exit(data->sioaddr, data->doexit);
 977         }
 978         return 0;
 979 }
 980
 981 static int _it87_io_read(struct it87_data *data, u16 reg)
 982 {
 983         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 984         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 985 }
 986
 987 static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
 988 {
 989         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 990         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 991 }
 992
 993 static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
 994 {
 995         u8 _bank = bank;
 996
 997         if (has_bank_sel(data)) {
 998                 u8 breg = _it87_io_read(data, IT87_REG_BANK);
 999
1000                 _bank = breg >> 5;
1001                 if (bank != _bank) {
1002                         breg &= 0x1f;
1003                         breg |= (bank << 5);
1004                         _it87_io_write(data, IT87_REG_BANK, breg);
1005                 }
1006         }
1007         return _bank;
1008 }
1009
1010 /*
1011  * Must be called with data->update_lock held, except during initialization.
1012  * Must be called with SMBus accesses disabled.
1013  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1014  * would slow down the IT87 access and should not be necessary.
1015  */
1016 static int it87_io_read(struct it87_data *data, u16 reg)
1017 {
1018         u8 bank;
1019         int val;
1020
1021         bank = it87_io_set_bank(data, reg >> 8);
1022         val = _it87_io_read(data, reg & 0xff);
1023         it87_io_set_bank(data, bank);
1024
1025         return val;
1026 }
1027
1028 /*
1029  * Must be called with data->update_lock held, except during initialization.
1030  * Must be called with SMBus accesses disabled
1031  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1032  * would slow down the IT87 access and should not be necessary.
1033  */
1034 static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1035 {
1036         u8 bank;
1037
1038         bank = it87_io_set_bank(data, reg >> 8);
1039         _it87_io_write(data, reg & 0xff, value);
1040         it87_io_set_bank(data, bank);
1041 }
1042
1043 static int it87_mmio_read(struct it87_data *data, u16 reg)
1044 {
1045         return readb(data->mmio + reg);
1046 }
1047
1048 static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1049 {
1050         writeb(value, data->mmio + reg);
1051 }
1052
1053 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1054 {
1055         u8 ctrl;
1056
1057         ctrl = data->read(data, data->REG_PWM[nr]);
1058         data->pwm_ctrl[nr] = ctrl;
1059         if (has_newer_autopwm(data)) {
1060                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1061                 data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1062         } else {
1063                 if (ctrl & 0x80)        /* Automatic mode */
1064                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1065                 else                            /* Manual mode */
1066                         data->pwm_duty[nr] = ctrl & 0x7f;
1067         }
1068
1069         if (has_old_autopwm(data)) {
1070                 int i;
1071
1072                 for (i = 0; i < 5 ; i++)
1073                         data->auto_temp[nr][i] = data->read(data,
1074                                                 IT87_REG_AUTO_TEMP(nr, i));
1075                 for (i = 0; i < 3 ; i++)
1076                         data->auto_pwm[nr][i] = data->read(data,
1077                                                 IT87_REG_AUTO_PWM(nr, i));
1078         } else if (has_newer_autopwm(data)) {
1079                 int i;
1080
1081                 /*
1082                  * 0: temperature hysteresis (base + 5)
1083                  * 1: fan off temperature (base + 0)
1084                  * 2: fan start temperature (base + 1)
1085                  * 3: fan max temperature (base + 2)
1086                  */
1087                 data->auto_temp[nr][0] =
1088                         data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1089
1090                 for (i = 0; i < 3 ; i++)
1091                         data->auto_temp[nr][i + 1] =
1092                                 data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1093                 /*
1094                  * 0: start pwm value (base + 3)
1095                  * 1: pwm slope (base + 4, 1/8th pwm)
1096                  */
1097                 data->auto_pwm[nr][0] =
1098                         data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1099                 data->auto_pwm[nr][1] =
1100                         data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1101         }
1102 }
1103
1104 static int it87_lock(struct it87_data *data)
1105 {
1106         int err;
1107
1108         mutex_lock(&data->update_lock);
1109         err = smbus_disable(data);
1110         if (err)
1111                 mutex_unlock(&data->update_lock);
1112         return err;
1113 }
1114
1115 static void it87_unlock(struct it87_data *data)
1116 {
1117         smbus_enable(data);
1118         mutex_unlock(&data->update_lock);
1119 }
1120
1121 static struct it87_data *it87_update_device(struct device *dev)
1122 {
1123         struct it87_data *data = dev_get_drvdata(dev);
1124         int err;
1125         int i;
1126
1127         err = it87_lock(data);
1128         if (err)
1129                 return ERR_PTR(err);
1130
1131         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1132             !data->valid) {
1133                 if (update_vbat) {
1134                         /*
1135                          * Cleared after each update, so reenable.  Value
1136                          * returned by this read will be previous value
1137                          */
1138                         data->write(data, IT87_REG_CONFIG,
1139                                     data->read(data, IT87_REG_CONFIG) | 0x40);
1140                 }
1141                 for (i = 0; i < NUM_VIN; i++) {
1142                         if (!(data->has_in & BIT(i)))
1143                                 continue;
1144
1145                         data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1146
1147                         /* VBAT and AVCC don't have limit registers */
1148                         if (i >= NUM_VIN_LIMIT)
1149                                 continue;
1150
1151                         data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1152                         data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1153                 }
1154
1155                 for (i = 0; i < NUM_FAN; i++) {
1156                         /* Skip disabled fans */
1157                         if (!(data->has_fan & BIT(i)))
1158                                 continue;
1159
1160                         data->fan[i][1] = data->read(data, data->REG_FAN_MIN[i]);
1161                         data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1162                         /* Add high byte if in 16-bit mode */
1163                         if (has_16bit_fans(data)) {
1164                                 data->fan[i][0] |= data->read(data,
1165                                                 data->REG_FANX[i]) << 8;
1166                                 data->fan[i][1] |= data->read(data,
1167                                                 data->REG_FANX_MIN[i]) << 8;
1168                         }
1169                 }
1170                 for (i = 0; i < NUM_TEMP; i++) {
1171                         if (!(data->has_temp & BIT(i)))
1172                                 continue;
1173                         data->temp[i][0] =
1174                                 data->read(data, IT87_REG_TEMP(i));
1175
1176                         if (i >= data->num_temp_limit)
1177                                 continue;
1178
1179                         if (i < data->num_temp_offset)
1180                                 data->temp[i][3] =
1181                                   data->read(data, data->REG_TEMP_OFFSET[i]);
1182
1183                         data->temp[i][1] =
1184                                 data->read(data, data->REG_TEMP_LOW[i]);
1185                         data->temp[i][2] =
1186                                 data->read(data, data->REG_TEMP_HIGH[i]);
1187                 }
1188
1189                 /* Newer chips don't have clock dividers */
1190                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1191                         i = data->read(data, IT87_REG_FAN_DIV);
1192                         data->fan_div[0] = i & 0x07;
1193                         data->fan_div[1] = (i >> 3) & 0x07;
1194                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1195                 }
1196
1197                 data->alarms =
1198                         data->read(data, IT87_REG_ALARM1) |
1199                         (data->read(data, IT87_REG_ALARM2) << 8) |
1200                         (data->read(data, IT87_REG_ALARM3) << 16);
1201                 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1202
1203                 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1204                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1205                 for (i = 0; i < NUM_PWM; i++) {
1206                         if (!(data->has_pwm & BIT(i)))
1207                                 continue;
1208                         it87_update_pwm_ctrl(data, i);
1209                 }
1210
1211                 data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1212                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1213                 /*
1214                  * The IT8705F does not have VID capability.
1215                  * The IT8718F and later don't use IT87_REG_VID for the
1216                  * same purpose.
1217                  */
1218                 if (data->type == it8712 || data->type == it8716) {
1219                         data->vid = data->read(data, IT87_REG_VID);
1220                         /*
1221                          * The older IT8712F revisions had only 5 VID pins,
1222                          * but we assume it is always safe to read 6 bits.
1223                          */
1224                         data->vid &= 0x3f;
1225                 }
1226                 data->last_updated = jiffies;
1227                 data->valid = 1;
1228         }
1229         it87_unlock(data);
1230         return data;
1231 }
1232
1233 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1234                        char *buf)
1235 {
1236         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1237         struct it87_data *data = it87_update_device(dev);
1238         int index = sattr->index;
1239         int nr = sattr->nr;
1240
1241         if (IS_ERR(data))
1242                 return PTR_ERR(data);
1243
1244         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1245 }
1246
1247 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1248                       const char *buf, size_t count)
1249 {
1250         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1251         struct it87_data *data = dev_get_drvdata(dev);
1252         int index = sattr->index;
1253         int nr = sattr->nr;
1254         unsigned long val;
1255         int err;
1256
1257         if (kstrtoul(buf, 10, &val) < 0)
1258                 return -EINVAL;
1259
1260         err = it87_lock(data);
1261         if (err)
1262                 return err;
1263
1264         data->in[nr][index] = in_to_reg(data, nr, val);
1265         data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1266                                      : IT87_REG_VIN_MAX(nr),
1267                     data->in[nr][index]);
1268         it87_unlock(data);
1269         return count;
1270 }
1271
1272 static SENSOR_DEVICE_ATTR_2(in0_input, 0444, show_in, NULL, 0, 0);
1273 static SENSOR_DEVICE_ATTR_2(in0_min, 0644, show_in, set_in, 0, 1);
1274 static SENSOR_DEVICE_ATTR_2(in0_max, 0644, show_in, set_in, 0, 2);
1275
1276 static SENSOR_DEVICE_ATTR_2(in1_input, 0444, show_in, NULL, 1, 0);
1277 static SENSOR_DEVICE_ATTR_2(in1_min, 0644, show_in, set_in, 1, 1);
1278 static SENSOR_DEVICE_ATTR_2(in1_max, 0644, show_in, set_in, 1, 2);
1279
1280 static SENSOR_DEVICE_ATTR_2(in2_input, 0444, show_in, NULL, 2, 0);
1281 static SENSOR_DEVICE_ATTR_2(in2_min, 0644, show_in, set_in, 2, 1);
1282 static SENSOR_DEVICE_ATTR_2(in2_max, 0644, show_in, set_in, 2, 2);
1283
1284 static SENSOR_DEVICE_ATTR_2(in3_input, 0444, show_in, NULL, 3, 0);
1285 static SENSOR_DEVICE_ATTR_2(in3_min, 0644, show_in, set_in, 3, 1);
1286 static SENSOR_DEVICE_ATTR_2(in3_max, 0644, show_in, set_in, 3, 2);
1287
1288 static SENSOR_DEVICE_ATTR_2(in4_input, 0444, show_in, NULL, 4, 0);
1289 static SENSOR_DEVICE_ATTR_2(in4_min, 0644, show_in, set_in, 4, 1);
1290 static SENSOR_DEVICE_ATTR_2(in4_max, 0644, show_in, set_in, 4, 2);
1291
1292 static SENSOR_DEVICE_ATTR_2(in5_input, 0444, show_in, NULL, 5, 0);
1293 static SENSOR_DEVICE_ATTR_2(in5_min, 0644, show_in, set_in, 5, 1);
1294 static SENSOR_DEVICE_ATTR_2(in5_max, 0644, show_in, set_in, 5, 2);
1295
1296 static SENSOR_DEVICE_ATTR_2(in6_input, 0444, show_in, NULL, 6, 0);
1297 static SENSOR_DEVICE_ATTR_2(in6_min, 0644, show_in, set_in, 6, 1);
1298 static SENSOR_DEVICE_ATTR_2(in6_max, 0644, show_in, set_in, 6, 2);
1299
1300 static SENSOR_DEVICE_ATTR_2(in7_input, 0444, show_in, NULL, 7, 0);
1301 static SENSOR_DEVICE_ATTR_2(in7_min, 0644, show_in, set_in, 7, 1);
1302 static SENSOR_DEVICE_ATTR_2(in7_max, 0644, show_in, set_in, 7, 2);
1303
1304 static SENSOR_DEVICE_ATTR_2(in8_input, 0444, show_in, NULL, 8, 0);
1305 static SENSOR_DEVICE_ATTR_2(in9_input, 0444, show_in, NULL, 9, 0);
1306 static SENSOR_DEVICE_ATTR_2(in10_input, 0444, show_in, NULL, 10, 0);
1307 static SENSOR_DEVICE_ATTR_2(in11_input, 0444, show_in, NULL, 11, 0);
1308 static SENSOR_DEVICE_ATTR_2(in12_input, 0444, show_in, NULL, 12, 0);
1309
1310 /* Up to 6 temperatures */
1311 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1312                          char *buf)
1313 {
1314         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1315         int nr = sattr->nr;
1316         int index = sattr->index;
1317         struct it87_data *data = it87_update_device(dev);
1318
1319         if (IS_ERR(data))
1320                 return PTR_ERR(data);
1321
1322         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1323 }
1324
1325 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1326                         const char *buf, size_t count)
1327 {
1328         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1329         int nr = sattr->nr;
1330         int index = sattr->index;
1331         struct it87_data *data = dev_get_drvdata(dev);
1332         long val;
1333         u8 reg, regval;
1334         int err;
1335
1336         if (kstrtol(buf, 10, &val) < 0)
1337                 return -EINVAL;
1338
1339         err = it87_lock(data);
1340         if (err)
1341                 return err;
1342
1343         switch (index) {
1344         default:
1345         case 1:
1346                 reg = data->REG_TEMP_LOW[nr];
1347                 break;
1348         case 2:
1349                 reg = data->REG_TEMP_HIGH[nr];
1350                 break;
1351         case 3:
1352                 regval = data->read(data, IT87_REG_BEEP_ENABLE);
1353                 if (!(regval & 0x80)) {
1354                         regval |= 0x80;
1355                         data->write(data, IT87_REG_BEEP_ENABLE, regval);
1356                 }
1357                 data->valid = 0;
1358                 reg = data->REG_TEMP_OFFSET[nr];
1359                 break;
1360         }
1361
1362         data->temp[nr][index] = TEMP_TO_REG(val);
1363         data->write(data, reg, data->temp[nr][index]);
1364         it87_unlock(data);
1365         return count;
1366 }
1367
1368 static SENSOR_DEVICE_ATTR_2(temp1_input, 0444, show_temp, NULL, 0, 0);
1369 static SENSOR_DEVICE_ATTR_2(temp1_min, 0644, show_temp, set_temp, 0, 1);
1370 static SENSOR_DEVICE_ATTR_2(temp1_max, 0644, show_temp, set_temp, 0, 2);
1371 static SENSOR_DEVICE_ATTR_2(temp1_offset, 0644, show_temp, set_temp, 0, 3);
1372 static SENSOR_DEVICE_ATTR_2(temp2_input, 0444, show_temp, NULL, 1, 0);
1373 static SENSOR_DEVICE_ATTR_2(temp2_min, 0644, show_temp, set_temp, 1, 1);
1374 static SENSOR_DEVICE_ATTR_2(temp2_max, 0644, show_temp, set_temp, 1, 2);
1375 static SENSOR_DEVICE_ATTR_2(temp2_offset, 0644, show_temp, set_temp, 1, 3);
1376 static SENSOR_DEVICE_ATTR_2(temp3_input, 0444, show_temp, NULL, 2, 0);
1377 static SENSOR_DEVICE_ATTR_2(temp3_min, 0644, show_temp, set_temp, 2, 1);
1378 static SENSOR_DEVICE_ATTR_2(temp3_max, 0644, show_temp, set_temp, 2, 2);
1379 static SENSOR_DEVICE_ATTR_2(temp3_offset, 0644, show_temp, set_temp, 2, 3);
1380 static SENSOR_DEVICE_ATTR_2(temp4_input, 0444, show_temp, NULL, 3, 0);
1381 static SENSOR_DEVICE_ATTR_2(temp4_min, 0644, show_temp, set_temp, 3, 1);
1382 static SENSOR_DEVICE_ATTR_2(temp4_max, 0644, show_temp, set_temp, 3, 2);
1383 static SENSOR_DEVICE_ATTR_2(temp4_offset, 0644, show_temp, set_temp, 3, 3);
1384 static SENSOR_DEVICE_ATTR_2(temp5_input, 0444, show_temp, NULL, 4, 0);
1385 static SENSOR_DEVICE_ATTR_2(temp5_min, 0644, show_temp, set_temp, 4, 1);
1386 static SENSOR_DEVICE_ATTR_2(temp5_max, 0644, show_temp, set_temp, 4, 2);
1387 static SENSOR_DEVICE_ATTR_2(temp5_offset, 0644, show_temp, set_temp, 4, 3);
1388 static SENSOR_DEVICE_ATTR_2(temp6_input, 0444, show_temp, NULL, 5, 0);
1389 static SENSOR_DEVICE_ATTR_2(temp6_min, 0644, show_temp, set_temp, 5, 1);
1390 static SENSOR_DEVICE_ATTR_2(temp6_max, 0644, show_temp, set_temp, 5, 2);
1391 static SENSOR_DEVICE_ATTR_2(temp6_offset, 0644, show_temp, set_temp, 5, 3);
1392
1393 static const u8 temp_types_8686[NUM_TEMP][9] = {
1394         { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1395         { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1396         { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1397         { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1398         { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1399         { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1400 };
1401
1402 static int get_temp_type(struct it87_data *data, int index)
1403 {
1404         u8 reg, extra;
1405         int ttype, type = 0;
1406
1407         if (has_bank_sel(data)) {
1408                 u8 src1, src2;
1409
1410                 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1411
1412                 switch (data->type) {
1413                 case it8686:
1414                         if (src1 < 9)
1415                                 type = temp_types_8686[index][src1];
1416                         break;
1417                 case it8625:
1418                         if (index < 3)
1419                                 break;
1420                 case it8655:
1421                 case it8665:
1422                         if (src1 < 3) {
1423                                 index = src1;
1424                                 break;
1425                         }
1426                         src2 = data->temp_src[3];
1427                         switch (src1) {
1428                         case 3:
1429                                 type = (src2 & BIT(index)) ? 6 : 5;
1430                                 break;
1431                         case 4 ... 8:
1432                                 type = (src2 & BIT(index)) ? 4 : 6;
1433                                 break;
1434                         case 9:
1435                                 type = (src2 & BIT(index)) ? 5 : 0;
1436                                 break;
1437                         default:
1438                                 break;
1439                         }
1440                         return type;
1441                 default:
1442                         return 0;
1443                 }
1444         }
1445         if (type)
1446                 return type;
1447
1448         /* Dectect PECI vs. AMDTSI if possible */
1449         ttype = 6;
1450         if ((has_temp_peci(data, index)) && data->type != it8721) {
1451                 extra = data->read(data, 0x98); /* PCH/AMDTSI host status */
1452                 if (extra & BIT(6))
1453                         ttype = 5;
1454         }
1455
1456         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1457
1458         /* Per chip special detection */
1459         switch (data->type) {
1460         case it8622:
1461                 if (!(reg & 0xc0) && index == 3)
1462                         type = ttype;
1463                 break;
1464         default:
1465                 break;
1466         }
1467
1468         if (type || index >= 3)
1469                 return type;
1470
1471         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1472
1473         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1474             (has_temp_old_peci(data, index) && (extra & 0x80)))
1475                 type = ttype;           /* Intel PECI or AMDTSI */
1476         if (reg & BIT(index))
1477                 type = 3;               /* thermal diode */
1478         else if (reg & BIT(index + 3))
1479                 type = 4;               /* thermistor */
1480
1481         return type;
1482 }
1483
1484 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1485                               char *buf)
1486 {
1487         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1488         struct it87_data *data = it87_update_device(dev);
1489         int type;
1490
1491         if (IS_ERR(data))
1492                 return PTR_ERR(data);
1493
1494         type = get_temp_type(data, sensor_attr->index);
1495         return sprintf(buf, "%d\n", type);
1496 }
1497
1498 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1499                              const char *buf, size_t count)
1500 {
1501         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1502         int nr = sensor_attr->index;
1503
1504         struct it87_data *data = dev_get_drvdata(dev);
1505         long val;
1506         u8 reg, extra;
1507         int err;
1508
1509         if (kstrtol(buf, 10, &val) < 0)
1510                 return -EINVAL;
1511
1512         err = it87_lock(data);
1513         if (err)
1514                 return err;
1515
1516         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1517         reg &= ~(1 << nr);
1518         reg &= ~(8 << nr);
1519         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1520                 reg &= 0x3f;
1521         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1522         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1523                 extra &= 0x7f;
1524         if (val == 2) { /* backwards compatibility */
1525                 dev_warn(dev,
1526                          "Sensor type 2 is deprecated, please use 4 instead\n");
1527                 val = 4;
1528         }
1529         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1530         if (val == 3)
1531                 reg |= 1 << nr;
1532         else if (val == 4)
1533                 reg |= 8 << nr;
1534         else if (has_temp_peci(data, nr) && val == 6)
1535                 reg |= (nr + 1) << 6;
1536         else if (has_temp_old_peci(data, nr) && val == 6)
1537                 extra |= 0x80;
1538         else if (val != 0) {
1539                 count = -EINVAL;
1540                 goto unlock;
1541         }
1542
1543         data->sensor = reg;
1544         data->extra = extra;
1545         data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1546         if (has_temp_old_peci(data, nr))
1547                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1548         data->valid = 0;        /* Force cache refresh */
1549 unlock:
1550         it87_unlock(data);
1551         return count;
1552 }
1553
1554 static SENSOR_DEVICE_ATTR(temp1_type, 0644, show_temp_type, set_temp_type, 0);
1555 static SENSOR_DEVICE_ATTR(temp2_type, 0644, show_temp_type, set_temp_type, 1);
1556 static SENSOR_DEVICE_ATTR(temp3_type, 0644, show_temp_type, set_temp_type, 2);
1557 static SENSOR_DEVICE_ATTR(temp4_type, 0644, show_temp_type, set_temp_type, 3);
1558 static SENSOR_DEVICE_ATTR(temp5_type, 0644, show_temp_type, set_temp_type, 4);
1559 static SENSOR_DEVICE_ATTR(temp6_type, 0644, show_temp_type, set_temp_type, 5);
1560
1561 /* 6 Fans */
1562
1563 static int pwm_mode(const struct it87_data *data, int nr)
1564 {
1565         if (has_fanctl_onoff(data) && nr < 3 &&
1566             !(data->fan_main_ctrl & BIT(nr)))
1567                 return 0;                               /* Full speed */
1568         if (data->pwm_ctrl[nr] & 0x80)
1569                 return 2;                               /* Automatic mode */
1570         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1571             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1572                 return 0;                       /* Full speed */
1573
1574         return 1;                               /* Manual mode */
1575 }
1576
1577 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1578                         char *buf)
1579 {
1580         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1581         int nr = sattr->nr;
1582         int index = sattr->index;
1583         int speed;
1584         struct it87_data *data = it87_update_device(dev);
1585
1586         if (IS_ERR(data))
1587                 return PTR_ERR(data);
1588
1589         speed = has_16bit_fans(data) ?
1590                 FAN16_FROM_REG(data->fan[nr][index]) :
1591                 FAN_FROM_REG(data->fan[nr][index],
1592                              DIV_FROM_REG(data->fan_div[nr]));
1593         return sprintf(buf, "%d\n", speed);
1594 }
1595
1596 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1597                             char *buf)
1598 {
1599         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1600         struct it87_data *data = it87_update_device(dev);
1601         int nr = sensor_attr->index;
1602
1603         if (IS_ERR(data))
1604                 return PTR_ERR(data);
1605
1606         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1607 }
1608
1609 static ssize_t show_pwm_enable(struct device *dev,
1610                                struct device_attribute *attr, char *buf)
1611 {
1612         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1613         struct it87_data *data = it87_update_device(dev);
1614         int nr = sensor_attr->index;
1615
1616         if (IS_ERR(data))
1617                 return PTR_ERR(data);
1618
1619         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1620 }
1621
1622 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1623                         char *buf)
1624 {
1625         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1626         struct it87_data *data = it87_update_device(dev);
1627         int nr = sensor_attr->index;
1628
1629         if (IS_ERR(data))
1630                 return PTR_ERR(data);
1631
1632         return sprintf(buf, "%d\n",
1633                        pwm_from_reg(data, data->pwm_duty[nr]));
1634 }
1635
1636 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1637                              char *buf)
1638 {
1639         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1640         struct it87_data *data = it87_update_device(dev);
1641         int nr = sensor_attr->index;
1642         unsigned int freq;
1643         int index;
1644
1645         if (IS_ERR(data))
1646                 return PTR_ERR(data);
1647
1648         if (has_pwm_freq2(data) && nr == 1)
1649                 index = (data->extra >> 4) & 0x07;
1650         else
1651                 index = (data->fan_ctl >> 4) & 0x07;
1652
1653         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1654
1655         return sprintf(buf, "%u\n", freq);
1656 }
1657
1658 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1659                        const char *buf, size_t count)
1660 {
1661         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1662         int nr = sattr->nr;
1663         int index = sattr->index;
1664
1665         struct it87_data *data = dev_get_drvdata(dev);
1666         long val;
1667         int err;
1668         u8 reg;
1669
1670         if (kstrtol(buf, 10, &val) < 0)
1671                 return -EINVAL;
1672
1673         err = it87_lock(data);
1674         if (err)
1675                 return err;
1676
1677         if (has_16bit_fans(data)) {
1678                 data->fan[nr][index] = FAN16_TO_REG(val);
1679                 data->write(data, data->REG_FAN_MIN[nr],
1680                             data->fan[nr][index] & 0xff);
1681                 data->write(data, data->REG_FANX_MIN[nr],
1682                             data->fan[nr][index] >> 8);
1683         } else {
1684                 reg = data->read(data, IT87_REG_FAN_DIV);
1685                 switch (nr) {
1686                 case 0:
1687                         data->fan_div[nr] = reg & 0x07;
1688                         break;
1689                 case 1:
1690                         data->fan_div[nr] = (reg >> 3) & 0x07;
1691                         break;
1692                 case 2:
1693                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1694                         break;
1695                 }
1696                 data->fan[nr][index] =
1697                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1698                 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1699         }
1700         it87_unlock(data);
1701         return count;
1702 }
1703
1704 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1705                            const char *buf, size_t count)
1706 {
1707         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1708         struct it87_data *data = dev_get_drvdata(dev);
1709         int nr = sensor_attr->index;
1710         unsigned long val;
1711         int min, err;
1712         u8 old;
1713
1714         if (kstrtoul(buf, 10, &val) < 0)
1715                 return -EINVAL;
1716
1717         err = it87_lock(data);
1718         if (err)
1719                 return err;
1720
1721         old = data->read(data, IT87_REG_FAN_DIV);
1722
1723         /* Save fan min limit */
1724         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1725
1726         switch (nr) {
1727         case 0:
1728         case 1:
1729                 data->fan_div[nr] = DIV_TO_REG(val);
1730                 break;
1731         case 2:
1732                 if (val < 8)
1733                         data->fan_div[nr] = 1;
1734                 else
1735                         data->fan_div[nr] = 3;
1736         }
1737         val = old & 0x80;
1738         val |= (data->fan_div[0] & 0x07);
1739         val |= (data->fan_div[1] & 0x07) << 3;
1740         if (data->fan_div[2] == 3)
1741                 val |= 0x1 << 6;
1742         data->write(data, IT87_REG_FAN_DIV, val);
1743
1744         /* Restore fan min limit */
1745         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1746         data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1747         it87_unlock(data);
1748         return count;
1749 }
1750
1751 /* Returns 0 if OK, -EINVAL otherwise */
1752 static int check_trip_points(struct device *dev, int nr)
1753 {
1754         const struct it87_data *data = dev_get_drvdata(dev);
1755         int i, err = 0;
1756
1757         if (has_old_autopwm(data)) {
1758                 for (i = 0; i < 3; i++) {
1759                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1760                                 err = -EINVAL;
1761                 }
1762                 for (i = 0; i < 2; i++) {
1763                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1764                                 err = -EINVAL;
1765                 }
1766         } else if (has_newer_autopwm(data)) {
1767                 for (i = 1; i < 3; i++) {
1768                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1769                                 err = -EINVAL;
1770                 }
1771         }
1772
1773         if (err) {
1774                 dev_err(dev,
1775                         "Inconsistent trip points, not switching to automatic mode\n");
1776                 dev_err(dev, "Adjust the trip points and try again\n");
1777         }
1778         return err;
1779 }
1780
1781 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1782                               const char *buf, size_t count)
1783 {
1784         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1785         struct it87_data *data = dev_get_drvdata(dev);
1786         int nr = sensor_attr->index;
1787         long val;
1788         int err;
1789
1790         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1791                 return -EINVAL;
1792
1793         /* Check trip points before switching to automatic mode */
1794         if (val == 2) {
1795                 if (check_trip_points(dev, nr) < 0)
1796                         return -EINVAL;
1797         }
1798
1799         err = it87_lock(data);
1800         if (err)
1801                 return err;
1802
1803         it87_update_pwm_ctrl(data, nr);
1804
1805         if (val == 0) {
1806                 if (nr < 3 && has_fanctl_onoff(data)) {
1807                         int tmp;
1808                         /* make sure the fan is on when in on/off mode */
1809                         tmp = data->read(data, IT87_REG_FAN_CTL);
1810                         data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1811                         /* set on/off mode */
1812                         data->fan_main_ctrl &= ~BIT(nr);
1813                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1814                                     data->fan_main_ctrl);
1815                 } else {
1816                         u8 ctrl;
1817
1818                         /* No on/off mode, set maximum pwm value */
1819                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1820                         data->write(data, IT87_REG_PWM_DUTY[nr],
1821                                     data->pwm_duty[nr]);
1822                         /* and set manual mode */
1823                         if (has_newer_autopwm(data)) {
1824                                 ctrl = temp_map_to_reg(data, nr,
1825                                                        data->pwm_temp_map[nr]);
1826                                 ctrl &= 0x7f;
1827                         } else {
1828                                 ctrl = data->pwm_duty[nr];
1829                         }
1830                         data->pwm_ctrl[nr] = ctrl;
1831                         data->write(data, data->REG_PWM[nr], ctrl);
1832                 }
1833         } else {
1834                 u8 ctrl;
1835
1836                 if (has_newer_autopwm(data)) {
1837                         ctrl = temp_map_to_reg(data, nr,
1838                                                data->pwm_temp_map[nr]);
1839                         if (val == 1)
1840                                 ctrl &= 0x7f;
1841                         else
1842                                 ctrl |= 0x80;
1843                 } else {
1844                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1845                 }
1846                 data->pwm_ctrl[nr] = ctrl;
1847                 data->write(data, data->REG_PWM[nr], ctrl);
1848
1849                 if (has_fanctl_onoff(data) && nr < 3) {
1850                         /* set SmartGuardian mode */
1851                         data->fan_main_ctrl |= BIT(nr);
1852                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1853                                     data->fan_main_ctrl);
1854                 }
1855         }
1856         it87_unlock(data);
1857         return count;
1858 }
1859
1860 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1861                        const char *buf, size_t count)
1862 {
1863         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1864         struct it87_data *data = dev_get_drvdata(dev);
1865         int nr = sensor_attr->index;
1866         long val;
1867         int err;
1868
1869         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1870                 return -EINVAL;
1871
1872         err = it87_lock(data);
1873         if (err)
1874                 return err;
1875
1876         it87_update_pwm_ctrl(data, nr);
1877         if (has_newer_autopwm(data)) {
1878                 /*
1879                  * If we are in automatic mode, the PWM duty cycle register
1880                  * is read-only so we can't write the value.
1881                  */
1882                 if (data->pwm_ctrl[nr] & 0x80) {
1883                         count = -EBUSY;
1884                         goto unlock;
1885                 }
1886                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1887                 data->write(data, IT87_REG_PWM_DUTY[nr],
1888                             data->pwm_duty[nr]);
1889         } else {
1890                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1891                 /*
1892                  * If we are in manual mode, write the duty cycle immediately;
1893                  * otherwise, just store it for later use.
1894                  */
1895                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1896                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1897                         data->write(data, data->REG_PWM[nr],
1898                                     data->pwm_ctrl[nr]);
1899                 }
1900         }
1901 unlock:
1902         it87_unlock(data);
1903         return count;
1904 }
1905
1906 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1907                             const char *buf, size_t count)
1908 {
1909         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1910         struct it87_data *data = dev_get_drvdata(dev);
1911         int nr = sensor_attr->index;
1912         unsigned long val;
1913         int err;
1914         int i;
1915
1916         if (kstrtoul(buf, 10, &val) < 0)
1917                 return -EINVAL;
1918
1919         val = clamp_val(val, 0, 1000000);
1920         val *= has_newer_autopwm(data) ? 256 : 128;
1921
1922         /* Search for the nearest available frequency */
1923         for (i = 0; i < 7; i++) {
1924                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1925                         break;
1926         }
1927
1928         err = it87_lock(data);
1929         if (err)
1930                 return err;
1931
1932         if (nr == 0) {
1933                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1934                 data->fan_ctl |= i << 4;
1935                 data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
1936         } else {
1937                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1938                 data->extra |= i << 4;
1939                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1940         }
1941         it87_unlock(data);
1942         return count;
1943 }
1944
1945 static ssize_t show_pwm_temp_map(struct device *dev,
1946                                  struct device_attribute *attr, char *buf)
1947 {
1948         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1949         struct it87_data *data = it87_update_device(dev);
1950         int nr = sensor_attr->index;
1951
1952         if (IS_ERR(data))
1953                 return PTR_ERR(data);
1954
1955         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1956 }
1957
1958 static ssize_t set_pwm_temp_map(struct device *dev,
1959                                 struct device_attribute *attr, const char *buf,
1960                                 size_t count)
1961 {
1962         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1963         struct it87_data *data = dev_get_drvdata(dev);
1964         int nr = sensor_attr->index;
1965         unsigned long val;
1966         int err;
1967         u8 map;
1968
1969         if (kstrtoul(buf, 10, &val) < 0)
1970                 return -EINVAL;
1971
1972         if (!val || val > data->pwm_num_temp_map)
1973                 return -EINVAL;
1974
1975         map = val - 1;
1976
1977         err = it87_lock(data);
1978         if (err)
1979                 return err;
1980
1981         it87_update_pwm_ctrl(data, nr);
1982         data->pwm_temp_map[nr] = map;
1983         /*
1984          * If we are in automatic mode, write the temp mapping immediately;
1985          * otherwise, just store it for later use.
1986          */
1987         if (data->pwm_ctrl[nr] & 0x80) {
1988                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
1989                 data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1990         }
1991         it87_unlock(data);
1992         return count;
1993 }
1994
1995 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1996                              char *buf)
1997 {
1998         struct it87_data *data = it87_update_device(dev);
1999         struct sensor_device_attribute_2 *sensor_attr =
2000                         to_sensor_dev_attr_2(attr);
2001         int nr = sensor_attr->nr;
2002         int point = sensor_attr->index;
2003
2004         if (IS_ERR(data))
2005                 return PTR_ERR(data);
2006
2007         return sprintf(buf, "%d\n",
2008                        pwm_from_reg(data, data->auto_pwm[nr][point]));
2009 }
2010
2011 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2012                             const char *buf, size_t count)
2013 {
2014         struct it87_data *data = dev_get_drvdata(dev);
2015         struct sensor_device_attribute_2 *sensor_attr =
2016                         to_sensor_dev_attr_2(attr);
2017         int nr = sensor_attr->nr;
2018         int point = sensor_attr->index;
2019         int regaddr;
2020         long val;
2021         int err;
2022
2023         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2024                 return -EINVAL;
2025
2026         err = it87_lock(data);
2027         if (err)
2028                 return err;
2029
2030         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2031         if (has_newer_autopwm(data))
2032                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2033         else
2034                 regaddr = IT87_REG_AUTO_PWM(nr, point);
2035         data->write(data, regaddr, data->auto_pwm[nr][point]);
2036         it87_unlock(data);
2037         return count;
2038 }
2039
2040 static ssize_t show_auto_pwm_slope(struct device *dev,
2041                                    struct device_attribute *attr, char *buf)
2042 {
2043         struct it87_data *data = it87_update_device(dev);
2044         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2045         int nr = sensor_attr->index;
2046
2047         if (IS_ERR(data))
2048                 return PTR_ERR(data);
2049
2050         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2051 }
2052
2053 static ssize_t set_auto_pwm_slope(struct device *dev,
2054                                   struct device_attribute *attr,
2055                                   const char *buf, size_t count)
2056 {
2057         struct it87_data *data = dev_get_drvdata(dev);
2058         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2059         int nr = sensor_attr->index;
2060         unsigned long val;
2061         int err;
2062
2063         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2064                 return -EINVAL;
2065
2066         err = it87_lock(data);
2067         if (err)
2068                 return err;
2069
2070         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2071         data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2072         it87_unlock(data);
2073         return count;
2074 }
2075
2076 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2077                               char *buf)
2078 {
2079         struct it87_data *data = it87_update_device(dev);
2080         struct sensor_device_attribute_2 *sensor_attr =
2081                         to_sensor_dev_attr_2(attr);
2082         int nr = sensor_attr->nr;
2083         int point = sensor_attr->index;
2084         int reg;
2085
2086         if (IS_ERR(data))
2087                 return PTR_ERR(data);
2088
2089         if (has_old_autopwm(data) || point)
2090                 reg = data->auto_temp[nr][point];
2091         else
2092                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2093
2094         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2095 }
2096
2097 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2098                              const char *buf, size_t count)
2099 {
2100         struct it87_data *data = dev_get_drvdata(dev);
2101         struct sensor_device_attribute_2 *sensor_attr =
2102                         to_sensor_dev_attr_2(attr);
2103         int nr = sensor_attr->nr;
2104         int point = sensor_attr->index;
2105         long val;
2106         int reg;
2107         int err;
2108
2109         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2110                 return -EINVAL;
2111
2112         err = it87_lock(data);
2113         if (err)
2114                 return err;
2115
2116         if (has_newer_autopwm(data) && !point) {
2117                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2118                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2119                 data->auto_temp[nr][0] = reg;
2120                 data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2121         } else {
2122                 reg = TEMP_TO_REG(val);
2123                 data->auto_temp[nr][point] = reg;
2124                 if (has_newer_autopwm(data))
2125                         point--;
2126                 data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2127         }
2128         it87_unlock(data);
2129         return count;
2130 }
2131
2132 static SENSOR_DEVICE_ATTR_2(fan1_input, 0444, show_fan, NULL, 0, 0);
2133 static SENSOR_DEVICE_ATTR_2(fan1_min, 0644, show_fan, set_fan, 0, 1);
2134 static SENSOR_DEVICE_ATTR(fan1_div, 0644, show_fan_div, set_fan_div, 0);
2135
2136 static SENSOR_DEVICE_ATTR_2(fan2_input, 0444, show_fan, NULL, 1, 0);
2137 static SENSOR_DEVICE_ATTR_2(fan2_min, 0644, show_fan, set_fan, 1, 1);
2138 static SENSOR_DEVICE_ATTR(fan2_div, 0644, show_fan_div, set_fan_div, 1);
2139
2140 static SENSOR_DEVICE_ATTR_2(fan3_input, 0444, show_fan, NULL, 2, 0);
2141 static SENSOR_DEVICE_ATTR_2(fan3_min, 0644, show_fan, set_fan, 2, 1);
2142 static SENSOR_DEVICE_ATTR(fan3_div, 0644, show_fan_div, set_fan_div, 2);
2143
2144 static SENSOR_DEVICE_ATTR_2(fan4_input, 0444, show_fan, NULL, 3, 0);
2145 static SENSOR_DEVICE_ATTR_2(fan4_min, 0644, show_fan, set_fan, 3, 1);
2146
2147 static SENSOR_DEVICE_ATTR_2(fan5_input, 0444, show_fan, NULL, 4, 0);
2148 static SENSOR_DEVICE_ATTR_2(fan5_min, 0644, show_fan, set_fan, 4, 1);
2149
2150 static SENSOR_DEVICE_ATTR_2(fan6_input, 0444, show_fan, NULL, 5, 0);
2151 static SENSOR_DEVICE_ATTR_2(fan6_min, 0644, show_fan, set_fan, 5, 1);
2152
2153 static SENSOR_DEVICE_ATTR(pwm1_enable, 0644,
2154                           show_pwm_enable, set_pwm_enable, 0);
2155 static SENSOR_DEVICE_ATTR(pwm1, 0644, show_pwm, set_pwm, 0);
2156 static SENSOR_DEVICE_ATTR(pwm1_freq, 0644, show_pwm_freq, set_pwm_freq, 0);
2157 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, 0444,
2158                           show_pwm_temp_map, set_pwm_temp_map, 0);
2159 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, 0644,
2160                             show_auto_pwm, set_auto_pwm, 0, 0);
2161 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, 0644,
2162                             show_auto_pwm, set_auto_pwm, 0, 1);
2163 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, 0644,
2164                             show_auto_pwm, set_auto_pwm, 0, 2);
2165 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, 0444,
2166                             show_auto_pwm, NULL, 0, 3);
2167 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, 0644,
2168                             show_auto_temp, set_auto_temp, 0, 1);
2169 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, 0644,
2170                             show_auto_temp, set_auto_temp, 0, 0);
2171 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, 0644,
2172                             show_auto_temp, set_auto_temp, 0, 2);
2173 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, 0644,
2174                             show_auto_temp, set_auto_temp, 0, 3);
2175 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, 0644,
2176                             show_auto_temp, set_auto_temp, 0, 4);
2177 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, 0644,
2178                             show_auto_pwm, set_auto_pwm, 0, 0);
2179 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, 0644,
2180                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2181
2182 static SENSOR_DEVICE_ATTR(pwm2_enable, 0644,
2183                           show_pwm_enable, set_pwm_enable, 1);
2184 static SENSOR_DEVICE_ATTR(pwm2, 0644, show_pwm, set_pwm, 1);
2185 static SENSOR_DEVICE_ATTR(pwm2_freq, 0444, show_pwm_freq, set_pwm_freq, 1);
2186 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, 0444,
2187                           show_pwm_temp_map, set_pwm_temp_map, 1);
2188 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, 0644,
2189                             show_auto_pwm, set_auto_pwm, 1, 0);
2190 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, 0644,
2191                             show_auto_pwm, set_auto_pwm, 1, 1);
2192 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, 0644,
2193                             show_auto_pwm, set_auto_pwm, 1, 2);
2194 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, 0444,
2195                             show_auto_pwm, NULL, 1, 3);
2196 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, 0644,
2197                             show_auto_temp, set_auto_temp, 1, 1);
2198 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, 0644,
2199                             show_auto_temp, set_auto_temp, 1, 0);
2200 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, 0644,
2201                             show_auto_temp, set_auto_temp, 1, 2);
2202 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, 0644,
2203                             show_auto_temp, set_auto_temp, 1, 3);
2204 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, 0644,
2205                             show_auto_temp, set_auto_temp, 1, 4);
2206 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, 0644,
2207                             show_auto_pwm, set_auto_pwm, 1, 0);
2208 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, 0644,
2209                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2210
2211 static SENSOR_DEVICE_ATTR(pwm3_enable, 0644,
2212                           show_pwm_enable, set_pwm_enable, 2);
2213 static SENSOR_DEVICE_ATTR(pwm3, 0644, show_pwm, set_pwm, 2);
2214 static SENSOR_DEVICE_ATTR(pwm3_freq, 0444, show_pwm_freq, NULL, 2);
2215 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, 0444,
2216                           show_pwm_temp_map, set_pwm_temp_map, 2);
2217 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, 0644,
2218                             show_auto_pwm, set_auto_pwm, 2, 0);
2219 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, 0644,
2220                             show_auto_pwm, set_auto_pwm, 2, 1);
2221 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, 0644,
2222                             show_auto_pwm, set_auto_pwm, 2, 2);
2223 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, 0444,
2224                             show_auto_pwm, NULL, 2, 3);
2225 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, 0644,
2226                             show_auto_temp, set_auto_temp, 2, 1);
2227 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, 0644,
2228                             show_auto_temp, set_auto_temp, 2, 0);
2229 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, 0644,
2230                             show_auto_temp, set_auto_temp, 2, 2);
2231 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, 0644,
2232                             show_auto_temp, set_auto_temp, 2, 3);
2233 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, 0644,
2234                             show_auto_temp, set_auto_temp, 2, 4);
2235 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, 0644,
2236                             show_auto_pwm, set_auto_pwm, 2, 0);
2237 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, 0644,
2238                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2239
2240 static SENSOR_DEVICE_ATTR(pwm4_enable, 0644,
2241                           show_pwm_enable, set_pwm_enable, 3);
2242 static SENSOR_DEVICE_ATTR(pwm4, 0644, show_pwm, set_pwm, 3);
2243 static SENSOR_DEVICE_ATTR(pwm4_freq, 0444, show_pwm_freq, NULL, 3);
2244 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, 0444,
2245                           show_pwm_temp_map, set_pwm_temp_map, 3);
2246 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, 0644,
2247                             show_auto_temp, set_auto_temp, 2, 1);
2248 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, 0644,
2249                             show_auto_temp, set_auto_temp, 2, 0);
2250 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, 0644,
2251                             show_auto_temp, set_auto_temp, 2, 2);
2252 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, 0644,
2253                             show_auto_temp, set_auto_temp, 2, 3);
2254 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, 0644,
2255                             show_auto_pwm, set_auto_pwm, 3, 0);
2256 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, 0644,
2257                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2258
2259 static SENSOR_DEVICE_ATTR(pwm5_enable, 0644,
2260                           show_pwm_enable, set_pwm_enable, 4);
2261 static SENSOR_DEVICE_ATTR(pwm5, 0644, show_pwm, set_pwm, 4);
2262 static SENSOR_DEVICE_ATTR(pwm5_freq, 0444, show_pwm_freq, NULL, 4);
2263 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, 0444,
2264                           show_pwm_temp_map, set_pwm_temp_map, 4);
2265 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, 0644,
2266                             show_auto_temp, set_auto_temp, 2, 1);
2267 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, 0644,
2268                             show_auto_temp, set_auto_temp, 2, 0);
2269 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, 0644,
2270                             show_auto_temp, set_auto_temp, 2, 2);
2271 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, 0644,
2272                             show_auto_temp, set_auto_temp, 2, 3);
2273 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, 0644,
2274                             show_auto_pwm, set_auto_pwm, 4, 0);
2275 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, 0644,
2276                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2277
2278 static SENSOR_DEVICE_ATTR(pwm6_enable, 0644,
2279                           show_pwm_enable, set_pwm_enable, 5);
2280 static SENSOR_DEVICE_ATTR(pwm6, 0644, show_pwm, set_pwm, 5);
2281 static SENSOR_DEVICE_ATTR(pwm6_freq, 0444, show_pwm_freq, NULL, 5);
2282 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, 0444,
2283                           show_pwm_temp_map, set_pwm_temp_map, 5);
2284 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, 0644,
2285                             show_auto_temp, set_auto_temp, 2, 1);
2286 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, 0644,
2287                             show_auto_temp, set_auto_temp, 2, 0);
2288 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, 0644,
2289                             show_auto_temp, set_auto_temp, 2, 2);
2290 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, 0644,
2291                             show_auto_temp, set_auto_temp, 2, 3);
2292 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, 0644,
2293                             show_auto_pwm, set_auto_pwm, 5, 0);
2294 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, 0644,
2295                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2296
2297 /* Alarms */
2298 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2299                            char *buf)
2300 {
2301         struct it87_data *data = it87_update_device(dev);
2302
2303         if (IS_ERR(data))
2304                 return PTR_ERR(data);
2305
2306         return sprintf(buf, "%u\n", data->alarms);
2307 }
2308 static DEVICE_ATTR(alarms, 0444, show_alarms, NULL);
2309
2310 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2311                           char *buf)
2312 {
2313         struct it87_data *data = it87_update_device(dev);
2314         int bitnr = to_sensor_dev_attr(attr)->index;
2315
2316         if (IS_ERR(data))
2317                 return PTR_ERR(data);
2318
2319         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2320 }
2321
2322 static ssize_t clear_intrusion(struct device *dev,
2323                                struct device_attribute *attr, const char *buf,
2324                                size_t count)
2325 {
2326         struct it87_data *data = dev_get_drvdata(dev);
2327         int err, config;
2328         long val;
2329
2330         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2331                 return -EINVAL;
2332
2333         err = it87_lock(data);
2334         if (err)
2335                 return err;
2336
2337         config = data->read(data, IT87_REG_CONFIG);
2338         config |= BIT(5);
2339         data->write(data, IT87_REG_CONFIG, config);
2340         /* Invalidate cache to force re-read */
2341         data->valid = 0;
2342         it87_unlock(data);
2343         return count;
2344 }
2345
2346 static SENSOR_DEVICE_ATTR(in0_alarm, 0444, show_alarm, NULL, 8);
2347 static SENSOR_DEVICE_ATTR(in1_alarm, 0444, show_alarm, NULL, 9);
2348 static SENSOR_DEVICE_ATTR(in2_alarm, 0444, show_alarm, NULL, 10);
2349 static SENSOR_DEVICE_ATTR(in3_alarm, 0444, show_alarm, NULL, 11);
2350 static SENSOR_DEVICE_ATTR(in4_alarm, 0444, show_alarm, NULL, 12);
2351 static SENSOR_DEVICE_ATTR(in5_alarm, 0444, show_alarm, NULL, 13);
2352 static SENSOR_DEVICE_ATTR(in6_alarm, 0444, show_alarm, NULL, 14);
2353 static SENSOR_DEVICE_ATTR(in7_alarm, 0444, show_alarm, NULL, 15);
2354 static SENSOR_DEVICE_ATTR(fan1_alarm, 0444, show_alarm, NULL, 0);
2355 static SENSOR_DEVICE_ATTR(fan2_alarm, 0444, show_alarm, NULL, 1);
2356 static SENSOR_DEVICE_ATTR(fan3_alarm, 0444, show_alarm, NULL, 2);
2357 static SENSOR_DEVICE_ATTR(fan4_alarm, 0444, show_alarm, NULL, 3);
2358 static SENSOR_DEVICE_ATTR(fan5_alarm, 0444, show_alarm, NULL, 6);
2359 static SENSOR_DEVICE_ATTR(fan6_alarm, 0444, show_alarm, NULL, 7);
2360 static SENSOR_DEVICE_ATTR(temp1_alarm, 0444, show_alarm, NULL, 16);
2361 static SENSOR_DEVICE_ATTR(temp2_alarm, 0444, show_alarm, NULL, 17);
2362 static SENSOR_DEVICE_ATTR(temp3_alarm, 0444, show_alarm, NULL, 18);
2363 static SENSOR_DEVICE_ATTR(temp4_alarm, 0444, show_alarm, NULL, 19);
2364 static SENSOR_DEVICE_ATTR(temp5_alarm, 0444, show_alarm, NULL, 20);
2365 static SENSOR_DEVICE_ATTR(temp6_alarm, 0444, show_alarm, NULL, 21);
2366 static SENSOR_DEVICE_ATTR(intrusion0_alarm, 0644,
2367                           show_alarm, clear_intrusion, 4);
2368
2369 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2370                          char *buf)
2371 {
2372         struct it87_data *data = it87_update_device(dev);
2373         int bitnr = to_sensor_dev_attr(attr)->index;
2374
2375         if (IS_ERR(data))
2376                 return PTR_ERR(data);
2377
2378         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2379 }
2380
2381 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2382                         const char *buf, size_t count)
2383 {
2384         int bitnr = to_sensor_dev_attr(attr)->index;
2385         struct it87_data *data = dev_get_drvdata(dev);
2386         long val;
2387         int err;
2388
2389         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2390                 return -EINVAL;
2391
2392         err = it87_lock(data);
2393         if (err)
2394                 return err;
2395
2396         data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2397         if (val)
2398                 data->beeps |= BIT(bitnr);
2399         else
2400                 data->beeps &= ~BIT(bitnr);
2401         data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2402         it87_unlock(data);
2403         return count;
2404 }
2405
2406 static SENSOR_DEVICE_ATTR(in0_beep, 0644,
2407                           show_beep, set_beep, 1);
2408 static SENSOR_DEVICE_ATTR(in1_beep, 0444, show_beep, NULL, 1);
2409 static SENSOR_DEVICE_ATTR(in2_beep, 0444, show_beep, NULL, 1);
2410 static SENSOR_DEVICE_ATTR(in3_beep, 0444, show_beep, NULL, 1);
2411 static SENSOR_DEVICE_ATTR(in4_beep, 0444, show_beep, NULL, 1);
2412 static SENSOR_DEVICE_ATTR(in5_beep, 0444, show_beep, NULL, 1);
2413 static SENSOR_DEVICE_ATTR(in6_beep, 0444, show_beep, NULL, 1);
2414 static SENSOR_DEVICE_ATTR(in7_beep, 0444, show_beep, NULL, 1);
2415 /* fanX_beep writability is set later */
2416 static SENSOR_DEVICE_ATTR(fan1_beep, 0444, show_beep, set_beep, 0);
2417 static SENSOR_DEVICE_ATTR(fan2_beep, 0444, show_beep, set_beep, 0);
2418 static SENSOR_DEVICE_ATTR(fan3_beep, 0444, show_beep, set_beep, 0);
2419 static SENSOR_DEVICE_ATTR(fan4_beep, 0444, show_beep, set_beep, 0);
2420 static SENSOR_DEVICE_ATTR(fan5_beep, 0444, show_beep, set_beep, 0);
2421 static SENSOR_DEVICE_ATTR(fan6_beep, 0444, show_beep, set_beep, 0);
2422 static SENSOR_DEVICE_ATTR(temp1_beep, 0644,
2423                           show_beep, set_beep, 2);
2424 static SENSOR_DEVICE_ATTR(temp2_beep, 0444, show_beep, NULL, 2);
2425 static SENSOR_DEVICE_ATTR(temp3_beep, 0444, show_beep, NULL, 2);
2426 static SENSOR_DEVICE_ATTR(temp4_beep, 0444, show_beep, NULL, 2);
2427 static SENSOR_DEVICE_ATTR(temp5_beep, 0444, show_beep, NULL, 2);
2428 static SENSOR_DEVICE_ATTR(temp6_beep, 0444, show_beep, NULL, 2);
2429
2430 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2431                             char *buf)
2432 {
2433         struct it87_data *data = dev_get_drvdata(dev);
2434
2435         return sprintf(buf, "%u\n", data->vrm);
2436 }
2437
2438 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2439                              const char *buf, size_t count)
2440 {
2441         struct it87_data *data = dev_get_drvdata(dev);
2442         unsigned long val;
2443
2444         if (kstrtoul(buf, 10, &val) < 0)
2445                 return -EINVAL;
2446
2447         data->vrm = val;
2448
2449         return count;
2450 }
2451 static DEVICE_ATTR(vrm, 0644, show_vrm_reg, store_vrm_reg);
2452
2453 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2454                             char *buf)
2455 {
2456         struct it87_data *data = it87_update_device(dev);
2457
2458         if (IS_ERR(data))
2459                 return PTR_ERR(data);
2460
2461         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2462 }
2463 static DEVICE_ATTR(cpu0_vid, 0444, show_vid_reg, NULL);
2464
2465 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2466                           char *buf)
2467 {
2468         static const char * const labels[] = {
2469                 "+5V",
2470                 "5VSB",
2471                 "Vbat",
2472                 "AVCC",
2473         };
2474         static const char * const labels_it8721[] = {
2475                 "+3.3V",
2476                 "3VSB",
2477                 "Vbat",
2478                 "+3.3V",
2479         };
2480         struct it87_data *data = dev_get_drvdata(dev);
2481         int nr = to_sensor_dev_attr(attr)->index;
2482         const char *label;
2483
2484         if (has_vin3_5v(data) && nr == 0)
2485                 label = labels[0];
2486         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2487                  has_11mv_adc(data))
2488                 label = labels_it8721[nr];
2489         else
2490                 label = labels[nr];
2491
2492         return sprintf(buf, "%s\n", label);
2493 }
2494 static SENSOR_DEVICE_ATTR(in3_label, 0444, show_label, NULL, 0);
2495 static SENSOR_DEVICE_ATTR(in7_label, 0444, show_label, NULL, 1);
2496 static SENSOR_DEVICE_ATTR(in8_label, 0444, show_label, NULL, 2);
2497 /* AVCC3 */
2498 static SENSOR_DEVICE_ATTR(in9_label, 0444, show_label, NULL, 3);
2499
2500 static umode_t it87_in_is_visible(struct kobject *kobj,
2501                                   struct attribute *attr, int index)
2502 {
2503         struct device *dev = container_of(kobj, struct device, kobj);
2504         struct it87_data *data = dev_get_drvdata(dev);
2505         int i = index / 5;      /* voltage index */
2506         int a = index % 5;      /* attribute index */
2507
2508         if (index >= 40) {      /* in8 and higher only have input attributes */
2509                 i = index - 40 + 8;
2510                 a = 0;
2511         }
2512
2513         if (!(data->has_in & BIT(i)))
2514                 return 0;
2515
2516         if (a == 4 && !data->has_beep)
2517                 return 0;
2518
2519         return attr->mode;
2520 }
2521
2522 static struct attribute *it87_attributes_in[] = {
2523         &sensor_dev_attr_in0_input.dev_attr.attr,
2524         &sensor_dev_attr_in0_min.dev_attr.attr,
2525         &sensor_dev_attr_in0_max.dev_attr.attr,
2526         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2527         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2528
2529         &sensor_dev_attr_in1_input.dev_attr.attr,
2530         &sensor_dev_attr_in1_min.dev_attr.attr,
2531         &sensor_dev_attr_in1_max.dev_attr.attr,
2532         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2533         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2534
2535         &sensor_dev_attr_in2_input.dev_attr.attr,
2536         &sensor_dev_attr_in2_min.dev_attr.attr,
2537         &sensor_dev_attr_in2_max.dev_attr.attr,
2538         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2539         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2540
2541         &sensor_dev_attr_in3_input.dev_attr.attr,
2542         &sensor_dev_attr_in3_min.dev_attr.attr,
2543         &sensor_dev_attr_in3_max.dev_attr.attr,
2544         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2545         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2546
2547         &sensor_dev_attr_in4_input.dev_attr.attr,
2548         &sensor_dev_attr_in4_min.dev_attr.attr,
2549         &sensor_dev_attr_in4_max.dev_attr.attr,
2550         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2551         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2552
2553         &sensor_dev_attr_in5_input.dev_attr.attr,
2554         &sensor_dev_attr_in5_min.dev_attr.attr,
2555         &sensor_dev_attr_in5_max.dev_attr.attr,
2556         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2557         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2558
2559         &sensor_dev_attr_in6_input.dev_attr.attr,
2560         &sensor_dev_attr_in6_min.dev_attr.attr,
2561         &sensor_dev_attr_in6_max.dev_attr.attr,
2562         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2563         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2564
2565         &sensor_dev_attr_in7_input.dev_attr.attr,
2566         &sensor_dev_attr_in7_min.dev_attr.attr,
2567         &sensor_dev_attr_in7_max.dev_attr.attr,
2568         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2569         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2570
2571         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2572         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2573         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2574         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2575         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2576         NULL
2577 };
2578
2579 static const struct attribute_group it87_group_in = {
2580         .attrs = it87_attributes_in,
2581         .is_visible = it87_in_is_visible,
2582 };
2583
2584 static umode_t it87_temp_is_visible(struct kobject *kobj,
2585                                     struct attribute *attr, int index)
2586 {
2587         struct device *dev = container_of(kobj, struct device, kobj);
2588         struct it87_data *data = dev_get_drvdata(dev);
2589         int i = index / 7;      /* temperature index */
2590         int a = index % 7;      /* attribute index */
2591
2592         if (!(data->has_temp & BIT(i)))
2593                 return 0;
2594
2595         if (a && i >= data->num_temp_limit)
2596                 return 0;
2597
2598         if (a == 3) {
2599                 int type = get_temp_type(data, i);
2600
2601                 if (type == 0)
2602                         return 0;
2603                 if (has_bank_sel(data))
2604                         return 0444;
2605                 return attr->mode;
2606         }
2607
2608         if (a == 5 && i >= data->num_temp_offset)
2609                 return 0;
2610
2611         if (a == 6 && !data->has_beep)
2612                 return 0;
2613
2614         return attr->mode;
2615 }
2616
2617 static struct attribute *it87_attributes_temp[] = {
2618         &sensor_dev_attr_temp1_input.dev_attr.attr,
2619         &sensor_dev_attr_temp1_max.dev_attr.attr,
2620         &sensor_dev_attr_temp1_min.dev_attr.attr,
2621         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2622         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2623         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2624         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2625
2626         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2627         &sensor_dev_attr_temp2_max.dev_attr.attr,
2628         &sensor_dev_attr_temp2_min.dev_attr.attr,
2629         &sensor_dev_attr_temp2_type.dev_attr.attr,
2630         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2631         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2632         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2633
2634         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2635         &sensor_dev_attr_temp3_max.dev_attr.attr,
2636         &sensor_dev_attr_temp3_min.dev_attr.attr,
2637         &sensor_dev_attr_temp3_type.dev_attr.attr,
2638         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2639         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2640         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2641
2642         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2643         &sensor_dev_attr_temp4_max.dev_attr.attr,
2644         &sensor_dev_attr_temp4_min.dev_attr.attr,
2645         &sensor_dev_attr_temp4_type.dev_attr.attr,
2646         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2647         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2648         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2649
2650         &sensor_dev_attr_temp5_input.dev_attr.attr,
2651         &sensor_dev_attr_temp5_max.dev_attr.attr,
2652         &sensor_dev_attr_temp5_min.dev_attr.attr,
2653         &sensor_dev_attr_temp5_type.dev_attr.attr,
2654         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2655         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2656         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2657
2658         &sensor_dev_attr_temp6_input.dev_attr.attr,
2659         &sensor_dev_attr_temp6_max.dev_attr.attr,
2660         &sensor_dev_attr_temp6_min.dev_attr.attr,
2661         &sensor_dev_attr_temp6_type.dev_attr.attr,
2662         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2663         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2664         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2665         NULL
2666 };
2667
2668 static const struct attribute_group it87_group_temp = {
2669         .attrs = it87_attributes_temp,
2670         .is_visible = it87_temp_is_visible,
2671 };
2672
2673 static umode_t it87_is_visible(struct kobject *kobj,
2674                                struct attribute *attr, int index)
2675 {
2676         struct device *dev = container_of(kobj, struct device, kobj);
2677         struct it87_data *data = dev_get_drvdata(dev);
2678
2679         if ((index == 2 || index == 3) && !data->has_vid)
2680                 return 0;
2681
2682         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2683                 return 0;
2684
2685         return attr->mode;
2686 }
2687
2688 static struct attribute *it87_attributes[] = {
2689         &dev_attr_alarms.attr,
2690         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2691         &dev_attr_vrm.attr,                             /* 2 */
2692         &dev_attr_cpu0_vid.attr,                        /* 3 */
2693         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2694         &sensor_dev_attr_in7_label.dev_attr.attr,
2695         &sensor_dev_attr_in8_label.dev_attr.attr,
2696         &sensor_dev_attr_in9_label.dev_attr.attr,
2697         NULL
2698 };
2699
2700 static const struct attribute_group it87_group = {
2701         .attrs = it87_attributes,
2702         .is_visible = it87_is_visible,
2703 };
2704
2705 static umode_t it87_fan_is_visible(struct kobject *kobj,
2706                                    struct attribute *attr, int index)
2707 {
2708         struct device *dev = container_of(kobj, struct device, kobj);
2709         struct it87_data *data = dev_get_drvdata(dev);
2710         int i = index / 5;      /* fan index */
2711         int a = index % 5;      /* attribute index */
2712
2713         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2714                 i = (index - 15) / 4 + 3;
2715                 a = (index - 15) % 4;
2716         }
2717
2718         if (!(data->has_fan & BIT(i)))
2719                 return 0;
2720
2721         if (a == 3) {                           /* beep */
2722                 if (!data->has_beep)
2723                         return 0;
2724                 /* first fan beep attribute is writable */
2725                 if (i == __ffs(data->has_fan))
2726                         return attr->mode | 0200;
2727         }
2728
2729         if (a == 4 && has_16bit_fans(data))     /* divisor */
2730                 return 0;
2731
2732         return attr->mode;
2733 }
2734
2735 static struct attribute *it87_attributes_fan[] = {
2736         &sensor_dev_attr_fan1_input.dev_attr.attr,
2737         &sensor_dev_attr_fan1_min.dev_attr.attr,
2738         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2739         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2740         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2741
2742         &sensor_dev_attr_fan2_input.dev_attr.attr,
2743         &sensor_dev_attr_fan2_min.dev_attr.attr,
2744         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2745         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2746         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2747
2748         &sensor_dev_attr_fan3_input.dev_attr.attr,
2749         &sensor_dev_attr_fan3_min.dev_attr.attr,
2750         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2751         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2752         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2753
2754         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2755         &sensor_dev_attr_fan4_min.dev_attr.attr,
2756         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2757         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2758
2759         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2760         &sensor_dev_attr_fan5_min.dev_attr.attr,
2761         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2762         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2763
2764         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2765         &sensor_dev_attr_fan6_min.dev_attr.attr,
2766         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2767         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2768         NULL
2769 };
2770
2771 static const struct attribute_group it87_group_fan = {
2772         .attrs = it87_attributes_fan,
2773         .is_visible = it87_fan_is_visible,
2774 };
2775
2776 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2777                                    struct attribute *attr, int index)
2778 {
2779         struct device *dev = container_of(kobj, struct device, kobj);
2780         struct it87_data *data = dev_get_drvdata(dev);
2781         int i = index / 4;      /* pwm index */
2782         int a = index % 4;      /* attribute index */
2783
2784         if (!(data->has_pwm & BIT(i)))
2785                 return 0;
2786
2787         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2788         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2789                 return attr->mode | 0200;
2790
2791         /* pwm2_freq is writable if there are two pwm frequency selects */
2792         if (has_pwm_freq2(data) && i == 1 && a == 2)
2793                 return attr->mode | 0200;
2794
2795         return attr->mode;
2796 }
2797
2798 static struct attribute *it87_attributes_pwm[] = {
2799         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2800         &sensor_dev_attr_pwm1.dev_attr.attr,
2801         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2802         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2803
2804         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2805         &sensor_dev_attr_pwm2.dev_attr.attr,
2806         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2807         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2808
2809         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2810         &sensor_dev_attr_pwm3.dev_attr.attr,
2811         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2812         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2813
2814         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2815         &sensor_dev_attr_pwm4.dev_attr.attr,
2816         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2817         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2818
2819         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2820         &sensor_dev_attr_pwm5.dev_attr.attr,
2821         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2822         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2823
2824         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2825         &sensor_dev_attr_pwm6.dev_attr.attr,
2826         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2827         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2828
2829         NULL
2830 };
2831
2832 static const struct attribute_group it87_group_pwm = {
2833         .attrs = it87_attributes_pwm,
2834         .is_visible = it87_pwm_is_visible,
2835 };
2836
2837 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2838                                         struct attribute *attr, int index)
2839 {
2840         struct device *dev = container_of(kobj, struct device, kobj);
2841         struct it87_data *data = dev_get_drvdata(dev);
2842         int i = index / 11;     /* pwm index */
2843         int a = index % 11;     /* attribute index */
2844
2845         if (index >= 33) {      /* pwm 4..6 */
2846                 i = (index - 33) / 6 + 3;
2847                 a = (index - 33) % 6 + 4;
2848         }
2849
2850         if (!(data->has_pwm & BIT(i)))
2851                 return 0;
2852
2853         if (has_newer_autopwm(data)) {
2854                 if (a < 4)      /* no auto point pwm */
2855                         return 0;
2856                 if (a == 8)     /* no auto_point4 */
2857                         return 0;
2858         }
2859         if (has_old_autopwm(data)) {
2860                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2861                         return 0;
2862         }
2863
2864         return attr->mode;
2865 }
2866
2867 static struct attribute *it87_attributes_auto_pwm[] = {
2868         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2869         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2870         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2871         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2872         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2873         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2874         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2875         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2876         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2877         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2878         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2879
2880         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2881         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2882         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2883         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2884         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2885         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2886         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2887         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2888         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2889         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2890         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2891
2892         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2893         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2894         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2895         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2896         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2897         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2898         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2899         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2900         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2901         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2902         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2903
2904         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2905         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2906         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2907         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2908         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2909         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2910
2911         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2912         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2913         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2914         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2915         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2916         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2917
2918         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2919         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2920         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2921         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2922         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2923         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2924
2925         NULL,
2926 };
2927
2928 static const struct attribute_group it87_group_auto_pwm = {
2929         .attrs = it87_attributes_auto_pwm,
2930         .is_visible = it87_auto_pwm_is_visible,
2931 };
2932
2933 /* SuperIO detection - will change isa_address if a chip is found */
2934 static int __init it87_find(int sioaddr, unsigned short *address,
2935                             phys_addr_t *mmio_address, struct it87_sio_data *sio_data)
2936 {
2937         const struct it87_devices *config;
2938         phys_addr_t base = 0;
2939         bool doexit = true;
2940         char mmio_str[32];
2941         u16 chip_type;
2942         int err;
2943
2944         err = superio_enter(sioaddr);
2945         if (err)
2946                 return err;
2947
2948         sio_data->sioaddr = sioaddr;
2949
2950         err = -ENODEV;
2951         chip_type = superio_inw(sioaddr, DEVID);
2952         if (chip_type == 0xffff)
2953                 goto exit;
2954
2955         if (force_id)
2956                 chip_type = force_id;
2957
2958         switch (chip_type) {
2959         case IT8705F_DEVID:
2960                 sio_data->type = it87;
2961                 break;
2962         case IT8712F_DEVID:
2963                 sio_data->type = it8712;
2964                 break;
2965         case IT8716F_DEVID:
2966         case IT8726F_DEVID:
2967                 sio_data->type = it8716;
2968                 break;
2969         case IT8718F_DEVID:
2970                 sio_data->type = it8718;
2971                 break;
2972         case IT8720F_DEVID:
2973                 sio_data->type = it8720;
2974                 break;
2975         case IT8721F_DEVID:
2976                 sio_data->type = it8721;
2977                 break;
2978         case IT8728F_DEVID:
2979                 sio_data->type = it8728;
2980                 break;
2981         case IT8732F_DEVID:
2982                 sio_data->type = it8732;
2983                 break;
2984         case IT8792E_DEVID:
2985                 sio_data->type = it8792;
2986                 /*
2987                  * Disabling configuration mode on IT8792E can result in system
2988                  * hang-ups and access failures to the Super-IO chip at the
2989                  * second SIO address. Never exit configuration mode on this
2990                  * chip to avoid the problem.
2991                  */
2992                 doexit = false;
2993                 break;
2994         case IT8771E_DEVID:
2995                 sio_data->type = it8771;
2996                 break;
2997         case IT8772E_DEVID:
2998                 sio_data->type = it8772;
2999                 break;
3000         case IT8781F_DEVID:
3001                 sio_data->type = it8781;
3002                 break;
3003         case IT8782F_DEVID:
3004                 sio_data->type = it8782;
3005                 break;
3006         case IT8783E_DEVID:
3007                 sio_data->type = it8783;
3008                 break;
3009         case IT8786E_DEVID:
3010                 sio_data->type = it8786;
3011                 break;
3012         case IT8790E_DEVID:
3013                 sio_data->type = it8790;
3014                 doexit = false;         /* See IT8792E comment above */
3015                 break;
3016         case IT8603E_DEVID:
3017         case IT8623E_DEVID:
3018                 sio_data->type = it8603;
3019                 break;
3020         case IT8607E_DEVID:
3021                 sio_data->type = it8607;
3022                 break;
3023         case IT8613E_DEVID:
3024                 sio_data->type = it8613;
3025                 break;
3026         case IT8620E_DEVID:
3027                 sio_data->type = it8620;
3028                 break;
3029         case IT8622E_DEVID:
3030                 sio_data->type = it8622;
3031                 break;
3032         case IT8625E_DEVID:
3033                 sio_data->type = it8625;
3034                 break;
3035         case IT8628E_DEVID:
3036                 sio_data->type = it8628;
3037                 break;
3038         case IT8655E_DEVID:
3039                 sio_data->type = it8655;
3040                 break;
3041         case IT8665E_DEVID:
3042                 sio_data->type = it8665;
3043                 break;
3044         case IT8686E_DEVID:
3045                 sio_data->type = it8686;
3046                 break;
3047         case 0xffff:    /* No device at all */
3048                 goto exit;
3049         default:
3050                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3051                 goto exit;
3052         }
3053
3054         superio_select(sioaddr, PME);
3055         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3056                 pr_info("Device not activated, skipping\n");
3057                 goto exit;
3058         }
3059
3060         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3061         if (*address == 0) {
3062                 pr_info("Base address not set, skipping\n");
3063                 goto exit;
3064         }
3065
3066         sio_data->doexit = doexit;
3067
3068         err = 0;
3069         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3070
3071         config = &it87_devices[sio_data->type];
3072
3073         if (has_mmio(config) && mmio) {
3074                 u8 reg;
3075
3076                 reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
3077                 if (reg & BIT(5)) {
3078                         base = 0xf0000000 + ((reg & 0x0f) << 24);
3079                         base += (reg & 0xc0) << 14;
3080                 }
3081         }
3082         *mmio_address = base;
3083
3084         mmio_str[0] = '\0';
3085         if (base)
3086                 snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
3087
3088         pr_info("Found IT%04x%s chip at 0x%x%s, revision %d\n", chip_type,
3089                 it87_devices[sio_data->type].suffix,
3090                 *address, mmio_str, sio_data->revision);
3091
3092         /* in7 (VSB or VCCH5V) is always internal on some chips */
3093         if (has_in7_internal(config))
3094                 sio_data->internal |= BIT(1);
3095
3096         /* in8 (Vbat) is always internal */
3097         sio_data->internal |= BIT(2);
3098
3099         /* in9 (AVCC3), always internal if supported */
3100         if (has_avcc3(config))
3101                 sio_data->internal |= BIT(3); /* in9 is AVCC */
3102         else
3103                 sio_data->skip_in |= BIT(9);
3104
3105         if (!has_four_pwm(config))
3106                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3107         else if (!has_five_pwm(config))
3108                 sio_data->skip_pwm |= BIT(4) | BIT(5);
3109         else if (!has_six_pwm(config))
3110                 sio_data->skip_pwm |= BIT(5);
3111
3112         if (!has_vid(config))
3113                 sio_data->skip_vid = 1;
3114
3115         /* Read GPIO config and VID value from LDN 7 (GPIO) */
3116         if (sio_data->type == it87) {
3117                 /* The IT8705F has a different LD number for GPIO */
3118                 superio_select(sioaddr, 5);
3119                 sio_data->beep_pin = superio_inb(sioaddr,
3120                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3121         } else if (sio_data->type == it8783) {
3122                 int reg25, reg27, reg2a, reg2c, regef;
3123
3124                 superio_select(sioaddr, GPIO);
3125
3126                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3127                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3128                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3129                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3130                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3131
3132                 /* Check if fan3 is there or not */
3133                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3134                         sio_data->skip_fan |= BIT(2);
3135                 if ((reg25 & BIT(4)) ||
3136                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
3137                         sio_data->skip_pwm |= BIT(2);
3138
3139                 /* Check if fan2 is there or not */
3140                 if (reg27 & BIT(7))
3141                         sio_data->skip_fan |= BIT(1);
3142                 if (reg27 & BIT(3))
3143                         sio_data->skip_pwm |= BIT(1);
3144
3145                 /* VIN5 */
3146                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3147                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3148
3149                 /* VIN6 */
3150                 if (reg27 & BIT(1))
3151                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3152
3153                 /*
3154                  * VIN7
3155                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3156                  */
3157                 if (reg27 & BIT(2)) {
3158                         /*
3159                          * The data sheet is a bit unclear regarding the
3160                          * internal voltage divider for VCCH5V. It says
3161                          * "This bit enables and switches VIN7 (pin 91) to the
3162                          * internal voltage divider for VCCH5V".
3163                          * This is different to other chips, where the internal
3164                          * voltage divider would connect VIN7 to an internal
3165                          * voltage source. Maybe that is the case here as well.
3166                          *
3167                          * Since we don't know for sure, re-route it if that is
3168                          * not the case, and ask the user to report if the
3169                          * resulting voltage is sane.
3170                          */
3171                         if (!(reg2c & BIT(1))) {
3172                                 reg2c |= BIT(1);
3173                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3174                                              reg2c);
3175                                 pr_notice("Routing internal VCCH5V to in7.\n");
3176                         }
3177                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3178                         pr_notice("Please report if it displays a reasonable voltage.\n");
3179                 }
3180
3181                 if (reg2c & BIT(0))
3182                         sio_data->internal |= BIT(0);
3183                 if (reg2c & BIT(1))
3184                         sio_data->internal |= BIT(1);
3185
3186                 sio_data->beep_pin = superio_inb(sioaddr,
3187                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3188         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3189                 int reg27, reg29;
3190
3191                 superio_select(sioaddr, GPIO);
3192
3193                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3194
3195                 /* Check if fan3 is there or not */
3196                 if (reg27 & BIT(6))
3197                         sio_data->skip_pwm |= BIT(2);
3198                 if (reg27 & BIT(7))
3199                         sio_data->skip_fan |= BIT(2);
3200
3201                 /* Check if fan2 is there or not */
3202                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3203                 if (reg29 & BIT(1))
3204                         sio_data->skip_pwm |= BIT(1);
3205                 if (reg29 & BIT(2))
3206                         sio_data->skip_fan |= BIT(1);
3207
3208                 switch (sio_data->type) {
3209                 case it8603:
3210                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3211                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3212                         break;
3213                 case it8607:
3214                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3215                         sio_data->skip_fan |= BIT(0);
3216                 default:
3217                         break;
3218                 }
3219
3220                 sio_data->beep_pin = superio_inb(sioaddr,
3221                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3222         } else if (sio_data->type == it8613) {
3223                 int reg27, reg29, reg2a;
3224
3225                 superio_select(sioaddr, GPIO);
3226
3227                 /* Check for pwm3, fan3, pwm5, fan5 */
3228                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3229                 if (reg27 & BIT(1))
3230                         sio_data->skip_fan |= BIT(4);
3231                 if (reg27 & BIT(3))
3232                         sio_data->skip_pwm |= BIT(4);
3233                 if (reg27 & BIT(6))
3234                         sio_data->skip_pwm |= BIT(2);
3235                 if (reg27 & BIT(7))
3236                         sio_data->skip_fan |= BIT(2);
3237
3238                 /* Check for pwm2, fan2 */
3239                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3240                 if (reg29 & BIT(1))
3241                         sio_data->skip_pwm |= BIT(1);
3242                 if (reg29 & BIT(2))
3243                         sio_data->skip_fan |= BIT(1);
3244
3245                 /* Check for pwm4, fan4 */
3246                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3247                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3248                         sio_data->skip_fan |= BIT(3);
3249                         sio_data->skip_pwm |= BIT(3);
3250                 }
3251
3252                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3253                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3254                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3255                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3256
3257                 sio_data->beep_pin = superio_inb(sioaddr,
3258                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3259         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3260                    sio_data->type == it8686) {
3261                 int reg;
3262
3263                 superio_select(sioaddr, GPIO);
3264
3265                 /* Check for pwm5 */
3266                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3267                 if (reg & BIT(6))
3268                         sio_data->skip_pwm |= BIT(4);
3269
3270                 /* Check for fan4, fan5 */
3271                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3272                 if (!(reg & BIT(5)))
3273                         sio_data->skip_fan |= BIT(3);
3274                 if (!(reg & BIT(4)))
3275                         sio_data->skip_fan |= BIT(4);
3276
3277                 /* Check for pwm3, fan3 */
3278                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3279                 if (reg & BIT(6))
3280                         sio_data->skip_pwm |= BIT(2);
3281                 if (reg & BIT(7))
3282                         sio_data->skip_fan |= BIT(2);
3283
3284                 /* Check for pwm4 */
3285                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3286                 if (reg & BIT(2))
3287                         sio_data->skip_pwm |= BIT(3);
3288
3289                 /* Check for pwm2, fan2 */
3290                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3291                 if (reg & BIT(1))
3292                         sio_data->skip_pwm |= BIT(1);
3293                 if (reg & BIT(2))
3294                         sio_data->skip_fan |= BIT(1);
3295                 /* Check for pwm6, fan6 */
3296                 if (!(reg & BIT(7))) {
3297                         sio_data->skip_pwm |= BIT(5);
3298                         sio_data->skip_fan |= BIT(5);
3299                 }
3300
3301                 /* Check if AVCC is on VIN3 */
3302                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3303                 if (reg & BIT(0)) {
3304                         /* For it8686, the bit just enables AVCC3 */
3305                         if (sio_data->type != it8686)
3306                                 sio_data->internal |= BIT(0);
3307                 } else {
3308                         sio_data->internal &= ~BIT(3);
3309                         sio_data->skip_in |= BIT(9);
3310                 }
3311
3312                 sio_data->beep_pin = superio_inb(sioaddr,
3313                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3314         } else if (sio_data->type == it8622) {
3315                 int reg;
3316
3317                 superio_select(sioaddr, GPIO);
3318
3319                 /* Check for pwm4, fan4 */
3320                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3321                 if (reg & BIT(6))
3322                         sio_data->skip_fan |= BIT(3);
3323                 if (reg & BIT(5))
3324                         sio_data->skip_pwm |= BIT(3);
3325
3326                 /* Check for pwm3, fan3, pwm5, fan5 */
3327                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3328                 if (reg & BIT(6))
3329                         sio_data->skip_pwm |= BIT(2);
3330                 if (reg & BIT(7))
3331                         sio_data->skip_fan |= BIT(2);
3332                 if (reg & BIT(3))
3333                         sio_data->skip_pwm |= BIT(4);
3334                 if (reg & BIT(1))
3335                         sio_data->skip_fan |= BIT(4);
3336
3337                 /* Check for pwm2, fan2 */
3338                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3339                 if (reg & BIT(1))
3340                         sio_data->skip_pwm |= BIT(1);
3341                 if (reg & BIT(2))
3342                         sio_data->skip_fan |= BIT(1);
3343
3344                 /* Check for AVCC */
3345                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3346                 if (!(reg & BIT(0)))
3347                         sio_data->skip_in |= BIT(9);
3348
3349                 sio_data->beep_pin = superio_inb(sioaddr,
3350                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3351         } else if (sio_data->type == it8732) {
3352                 int reg;
3353
3354                 superio_select(sioaddr, GPIO);
3355
3356                 /* Check for pwm2, fan2 */
3357                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3358                 if (reg & BIT(1))
3359                         sio_data->skip_pwm |= BIT(1);
3360                 if (reg & BIT(2))
3361                         sio_data->skip_fan |= BIT(1);
3362
3363                 /* Check for pwm3, fan3, fan4 */
3364                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3365                 if (reg & BIT(6))
3366                         sio_data->skip_pwm |= BIT(2);
3367                 if (reg & BIT(7))
3368                         sio_data->skip_fan |= BIT(2);
3369                 if (reg & BIT(5))
3370                         sio_data->skip_fan |= BIT(3);
3371
3372                 /* Check if AVCC is on VIN3 */
3373                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3374                 if (reg & BIT(0))
3375                         sio_data->internal |= BIT(0);
3376
3377                 sio_data->beep_pin = superio_inb(sioaddr,
3378                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3379         } else if (sio_data->type == it8655) {
3380                 int reg;
3381
3382                 superio_select(sioaddr, GPIO);
3383
3384                 /* Check for pwm2 */
3385                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3386                 if (reg & BIT(1))
3387                         sio_data->skip_pwm |= BIT(1);
3388
3389                 /* Check for fan2 */
3390                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3391                 if (reg & BIT(4))
3392                         sio_data->skip_fan |= BIT(1);
3393
3394                 /* Check for pwm3, fan3 */
3395                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3396                 if (reg & BIT(6))
3397                         sio_data->skip_pwm |= BIT(2);
3398                 if (reg & BIT(7))
3399                         sio_data->skip_fan |= BIT(2);
3400
3401                 sio_data->beep_pin = superio_inb(sioaddr,
3402                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3403         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3404                 int reg27, reg29, reg2d, regd3;
3405
3406                 superio_select(sioaddr, GPIO);
3407
3408                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3409                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3410                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3411                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3412
3413                 /* Check for pwm2, fan2 */
3414                 if (reg29 & BIT(1))
3415                         sio_data->skip_pwm |= BIT(1);
3416                 /*
3417                  * Note: Table 6-1 in datasheet claims that FAN_TAC2
3418                  * would be enabled with 29h[2]=0.
3419                  */
3420                 if (reg2d & BIT(4))
3421                         sio_data->skip_fan |= BIT(1);
3422
3423                 /* Check for pwm3, fan3 */
3424                 if (reg27 & BIT(6))
3425                         sio_data->skip_pwm |= BIT(2);
3426                 if (reg27 & BIT(7))
3427                         sio_data->skip_fan |= BIT(2);
3428
3429                 /* Check for pwm4, fan4, pwm5, fan5 */
3430                 if (sio_data->type == it8625) {
3431                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3432
3433                         if (reg25 & BIT(6))
3434                                 sio_data->skip_fan |= BIT(3);
3435                         if (reg25 & BIT(5))
3436                                 sio_data->skip_pwm |= BIT(3);
3437                         if (reg27 & BIT(3))
3438                                 sio_data->skip_pwm |= BIT(4);
3439                         if (reg27 & BIT(1))
3440                                 sio_data->skip_fan |= BIT(4);
3441                 } else {
3442                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3443
3444                         if (regd3 & BIT(2))
3445                                 sio_data->skip_pwm |= BIT(3);
3446                         if (regd3 & BIT(3))
3447                                 sio_data->skip_fan |= BIT(3);
3448                         if (reg26 & BIT(5))
3449                                 sio_data->skip_pwm |= BIT(4);
3450                         if (reg26 & BIT(4))
3451                                 sio_data->skip_fan |= BIT(4);
3452                 }
3453
3454                 /* Check for pwm6, fan6 */
3455                 if (regd3 & BIT(0))
3456                         sio_data->skip_pwm |= BIT(5);
3457                 if (regd3 & BIT(1))
3458                         sio_data->skip_fan |= BIT(5);
3459
3460                 sio_data->beep_pin = superio_inb(sioaddr,
3461                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3462         } else {
3463                 int reg;
3464                 bool uart6;
3465
3466                 superio_select(sioaddr, GPIO);
3467
3468                 /* Check for fan4, fan5 */
3469                 if (has_five_fans(config)) {
3470                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3471                         switch (sio_data->type) {
3472                         case it8718:
3473                                 if (reg & BIT(5))
3474                                         sio_data->skip_fan |= BIT(3);
3475                                 if (reg & BIT(4))
3476                                         sio_data->skip_fan |= BIT(4);
3477                                 break;
3478                         case it8720:
3479                         case it8721:
3480                         case it8728:
3481                                 if (!(reg & BIT(5)))
3482                                         sio_data->skip_fan |= BIT(3);
3483                                 if (!(reg & BIT(4)))
3484                                         sio_data->skip_fan |= BIT(4);
3485                                 break;
3486                         default:
3487                                 break;
3488                         }
3489                 }
3490
3491                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3492                 if (!sio_data->skip_vid) {
3493                         /* We need at least 4 VID pins */
3494                         if (reg & 0x0f) {
3495                                 pr_info("VID is disabled (pins used for GPIO)\n");
3496                                 sio_data->skip_vid = 1;
3497                         }
3498                 }
3499
3500                 /* Check if fan3 is there or not */
3501                 if (reg & BIT(6))
3502                         sio_data->skip_pwm |= BIT(2);
3503                 if (reg & BIT(7))
3504                         sio_data->skip_fan |= BIT(2);
3505
3506                 /* Check if fan2 is there or not */
3507                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3508                 if (reg & BIT(1))
3509                         sio_data->skip_pwm |= BIT(1);
3510                 if (reg & BIT(2))
3511                         sio_data->skip_fan |= BIT(1);
3512
3513                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3514                     !(sio_data->skip_vid))
3515                         sio_data->vid_value = superio_inb(sioaddr,
3516                                                           IT87_SIO_VID_REG);
3517
3518                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3519
3520                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3521
3522                 /*
3523                  * The IT8720F has no VIN7 pin, so VCCH should always be
3524                  * routed internally to VIN7 with an internal divider.
3525                  * Curiously, there still is a configuration bit to control
3526                  * this, which means it can be set incorrectly. And even
3527                  * more curiously, many boards out there are improperly
3528                  * configured, even though the IT8720F datasheet claims
3529                  * that the internal routing of VCCH to VIN7 is the default
3530                  * setting. So we force the internal routing in this case.
3531                  *
3532                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3533                  * If UART6 is enabled, re-route VIN7 to the internal divider
3534                  * if that is not already the case.
3535                  */
3536                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3537                         reg |= BIT(1);
3538                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3539                         pr_notice("Routing internal VCCH to in7\n");
3540                 }
3541                 if (reg & BIT(0))
3542                         sio_data->internal |= BIT(0);
3543                 if (reg & BIT(1))
3544                         sio_data->internal |= BIT(1);
3545
3546                 /*
3547                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3548                  * While VIN7 can be routed to the internal voltage divider,
3549                  * VIN5 and VIN6 are not available if UART6 is enabled.
3550                  *
3551                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3552                  * is the temperature source. Since we can not read the
3553                  * temperature source here, skip_temp is preliminary.
3554                  */
3555                 if (uart6) {
3556                         sio_data->skip_in |= BIT(5) | BIT(6);
3557                         sio_data->skip_temp |= BIT(2);
3558                 }
3559
3560                 sio_data->beep_pin = superio_inb(sioaddr,
3561                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3562         }
3563         if (sio_data->beep_pin)
3564                 pr_info("Beeping is supported\n");
3565
3566         if (config->smbus_bitmap && !base) {
3567                 u8 reg;
3568
3569                 superio_select(sioaddr, PME);
3570                 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3571                 sio_data->ec_special_config = reg;
3572                 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3573         }
3574
3575 exit:
3576         superio_exit(sioaddr, doexit);
3577         return err;
3578 }
3579
3580 static void it87_init_regs(struct platform_device *pdev)
3581 {
3582         struct it87_data *data = platform_get_drvdata(pdev);
3583
3584         /* Initialize chip specific register pointers */
3585         switch (data->type) {
3586         case it8628:
3587         case it8686:
3588                 data->REG_FAN = IT87_REG_FAN;
3589                 data->REG_FANX = IT87_REG_FANX;
3590                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3591                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3592                 data->REG_PWM = IT87_REG_PWM;
3593                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3594                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3595                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3596                 break;
3597         case it8625:
3598         case it8655:
3599         case it8665:
3600                 data->REG_FAN = IT87_REG_FAN_8665;
3601                 data->REG_FANX = IT87_REG_FANX_8665;
3602                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3603                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3604                 data->REG_PWM = IT87_REG_PWM_8665;
3605                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3606                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3607                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3608                 break;
3609         case it8622:
3610                 data->REG_FAN = IT87_REG_FAN;
3611                 data->REG_FANX = IT87_REG_FANX;
3612                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3613                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3614                 data->REG_PWM = IT87_REG_PWM_8665;
3615                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3616                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3617                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3618                 break;
3619         case it8613:
3620                 data->REG_FAN = IT87_REG_FAN;
3621                 data->REG_FANX = IT87_REG_FANX;
3622                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3623                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3624                 data->REG_PWM = IT87_REG_PWM_8665;
3625                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3626                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3627                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3628                 break;
3629         default:
3630                 data->REG_FAN = IT87_REG_FAN;
3631                 data->REG_FANX = IT87_REG_FANX;
3632                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3633                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3634                 data->REG_PWM = IT87_REG_PWM;
3635                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3636                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3637                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3638                 break;
3639         }
3640
3641         if (data->mmio) {
3642                 data->read = it87_mmio_read;
3643                 data->write = it87_mmio_write;
3644         } else if (has_bank_sel(data)) {
3645                 data->read = it87_io_read;
3646                 data->write = it87_io_write;
3647         } else {
3648                 data->read = _it87_io_read;
3649                 data->write = _it87_io_write;
3650         }
3651 }
3652
3653 /* Called when we have found a new IT87. */
3654 static void it87_init_device(struct platform_device *pdev)
3655 {
3656         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3657         struct it87_data *data = platform_get_drvdata(pdev);
3658         int tmp, i;
3659         u8 mask;
3660
3661         if (has_new_tempmap(data)) {
3662                 data->pwm_temp_map_shift = 3;
3663                 data->pwm_temp_map_mask = 0x07;
3664         } else {
3665                 data->pwm_temp_map_shift = 0;
3666                 data->pwm_temp_map_mask = 0x03;
3667         }
3668
3669         /*
3670          * For each PWM channel:
3671          * - If it is in automatic mode, setting to manual mode should set
3672          *   the fan to full speed by default.
3673          * - If it is in manual mode, we need a mapping to temperature
3674          *   channels to use when later setting to automatic mode later.
3675          *   Map to the first sensor by default (we are clueless.)
3676          * In both cases, the value can (and should) be changed by the user
3677          * prior to switching to a different mode.
3678          * Note that this is no longer needed for the IT8721F and later, as
3679          * these have separate registers for the temperature mapping and the
3680          * manual duty cycle.
3681          */
3682         for (i = 0; i < NUM_AUTO_PWM; i++) {
3683                 data->pwm_temp_map[i] = 0;
3684                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3685                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3686         }
3687
3688         /*
3689          * Some chips seem to have default value 0xff for all limit
3690          * registers. For low voltage limits it makes no sense and triggers
3691          * alarms, so change to 0 instead. For high temperature limits, it
3692          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3693          * but is still confusing, so change to 127 degrees C.
3694          */
3695         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3696                 tmp = data->read(data, IT87_REG_VIN_MIN(i));
3697                 if (tmp == 0xff)
3698                         data->write(data, IT87_REG_VIN_MIN(i), 0);
3699         }
3700         for (i = 0; i < data->num_temp_limit; i++) {
3701                 tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3702                 if (tmp == 0xff)
3703                         data->write(data, data->REG_TEMP_HIGH[i], 127);
3704         }
3705
3706         /*
3707          * Temperature channels are not forcibly enabled, as they can be
3708          * set to two different sensor types and we can't guess which one
3709          * is correct for a given system. These channels can be enabled at
3710          * run-time through the temp{1-3}_type sysfs accessors if needed.
3711          */
3712
3713         /* Check if voltage monitors are reset manually or by some reason */
3714         tmp = data->read(data, IT87_REG_VIN_ENABLE);
3715         if ((tmp & 0xff) == 0) {
3716                 /* Enable all voltage monitors */
3717                 data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3718         }
3719
3720         /* Check if tachometers are reset manually or by some reason */
3721         mask = 0x70 & ~(sio_data->skip_fan << 4);
3722         data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3723         if ((data->fan_main_ctrl & mask) == 0) {
3724                 /* Enable all fan tachometers */
3725                 data->fan_main_ctrl |= mask;
3726                 data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3727         }
3728         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3729
3730         tmp = data->read(data, IT87_REG_FAN_16BIT);
3731
3732         /* Set tachometers to 16-bit mode if needed */
3733         if (has_fan16_config(data)) {
3734                 if (~tmp & 0x07 & data->has_fan) {
3735                         dev_dbg(&pdev->dev,
3736                                 "Setting fan1-3 to 16-bit mode\n");
3737                         data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3738                 }
3739         }
3740
3741         /* Check for additional fans */
3742         if (has_four_fans(data) && (tmp & BIT(4)))
3743                 data->has_fan |= BIT(3); /* fan4 enabled */
3744         if (has_five_fans(data) && (tmp & BIT(5)))
3745                 data->has_fan |= BIT(4); /* fan5 enabled */
3746         if (has_six_fans(data)) {
3747                 switch (data->type) {
3748                 case it8620:
3749                 case it8628:
3750                 case it8686:
3751                         if (tmp & BIT(2))
3752                                 data->has_fan |= BIT(5); /* fan6 enabled */
3753                         break;
3754                 case it8625:
3755                 case it8665:
3756                         tmp = data->read(data, IT87_REG_FAN_DIV);
3757                         if (tmp & BIT(3))
3758                                 data->has_fan |= BIT(5); /* fan6 enabled */
3759                         break;
3760                 default:
3761                         break;
3762                 }
3763         }
3764
3765         /* Fan input pins may be used for alternative functions */
3766         data->has_fan &= ~sio_data->skip_fan;
3767
3768         /* Check if pwm6 is enabled */
3769         if (has_six_pwm(data)) {
3770                 switch (data->type) {
3771                 case it8620:
3772                 case it8686:
3773                         tmp = data->read(data, IT87_REG_FAN_DIV);
3774                         if (!(tmp & BIT(3)))
3775                                 sio_data->skip_pwm |= BIT(5);
3776                         break;
3777                 default:
3778                         break;
3779                 }
3780         }
3781
3782         if (has_bank_sel(data)) {
3783                 for (i = 0; i < 3; i++)
3784                         data->temp_src[i] =
3785                                 data->read(data, IT87_REG_TEMP_SRC1[i]);
3786                 data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3787         }
3788
3789         /* Start monitoring */
3790         data->write(data, IT87_REG_CONFIG,
3791                     (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3792                                         (update_vbat ? 0x41 : 0x01));
3793 }
3794
3795 /* Return 1 if and only if the PWM interface is safe to use */
3796 static int it87_check_pwm(struct device *dev)
3797 {
3798         struct it87_data *data = dev_get_drvdata(dev);
3799         /*
3800          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3801          * and polarity set to active low is sign that this is the case so we
3802          * disable pwm control to protect the user.
3803          */
3804         int tmp = data->read(data, IT87_REG_FAN_CTL);
3805
3806         if ((tmp & 0x87) == 0) {
3807                 if (fix_pwm_polarity) {
3808                         /*
3809                          * The user asks us to attempt a chip reconfiguration.
3810                          * This means switching to active high polarity and
3811                          * inverting all fan speed values.
3812                          */
3813                         int i;
3814                         u8 pwm[3];
3815
3816                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3817                                 pwm[i] = data->read(data,
3818                                                          data->REG_PWM[i]);
3819
3820                         /*
3821                          * If any fan is in automatic pwm mode, the polarity
3822                          * might be correct, as suspicious as it seems, so we
3823                          * better don't change anything (but still disable the
3824                          * PWM interface).
3825                          */
3826                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3827                                 dev_info(dev,
3828                                          "Reconfiguring PWM to active high polarity\n");
3829                                 data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3830                                 for (i = 0; i < 3; i++)
3831                                         data->write(data, data->REG_PWM[i],
3832                                                     0x7f & ~pwm[i]);
3833                                 return 1;
3834                         }
3835
3836                         dev_info(dev,
3837                                  "PWM configuration is too broken to be fixed\n");
3838                 }
3839
3840                 dev_info(dev,
3841                          "Detected broken BIOS defaults, disabling PWM interface\n");
3842                 return 0;
3843         } else if (fix_pwm_polarity) {
3844                 dev_info(dev,
3845                          "PWM configuration looks sane, won't touch\n");
3846         }
3847
3848         return 1;
3849 }
3850
3851 static int it87_probe(struct platform_device *pdev)
3852 {
3853         struct it87_data *data;
3854         struct resource *res;
3855         struct device *dev = &pdev->dev;
3856         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3857         int enable_pwm_interface;
3858         struct device *hwmon_dev;
3859         int err;
3860
3861         data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3862         if (!data)
3863                 return -ENOMEM;
3864
3865         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3866         if (res) {
3867                 if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3868                                          DRVNAME)) {
3869                         dev_err(dev, "Failed to request region %pR\n", res);
3870                         return -EBUSY;
3871                 }
3872         } else {
3873                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3874                 data->mmio = devm_ioremap_resource(dev, res);
3875                 if (IS_ERR(data->mmio))
3876                         return PTR_ERR(data->mmio);
3877         }
3878
3879         data->addr = res->start;
3880         data->type = sio_data->type;
3881         data->sioaddr = sio_data->sioaddr;
3882         data->smbus_bitmap = sio_data->smbus_bitmap;
3883         data->ec_special_config = sio_data->ec_special_config;
3884         data->doexit = sio_data->doexit;
3885         data->features = it87_devices[sio_data->type].features;
3886         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3887         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3888         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3889         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3890         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3891
3892         /*
3893          * IT8705F Datasheet 0.4.1, 3h == Version G.
3894          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3895          * These are the first revisions with 16-bit tachometer support.
3896          */
3897         switch (data->type) {
3898         case it87:
3899                 if (sio_data->revision >= 0x03) {
3900                         data->features &= ~FEAT_OLD_AUTOPWM;
3901                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3902                 }
3903                 break;
3904         case it8712:
3905                 if (sio_data->revision >= 0x08) {
3906                         data->features &= ~FEAT_OLD_AUTOPWM;
3907                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3908                                           FEAT_FIVE_FANS;
3909                 }
3910                 break;
3911         default:
3912                 break;
3913         }
3914
3915         platform_set_drvdata(pdev, data);
3916
3917         mutex_init(&data->update_lock);
3918
3919         /* Initialize register pointers */
3920         it87_init_regs(pdev);
3921
3922         err = smbus_disable(data);
3923         if (err)
3924                 return err;
3925
3926         /* Now, we do the remaining detection. */
3927         if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
3928             data->read(data, IT87_REG_CHIPID) != 0x90) {
3929                 smbus_enable(data);
3930                 return -ENODEV;
3931         }
3932
3933         /* Check PWM configuration */
3934         enable_pwm_interface = it87_check_pwm(dev);
3935
3936         /* Starting with IT8721F, we handle scaling of internal voltages */
3937         if (has_scaling(data)) {
3938                 if (sio_data->internal & BIT(0))
3939                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3940                 if (sio_data->internal & BIT(1))
3941                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3942                 if (sio_data->internal & BIT(2))
3943                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3944                 if (sio_data->internal & BIT(3))
3945                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3946         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3947                    sio_data->type == it8783) {
3948                 if (sio_data->internal & BIT(0))
3949                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3950                 if (sio_data->internal & BIT(1))
3951                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3952         }
3953
3954         data->has_temp = 0x07;
3955         if (sio_data->skip_temp & BIT(2)) {
3956                 if (sio_data->type == it8782 &&
3957                     !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
3958                         data->has_temp &= ~BIT(2);
3959         }
3960
3961         data->in_internal = sio_data->internal;
3962         data->has_in = 0x3ff & ~sio_data->skip_in;
3963
3964         if (has_four_temp(data)) {
3965                 data->has_temp |= BIT(3);
3966         } else if (has_six_temp(data)) {
3967                 u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
3968
3969                 /* Check for additional temperature sensors */
3970                 if ((reg & 0x03) >= 0x02)
3971                         data->has_temp |= BIT(3);
3972                 if (((reg >> 2) & 0x03) >= 0x02)
3973                         data->has_temp |= BIT(4);
3974                 if (((reg >> 4) & 0x03) >= 0x02)
3975                         data->has_temp |= BIT(5);
3976
3977                 /* Check for additional voltage sensors */
3978                 if ((reg & 0x03) == 0x01)
3979                         data->has_in |= BIT(10);
3980                 if (((reg >> 2) & 0x03) == 0x01)
3981                         data->has_in |= BIT(11);
3982                 if (((reg >> 4) & 0x03) == 0x01)
3983                         data->has_in |= BIT(12);
3984         }
3985
3986         data->has_beep = !!sio_data->beep_pin;
3987
3988         /* Initialize the IT87 chip */
3989         it87_init_device(pdev);
3990
3991         smbus_enable(data);
3992
3993         if (!sio_data->skip_vid) {
3994                 data->has_vid = true;
3995                 data->vrm = vid_which_vrm();
3996                 /* VID reading from Super-I/O config space if available */
3997                 data->vid = sio_data->vid_value;
3998         }
3999
4000         /* Prepare for sysfs hooks */
4001         data->groups[0] = &it87_group;
4002         data->groups[1] = &it87_group_in;
4003         data->groups[2] = &it87_group_temp;
4004         data->groups[3] = &it87_group_fan;
4005
4006         if (enable_pwm_interface) {
4007                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
4008                 data->has_pwm &= ~sio_data->skip_pwm;
4009
4010                 data->groups[4] = &it87_group_pwm;
4011                 if (has_old_autopwm(data) || has_newer_autopwm(data))
4012                         data->groups[5] = &it87_group_auto_pwm;
4013         }
4014
4015         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
4016                                         it87_devices[sio_data->type].name,
4017                                         data, data->groups);
4018         return PTR_ERR_OR_ZERO(hwmon_dev);
4019 }
4020
4021 static struct platform_driver it87_driver = {
4022         .driver = {
4023                 .name   = DRVNAME,
4024         },
4025         .probe  = it87_probe,
4026 };
4027
4028 static int __init it87_device_add(int index, unsigned short sio_address,
4029                                   phys_addr_t mmio_address,
4030                                   const struct it87_sio_data *sio_data)
4031 {
4032         struct platform_device *pdev;
4033         struct resource res = {
4034                 .name   = DRVNAME,
4035         };
4036         int err;
4037
4038         if (mmio_address) {
4039                 res.start = mmio_address;
4040                 res.end = mmio_address + 0x400 - 1;
4041                 res.flags = IORESOURCE_MEM;
4042         } else {
4043                 res.start = sio_address + IT87_EC_OFFSET;
4044                 res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
4045                 res.flags = IORESOURCE_IO;
4046         }
4047
4048         err = acpi_check_resource_conflict(&res);
4049         if (err) {
4050                 if (!ignore_resource_conflict)
4051                         return err;
4052         }
4053
4054         pdev = platform_device_alloc(DRVNAME, sio_address);
4055         if (!pdev)
4056                 return -ENOMEM;
4057
4058         err = platform_device_add_resources(pdev, &res, 1);
4059         if (err) {
4060                 pr_err("Device resource addition failed (%d)\n", err);
4061                 goto exit_device_put;
4062         }
4063
4064         err = platform_device_add_data(pdev, sio_data,
4065                                        sizeof(struct it87_sio_data));
4066         if (err) {
4067                 pr_err("Platform data allocation failed\n");
4068                 goto exit_device_put;
4069         }
4070
4071         err = platform_device_add(pdev);
4072         if (err) {
4073                 pr_err("Device addition failed (%d)\n", err);
4074                 goto exit_device_put;
4075         }
4076
4077         it87_pdev[index] = pdev;
4078         return 0;
4079
4080 exit_device_put:
4081         platform_device_put(pdev);
4082         return err;
4083 }
4084
4085 struct it87_dmi_data {
4086         bool sio2_force_config; /* force sio2 into configuration mode   */
4087         u8 skip_pwm;            /* pwm channels to skip for this board  */
4088 };
4089
4090 /*
4091  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4092  * (IT8792E) needs to be in configuration mode before accessing the first
4093  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4094  * This needs to be done before accessing the first Super-IO chip since
4095  * the second chip may have been accessed prior to loading this driver.
4096  *
4097  * The problem is also reported to affect IT8795E, which is used on X299 boards
4098  * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4099  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4100  * Z87X-OC.
4101  * DMI entries for those systems will be added as they become available and
4102  * as the problem is confirmed to affect those boards.
4103  */
4104 static struct it87_dmi_data gigabyte_sio2_force = {
4105         .sio2_force_config = true,
4106 };
4107
4108 /*
4109  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4110  * connected to a fan, but to something else. One user
4111  * has reported instant system power-off when changing
4112  * the PWM2 duty cycle, so we disable it.
4113  * I use the board name string as the trigger in case
4114  * the same board is ever used in other systems.
4115  */
4116 static struct it87_dmi_data nvidia_fn68pt = {
4117         .skip_pwm = BIT(1),
4118 };
4119
4120 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4121         {
4122                 .matches = {
4123                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4124                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4125                 },
4126                 .driver_data = &gigabyte_sio2_force,
4127         },
4128         {
4129                 .matches = {
4130                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4131                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4132                 },
4133                 .driver_data = &gigabyte_sio2_force,
4134         },
4135         {
4136                 .matches = {
4137                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4138                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4139                 },
4140                 .driver_data = &gigabyte_sio2_force,
4141         },
4142         {
4143                 .matches = {
4144                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4145                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4146                 },
4147                 .driver_data = &nvidia_fn68pt,
4148         },
4149         { }
4150 };
4151
4152 static int __init sm_it87_init(void)
4153 {
4154         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4155         struct it87_dmi_data *dmi_data = NULL;
4156         int sioaddr[2] = { REG_2E, REG_4E };
4157         struct it87_sio_data sio_data;
4158         unsigned short isa_address;
4159         phys_addr_t mmio_address;
4160         bool found = false;
4161         int i, err;
4162
4163         pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4164
4165         if (dmi)
4166                 dmi_data = dmi->driver_data;
4167
4168         err = platform_driver_register(&it87_driver);
4169         if (err)
4170                 return err;
4171
4172         if (dmi_data && dmi_data->sio2_force_config)
4173                 __superio_enter(REG_4E);
4174
4175         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4176                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4177                 isa_address = 0;
4178                 mmio_address = 0;
4179                 err = it87_find(sioaddr[i], &isa_address, &mmio_address,
4180                                 &sio_data);
4181                 if (err || isa_address == 0)
4182                         continue;
4183
4184                 if (dmi_data)
4185                         sio_data.skip_pwm |= dmi_data->skip_pwm;
4186                 err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4187                 if (err)
4188                         goto exit_dev_unregister;
4189                 found = true;
4190         }
4191
4192         if (!found) {
4193                 err = -ENODEV;
4194                 goto exit_unregister;
4195         }
4196         return 0;
4197
4198 exit_dev_unregister:
4199         /* NULL check handled by platform_device_unregister */
4200         platform_device_unregister(it87_pdev[0]);
4201 exit_unregister:
4202         platform_driver_unregister(&it87_driver);
4203         return err;
4204 }
4205
4206 static void __exit sm_it87_exit(void)
4207 {
4208         /* NULL check handled by platform_device_unregister */
4209         platform_device_unregister(it87_pdev[1]);
4210         platform_device_unregister(it87_pdev[0]);
4211         platform_driver_unregister(&it87_driver);
4212 }
4213
4214 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4215 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4216 module_param(update_vbat, bool, 0000);
4217 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4218 module_param(fix_pwm_polarity, bool, 0000);
4219 MODULE_PARM_DESC(fix_pwm_polarity,
4220                  "Force PWM polarity to active high (DANGEROUS)");
4221 MODULE_LICENSE("GPL");
4222
4223 module_init(sm_it87_init);
4224 module_exit(sm_it87_exit);