git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8606E  Super I/O chip w/LPC interface
  15  *            IT8607E  Super I/O chip w/LPC interface
  16  *            IT8613E  Super I/O chip w/LPC interface
  17  *            IT8620E  Super I/O chip w/LPC interface
  18  *            IT8622E  Super I/O chip w/LPC interface
  19  *            IT8623E  Super I/O chip w/LPC interface
  20  *            IT8625E  Super I/O chip w/LPC interface
  21  *            IT8628E  Super I/O chip w/LPC interface
  22  *            IT8655E  Super I/O chip w/LPC interface
  23  *            IT8665E  Super I/O chip w/LPC interface
  24  *            IT8686E  Super I/O chip w/LPC interface
  25  *            IT8705F  Super I/O chip w/LPC interface
  26  *            IT8712F  Super I/O chip w/LPC interface
  27  *            IT8716F  Super I/O chip w/LPC interface
  28  *            IT8718F  Super I/O chip w/LPC interface
  29  *            IT8720F  Super I/O chip w/LPC interface
  30  *            IT8721F  Super I/O chip w/LPC interface
  31  *            IT8726F  Super I/O chip w/LPC interface
  32  *            IT8728F  Super I/O chip w/LPC interface
  33  *            IT8732F  Super I/O chip w/LPC interface
  34  *            IT8758E  Super I/O chip w/LPC interface
  35  *            IT8771E  Super I/O chip w/LPC interface
  36  *            IT8772E  Super I/O chip w/LPC interface
  37  *            IT8781F  Super I/O chip w/LPC interface
  38  *            IT8782F  Super I/O chip w/LPC interface
  39  *            IT8783E/F Super I/O chip w/LPC interface
  40  *            IT8786E  Super I/O chip w/LPC interface
  41  *            IT8790E  Super I/O chip w/LPC interface
  42  *            IT8792E  Super I/O chip w/LPC interface
  43  *            Sis950   A clone of the IT8705F
  44  *
  45  *  Copyright (C) 2001 Chris Gauthron
  46  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  47  *
  48  *  This program is free software; you can redistribute it and/or modify
  49  *  it under the terms of the GNU General Public License as published by
  50  *  the Free Software Foundation; either version 2 of the License, or
  51  *  (at your option) any later version.
  52  *
  53  *  This program is distributed in the hope that it will be useful,
  54  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  55  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  56  *  GNU General Public License for more details.
  57  */
  58
  59 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  60
  61 #include <linux/bitops.h>
  62 #include <linux/module.h>
  63 #include <linux/init.h>
  64 #include <linux/slab.h>
  65 #include <linux/jiffies.h>
  66 #include <linux/platform_device.h>
  67 #include <linux/hwmon.h>
  68 #include <linux/hwmon-sysfs.h>
  69 #include <linux/hwmon-vid.h>
  70 #include <linux/err.h>
  71 #include <linux/mutex.h>
  72 #include <linux/sysfs.h>
  73 #include <linux/string.h>
  74 #include <linux/dmi.h>
  75 #include <linux/acpi.h>
  76 #include <linux/io.h>
  77 #include "compat.h"
  78
  79 #ifndef IT87_DRIVER_VERSION
  80 #define IT87_DRIVER_VERSION     "<not provided>"
  81 #endif
  82
  83 #define DRVNAME "it87"
  84
  85 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  86              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  87              it8792, it8603, it8606, it8607, it8613, it8620, it8622, it8625,
  88              it8628, it8655, it8665, it8686 };
  89
  90 static unsigned short force_id;
  91 module_param(force_id, ushort, 0000);
  92 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  93
  94 static bool ignore_resource_conflict;
  95 module_param(ignore_resource_conflict, bool, 0000);
  96 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
  97
  98 static bool mmio;
  99 module_param(mmio, bool, 0000);
 100 MODULE_PARM_DESC(mmio, "Use MMIO if available");
 101
 102 static struct platform_device *it87_pdev[2];
 103
 104 #define REG_2E  0x2e    /* The register to read/write */
 105 #define REG_4E  0x4e    /* Secondary register to read/write */
 106
 107 #define DEV     0x07    /* Register: Logical device select */
 108 #define PME     0x04    /* The device with the fan registers in it */
 109
 110 /* The device with the IT8718F/IT8720F VID value in it */
 111 #define GPIO    0x07
 112
 113 #define DEVID   0x20    /* Register: Device ID */
 114 #define DEVREV  0x22    /* Register: Device Revision */
 115
 116 static inline void __superio_enter(int ioreg)
 117 {
 118         outb(0x87, ioreg);
 119         outb(0x01, ioreg);
 120         outb(0x55, ioreg);
 121         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 122 }
 123
 124 static inline int superio_inb(int ioreg, int reg)
 125 {
 126         int val;
 127
 128         outb(reg, ioreg);
 129         val = inb(ioreg + 1);
 130
 131         return val;
 132 }
 133
 134 static inline void superio_outb(int ioreg, int reg, int val)
 135 {
 136         outb(reg, ioreg);
 137         outb(val, ioreg + 1);
 138 }
 139
 140 static int superio_inw(int ioreg, int reg)
 141 {
 142         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 143 }
 144
 145 static inline void superio_select(int ioreg, int ldn)
 146 {
 147         outb(DEV, ioreg);
 148         outb(ldn, ioreg + 1);
 149 }
 150
 151 static inline int superio_enter(int ioreg)
 152 {
 153         /*
 154          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 155          */
 156         if (!request_muxed_region(ioreg, 2, DRVNAME))
 157                 return -EBUSY;
 158
 159         __superio_enter(ioreg);
 160         return 0;
 161 }
 162
 163 static inline void superio_exit(int ioreg, bool doexit)
 164 {
 165         if (doexit) {
 166                 outb(0x02, ioreg);
 167                 outb(0x02, ioreg + 1);
 168         }
 169         release_region(ioreg, 2);
 170 }
 171
 172 /* Logical device 4 registers */
 173 #define IT8712F_DEVID 0x8712
 174 #define IT8705F_DEVID 0x8705
 175 #define IT8716F_DEVID 0x8716
 176 #define IT8718F_DEVID 0x8718
 177 #define IT8720F_DEVID 0x8720
 178 #define IT8721F_DEVID 0x8721
 179 #define IT8726F_DEVID 0x8726
 180 #define IT8728F_DEVID 0x8728
 181 #define IT8732F_DEVID 0x8732
 182 #define IT8792E_DEVID 0x8733
 183 #define IT8771E_DEVID 0x8771
 184 #define IT8772E_DEVID 0x8772
 185 #define IT8781F_DEVID 0x8781
 186 #define IT8782F_DEVID 0x8782
 187 #define IT8783E_DEVID 0x8783
 188 #define IT8786E_DEVID 0x8786
 189 #define IT8790E_DEVID 0x8790
 190 #define IT8603E_DEVID 0x8603
 191 #define IT8606E_DEVID 0x8606
 192 #define IT8607E_DEVID 0x8607
 193 #define IT8613E_DEVID 0x8613
 194 #define IT8620E_DEVID 0x8620
 195 #define IT8622E_DEVID 0x8622
 196 #define IT8623E_DEVID 0x8623
 197 #define IT8625E_DEVID 0x8625
 198 #define IT8628E_DEVID 0x8628
 199 #define IT8655E_DEVID 0x8655
 200 #define IT8665E_DEVID 0x8665
 201 #define IT8686E_DEVID 0x8686
 202
 203 /* Logical device 4 (Environmental Monitor) registers */
 204 #define IT87_ACT_REG            0x30
 205 #define IT87_BASE_REG           0x60
 206 #define IT87_SPECIAL_CFG_REG    0xf3    /* special configuration register */
 207
 208 /* Global configuration registers (IT8712F and later) */
 209 #define IT87_EC_HWM_MIO_REG     0x24    /* MMIO configuration register */
 210 #define IT87_SIO_GPIO1_REG      0x25
 211 #define IT87_SIO_GPIO2_REG      0x26
 212 #define IT87_SIO_GPIO3_REG      0x27
 213 #define IT87_SIO_GPIO4_REG      0x28
 214 #define IT87_SIO_GPIO5_REG      0x29
 215 #define IT87_SIO_GPIO9_REG      0xd3
 216 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 217 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 218 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 219
 220 /* Logical device 7 (GPIO) registers (IT8712F and later) */
 221 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 222 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 223 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 224
 225 /* Update battery voltage after every reading if true */
 226 static bool update_vbat;
 227
 228 /* Not all BIOSes properly configure the PWM registers */
 229 static bool fix_pwm_polarity;
 230
 231 /* Many IT87 constants specified below */
 232
 233 /* Length of ISA address segment */
 234 #define IT87_EXTENT 8
 235
 236 /* Length of ISA address segment for Environmental Controller */
 237 #define IT87_EC_EXTENT 2
 238
 239 /* Offset of EC registers from ISA base address */
 240 #define IT87_EC_OFFSET 5
 241
 242 /* Where are the ISA address/data registers relative to the EC base address */
 243 #define IT87_ADDR_REG_OFFSET 0
 244 #define IT87_DATA_REG_OFFSET 1
 245
 246 /*----- The IT87 registers -----*/
 247
 248 #define IT87_REG_CONFIG        0x00
 249
 250 #define IT87_REG_ALARM1        0x01
 251 #define IT87_REG_ALARM2        0x02
 252 #define IT87_REG_ALARM3        0x03
 253
 254 #define IT87_REG_BANK           0x06
 255
 256 /*
 257  * The IT8718F and IT8720F have the VID value in a different register, in
 258  * Super-I/O configuration space.
 259  */
 260 #define IT87_REG_VID           0x0a
 261 /*
 262  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 263  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 264  * mode.
 265  */
 266 #define IT87_REG_FAN_DIV       0x0b
 267 #define IT87_REG_FAN_16BIT     0x0c
 268
 269 /*
 270  * Monitors:
 271  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 272  * - up to 6 temp (1 to 6)
 273  * - up to 6 fan (1 to 6)
 274  */
 275
 276 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 277 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 278 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 279 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 280
 281 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 282 static const u8 IT87_REG_FAN_MIN_8665[] = {
 283                                         0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 284 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 285 static const u8 IT87_REG_FANX_MIN_8665[] = {
 286                                         0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 287
 288 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 289
 290 static const u8 IT87_REG_TEMP_OFFSET_8686[] = {
 291                                         0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 292
 293 #define IT87_REG_FAN_MAIN_CTRL 0x13
 294 #define IT87_REG_FAN_CTL       0x14
 295
 296 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 297 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 298
 299 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 300
 301 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 302                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 303
 304 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 305
 306 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 307 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 308
 309 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 310 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 311
 312 static const u8 IT87_REG_TEMP_HIGH_8686[] = {
 313                                         0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 314 static const u8 IT87_REG_TEMP_LOW_8686[] = {
 315                                         0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 316
 317 #define IT87_REG_VIN_ENABLE    0x50
 318 #define IT87_REG_TEMP_ENABLE   0x51
 319 #define IT87_REG_TEMP_EXTRA    0x55
 320 #define IT87_REG_BEEP_ENABLE   0x5c
 321
 322 #define IT87_REG_CHIPID        0x58
 323
 324 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 325
 326 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 327 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 328
 329 #define IT87_REG_TEMP456_ENABLE 0x77
 330
 331 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 332 #define IT87_REG_TEMP_SRC2      0x23d
 333
 334 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 335 #define NUM_VIN_LIMIT           8
 336 #define NUM_TEMP                6
 337 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 338 #define NUM_FAN_DIV             3
 339 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 340 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 341
 342 struct it87_devices {
 343         const char *name;
 344         const char * const model;
 345         u32 features;
 346         u8 num_temp_limit;
 347         u8 num_temp_offset;
 348         u8 num_temp_map;        /* Number of temperature sources for pwm */
 349         u8 peci_mask;
 350         u8 old_peci_mask;
 351         u8 smbus_bitmap;        /* SMBus enable bits in extra config register */
 352         u8 ec_special_config;
 353 };
 354
 355 #define FEAT_12MV_ADC           BIT(0)
 356 #define FEAT_NEWER_AUTOPWM      BIT(1)
 357 #define FEAT_OLD_AUTOPWM        BIT(2)
 358 #define FEAT_16BIT_FANS         BIT(3)
 359 #define FEAT_TEMP_PECI          BIT(5)
 360 #define FEAT_TEMP_OLD_PECI      BIT(6)
 361 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 362 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 363 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 364 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 365 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 366 #define FEAT_10_9MV_ADC         BIT(12)
 367 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 368 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 369 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 370 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 371 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 372 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 373 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 374 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 375 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 376 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 377 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 378 #define FEAT_11MV_ADC           BIT(24)
 379 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 380 #define FEAT_MMIO               BIT(26) /* Chip supports MMIO */
 381 #define FEAT_FOUR_TEMP          BIT(27)
 382
 383 static const struct it87_devices it87_devices[] = {
 384         [it87] = {
 385                 .name = "it87",
 386                 .model = "IT87F",
 387                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 388                                                 /* may need to overwrite */
 389                 .num_temp_limit = 3,
 390                 .num_temp_offset = 0,
 391                 .num_temp_map = 3,
 392         },
 393         [it8712] = {
 394                 .name = "it8712",
 395                 .model = "IT8712F",
 396                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 397                                                 /* may need to overwrite */
 398                 .num_temp_limit = 3,
 399                 .num_temp_offset = 0,
 400                 .num_temp_map = 3,
 401         },
 402         [it8716] = {
 403                 .name = "it8716",
 404                 .model = "IT8716F",
 405                 .features = FEAT_16BIT_FANS | FEAT_VID
 406                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 407                   | FEAT_FANCTL_ONOFF,
 408                 .num_temp_limit = 3,
 409                 .num_temp_offset = 3,
 410                 .num_temp_map = 3,
 411         },
 412         [it8718] = {
 413                 .name = "it8718",
 414                 .model = "IT8718F",
 415                 .features = FEAT_16BIT_FANS | FEAT_VID
 416                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 417                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 418                 .num_temp_limit = 3,
 419                 .num_temp_offset = 3,
 420                 .num_temp_map = 3,
 421                 .old_peci_mask = 0x4,
 422         },
 423         [it8720] = {
 424                 .name = "it8720",
 425                 .model = "IT8720F",
 426                 .features = FEAT_16BIT_FANS | FEAT_VID
 427                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 428                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 429                 .num_temp_limit = 3,
 430                 .num_temp_offset = 3,
 431                 .num_temp_map = 3,
 432                 .old_peci_mask = 0x4,
 433         },
 434         [it8721] = {
 435                 .name = "it8721",
 436                 .model = "IT8721F",
 437                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 438                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 439                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 440                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 441                 .num_temp_limit = 3,
 442                 .num_temp_offset = 3,
 443                 .num_temp_map = 3,
 444                 .peci_mask = 0x05,
 445                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 446         },
 447         [it8728] = {
 448                 .name = "it8728",
 449                 .model = "IT8728F",
 450                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 451                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 452                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 453                   | FEAT_FANCTL_ONOFF,
 454                 .num_temp_limit = 6,
 455                 .num_temp_offset = 3,
 456                 .num_temp_map = 3,
 457                 .peci_mask = 0x07,
 458         },
 459         [it8732] = {
 460                 .name = "it8732",
 461                 .model = "IT8732F",
 462                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 463                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 464                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 465                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 466                 .num_temp_limit = 3,
 467                 .num_temp_offset = 3,
 468                 .num_temp_map = 3,
 469                 .peci_mask = 0x07,
 470                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 471         },
 472         [it8771] = {
 473                 .name = "it8771",
 474                 .model = "IT8771E",
 475                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 476                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 477                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 478                                 /* PECI: guesswork */
 479                                 /* 12mV ADC (OHM) */
 480                                 /* 16 bit fans (OHM) */
 481                                 /* three fans, always 16 bit (guesswork) */
 482                 .num_temp_limit = 3,
 483                 .num_temp_offset = 3,
 484                 .num_temp_map = 3,
 485                 .peci_mask = 0x07,
 486         },
 487         [it8772] = {
 488                 .name = "it8772",
 489                 .model = "IT8772E",
 490                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 491                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 492                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 493                                 /* PECI (coreboot) */
 494                                 /* 12mV ADC (HWSensors4, OHM) */
 495                                 /* 16 bit fans (HWSensors4, OHM) */
 496                                 /* three fans, always 16 bit (datasheet) */
 497                 .num_temp_limit = 3,
 498                 .num_temp_offset = 3,
 499                 .num_temp_map = 3,
 500                 .peci_mask = 0x07,
 501         },
 502         [it8781] = {
 503                 .name = "it8781",
 504                 .model = "IT8781F",
 505                 .features = FEAT_16BIT_FANS
 506                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 507                   | FEAT_FANCTL_ONOFF,
 508                 .num_temp_limit = 3,
 509                 .num_temp_offset = 3,
 510                 .num_temp_map = 3,
 511                 .old_peci_mask = 0x4,
 512         },
 513         [it8782] = {
 514                 .name = "it8782",
 515                 .model = "IT8782F",
 516                 .features = FEAT_16BIT_FANS
 517                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 518                   | FEAT_FANCTL_ONOFF,
 519                 .num_temp_limit = 3,
 520                 .num_temp_offset = 3,
 521                 .num_temp_map = 3,
 522                 .old_peci_mask = 0x4,
 523         },
 524         [it8783] = {
 525                 .name = "it8783",
 526                 .model = "IT8783E/F",
 527                 .features = FEAT_16BIT_FANS
 528                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 529                   | FEAT_FANCTL_ONOFF,
 530                 .num_temp_limit = 3,
 531                 .num_temp_offset = 3,
 532                 .num_temp_map = 3,
 533                 .old_peci_mask = 0x4,
 534         },
 535         [it8786] = {
 536                 .name = "it8786",
 537                 .model = "IT8786E",
 538                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 539                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 540                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 541                 .num_temp_limit = 3,
 542                 .num_temp_offset = 3,
 543                 .num_temp_map = 3,
 544                 .peci_mask = 0x07,
 545         },
 546         [it8790] = {
 547                 .name = "it8790",
 548                 .model = "IT8790E",
 549                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 550                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 551                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 552                 .num_temp_limit = 3,
 553                 .num_temp_offset = 3,
 554                 .num_temp_map = 3,
 555                 .peci_mask = 0x07,
 556         },
 557         [it8792] = {
 558                 .name = "it8792",
 559                 .model = "IT8792E/IT8795E",
 560                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 561                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 562                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 563                 .num_temp_limit = 3,
 564                 .num_temp_offset = 3,
 565                 .num_temp_map = 3,
 566                 .peci_mask = 0x07,
 567         },
 568         [it8603] = {
 569                 .name = "it8603",
 570                 .model = "IT8603E",
 571                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 572                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 573                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 574                 .num_temp_limit = 3,
 575                 .num_temp_offset = 3,
 576                 .num_temp_map = 4,
 577                 .peci_mask = 0x07,
 578         },
 579         [it8606] = {
 580                 .name = "it8606",
 581                 .model = "IT8606E",
 582                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 583                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 584                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 585                 .num_temp_limit = 3,
 586                 .num_temp_offset = 3,
 587                 .num_temp_map = 3,
 588                 .peci_mask = 0x07,
 589         },
 590         [it8607] = {
 591                 .name = "it8607",
 592                 .model = "IT8607E",
 593                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 594                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 595                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 596                   | FEAT_FANCTL_ONOFF,
 597                 .num_temp_limit = 3,
 598                 .num_temp_offset = 3,
 599                 .num_temp_map = 6,
 600                 .peci_mask = 0x07,
 601         },
 602         [it8613] = {
 603                 .name = "it8613",
 604                 .model = "IT8613E",
 605                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 606                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 607                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 608                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 609                 .num_temp_limit = 6,
 610                 .num_temp_offset = 6,
 611                 .num_temp_map = 6,
 612                 .peci_mask = 0x07,
 613         },
 614         [it8620] = {
 615                 .name = "it8620",
 616                 .model = "IT8620E",
 617                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 618                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 619                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 620                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 621                   | FEAT_FANCTL_ONOFF,
 622                 .num_temp_limit = 3,
 623                 .num_temp_offset = 3,
 624                 .num_temp_map = 3,
 625                 .peci_mask = 0x07,
 626         },
 627         [it8622] = {
 628                 .name = "it8622",
 629                 .model = "IT8622E",
 630                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 631                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
 632                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 633                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 634                 .num_temp_limit = 3,
 635                 .num_temp_offset = 3,
 636                 .num_temp_map = 4,
 637                 .peci_mask = 0x0f,
 638                 .smbus_bitmap = BIT(1) | BIT(2),
 639         },
 640         [it8625] = {
 641                 .name = "it8625",
 642                 .model = "IT8625E",
 643                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 644                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 645                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 646                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 647                 .num_temp_limit = 6,
 648                 .num_temp_offset = 6,
 649                 .num_temp_map = 6,
 650                 .smbus_bitmap = BIT(1) | BIT(2),
 651         },
 652         [it8628] = {
 653                 .name = "it8628",
 654                 .model = "IT8628E",
 655                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 656                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 657                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 658                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 659                   | FEAT_FANCTL_ONOFF,
 660                 .num_temp_limit = 6,
 661                 .num_temp_offset = 3,
 662                 .num_temp_map = 3,
 663                 .peci_mask = 0x07,
 664         },
 665         [it8655] = {
 666                 .name = "it8655",
 667                 .model = "IT8655E",
 668                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 669                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 670                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
 671                   | FEAT_MMIO,
 672                 .num_temp_limit = 6,
 673                 .num_temp_offset = 6,
 674                 .num_temp_map = 6,
 675                 .smbus_bitmap = BIT(2),
 676         },
 677         [it8665] = {
 678                 .name = "it8665",
 679                 .model = "IT8665E",
 680                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 681                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 682                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 683                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO,
 684                 .num_temp_limit = 6,
 685                 .num_temp_offset = 6,
 686                 .num_temp_map = 6,
 687                 .smbus_bitmap = BIT(2),
 688         },
 689         [it8686] = {
 690                 .name = "it8686",
 691                 .model = "IT8686E",
 692                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 693                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 694                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 695                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 696                 .num_temp_limit = 6,
 697                 .num_temp_offset = 6,
 698                 .num_temp_map = 7,
 699                 .smbus_bitmap = BIT(1) | BIT(2),
 700         },
 701 };
 702
 703 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 704 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 705 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 706 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 707 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 708 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 709                                  ((data)->peci_mask & BIT(nr)))
 710 #define has_temp_old_peci(data, nr) \
 711                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 712                                  ((data)->old_peci_mask & BIT(nr)))
 713 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 714 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 715                                                      FEAT_SIX_FANS))
 716 #define has_vid(data)           ((data)->features & FEAT_VID)
 717 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 718 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 719 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 720 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 721                                                      | FEAT_SIX_PWM))
 722 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 723 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 724 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 725 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 726 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 727                                                      FEAT_FIVE_FANS | \
 728                                                      FEAT_SIX_FANS))
 729 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 730                                                      FEAT_FIVE_PWM \
 731                                                      | FEAT_SIX_PWM))
 732 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 733 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 734 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 735 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 736 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 737 #define has_mmio(data)          ((data)->features & FEAT_MMIO)
 738 #define has_four_temp(data)     ((data)->features & FEAT_FOUR_TEMP)
 739
 740 struct it87_sio_data {
 741         enum chips type;
 742         u8 sioaddr;
 743         u8 doexit;
 744         /* Values read from Super-I/O config space */
 745         u8 revision;
 746         u8 vid_value;
 747         u8 beep_pin;
 748         u8 internal;    /* Internal sensors can be labeled */
 749         /* Features skipped based on config or DMI */
 750         u16 skip_in;
 751         u8 skip_vid;
 752         u8 skip_fan;
 753         u8 skip_pwm;
 754         u8 skip_temp;
 755         u8 smbus_bitmap;
 756         u8 ec_special_config;
 757 };
 758
 759 /*
 760  * For each registered chip, we need to keep some data in memory.
 761  * The structure is dynamically allocated.
 762  */
 763 struct it87_data {
 764         const struct attribute_group *groups[7];
 765         enum chips type;
 766         u32 features;
 767         u8 peci_mask;
 768         u8 old_peci_mask;
 769
 770         u8 smbus_bitmap;        /* !=0 if SMBus needs to be disabled */
 771         u8 ec_special_config;   /* EC special config register restore value */
 772         u8 sioaddr;             /* SIO port address */
 773         bool doexit;            /* true if exit from sio config is ok */
 774
 775         void __iomem *mmio;     /* Remapped MMIO address if available */
 776         int (*read)(struct it87_data *, u16);
 777         void (*write)(struct it87_data *, u16, u8);
 778
 779         const u8 *REG_FAN;
 780         const u8 *REG_FANX;
 781         const u8 *REG_FAN_MIN;
 782         const u8 *REG_FANX_MIN;
 783
 784         const u8 *REG_PWM;
 785
 786         const u8 *REG_TEMP_OFFSET;
 787         const u8 *REG_TEMP_LOW;
 788         const u8 *REG_TEMP_HIGH;
 789
 790         unsigned short addr;
 791         const char *name;
 792         struct mutex update_lock;
 793         char valid;             /* !=0 if following fields are valid */
 794         unsigned long last_updated;     /* In jiffies */
 795
 796         u16 in_scaled;          /* Internal voltage sensors are scaled */
 797         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 798         u16 has_in;             /* Bitfield, voltage sensors enabled */
 799         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 800         u8 has_fan;             /* Bitfield, fans enabled */
 801         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 802         u8 has_temp;            /* Bitfield, temp sensors enabled */
 803         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 804         u8 num_temp_limit;      /* Number of temperature limit registers */
 805         u8 num_temp_offset;     /* Number of temperature offset registers */
 806         u8 temp_src[4];         /* Up to 4 temperature source registers */
 807         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 808         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 809         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 810         bool has_vid;           /* True if VID supported */
 811         u8 vid;                 /* Register encoding, combined */
 812         u8 vrm;
 813         u32 alarms;             /* Register encoding, combined */
 814         bool has_beep;          /* true if beep supported */
 815         u8 beeps;               /* Register encoding */
 816         u8 fan_main_ctrl;       /* Register value */
 817         u8 fan_ctl;             /* Register value */
 818
 819         /*
 820          * The following 3 arrays correspond to the same registers up to
 821          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 822          * 7, and we want to preserve settings on mode changes, so we have
 823          * to track all values separately.
 824          * Starting with the IT8721F, the manual PWM duty cycles are stored
 825          * in separate registers (8-bit values), so the separate tracking
 826          * is no longer needed, but it is still done to keep the driver
 827          * simple.
 828          */
 829         u8 has_pwm;             /* Bitfield, pwm control enabled */
 830         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 831         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 832         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 833         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 834         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 835         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 836
 837         /* Automatic fan speed control registers */
 838         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 839         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 840 };
 841
 842 static int adc_lsb(const struct it87_data *data, int nr)
 843 {
 844         int lsb;
 845
 846         if (has_12mv_adc(data))
 847                 lsb = 120;
 848         else if (has_10_9mv_adc(data))
 849                 lsb = 109;
 850         else if (has_11mv_adc(data))
 851                 lsb = 110;
 852         else
 853                 lsb = 160;
 854         if (data->in_scaled & BIT(nr))
 855                 lsb <<= 1;
 856         return lsb;
 857 }
 858
 859 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 860 {
 861         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 862         return clamp_val(val, 0, 255);
 863 }
 864
 865 static int in_from_reg(const struct it87_data *data, int nr, int val)
 866 {
 867         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 868 }
 869
 870 static inline u8 FAN_TO_REG(long rpm, int div)
 871 {
 872         if (rpm == 0)
 873                 return 255;
 874         rpm = clamp_val(rpm, 1, 1000000);
 875         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 876 }
 877
 878 static inline u16 FAN16_TO_REG(long rpm)
 879 {
 880         if (rpm == 0)
 881                 return 0xffff;
 882         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 883 }
 884
 885 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 886                                 1350000 / ((val) * (div)))
 887 /* The divider is fixed to 2 in 16-bit mode */
 888 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 889                              1350000 / ((val) * 2))
 890
 891 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 892                                     ((val) + 500) / 1000), -128, 127))
 893 #define TEMP_FROM_REG(val) ((val) * 1000)
 894
 895 static u8 pwm_to_reg(const struct it87_data *data, long val)
 896 {
 897         if (has_newer_autopwm(data))
 898                 return val;
 899         else
 900                 return val >> 1;
 901 }
 902
 903 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 904 {
 905         if (has_newer_autopwm(data))
 906                 return reg;
 907         else
 908                 return (reg & 0x7f) << 1;
 909 }
 910
 911 static int DIV_TO_REG(int val)
 912 {
 913         int answer = 0;
 914
 915         while (answer < 7 && (val >>= 1))
 916                 answer++;
 917         return answer;
 918 }
 919
 920 #define DIV_FROM_REG(val) BIT(val)
 921
 922 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 923 {
 924         u8 map;
 925
 926         map  = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 927         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 928                 map = 0;
 929
 930         return map;
 931 }
 932
 933 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 934 {
 935         u8 ctrl = data->pwm_ctrl[nr];
 936
 937         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 938                (map << data->pwm_temp_map_shift);
 939 }
 940
 941 /*
 942  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 943  * depending on the chip type, to calculate the actual PWM frequency.
 944  *
 945  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 946  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 947  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 948  * sometimes just one. It is unknown if this is a datasheet error or real,
 949  * so this is ignored for now.
 950  */
 951 static const unsigned int pwm_freq[8] = {
 952         48000000,
 953         24000000,
 954         12000000,
 955         8000000,
 956         6000000,
 957         3000000,
 958         1500000,
 959         750000,
 960 };
 961
 962 static int smbus_disable(struct it87_data *data)
 963 {
 964         int err;
 965
 966         if (data->smbus_bitmap) {
 967                 err = superio_enter(data->sioaddr);
 968                 if (err)
 969                         return err;
 970                 superio_select(data->sioaddr, PME);
 971                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 972                              data->ec_special_config & ~data->smbus_bitmap);
 973                 superio_exit(data->sioaddr, data->doexit);
 974         }
 975         return 0;
 976 }
 977
 978 static int smbus_enable(struct it87_data *data)
 979 {
 980         int err;
 981
 982         if (data->smbus_bitmap) {
 983                 err = superio_enter(data->sioaddr);
 984                 if (err)
 985                         return err;
 986
 987                 superio_select(data->sioaddr, PME);
 988                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 989                              data->ec_special_config);
 990                 superio_exit(data->sioaddr, data->doexit);
 991         }
 992         return 0;
 993 }
 994
 995 static int _it87_io_read(struct it87_data *data, u16 reg)
 996 {
 997         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 998         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 999 }
1000
1001 static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
1002 {
1003         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
1004         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1005 }
1006
1007 static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
1008 {
1009         u8 _bank = bank;
1010
1011         if (has_bank_sel(data)) {
1012                 u8 breg = _it87_io_read(data, IT87_REG_BANK);
1013
1014                 _bank = breg >> 5;
1015                 if (bank != _bank) {
1016                         breg &= 0x1f;
1017                         breg |= (bank << 5);
1018                         _it87_io_write(data, IT87_REG_BANK, breg);
1019                 }
1020         }
1021         return _bank;
1022 }
1023
1024 /*
1025  * Must be called with data->update_lock held, except during initialization.
1026  * Must be called with SMBus accesses disabled.
1027  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1028  * would slow down the IT87 access and should not be necessary.
1029  */
1030 static int it87_io_read(struct it87_data *data, u16 reg)
1031 {
1032         u8 bank;
1033         int val;
1034
1035         bank = it87_io_set_bank(data, reg >> 8);
1036         val = _it87_io_read(data, reg & 0xff);
1037         it87_io_set_bank(data, bank);
1038
1039         return val;
1040 }
1041
1042 /*
1043  * Must be called with data->update_lock held, except during initialization.
1044  * Must be called with SMBus accesses disabled
1045  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1046  * would slow down the IT87 access and should not be necessary.
1047  */
1048 static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1049 {
1050         u8 bank;
1051
1052         bank = it87_io_set_bank(data, reg >> 8);
1053         _it87_io_write(data, reg & 0xff, value);
1054         it87_io_set_bank(data, bank);
1055 }
1056
1057 static int it87_mmio_read(struct it87_data *data, u16 reg)
1058 {
1059         return readb(data->mmio + reg);
1060 }
1061
1062 static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1063 {
1064         writeb(value, data->mmio + reg);
1065 }
1066
1067 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1068 {
1069         u8 ctrl;
1070
1071         ctrl = data->read(data, data->REG_PWM[nr]);
1072         data->pwm_ctrl[nr] = ctrl;
1073         if (has_newer_autopwm(data)) {
1074                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1075                 data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1076         } else {
1077                 if (ctrl & 0x80)        /* Automatic mode */
1078                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1079                 else                            /* Manual mode */
1080                         data->pwm_duty[nr] = ctrl & 0x7f;
1081         }
1082
1083         if (has_old_autopwm(data)) {
1084                 int i;
1085
1086                 for (i = 0; i < 5 ; i++)
1087                         data->auto_temp[nr][i] = data->read(data,
1088                                                 IT87_REG_AUTO_TEMP(nr, i));
1089                 for (i = 0; i < 3 ; i++)
1090                         data->auto_pwm[nr][i] = data->read(data,
1091                                                 IT87_REG_AUTO_PWM(nr, i));
1092         } else if (has_newer_autopwm(data)) {
1093                 int i;
1094
1095                 /*
1096                  * 0: temperature hysteresis (base + 5)
1097                  * 1: fan off temperature (base + 0)
1098                  * 2: fan start temperature (base + 1)
1099                  * 3: fan max temperature (base + 2)
1100                  */
1101                 data->auto_temp[nr][0] =
1102                         data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1103
1104                 for (i = 0; i < 3 ; i++)
1105                         data->auto_temp[nr][i + 1] =
1106                                 data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1107                 /*
1108                  * 0: start pwm value (base + 3)
1109                  * 1: pwm slope (base + 4, 1/8th pwm)
1110                  */
1111                 data->auto_pwm[nr][0] =
1112                         data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1113                 data->auto_pwm[nr][1] =
1114                         data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1115         }
1116 }
1117
1118 static int it87_lock(struct it87_data *data)
1119 {
1120         int err;
1121
1122         mutex_lock(&data->update_lock);
1123         err = smbus_disable(data);
1124         if (err)
1125                 mutex_unlock(&data->update_lock);
1126         return err;
1127 }
1128
1129 static void it87_unlock(struct it87_data *data)
1130 {
1131         smbus_enable(data);
1132         mutex_unlock(&data->update_lock);
1133 }
1134
1135 static struct it87_data *it87_update_device(struct device *dev)
1136 {
1137         struct it87_data *data = dev_get_drvdata(dev);
1138         int err;
1139         int i;
1140
1141         err = it87_lock(data);
1142         if (err)
1143                 return ERR_PTR(err);
1144
1145         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1146             !data->valid) {
1147                 if (update_vbat) {
1148                         /*
1149                          * Cleared after each update, so reenable.  Value
1150                          * returned by this read will be previous value
1151                          */
1152                         data->write(data, IT87_REG_CONFIG,
1153                                     data->read(data, IT87_REG_CONFIG) | 0x40);
1154                 }
1155                 for (i = 0; i < NUM_VIN; i++) {
1156                         if (!(data->has_in & BIT(i)))
1157                                 continue;
1158
1159                         data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1160
1161                         /* VBAT and AVCC don't have limit registers */
1162                         if (i >= NUM_VIN_LIMIT)
1163                                 continue;
1164
1165                         data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1166                         data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1167                 }
1168
1169                 for (i = 0; i < NUM_FAN; i++) {
1170                         /* Skip disabled fans */
1171                         if (!(data->has_fan & BIT(i)))
1172                                 continue;
1173
1174                         data->fan[i][1] = data->read(data,
1175                                                      data->REG_FAN_MIN[i]);
1176                         data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1177                         /* Add high byte if in 16-bit mode */
1178                         if (has_16bit_fans(data)) {
1179                                 data->fan[i][0] |= data->read(data,
1180                                                 data->REG_FANX[i]) << 8;
1181                                 data->fan[i][1] |= data->read(data,
1182                                                 data->REG_FANX_MIN[i]) << 8;
1183                         }
1184                 }
1185                 for (i = 0; i < NUM_TEMP; i++) {
1186                         if (!(data->has_temp & BIT(i)))
1187                                 continue;
1188                         data->temp[i][0] =
1189                                 data->read(data, IT87_REG_TEMP(i));
1190
1191                         if (i >= data->num_temp_limit)
1192                                 continue;
1193
1194                         if (i < data->num_temp_offset)
1195                                 data->temp[i][3] =
1196                                   data->read(data, data->REG_TEMP_OFFSET[i]);
1197
1198                         data->temp[i][1] =
1199                                 data->read(data, data->REG_TEMP_LOW[i]);
1200                         data->temp[i][2] =
1201                                 data->read(data, data->REG_TEMP_HIGH[i]);
1202                 }
1203
1204                 /* Newer chips don't have clock dividers */
1205                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1206                         i = data->read(data, IT87_REG_FAN_DIV);
1207                         data->fan_div[0] = i & 0x07;
1208                         data->fan_div[1] = (i >> 3) & 0x07;
1209                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1210                 }
1211
1212                 data->alarms =
1213                         data->read(data, IT87_REG_ALARM1) |
1214                         (data->read(data, IT87_REG_ALARM2) << 8) |
1215                         (data->read(data, IT87_REG_ALARM3) << 16);
1216                 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1217
1218                 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1219                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1220                 for (i = 0; i < NUM_PWM; i++) {
1221                         if (!(data->has_pwm & BIT(i)))
1222                                 continue;
1223                         it87_update_pwm_ctrl(data, i);
1224                 }
1225
1226                 data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1227                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1228                 /*
1229                  * The IT8705F does not have VID capability.
1230                  * The IT8718F and later don't use IT87_REG_VID for the
1231                  * same purpose.
1232                  */
1233                 if (data->type == it8712 || data->type == it8716) {
1234                         data->vid = data->read(data, IT87_REG_VID);
1235                         /*
1236                          * The older IT8712F revisions had only 5 VID pins,
1237                          * but we assume it is always safe to read 6 bits.
1238                          */
1239                         data->vid &= 0x3f;
1240                 }
1241                 data->last_updated = jiffies;
1242                 data->valid = 1;
1243         }
1244         it87_unlock(data);
1245         return data;
1246 }
1247
1248 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1249                        char *buf)
1250 {
1251         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1252         struct it87_data *data = it87_update_device(dev);
1253         int index = sattr->index;
1254         int nr = sattr->nr;
1255
1256         if (IS_ERR(data))
1257                 return PTR_ERR(data);
1258
1259         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1260 }
1261
1262 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1263                       const char *buf, size_t count)
1264 {
1265         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1266         struct it87_data *data = dev_get_drvdata(dev);
1267         int index = sattr->index;
1268         int nr = sattr->nr;
1269         unsigned long val;
1270         int err;
1271
1272         if (kstrtoul(buf, 10, &val) < 0)
1273                 return -EINVAL;
1274
1275         err = it87_lock(data);
1276         if (err)
1277                 return err;
1278
1279         data->in[nr][index] = in_to_reg(data, nr, val);
1280         data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1281                                      : IT87_REG_VIN_MAX(nr),
1282                     data->in[nr][index]);
1283         it87_unlock(data);
1284         return count;
1285 }
1286
1287 static SENSOR_DEVICE_ATTR_2(in0_input, 0444, show_in, NULL, 0, 0);
1288 static SENSOR_DEVICE_ATTR_2(in0_min, 0644, show_in, set_in, 0, 1);
1289 static SENSOR_DEVICE_ATTR_2(in0_max, 0644, show_in, set_in, 0, 2);
1290
1291 static SENSOR_DEVICE_ATTR_2(in1_input, 0444, show_in, NULL, 1, 0);
1292 static SENSOR_DEVICE_ATTR_2(in1_min, 0644, show_in, set_in, 1, 1);
1293 static SENSOR_DEVICE_ATTR_2(in1_max, 0644, show_in, set_in, 1, 2);
1294
1295 static SENSOR_DEVICE_ATTR_2(in2_input, 0444, show_in, NULL, 2, 0);
1296 static SENSOR_DEVICE_ATTR_2(in2_min, 0644, show_in, set_in, 2, 1);
1297 static SENSOR_DEVICE_ATTR_2(in2_max, 0644, show_in, set_in, 2, 2);
1298
1299 static SENSOR_DEVICE_ATTR_2(in3_input, 0444, show_in, NULL, 3, 0);
1300 static SENSOR_DEVICE_ATTR_2(in3_min, 0644, show_in, set_in, 3, 1);
1301 static SENSOR_DEVICE_ATTR_2(in3_max, 0644, show_in, set_in, 3, 2);
1302
1303 static SENSOR_DEVICE_ATTR_2(in4_input, 0444, show_in, NULL, 4, 0);
1304 static SENSOR_DEVICE_ATTR_2(in4_min, 0644, show_in, set_in, 4, 1);
1305 static SENSOR_DEVICE_ATTR_2(in4_max, 0644, show_in, set_in, 4, 2);
1306
1307 static SENSOR_DEVICE_ATTR_2(in5_input, 0444, show_in, NULL, 5, 0);
1308 static SENSOR_DEVICE_ATTR_2(in5_min, 0644, show_in, set_in, 5, 1);
1309 static SENSOR_DEVICE_ATTR_2(in5_max, 0644, show_in, set_in, 5, 2);
1310
1311 static SENSOR_DEVICE_ATTR_2(in6_input, 0444, show_in, NULL, 6, 0);
1312 static SENSOR_DEVICE_ATTR_2(in6_min, 0644, show_in, set_in, 6, 1);
1313 static SENSOR_DEVICE_ATTR_2(in6_max, 0644, show_in, set_in, 6, 2);
1314
1315 static SENSOR_DEVICE_ATTR_2(in7_input, 0444, show_in, NULL, 7, 0);
1316 static SENSOR_DEVICE_ATTR_2(in7_min, 0644, show_in, set_in, 7, 1);
1317 static SENSOR_DEVICE_ATTR_2(in7_max, 0644, show_in, set_in, 7, 2);
1318
1319 static SENSOR_DEVICE_ATTR_2(in8_input, 0444, show_in, NULL, 8, 0);
1320 static SENSOR_DEVICE_ATTR_2(in9_input, 0444, show_in, NULL, 9, 0);
1321 static SENSOR_DEVICE_ATTR_2(in10_input, 0444, show_in, NULL, 10, 0);
1322 static SENSOR_DEVICE_ATTR_2(in11_input, 0444, show_in, NULL, 11, 0);
1323 static SENSOR_DEVICE_ATTR_2(in12_input, 0444, show_in, NULL, 12, 0);
1324
1325 /* Up to 6 temperatures */
1326 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1327                          char *buf)
1328 {
1329         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1330         int nr = sattr->nr;
1331         int index = sattr->index;
1332         struct it87_data *data = it87_update_device(dev);
1333
1334         if (IS_ERR(data))
1335                 return PTR_ERR(data);
1336
1337         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1338 }
1339
1340 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1341                         const char *buf, size_t count)
1342 {
1343         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1344         int nr = sattr->nr;
1345         int index = sattr->index;
1346         struct it87_data *data = dev_get_drvdata(dev);
1347         long val;
1348         u8 reg, regval;
1349         int err;
1350
1351         if (kstrtol(buf, 10, &val) < 0)
1352                 return -EINVAL;
1353
1354         err = it87_lock(data);
1355         if (err)
1356                 return err;
1357
1358         switch (index) {
1359         default:
1360         case 1:
1361                 reg = data->REG_TEMP_LOW[nr];
1362                 break;
1363         case 2:
1364                 reg = data->REG_TEMP_HIGH[nr];
1365                 break;
1366         case 3:
1367                 regval = data->read(data, IT87_REG_BEEP_ENABLE);
1368                 if (!(regval & 0x80)) {
1369                         regval |= 0x80;
1370                         data->write(data, IT87_REG_BEEP_ENABLE, regval);
1371                 }
1372                 data->valid = 0;
1373                 reg = data->REG_TEMP_OFFSET[nr];
1374                 break;
1375         }
1376
1377         data->temp[nr][index] = TEMP_TO_REG(val);
1378         data->write(data, reg, data->temp[nr][index]);
1379         it87_unlock(data);
1380         return count;
1381 }
1382
1383 static SENSOR_DEVICE_ATTR_2(temp1_input, 0444, show_temp, NULL, 0, 0);
1384 static SENSOR_DEVICE_ATTR_2(temp1_min, 0644, show_temp, set_temp, 0, 1);
1385 static SENSOR_DEVICE_ATTR_2(temp1_max, 0644, show_temp, set_temp, 0, 2);
1386 static SENSOR_DEVICE_ATTR_2(temp1_offset, 0644, show_temp, set_temp, 0, 3);
1387 static SENSOR_DEVICE_ATTR_2(temp2_input, 0444, show_temp, NULL, 1, 0);
1388 static SENSOR_DEVICE_ATTR_2(temp2_min, 0644, show_temp, set_temp, 1, 1);
1389 static SENSOR_DEVICE_ATTR_2(temp2_max, 0644, show_temp, set_temp, 1, 2);
1390 static SENSOR_DEVICE_ATTR_2(temp2_offset, 0644, show_temp, set_temp, 1, 3);
1391 static SENSOR_DEVICE_ATTR_2(temp3_input, 0444, show_temp, NULL, 2, 0);
1392 static SENSOR_DEVICE_ATTR_2(temp3_min, 0644, show_temp, set_temp, 2, 1);
1393 static SENSOR_DEVICE_ATTR_2(temp3_max, 0644, show_temp, set_temp, 2, 2);
1394 static SENSOR_DEVICE_ATTR_2(temp3_offset, 0644, show_temp, set_temp, 2, 3);
1395 static SENSOR_DEVICE_ATTR_2(temp4_input, 0444, show_temp, NULL, 3, 0);
1396 static SENSOR_DEVICE_ATTR_2(temp4_min, 0644, show_temp, set_temp, 3, 1);
1397 static SENSOR_DEVICE_ATTR_2(temp4_max, 0644, show_temp, set_temp, 3, 2);
1398 static SENSOR_DEVICE_ATTR_2(temp4_offset, 0644, show_temp, set_temp, 3, 3);
1399 static SENSOR_DEVICE_ATTR_2(temp5_input, 0444, show_temp, NULL, 4, 0);
1400 static SENSOR_DEVICE_ATTR_2(temp5_min, 0644, show_temp, set_temp, 4, 1);
1401 static SENSOR_DEVICE_ATTR_2(temp5_max, 0644, show_temp, set_temp, 4, 2);
1402 static SENSOR_DEVICE_ATTR_2(temp5_offset, 0644, show_temp, set_temp, 4, 3);
1403 static SENSOR_DEVICE_ATTR_2(temp6_input, 0444, show_temp, NULL, 5, 0);
1404 static SENSOR_DEVICE_ATTR_2(temp6_min, 0644, show_temp, set_temp, 5, 1);
1405 static SENSOR_DEVICE_ATTR_2(temp6_max, 0644, show_temp, set_temp, 5, 2);
1406 static SENSOR_DEVICE_ATTR_2(temp6_offset, 0644, show_temp, set_temp, 5, 3);
1407
1408 static const u8 temp_types_8686[NUM_TEMP][9] = {
1409         { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1410         { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1411         { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1412         { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1413         { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1414         { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1415 };
1416
1417 static int get_temp_type(struct it87_data *data, int index)
1418 {
1419         u8 reg, extra;
1420         int ttype, type = 0;
1421
1422         if (has_bank_sel(data)) {
1423                 u8 src1, src2;
1424
1425                 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1426
1427                 switch (data->type) {
1428                 case it8686:
1429                         if (src1 < 9)
1430                                 type = temp_types_8686[index][src1];
1431                         break;
1432                 case it8625:
1433                         if (index < 3)
1434                                 break;
1435                 case it8655:
1436                 case it8665:
1437                         if (src1 < 3) {
1438                                 index = src1;
1439                                 break;
1440                         }
1441                         src2 = data->temp_src[3];
1442                         switch (src1) {
1443                         case 3:
1444                                 type = (src2 & BIT(index)) ? 6 : 5;
1445                                 break;
1446                         case 4 ... 8:
1447                                 type = (src2 & BIT(index)) ? 4 : 6;
1448                                 break;
1449                         case 9:
1450                                 type = (src2 & BIT(index)) ? 5 : 0;
1451                                 break;
1452                         default:
1453                                 break;
1454                         }
1455                         return type;
1456                 default:
1457                         return 0;
1458                 }
1459         }
1460         if (type)
1461                 return type;
1462
1463         /* Dectect PECI vs. AMDTSI if possible */
1464         ttype = 6;
1465         if ((has_temp_peci(data, index)) && data->type != it8721) {
1466                 extra = data->read(data, 0x98); /* PCH/AMDTSI host status */
1467                 if (extra & BIT(6))
1468                         ttype = 5;
1469         }
1470
1471         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1472
1473         /* Per chip special detection */
1474         switch (data->type) {
1475         case it8622:
1476                 if (!(reg & 0xc0) && index == 3)
1477                         type = ttype;
1478                 break;
1479         default:
1480                 break;
1481         }
1482
1483         if (type || index >= 3)
1484                 return type;
1485
1486         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1487
1488         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1489             (has_temp_old_peci(data, index) && (extra & 0x80)))
1490                 type = ttype;           /* Intel PECI or AMDTSI */
1491         if (reg & BIT(index))
1492                 type = 3;               /* thermal diode */
1493         else if (reg & BIT(index + 3))
1494                 type = 4;               /* thermistor */
1495
1496         return type;
1497 }
1498
1499 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1500                               char *buf)
1501 {
1502         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1503         struct it87_data *data = it87_update_device(dev);
1504         int type;
1505
1506         if (IS_ERR(data))
1507                 return PTR_ERR(data);
1508
1509         type = get_temp_type(data, sensor_attr->index);
1510         return sprintf(buf, "%d\n", type);
1511 }
1512
1513 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1514                              const char *buf, size_t count)
1515 {
1516         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1517         int nr = sensor_attr->index;
1518
1519         struct it87_data *data = dev_get_drvdata(dev);
1520         long val;
1521         u8 reg, extra;
1522         int err;
1523
1524         if (kstrtol(buf, 10, &val) < 0)
1525                 return -EINVAL;
1526
1527         err = it87_lock(data);
1528         if (err)
1529                 return err;
1530
1531         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1532         reg &= ~(1 << nr);
1533         reg &= ~(8 << nr);
1534         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1535                 reg &= 0x3f;
1536         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1537         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1538                 extra &= 0x7f;
1539         if (val == 2) { /* backwards compatibility */
1540                 dev_warn(dev,
1541                          "Sensor type 2 is deprecated, please use 4 instead\n");
1542                 val = 4;
1543         }
1544         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1545         if (val == 3)
1546                 reg |= 1 << nr;
1547         else if (val == 4)
1548                 reg |= 8 << nr;
1549         else if (has_temp_peci(data, nr) && val == 6)
1550                 reg |= (nr + 1) << 6;
1551         else if (has_temp_old_peci(data, nr) && val == 6)
1552                 extra |= 0x80;
1553         else if (val != 0) {
1554                 count = -EINVAL;
1555                 goto unlock;
1556         }
1557
1558         data->sensor = reg;
1559         data->extra = extra;
1560         data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1561         if (has_temp_old_peci(data, nr))
1562                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1563         data->valid = 0;        /* Force cache refresh */
1564 unlock:
1565         it87_unlock(data);
1566         return count;
1567 }
1568
1569 static SENSOR_DEVICE_ATTR(temp1_type, 0644, show_temp_type, set_temp_type, 0);
1570 static SENSOR_DEVICE_ATTR(temp2_type, 0644, show_temp_type, set_temp_type, 1);
1571 static SENSOR_DEVICE_ATTR(temp3_type, 0644, show_temp_type, set_temp_type, 2);
1572 static SENSOR_DEVICE_ATTR(temp4_type, 0644, show_temp_type, set_temp_type, 3);
1573 static SENSOR_DEVICE_ATTR(temp5_type, 0644, show_temp_type, set_temp_type, 4);
1574 static SENSOR_DEVICE_ATTR(temp6_type, 0644, show_temp_type, set_temp_type, 5);
1575
1576 /* 6 Fans */
1577
1578 static int pwm_mode(const struct it87_data *data, int nr)
1579 {
1580         if (has_fanctl_onoff(data) && nr < 3 &&
1581             !(data->fan_main_ctrl & BIT(nr)))
1582                 return 0;                               /* Full speed */
1583         if (data->pwm_ctrl[nr] & 0x80)
1584                 return 2;                               /* Automatic mode */
1585         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1586             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1587                 return 0;                       /* Full speed */
1588
1589         return 1;                               /* Manual mode */
1590 }
1591
1592 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1593                         char *buf)
1594 {
1595         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1596         int nr = sattr->nr;
1597         int index = sattr->index;
1598         int speed;
1599         struct it87_data *data = it87_update_device(dev);
1600
1601         if (IS_ERR(data))
1602                 return PTR_ERR(data);
1603
1604         speed = has_16bit_fans(data) ?
1605                 FAN16_FROM_REG(data->fan[nr][index]) :
1606                 FAN_FROM_REG(data->fan[nr][index],
1607                              DIV_FROM_REG(data->fan_div[nr]));
1608         return sprintf(buf, "%d\n", speed);
1609 }
1610
1611 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1612                             char *buf)
1613 {
1614         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1615         struct it87_data *data = it87_update_device(dev);
1616         int nr = sensor_attr->index;
1617
1618         if (IS_ERR(data))
1619                 return PTR_ERR(data);
1620
1621         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1622 }
1623
1624 static ssize_t show_pwm_enable(struct device *dev,
1625                                struct device_attribute *attr, char *buf)
1626 {
1627         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1628         struct it87_data *data = it87_update_device(dev);
1629         int nr = sensor_attr->index;
1630
1631         if (IS_ERR(data))
1632                 return PTR_ERR(data);
1633
1634         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1635 }
1636
1637 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1638                         char *buf)
1639 {
1640         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1641         struct it87_data *data = it87_update_device(dev);
1642         int nr = sensor_attr->index;
1643
1644         if (IS_ERR(data))
1645                 return PTR_ERR(data);
1646
1647         return sprintf(buf, "%d\n",
1648                        pwm_from_reg(data, data->pwm_duty[nr]));
1649 }
1650
1651 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1652                              char *buf)
1653 {
1654         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1655         struct it87_data *data = it87_update_device(dev);
1656         int nr = sensor_attr->index;
1657         unsigned int freq;
1658         int index;
1659
1660         if (IS_ERR(data))
1661                 return PTR_ERR(data);
1662
1663         if (has_pwm_freq2(data) && nr == 1)
1664                 index = (data->extra >> 4) & 0x07;
1665         else
1666                 index = (data->fan_ctl >> 4) & 0x07;
1667
1668         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1669
1670         return sprintf(buf, "%u\n", freq);
1671 }
1672
1673 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1674                        const char *buf, size_t count)
1675 {
1676         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1677         int nr = sattr->nr;
1678         int index = sattr->index;
1679
1680         struct it87_data *data = dev_get_drvdata(dev);
1681         long val;
1682         int err;
1683         u8 reg;
1684
1685         if (kstrtol(buf, 10, &val) < 0)
1686                 return -EINVAL;
1687
1688         err = it87_lock(data);
1689         if (err)
1690                 return err;
1691
1692         if (has_16bit_fans(data)) {
1693                 data->fan[nr][index] = FAN16_TO_REG(val);
1694                 data->write(data, data->REG_FAN_MIN[nr],
1695                             data->fan[nr][index] & 0xff);
1696                 data->write(data, data->REG_FANX_MIN[nr],
1697                             data->fan[nr][index] >> 8);
1698         } else {
1699                 reg = data->read(data, IT87_REG_FAN_DIV);
1700                 switch (nr) {
1701                 case 0:
1702                         data->fan_div[nr] = reg & 0x07;
1703                         break;
1704                 case 1:
1705                         data->fan_div[nr] = (reg >> 3) & 0x07;
1706                         break;
1707                 case 2:
1708                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1709                         break;
1710                 }
1711                 data->fan[nr][index] =
1712                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1713                 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1714         }
1715         it87_unlock(data);
1716         return count;
1717 }
1718
1719 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1720                            const char *buf, size_t count)
1721 {
1722         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1723         struct it87_data *data = dev_get_drvdata(dev);
1724         int nr = sensor_attr->index;
1725         unsigned long val;
1726         int min, err;
1727         u8 old;
1728
1729         if (kstrtoul(buf, 10, &val) < 0)
1730                 return -EINVAL;
1731
1732         err = it87_lock(data);
1733         if (err)
1734                 return err;
1735
1736         old = data->read(data, IT87_REG_FAN_DIV);
1737
1738         /* Save fan min limit */
1739         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1740
1741         switch (nr) {
1742         case 0:
1743         case 1:
1744                 data->fan_div[nr] = DIV_TO_REG(val);
1745                 break;
1746         case 2:
1747                 if (val < 8)
1748                         data->fan_div[nr] = 1;
1749                 else
1750                         data->fan_div[nr] = 3;
1751         }
1752         val = old & 0x80;
1753         val |= (data->fan_div[0] & 0x07);
1754         val |= (data->fan_div[1] & 0x07) << 3;
1755         if (data->fan_div[2] == 3)
1756                 val |= 0x1 << 6;
1757         data->write(data, IT87_REG_FAN_DIV, val);
1758
1759         /* Restore fan min limit */
1760         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1761         data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1762         it87_unlock(data);
1763         return count;
1764 }
1765
1766 /* Returns 0 if OK, -EINVAL otherwise */
1767 static int check_trip_points(struct device *dev, int nr)
1768 {
1769         const struct it87_data *data = dev_get_drvdata(dev);
1770         int i, err = 0;
1771
1772         if (has_old_autopwm(data)) {
1773                 for (i = 0; i < 3; i++) {
1774                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1775                                 err = -EINVAL;
1776                 }
1777                 for (i = 0; i < 2; i++) {
1778                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1779                                 err = -EINVAL;
1780                 }
1781         } else if (has_newer_autopwm(data)) {
1782                 for (i = 1; i < 3; i++) {
1783                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1784                                 err = -EINVAL;
1785                 }
1786         }
1787
1788         if (err) {
1789                 dev_err(dev,
1790                         "Inconsistent trip points, not switching to automatic mode\n");
1791                 dev_err(dev, "Adjust the trip points and try again\n");
1792         }
1793         return err;
1794 }
1795
1796 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1797                               const char *buf, size_t count)
1798 {
1799         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1800         struct it87_data *data = dev_get_drvdata(dev);
1801         int nr = sensor_attr->index;
1802         long val;
1803         int err;
1804
1805         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1806                 return -EINVAL;
1807
1808         /* Check trip points before switching to automatic mode */
1809         if (val == 2) {
1810                 if (check_trip_points(dev, nr) < 0)
1811                         return -EINVAL;
1812         }
1813
1814         err = it87_lock(data);
1815         if (err)
1816                 return err;
1817
1818         it87_update_pwm_ctrl(data, nr);
1819
1820         if (val == 0) {
1821                 if (nr < 3 && has_fanctl_onoff(data)) {
1822                         int tmp;
1823                         /* make sure the fan is on when in on/off mode */
1824                         tmp = data->read(data, IT87_REG_FAN_CTL);
1825                         data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1826                         /* set on/off mode */
1827                         data->fan_main_ctrl &= ~BIT(nr);
1828                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1829                                     data->fan_main_ctrl);
1830                 } else {
1831                         u8 ctrl;
1832
1833                         /* No on/off mode, set maximum pwm value */
1834                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1835                         data->write(data, IT87_REG_PWM_DUTY[nr],
1836                                     data->pwm_duty[nr]);
1837                         /* and set manual mode */
1838                         if (has_newer_autopwm(data)) {
1839                                 ctrl = temp_map_to_reg(data, nr,
1840                                                        data->pwm_temp_map[nr]);
1841                                 ctrl &= 0x7f;
1842                         } else {
1843                                 ctrl = data->pwm_duty[nr];
1844                         }
1845                         data->pwm_ctrl[nr] = ctrl;
1846                         data->write(data, data->REG_PWM[nr], ctrl);
1847                 }
1848         } else {
1849                 u8 ctrl;
1850
1851                 if (has_newer_autopwm(data)) {
1852                         ctrl = temp_map_to_reg(data, nr,
1853                                                data->pwm_temp_map[nr]);
1854                         if (val == 1)
1855                                 ctrl &= 0x7f;
1856                         else
1857                                 ctrl |= 0x80;
1858                 } else {
1859                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1860                 }
1861                 data->pwm_ctrl[nr] = ctrl;
1862                 data->write(data, data->REG_PWM[nr], ctrl);
1863
1864                 if (has_fanctl_onoff(data) && nr < 3) {
1865                         /* set SmartGuardian mode */
1866                         data->fan_main_ctrl |= BIT(nr);
1867                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1868                                     data->fan_main_ctrl);
1869                 }
1870         }
1871         it87_unlock(data);
1872         return count;
1873 }
1874
1875 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1876                        const char *buf, size_t count)
1877 {
1878         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1879         struct it87_data *data = dev_get_drvdata(dev);
1880         int nr = sensor_attr->index;
1881         long val;
1882         int err;
1883
1884         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1885                 return -EINVAL;
1886
1887         err = it87_lock(data);
1888         if (err)
1889                 return err;
1890
1891         it87_update_pwm_ctrl(data, nr);
1892         if (has_newer_autopwm(data)) {
1893                 /*
1894                  * If we are in automatic mode, the PWM duty cycle register
1895                  * is read-only so we can't write the value.
1896                  */
1897                 if (data->pwm_ctrl[nr] & 0x80) {
1898                         count = -EBUSY;
1899                         goto unlock;
1900                 }
1901                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1902                 data->write(data, IT87_REG_PWM_DUTY[nr],
1903                             data->pwm_duty[nr]);
1904         } else {
1905                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1906                 /*
1907                  * If we are in manual mode, write the duty cycle immediately;
1908                  * otherwise, just store it for later use.
1909                  */
1910                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1911                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1912                         data->write(data, data->REG_PWM[nr],
1913                                     data->pwm_ctrl[nr]);
1914                 }
1915         }
1916 unlock:
1917         it87_unlock(data);
1918         return count;
1919 }
1920
1921 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1922                             const char *buf, size_t count)
1923 {
1924         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1925         struct it87_data *data = dev_get_drvdata(dev);
1926         int nr = sensor_attr->index;
1927         unsigned long val;
1928         int err;
1929         int i;
1930
1931         if (kstrtoul(buf, 10, &val) < 0)
1932                 return -EINVAL;
1933
1934         val = clamp_val(val, 0, 1000000);
1935         val *= has_newer_autopwm(data) ? 256 : 128;
1936
1937         /* Search for the nearest available frequency */
1938         for (i = 0; i < 7; i++) {
1939                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1940                         break;
1941         }
1942
1943         err = it87_lock(data);
1944         if (err)
1945                 return err;
1946
1947         if (nr == 0) {
1948                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1949                 data->fan_ctl |= i << 4;
1950                 data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
1951         } else {
1952                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1953                 data->extra |= i << 4;
1954                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1955         }
1956         it87_unlock(data);
1957         return count;
1958 }
1959
1960 static ssize_t show_pwm_temp_map(struct device *dev,
1961                                  struct device_attribute *attr, char *buf)
1962 {
1963         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1964         struct it87_data *data = it87_update_device(dev);
1965         int nr = sensor_attr->index;
1966
1967         if (IS_ERR(data))
1968                 return PTR_ERR(data);
1969
1970         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1971 }
1972
1973 static ssize_t set_pwm_temp_map(struct device *dev,
1974                                 struct device_attribute *attr, const char *buf,
1975                                 size_t count)
1976 {
1977         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1978         struct it87_data *data = dev_get_drvdata(dev);
1979         int nr = sensor_attr->index;
1980         unsigned long val;
1981         int err;
1982         u8 map;
1983
1984         if (kstrtoul(buf, 10, &val) < 0)
1985                 return -EINVAL;
1986
1987         if (!val || val > data->pwm_num_temp_map)
1988                 return -EINVAL;
1989
1990         map = val - 1;
1991
1992         err = it87_lock(data);
1993         if (err)
1994                 return err;
1995
1996         it87_update_pwm_ctrl(data, nr);
1997         data->pwm_temp_map[nr] = map;
1998         /*
1999          * If we are in automatic mode, write the temp mapping immediately;
2000          * otherwise, just store it for later use.
2001          */
2002         if (data->pwm_ctrl[nr] & 0x80) {
2003                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
2004                 data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
2005         }
2006         it87_unlock(data);
2007         return count;
2008 }
2009
2010 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
2011                              char *buf)
2012 {
2013         struct it87_data *data = it87_update_device(dev);
2014         struct sensor_device_attribute_2 *sensor_attr =
2015                         to_sensor_dev_attr_2(attr);
2016         int nr = sensor_attr->nr;
2017         int point = sensor_attr->index;
2018
2019         if (IS_ERR(data))
2020                 return PTR_ERR(data);
2021
2022         return sprintf(buf, "%d\n",
2023                        pwm_from_reg(data, data->auto_pwm[nr][point]));
2024 }
2025
2026 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2027                             const char *buf, size_t count)
2028 {
2029         struct it87_data *data = dev_get_drvdata(dev);
2030         struct sensor_device_attribute_2 *sensor_attr =
2031                         to_sensor_dev_attr_2(attr);
2032         int nr = sensor_attr->nr;
2033         int point = sensor_attr->index;
2034         int regaddr;
2035         long val;
2036         int err;
2037
2038         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2039                 return -EINVAL;
2040
2041         err = it87_lock(data);
2042         if (err)
2043                 return err;
2044
2045         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2046         if (has_newer_autopwm(data))
2047                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2048         else
2049                 regaddr = IT87_REG_AUTO_PWM(nr, point);
2050         data->write(data, regaddr, data->auto_pwm[nr][point]);
2051         it87_unlock(data);
2052         return count;
2053 }
2054
2055 static ssize_t show_auto_pwm_slope(struct device *dev,
2056                                    struct device_attribute *attr, char *buf)
2057 {
2058         struct it87_data *data = it87_update_device(dev);
2059         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2060         int nr = sensor_attr->index;
2061
2062         if (IS_ERR(data))
2063                 return PTR_ERR(data);
2064
2065         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2066 }
2067
2068 static ssize_t set_auto_pwm_slope(struct device *dev,
2069                                   struct device_attribute *attr,
2070                                   const char *buf, size_t count)
2071 {
2072         struct it87_data *data = dev_get_drvdata(dev);
2073         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2074         int nr = sensor_attr->index;
2075         unsigned long val;
2076         int err;
2077
2078         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2079                 return -EINVAL;
2080
2081         err = it87_lock(data);
2082         if (err)
2083                 return err;
2084
2085         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2086         data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2087         it87_unlock(data);
2088         return count;
2089 }
2090
2091 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2092                               char *buf)
2093 {
2094         struct it87_data *data = it87_update_device(dev);
2095         struct sensor_device_attribute_2 *sensor_attr =
2096                         to_sensor_dev_attr_2(attr);
2097         int nr = sensor_attr->nr;
2098         int point = sensor_attr->index;
2099         int reg;
2100
2101         if (IS_ERR(data))
2102                 return PTR_ERR(data);
2103
2104         if (has_old_autopwm(data) || point)
2105                 reg = data->auto_temp[nr][point];
2106         else
2107                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2108
2109         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2110 }
2111
2112 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2113                              const char *buf, size_t count)
2114 {
2115         struct it87_data *data = dev_get_drvdata(dev);
2116         struct sensor_device_attribute_2 *sensor_attr =
2117                         to_sensor_dev_attr_2(attr);
2118         int nr = sensor_attr->nr;
2119         int point = sensor_attr->index;
2120         long val;
2121         int reg;
2122         int err;
2123
2124         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2125                 return -EINVAL;
2126
2127         err = it87_lock(data);
2128         if (err)
2129                 return err;
2130
2131         if (has_newer_autopwm(data) && !point) {
2132                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2133                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2134                 data->auto_temp[nr][0] = reg;
2135                 data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2136         } else {
2137                 reg = TEMP_TO_REG(val);
2138                 data->auto_temp[nr][point] = reg;
2139                 if (has_newer_autopwm(data))
2140                         point--;
2141                 data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2142         }
2143         it87_unlock(data);
2144         return count;
2145 }
2146
2147 static SENSOR_DEVICE_ATTR_2(fan1_input, 0444, show_fan, NULL, 0, 0);
2148 static SENSOR_DEVICE_ATTR_2(fan1_min, 0644, show_fan, set_fan, 0, 1);
2149 static SENSOR_DEVICE_ATTR(fan1_div, 0644, show_fan_div, set_fan_div, 0);
2150
2151 static SENSOR_DEVICE_ATTR_2(fan2_input, 0444, show_fan, NULL, 1, 0);
2152 static SENSOR_DEVICE_ATTR_2(fan2_min, 0644, show_fan, set_fan, 1, 1);
2153 static SENSOR_DEVICE_ATTR(fan2_div, 0644, show_fan_div, set_fan_div, 1);
2154
2155 static SENSOR_DEVICE_ATTR_2(fan3_input, 0444, show_fan, NULL, 2, 0);
2156 static SENSOR_DEVICE_ATTR_2(fan3_min, 0644, show_fan, set_fan, 2, 1);
2157 static SENSOR_DEVICE_ATTR(fan3_div, 0644, show_fan_div, set_fan_div, 2);
2158
2159 static SENSOR_DEVICE_ATTR_2(fan4_input, 0444, show_fan, NULL, 3, 0);
2160 static SENSOR_DEVICE_ATTR_2(fan4_min, 0644, show_fan, set_fan, 3, 1);
2161
2162 static SENSOR_DEVICE_ATTR_2(fan5_input, 0444, show_fan, NULL, 4, 0);
2163 static SENSOR_DEVICE_ATTR_2(fan5_min, 0644, show_fan, set_fan, 4, 1);
2164
2165 static SENSOR_DEVICE_ATTR_2(fan6_input, 0444, show_fan, NULL, 5, 0);
2166 static SENSOR_DEVICE_ATTR_2(fan6_min, 0644, show_fan, set_fan, 5, 1);
2167
2168 static SENSOR_DEVICE_ATTR(pwm1_enable, 0644,
2169                           show_pwm_enable, set_pwm_enable, 0);
2170 static SENSOR_DEVICE_ATTR(pwm1, 0644, show_pwm, set_pwm, 0);
2171 static SENSOR_DEVICE_ATTR(pwm1_freq, 0644, show_pwm_freq, set_pwm_freq, 0);
2172 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, 0444,
2173                           show_pwm_temp_map, set_pwm_temp_map, 0);
2174 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, 0644,
2175                             show_auto_pwm, set_auto_pwm, 0, 0);
2176 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, 0644,
2177                             show_auto_pwm, set_auto_pwm, 0, 1);
2178 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, 0644,
2179                             show_auto_pwm, set_auto_pwm, 0, 2);
2180 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, 0444,
2181                             show_auto_pwm, NULL, 0, 3);
2182 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, 0644,
2183                             show_auto_temp, set_auto_temp, 0, 1);
2184 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, 0644,
2185                             show_auto_temp, set_auto_temp, 0, 0);
2186 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, 0644,
2187                             show_auto_temp, set_auto_temp, 0, 2);
2188 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, 0644,
2189                             show_auto_temp, set_auto_temp, 0, 3);
2190 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, 0644,
2191                             show_auto_temp, set_auto_temp, 0, 4);
2192 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, 0644,
2193                             show_auto_pwm, set_auto_pwm, 0, 0);
2194 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, 0644,
2195                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2196
2197 static SENSOR_DEVICE_ATTR(pwm2_enable, 0644,
2198                           show_pwm_enable, set_pwm_enable, 1);
2199 static SENSOR_DEVICE_ATTR(pwm2, 0644, show_pwm, set_pwm, 1);
2200 static SENSOR_DEVICE_ATTR(pwm2_freq, 0444, show_pwm_freq, set_pwm_freq, 1);
2201 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, 0444,
2202                           show_pwm_temp_map, set_pwm_temp_map, 1);
2203 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, 0644,
2204                             show_auto_pwm, set_auto_pwm, 1, 0);
2205 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, 0644,
2206                             show_auto_pwm, set_auto_pwm, 1, 1);
2207 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, 0644,
2208                             show_auto_pwm, set_auto_pwm, 1, 2);
2209 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, 0444,
2210                             show_auto_pwm, NULL, 1, 3);
2211 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, 0644,
2212                             show_auto_temp, set_auto_temp, 1, 1);
2213 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, 0644,
2214                             show_auto_temp, set_auto_temp, 1, 0);
2215 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, 0644,
2216                             show_auto_temp, set_auto_temp, 1, 2);
2217 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, 0644,
2218                             show_auto_temp, set_auto_temp, 1, 3);
2219 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, 0644,
2220                             show_auto_temp, set_auto_temp, 1, 4);
2221 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, 0644,
2222                             show_auto_pwm, set_auto_pwm, 1, 0);
2223 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, 0644,
2224                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2225
2226 static SENSOR_DEVICE_ATTR(pwm3_enable, 0644,
2227                           show_pwm_enable, set_pwm_enable, 2);
2228 static SENSOR_DEVICE_ATTR(pwm3, 0644, show_pwm, set_pwm, 2);
2229 static SENSOR_DEVICE_ATTR(pwm3_freq, 0444, show_pwm_freq, NULL, 2);
2230 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, 0444,
2231                           show_pwm_temp_map, set_pwm_temp_map, 2);
2232 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, 0644,
2233                             show_auto_pwm, set_auto_pwm, 2, 0);
2234 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, 0644,
2235                             show_auto_pwm, set_auto_pwm, 2, 1);
2236 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, 0644,
2237                             show_auto_pwm, set_auto_pwm, 2, 2);
2238 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, 0444,
2239                             show_auto_pwm, NULL, 2, 3);
2240 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, 0644,
2241                             show_auto_temp, set_auto_temp, 2, 1);
2242 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, 0644,
2243                             show_auto_temp, set_auto_temp, 2, 0);
2244 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, 0644,
2245                             show_auto_temp, set_auto_temp, 2, 2);
2246 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, 0644,
2247                             show_auto_temp, set_auto_temp, 2, 3);
2248 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, 0644,
2249                             show_auto_temp, set_auto_temp, 2, 4);
2250 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, 0644,
2251                             show_auto_pwm, set_auto_pwm, 2, 0);
2252 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, 0644,
2253                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2254
2255 static SENSOR_DEVICE_ATTR(pwm4_enable, 0644,
2256                           show_pwm_enable, set_pwm_enable, 3);
2257 static SENSOR_DEVICE_ATTR(pwm4, 0644, show_pwm, set_pwm, 3);
2258 static SENSOR_DEVICE_ATTR(pwm4_freq, 0444, show_pwm_freq, NULL, 3);
2259 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, 0444,
2260                           show_pwm_temp_map, set_pwm_temp_map, 3);
2261 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, 0644,
2262                             show_auto_temp, set_auto_temp, 2, 1);
2263 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, 0644,
2264                             show_auto_temp, set_auto_temp, 2, 0);
2265 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, 0644,
2266                             show_auto_temp, set_auto_temp, 2, 2);
2267 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, 0644,
2268                             show_auto_temp, set_auto_temp, 2, 3);
2269 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, 0644,
2270                             show_auto_pwm, set_auto_pwm, 3, 0);
2271 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, 0644,
2272                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2273
2274 static SENSOR_DEVICE_ATTR(pwm5_enable, 0644,
2275                           show_pwm_enable, set_pwm_enable, 4);
2276 static SENSOR_DEVICE_ATTR(pwm5, 0644, show_pwm, set_pwm, 4);
2277 static SENSOR_DEVICE_ATTR(pwm5_freq, 0444, show_pwm_freq, NULL, 4);
2278 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, 0444,
2279                           show_pwm_temp_map, set_pwm_temp_map, 4);
2280 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, 0644,
2281                             show_auto_temp, set_auto_temp, 2, 1);
2282 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, 0644,
2283                             show_auto_temp, set_auto_temp, 2, 0);
2284 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, 0644,
2285                             show_auto_temp, set_auto_temp, 2, 2);
2286 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, 0644,
2287                             show_auto_temp, set_auto_temp, 2, 3);
2288 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, 0644,
2289                             show_auto_pwm, set_auto_pwm, 4, 0);
2290 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, 0644,
2291                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2292
2293 static SENSOR_DEVICE_ATTR(pwm6_enable, 0644,
2294                           show_pwm_enable, set_pwm_enable, 5);
2295 static SENSOR_DEVICE_ATTR(pwm6, 0644, show_pwm, set_pwm, 5);
2296 static SENSOR_DEVICE_ATTR(pwm6_freq, 0444, show_pwm_freq, NULL, 5);
2297 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, 0444,
2298                           show_pwm_temp_map, set_pwm_temp_map, 5);
2299 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, 0644,
2300                             show_auto_temp, set_auto_temp, 2, 1);
2301 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, 0644,
2302                             show_auto_temp, set_auto_temp, 2, 0);
2303 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, 0644,
2304                             show_auto_temp, set_auto_temp, 2, 2);
2305 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, 0644,
2306                             show_auto_temp, set_auto_temp, 2, 3);
2307 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, 0644,
2308                             show_auto_pwm, set_auto_pwm, 5, 0);
2309 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, 0644,
2310                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2311
2312 /* Alarms */
2313 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2314                            char *buf)
2315 {
2316         struct it87_data *data = it87_update_device(dev);
2317
2318         if (IS_ERR(data))
2319                 return PTR_ERR(data);
2320
2321         return sprintf(buf, "%u\n", data->alarms);
2322 }
2323 static DEVICE_ATTR(alarms, 0444, show_alarms, NULL);
2324
2325 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2326                           char *buf)
2327 {
2328         struct it87_data *data = it87_update_device(dev);
2329         int bitnr = to_sensor_dev_attr(attr)->index;
2330
2331         if (IS_ERR(data))
2332                 return PTR_ERR(data);
2333
2334         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2335 }
2336
2337 static ssize_t clear_intrusion(struct device *dev,
2338                                struct device_attribute *attr, const char *buf,
2339                                size_t count)
2340 {
2341         struct it87_data *data = dev_get_drvdata(dev);
2342         int err, config;
2343         long val;
2344
2345         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2346                 return -EINVAL;
2347
2348         err = it87_lock(data);
2349         if (err)
2350                 return err;
2351
2352         config = data->read(data, IT87_REG_CONFIG);
2353         config |= BIT(5);
2354         data->write(data, IT87_REG_CONFIG, config);
2355         /* Invalidate cache to force re-read */
2356         data->valid = 0;
2357         it87_unlock(data);
2358         return count;
2359 }
2360
2361 static SENSOR_DEVICE_ATTR(in0_alarm, 0444, show_alarm, NULL, 8);
2362 static SENSOR_DEVICE_ATTR(in1_alarm, 0444, show_alarm, NULL, 9);
2363 static SENSOR_DEVICE_ATTR(in2_alarm, 0444, show_alarm, NULL, 10);
2364 static SENSOR_DEVICE_ATTR(in3_alarm, 0444, show_alarm, NULL, 11);
2365 static SENSOR_DEVICE_ATTR(in4_alarm, 0444, show_alarm, NULL, 12);
2366 static SENSOR_DEVICE_ATTR(in5_alarm, 0444, show_alarm, NULL, 13);
2367 static SENSOR_DEVICE_ATTR(in6_alarm, 0444, show_alarm, NULL, 14);
2368 static SENSOR_DEVICE_ATTR(in7_alarm, 0444, show_alarm, NULL, 15);
2369 static SENSOR_DEVICE_ATTR(fan1_alarm, 0444, show_alarm, NULL, 0);
2370 static SENSOR_DEVICE_ATTR(fan2_alarm, 0444, show_alarm, NULL, 1);
2371 static SENSOR_DEVICE_ATTR(fan3_alarm, 0444, show_alarm, NULL, 2);
2372 static SENSOR_DEVICE_ATTR(fan4_alarm, 0444, show_alarm, NULL, 3);
2373 static SENSOR_DEVICE_ATTR(fan5_alarm, 0444, show_alarm, NULL, 6);
2374 static SENSOR_DEVICE_ATTR(fan6_alarm, 0444, show_alarm, NULL, 7);
2375 static SENSOR_DEVICE_ATTR(temp1_alarm, 0444, show_alarm, NULL, 16);
2376 static SENSOR_DEVICE_ATTR(temp2_alarm, 0444, show_alarm, NULL, 17);
2377 static SENSOR_DEVICE_ATTR(temp3_alarm, 0444, show_alarm, NULL, 18);
2378 static SENSOR_DEVICE_ATTR(temp4_alarm, 0444, show_alarm, NULL, 19);
2379 static SENSOR_DEVICE_ATTR(temp5_alarm, 0444, show_alarm, NULL, 20);
2380 static SENSOR_DEVICE_ATTR(temp6_alarm, 0444, show_alarm, NULL, 21);
2381 static SENSOR_DEVICE_ATTR(intrusion0_alarm, 0644,
2382                           show_alarm, clear_intrusion, 4);
2383
2384 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2385                          char *buf)
2386 {
2387         struct it87_data *data = it87_update_device(dev);
2388         int bitnr = to_sensor_dev_attr(attr)->index;
2389
2390         if (IS_ERR(data))
2391                 return PTR_ERR(data);
2392
2393         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2394 }
2395
2396 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2397                         const char *buf, size_t count)
2398 {
2399         int bitnr = to_sensor_dev_attr(attr)->index;
2400         struct it87_data *data = dev_get_drvdata(dev);
2401         long val;
2402         int err;
2403
2404         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2405                 return -EINVAL;
2406
2407         err = it87_lock(data);
2408         if (err)
2409                 return err;
2410
2411         data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2412         if (val)
2413                 data->beeps |= BIT(bitnr);
2414         else
2415                 data->beeps &= ~BIT(bitnr);
2416         data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2417         it87_unlock(data);
2418         return count;
2419 }
2420
2421 static SENSOR_DEVICE_ATTR(in0_beep, 0644,
2422                           show_beep, set_beep, 1);
2423 static SENSOR_DEVICE_ATTR(in1_beep, 0444, show_beep, NULL, 1);
2424 static SENSOR_DEVICE_ATTR(in2_beep, 0444, show_beep, NULL, 1);
2425 static SENSOR_DEVICE_ATTR(in3_beep, 0444, show_beep, NULL, 1);
2426 static SENSOR_DEVICE_ATTR(in4_beep, 0444, show_beep, NULL, 1);
2427 static SENSOR_DEVICE_ATTR(in5_beep, 0444, show_beep, NULL, 1);
2428 static SENSOR_DEVICE_ATTR(in6_beep, 0444, show_beep, NULL, 1);
2429 static SENSOR_DEVICE_ATTR(in7_beep, 0444, show_beep, NULL, 1);
2430 /* fanX_beep writability is set later */
2431 static SENSOR_DEVICE_ATTR(fan1_beep, 0444, show_beep, set_beep, 0);
2432 static SENSOR_DEVICE_ATTR(fan2_beep, 0444, show_beep, set_beep, 0);
2433 static SENSOR_DEVICE_ATTR(fan3_beep, 0444, show_beep, set_beep, 0);
2434 static SENSOR_DEVICE_ATTR(fan4_beep, 0444, show_beep, set_beep, 0);
2435 static SENSOR_DEVICE_ATTR(fan5_beep, 0444, show_beep, set_beep, 0);
2436 static SENSOR_DEVICE_ATTR(fan6_beep, 0444, show_beep, set_beep, 0);
2437 static SENSOR_DEVICE_ATTR(temp1_beep, 0644,
2438                           show_beep, set_beep, 2);
2439 static SENSOR_DEVICE_ATTR(temp2_beep, 0444, show_beep, NULL, 2);
2440 static SENSOR_DEVICE_ATTR(temp3_beep, 0444, show_beep, NULL, 2);
2441 static SENSOR_DEVICE_ATTR(temp4_beep, 0444, show_beep, NULL, 2);
2442 static SENSOR_DEVICE_ATTR(temp5_beep, 0444, show_beep, NULL, 2);
2443 static SENSOR_DEVICE_ATTR(temp6_beep, 0444, show_beep, NULL, 2);
2444
2445 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2446                             char *buf)
2447 {
2448         struct it87_data *data = dev_get_drvdata(dev);
2449
2450         return sprintf(buf, "%u\n", data->vrm);
2451 }
2452
2453 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2454                              const char *buf, size_t count)
2455 {
2456         struct it87_data *data = dev_get_drvdata(dev);
2457         unsigned long val;
2458
2459         if (kstrtoul(buf, 10, &val) < 0)
2460                 return -EINVAL;
2461
2462         data->vrm = val;
2463
2464         return count;
2465 }
2466 static DEVICE_ATTR(vrm, 0644, show_vrm_reg, store_vrm_reg);
2467
2468 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2469                             char *buf)
2470 {
2471         struct it87_data *data = it87_update_device(dev);
2472
2473         if (IS_ERR(data))
2474                 return PTR_ERR(data);
2475
2476         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2477 }
2478 static DEVICE_ATTR(cpu0_vid, 0444, show_vid_reg, NULL);
2479
2480 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2481                           char *buf)
2482 {
2483         static const char * const labels[] = {
2484                 "+5V",
2485                 "5VSB",
2486                 "Vbat",
2487                 "AVCC",
2488         };
2489         static const char * const labels_it8721[] = {
2490                 "+3.3V",
2491                 "3VSB",
2492                 "Vbat",
2493                 "+3.3V",
2494         };
2495         struct it87_data *data = dev_get_drvdata(dev);
2496         int nr = to_sensor_dev_attr(attr)->index;
2497         const char *label;
2498
2499         if (has_vin3_5v(data) && nr == 0)
2500                 label = labels[0];
2501         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2502                  has_11mv_adc(data))
2503                 label = labels_it8721[nr];
2504         else
2505                 label = labels[nr];
2506
2507         return sprintf(buf, "%s\n", label);
2508 }
2509 static SENSOR_DEVICE_ATTR(in3_label, 0444, show_label, NULL, 0);
2510 static SENSOR_DEVICE_ATTR(in7_label, 0444, show_label, NULL, 1);
2511 static SENSOR_DEVICE_ATTR(in8_label, 0444, show_label, NULL, 2);
2512 /* AVCC3 */
2513 static SENSOR_DEVICE_ATTR(in9_label, 0444, show_label, NULL, 3);
2514
2515 static umode_t it87_in_is_visible(struct kobject *kobj,
2516                                   struct attribute *attr, int index)
2517 {
2518         struct device *dev = container_of(kobj, struct device, kobj);
2519         struct it87_data *data = dev_get_drvdata(dev);
2520         int i = index / 5;      /* voltage index */
2521         int a = index % 5;      /* attribute index */
2522
2523         if (index >= 40) {      /* in8 and higher only have input attributes */
2524                 i = index - 40 + 8;
2525                 a = 0;
2526         }
2527
2528         if (!(data->has_in & BIT(i)))
2529                 return 0;
2530
2531         if (a == 4 && !data->has_beep)
2532                 return 0;
2533
2534         return attr->mode;
2535 }
2536
2537 static struct attribute *it87_attributes_in[] = {
2538         &sensor_dev_attr_in0_input.dev_attr.attr,
2539         &sensor_dev_attr_in0_min.dev_attr.attr,
2540         &sensor_dev_attr_in0_max.dev_attr.attr,
2541         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2542         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2543
2544         &sensor_dev_attr_in1_input.dev_attr.attr,
2545         &sensor_dev_attr_in1_min.dev_attr.attr,
2546         &sensor_dev_attr_in1_max.dev_attr.attr,
2547         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2548         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2549
2550         &sensor_dev_attr_in2_input.dev_attr.attr,
2551         &sensor_dev_attr_in2_min.dev_attr.attr,
2552         &sensor_dev_attr_in2_max.dev_attr.attr,
2553         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2554         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2555
2556         &sensor_dev_attr_in3_input.dev_attr.attr,
2557         &sensor_dev_attr_in3_min.dev_attr.attr,
2558         &sensor_dev_attr_in3_max.dev_attr.attr,
2559         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2560         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2561
2562         &sensor_dev_attr_in4_input.dev_attr.attr,
2563         &sensor_dev_attr_in4_min.dev_attr.attr,
2564         &sensor_dev_attr_in4_max.dev_attr.attr,
2565         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2566         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2567
2568         &sensor_dev_attr_in5_input.dev_attr.attr,
2569         &sensor_dev_attr_in5_min.dev_attr.attr,
2570         &sensor_dev_attr_in5_max.dev_attr.attr,
2571         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2572         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2573
2574         &sensor_dev_attr_in6_input.dev_attr.attr,
2575         &sensor_dev_attr_in6_min.dev_attr.attr,
2576         &sensor_dev_attr_in6_max.dev_attr.attr,
2577         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2578         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2579
2580         &sensor_dev_attr_in7_input.dev_attr.attr,
2581         &sensor_dev_attr_in7_min.dev_attr.attr,
2582         &sensor_dev_attr_in7_max.dev_attr.attr,
2583         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2584         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2585
2586         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2587         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2588         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2589         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2590         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2591         NULL
2592 };
2593
2594 static const struct attribute_group it87_group_in = {
2595         .attrs = it87_attributes_in,
2596         .is_visible = it87_in_is_visible,
2597 };
2598
2599 static umode_t it87_temp_is_visible(struct kobject *kobj,
2600                                     struct attribute *attr, int index)
2601 {
2602         struct device *dev = container_of(kobj, struct device, kobj);
2603         struct it87_data *data = dev_get_drvdata(dev);
2604         int i = index / 7;      /* temperature index */
2605         int a = index % 7;      /* attribute index */
2606
2607         if (!(data->has_temp & BIT(i)))
2608                 return 0;
2609
2610         if (a && i >= data->num_temp_limit)
2611                 return 0;
2612
2613         if (a == 3) {
2614                 int type = get_temp_type(data, i);
2615
2616                 if (type == 0)
2617                         return 0;
2618                 if (has_bank_sel(data))
2619                         return 0444;
2620                 return attr->mode;
2621         }
2622
2623         if (a == 5 && i >= data->num_temp_offset)
2624                 return 0;
2625
2626         if (a == 6 && !data->has_beep)
2627                 return 0;
2628
2629         return attr->mode;
2630 }
2631
2632 static struct attribute *it87_attributes_temp[] = {
2633         &sensor_dev_attr_temp1_input.dev_attr.attr,
2634         &sensor_dev_attr_temp1_max.dev_attr.attr,
2635         &sensor_dev_attr_temp1_min.dev_attr.attr,
2636         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2637         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2638         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2639         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2640
2641         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2642         &sensor_dev_attr_temp2_max.dev_attr.attr,
2643         &sensor_dev_attr_temp2_min.dev_attr.attr,
2644         &sensor_dev_attr_temp2_type.dev_attr.attr,
2645         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2646         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2647         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2648
2649         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2650         &sensor_dev_attr_temp3_max.dev_attr.attr,
2651         &sensor_dev_attr_temp3_min.dev_attr.attr,
2652         &sensor_dev_attr_temp3_type.dev_attr.attr,
2653         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2654         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2655         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2656
2657         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2658         &sensor_dev_attr_temp4_max.dev_attr.attr,
2659         &sensor_dev_attr_temp4_min.dev_attr.attr,
2660         &sensor_dev_attr_temp4_type.dev_attr.attr,
2661         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2662         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2663         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2664
2665         &sensor_dev_attr_temp5_input.dev_attr.attr,
2666         &sensor_dev_attr_temp5_max.dev_attr.attr,
2667         &sensor_dev_attr_temp5_min.dev_attr.attr,
2668         &sensor_dev_attr_temp5_type.dev_attr.attr,
2669         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2670         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2671         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2672
2673         &sensor_dev_attr_temp6_input.dev_attr.attr,
2674         &sensor_dev_attr_temp6_max.dev_attr.attr,
2675         &sensor_dev_attr_temp6_min.dev_attr.attr,
2676         &sensor_dev_attr_temp6_type.dev_attr.attr,
2677         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2678         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2679         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2680         NULL
2681 };
2682
2683 static const struct attribute_group it87_group_temp = {
2684         .attrs = it87_attributes_temp,
2685         .is_visible = it87_temp_is_visible,
2686 };
2687
2688 static umode_t it87_is_visible(struct kobject *kobj,
2689                                struct attribute *attr, int index)
2690 {
2691         struct device *dev = container_of(kobj, struct device, kobj);
2692         struct it87_data *data = dev_get_drvdata(dev);
2693
2694         if ((index == 2 || index == 3) && !data->has_vid)
2695                 return 0;
2696
2697         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2698                 return 0;
2699
2700         return attr->mode;
2701 }
2702
2703 static struct attribute *it87_attributes[] = {
2704         &dev_attr_alarms.attr,
2705         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2706         &dev_attr_vrm.attr,                             /* 2 */
2707         &dev_attr_cpu0_vid.attr,                        /* 3 */
2708         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2709         &sensor_dev_attr_in7_label.dev_attr.attr,
2710         &sensor_dev_attr_in8_label.dev_attr.attr,
2711         &sensor_dev_attr_in9_label.dev_attr.attr,
2712         NULL
2713 };
2714
2715 static const struct attribute_group it87_group = {
2716         .attrs = it87_attributes,
2717         .is_visible = it87_is_visible,
2718 };
2719
2720 static umode_t it87_fan_is_visible(struct kobject *kobj,
2721                                    struct attribute *attr, int index)
2722 {
2723         struct device *dev = container_of(kobj, struct device, kobj);
2724         struct it87_data *data = dev_get_drvdata(dev);
2725         int i = index / 5;      /* fan index */
2726         int a = index % 5;      /* attribute index */
2727
2728         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2729                 i = (index - 15) / 4 + 3;
2730                 a = (index - 15) % 4;
2731         }
2732
2733         if (!(data->has_fan & BIT(i)))
2734                 return 0;
2735
2736         if (a == 3) {                           /* beep */
2737                 if (!data->has_beep)
2738                         return 0;
2739                 /* first fan beep attribute is writable */
2740                 if (i == __ffs(data->has_fan))
2741                         return attr->mode | 0200;
2742         }
2743
2744         if (a == 4 && has_16bit_fans(data))     /* divisor */
2745                 return 0;
2746
2747         return attr->mode;
2748 }
2749
2750 static struct attribute *it87_attributes_fan[] = {
2751         &sensor_dev_attr_fan1_input.dev_attr.attr,
2752         &sensor_dev_attr_fan1_min.dev_attr.attr,
2753         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2754         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2755         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2756
2757         &sensor_dev_attr_fan2_input.dev_attr.attr,
2758         &sensor_dev_attr_fan2_min.dev_attr.attr,
2759         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2760         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2761         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2762
2763         &sensor_dev_attr_fan3_input.dev_attr.attr,
2764         &sensor_dev_attr_fan3_min.dev_attr.attr,
2765         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2766         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2767         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2768
2769         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2770         &sensor_dev_attr_fan4_min.dev_attr.attr,
2771         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2772         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2773
2774         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2775         &sensor_dev_attr_fan5_min.dev_attr.attr,
2776         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2777         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2778
2779         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2780         &sensor_dev_attr_fan6_min.dev_attr.attr,
2781         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2782         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2783         NULL
2784 };
2785
2786 static const struct attribute_group it87_group_fan = {
2787         .attrs = it87_attributes_fan,
2788         .is_visible = it87_fan_is_visible,
2789 };
2790
2791 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2792                                    struct attribute *attr, int index)
2793 {
2794         struct device *dev = container_of(kobj, struct device, kobj);
2795         struct it87_data *data = dev_get_drvdata(dev);
2796         int i = index / 4;      /* pwm index */
2797         int a = index % 4;      /* attribute index */
2798
2799         if (!(data->has_pwm & BIT(i)))
2800                 return 0;
2801
2802         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2803         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2804                 return attr->mode | 0200;
2805
2806         /* pwm2_freq is writable if there are two pwm frequency selects */
2807         if (has_pwm_freq2(data) && i == 1 && a == 2)
2808                 return attr->mode | 0200;
2809
2810         return attr->mode;
2811 }
2812
2813 static struct attribute *it87_attributes_pwm[] = {
2814         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2815         &sensor_dev_attr_pwm1.dev_attr.attr,
2816         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2817         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2818
2819         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2820         &sensor_dev_attr_pwm2.dev_attr.attr,
2821         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2822         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2823
2824         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2825         &sensor_dev_attr_pwm3.dev_attr.attr,
2826         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2827         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2828
2829         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2830         &sensor_dev_attr_pwm4.dev_attr.attr,
2831         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2832         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2833
2834         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2835         &sensor_dev_attr_pwm5.dev_attr.attr,
2836         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2837         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2838
2839         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2840         &sensor_dev_attr_pwm6.dev_attr.attr,
2841         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2842         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2843
2844         NULL
2845 };
2846
2847 static const struct attribute_group it87_group_pwm = {
2848         .attrs = it87_attributes_pwm,
2849         .is_visible = it87_pwm_is_visible,
2850 };
2851
2852 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2853                                         struct attribute *attr, int index)
2854 {
2855         struct device *dev = container_of(kobj, struct device, kobj);
2856         struct it87_data *data = dev_get_drvdata(dev);
2857         int i = index / 11;     /* pwm index */
2858         int a = index % 11;     /* attribute index */
2859
2860         if (index >= 33) {      /* pwm 4..6 */
2861                 i = (index - 33) / 6 + 3;
2862                 a = (index - 33) % 6 + 4;
2863         }
2864
2865         if (!(data->has_pwm & BIT(i)))
2866                 return 0;
2867
2868         if (has_newer_autopwm(data)) {
2869                 if (a < 4)      /* no auto point pwm */
2870                         return 0;
2871                 if (a == 8)     /* no auto_point4 */
2872                         return 0;
2873         }
2874         if (has_old_autopwm(data)) {
2875                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2876                         return 0;
2877         }
2878
2879         return attr->mode;
2880 }
2881
2882 static struct attribute *it87_attributes_auto_pwm[] = {
2883         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2884         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2885         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2886         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2887         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2888         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2889         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2890         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2891         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2892         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2893         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2894
2895         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2896         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2897         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2898         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2899         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2900         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2901         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2902         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2903         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2904         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2905         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2906
2907         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2908         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2909         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2910         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2911         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2912         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2913         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2914         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2915         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2916         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2917         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2918
2919         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2920         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2921         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2922         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2923         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2924         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2925
2926         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2927         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2928         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2929         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2930         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2931         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2932
2933         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2934         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2935         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2936         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2937         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2938         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2939
2940         NULL,
2941 };
2942
2943 static const struct attribute_group it87_group_auto_pwm = {
2944         .attrs = it87_attributes_auto_pwm,
2945         .is_visible = it87_auto_pwm_is_visible,
2946 };
2947
2948 /* SuperIO detection - will change isa_address if a chip is found */
2949 static int __init it87_find(int sioaddr, unsigned short *address,
2950                             phys_addr_t *mmio_address,
2951                             struct it87_sio_data *sio_data)
2952 {
2953         const struct it87_devices *config;
2954         phys_addr_t base = 0;
2955         bool doexit = true;
2956         char mmio_str[32];
2957         u16 chip_type;
2958         int err;
2959
2960         err = superio_enter(sioaddr);
2961         if (err)
2962                 return err;
2963
2964         sio_data->sioaddr = sioaddr;
2965
2966         err = -ENODEV;
2967         chip_type = superio_inw(sioaddr, DEVID);
2968         if (chip_type == 0xffff)
2969                 goto exit;
2970
2971         if (force_id)
2972                 chip_type = force_id;
2973
2974         switch (chip_type) {
2975         case IT8705F_DEVID:
2976                 sio_data->type = it87;
2977                 break;
2978         case IT8712F_DEVID:
2979                 sio_data->type = it8712;
2980                 break;
2981         case IT8716F_DEVID:
2982         case IT8726F_DEVID:
2983                 sio_data->type = it8716;
2984                 break;
2985         case IT8718F_DEVID:
2986                 sio_data->type = it8718;
2987                 break;
2988         case IT8720F_DEVID:
2989                 sio_data->type = it8720;
2990                 break;
2991         case IT8721F_DEVID:
2992                 sio_data->type = it8721;
2993                 break;
2994         case IT8728F_DEVID:
2995                 sio_data->type = it8728;
2996                 break;
2997         case IT8732F_DEVID:
2998                 sio_data->type = it8732;
2999                 break;
3000         case IT8792E_DEVID:
3001                 sio_data->type = it8792;
3002                 /*
3003                  * Disabling configuration mode on IT8792E can result in system
3004                  * hang-ups and access failures to the Super-IO chip at the
3005                  * second SIO address. Never exit configuration mode on this
3006                  * chip to avoid the problem.
3007                  */
3008                 doexit = false;
3009                 break;
3010         case IT8771E_DEVID:
3011                 sio_data->type = it8771;
3012                 break;
3013         case IT8772E_DEVID:
3014                 sio_data->type = it8772;
3015                 break;
3016         case IT8781F_DEVID:
3017                 sio_data->type = it8781;
3018                 break;
3019         case IT8782F_DEVID:
3020                 sio_data->type = it8782;
3021                 break;
3022         case IT8783E_DEVID:
3023                 sio_data->type = it8783;
3024                 break;
3025         case IT8786E_DEVID:
3026                 sio_data->type = it8786;
3027                 break;
3028         case IT8790E_DEVID:
3029                 sio_data->type = it8790;
3030                 doexit = false;         /* See IT8792E comment above */
3031                 break;
3032         case IT8603E_DEVID:
3033         case IT8623E_DEVID:
3034                 sio_data->type = it8603;
3035                 break;
3036         case IT8606E_DEVID:
3037                 sio_data->type = it8606;
3038                 break;
3039         case IT8607E_DEVID:
3040                 sio_data->type = it8607;
3041                 break;
3042         case IT8613E_DEVID:
3043                 sio_data->type = it8613;
3044                 break;
3045         case IT8620E_DEVID:
3046                 sio_data->type = it8620;
3047                 break;
3048         case IT8622E_DEVID:
3049                 sio_data->type = it8622;
3050                 break;
3051         case IT8625E_DEVID:
3052                 sio_data->type = it8625;
3053                 break;
3054         case IT8628E_DEVID:
3055                 sio_data->type = it8628;
3056                 break;
3057         case IT8655E_DEVID:
3058                 sio_data->type = it8655;
3059                 break;
3060         case IT8665E_DEVID:
3061                 sio_data->type = it8665;
3062                 break;
3063         case IT8686E_DEVID:
3064                 sio_data->type = it8686;
3065                 break;
3066         case 0xffff:    /* No device at all */
3067                 goto exit;
3068         default:
3069                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3070                 goto exit;
3071         }
3072
3073         superio_select(sioaddr, PME);
3074         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3075                 pr_info("Device not activated, skipping\n");
3076                 goto exit;
3077         }
3078
3079         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3080         if (*address == 0) {
3081                 pr_info("Base address not set, skipping\n");
3082                 goto exit;
3083         }
3084
3085         sio_data->doexit = doexit;
3086
3087         err = 0;
3088         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3089
3090         config = &it87_devices[sio_data->type];
3091
3092         if (has_mmio(config) && mmio) {
3093                 u8 reg;
3094
3095                 reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
3096                 if (reg & BIT(5)) {
3097                         base = 0xf0000000 + ((reg & 0x0f) << 24);
3098                         base += (reg & 0xc0) << 14;
3099                 }
3100         }
3101         *mmio_address = base;
3102
3103         mmio_str[0] = '\0';
3104         if (base)
3105                 snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
3106
3107         pr_info("Found %s chip at 0x%x%s, revision %d\n",
3108                 it87_devices[sio_data->type].model,
3109                 *address, mmio_str, sio_data->revision);
3110
3111         /* in7 (VSB or VCCH5V) is always internal on some chips */
3112         if (has_in7_internal(config))
3113                 sio_data->internal |= BIT(1);
3114
3115         /* in8 (Vbat) is always internal */
3116         sio_data->internal |= BIT(2);
3117
3118         /* in9 (AVCC3), always internal if supported */
3119         if (has_avcc3(config))
3120                 sio_data->internal |= BIT(3); /* in9 is AVCC */
3121         else
3122                 sio_data->skip_in |= BIT(9);
3123
3124         if (!has_four_pwm(config))
3125                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3126         else if (!has_five_pwm(config))
3127                 sio_data->skip_pwm |= BIT(4) | BIT(5);
3128         else if (!has_six_pwm(config))
3129                 sio_data->skip_pwm |= BIT(5);
3130
3131         if (!has_vid(config))
3132                 sio_data->skip_vid = 1;
3133
3134         /* Read GPIO config and VID value from LDN 7 (GPIO) */
3135         if (sio_data->type == it87) {
3136                 /* The IT8705F has a different LD number for GPIO */
3137                 superio_select(sioaddr, 5);
3138                 sio_data->beep_pin = superio_inb(sioaddr,
3139                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3140         } else if (sio_data->type == it8783) {
3141                 int reg25, reg27, reg2a, reg2c, regef;
3142
3143                 superio_select(sioaddr, GPIO);
3144
3145                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3146                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3147                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3148                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3149                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3150
3151                 /* Check if fan3 is there or not */
3152                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3153                         sio_data->skip_fan |= BIT(2);
3154                 if ((reg25 & BIT(4)) ||
3155                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
3156                         sio_data->skip_pwm |= BIT(2);
3157
3158                 /* Check if fan2 is there or not */
3159                 if (reg27 & BIT(7))
3160                         sio_data->skip_fan |= BIT(1);
3161                 if (reg27 & BIT(3))
3162                         sio_data->skip_pwm |= BIT(1);
3163
3164                 /* VIN5 */
3165                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3166                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3167
3168                 /* VIN6 */
3169                 if (reg27 & BIT(1))
3170                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3171
3172                 /*
3173                  * VIN7
3174                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3175                  */
3176                 if (reg27 & BIT(2)) {
3177                         /*
3178                          * The data sheet is a bit unclear regarding the
3179                          * internal voltage divider for VCCH5V. It says
3180                          * "This bit enables and switches VIN7 (pin 91) to the
3181                          * internal voltage divider for VCCH5V".
3182                          * This is different to other chips, where the internal
3183                          * voltage divider would connect VIN7 to an internal
3184                          * voltage source. Maybe that is the case here as well.
3185                          *
3186                          * Since we don't know for sure, re-route it if that is
3187                          * not the case, and ask the user to report if the
3188                          * resulting voltage is sane.
3189                          */
3190                         if (!(reg2c & BIT(1))) {
3191                                 reg2c |= BIT(1);
3192                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3193                                              reg2c);
3194                                 pr_notice("Routing internal VCCH5V to in7.\n");
3195                         }
3196                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3197                         pr_notice("Please report if it displays a reasonable voltage.\n");
3198                 }
3199
3200                 if (reg2c & BIT(0))
3201                         sio_data->internal |= BIT(0);
3202                 if (reg2c & BIT(1))
3203                         sio_data->internal |= BIT(1);
3204
3205                 sio_data->beep_pin = superio_inb(sioaddr,
3206                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3207         } else if (sio_data->type == it8603 || sio_data->type == it8606 ||
3208                    sio_data->type == it8607) {
3209                 int reg27, reg29;
3210
3211                 superio_select(sioaddr, GPIO);
3212
3213                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3214
3215                 /* Check if fan3 is there or not */
3216                 if (reg27 & BIT(6))
3217                         sio_data->skip_pwm |= BIT(2);
3218                 if (reg27 & BIT(7))
3219                         sio_data->skip_fan |= BIT(2);
3220
3221                 /* Check if fan2 is there or not */
3222                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3223                 if (reg29 & BIT(1))
3224                         sio_data->skip_pwm |= BIT(1);
3225                 if (reg29 & BIT(2))
3226                         sio_data->skip_fan |= BIT(1);
3227
3228                 switch (sio_data->type) {
3229                 case it8603:
3230                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3231                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3232                         break;
3233                 case it8607:
3234                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3235                         sio_data->skip_fan |= BIT(0);
3236                 default:
3237                         break;
3238                 }
3239
3240                 sio_data->beep_pin = superio_inb(sioaddr,
3241                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3242         } else if (sio_data->type == it8613) {
3243                 int reg27, reg29, reg2a;
3244
3245                 superio_select(sioaddr, GPIO);
3246
3247                 /* Check for pwm3, fan3, pwm5, fan5 */
3248                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3249                 if (reg27 & BIT(1))
3250                         sio_data->skip_fan |= BIT(4);
3251                 if (reg27 & BIT(3))
3252                         sio_data->skip_pwm |= BIT(4);
3253                 if (reg27 & BIT(6))
3254                         sio_data->skip_pwm |= BIT(2);
3255                 if (reg27 & BIT(7))
3256                         sio_data->skip_fan |= BIT(2);
3257
3258                 /* Check for pwm2, fan2 */
3259                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3260                 if (reg29 & BIT(1))
3261                         sio_data->skip_pwm |= BIT(1);
3262                 if (reg29 & BIT(2))
3263                         sio_data->skip_fan |= BIT(1);
3264
3265                 /* Check for pwm4, fan4 */
3266                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3267                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3268                         sio_data->skip_fan |= BIT(3);
3269                         sio_data->skip_pwm |= BIT(3);
3270                 }
3271
3272                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3273                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3274                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3275                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3276
3277                 sio_data->beep_pin = superio_inb(sioaddr,
3278                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3279         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3280                    sio_data->type == it8686) {
3281                 int reg;
3282
3283                 superio_select(sioaddr, GPIO);
3284
3285                 /* Check for pwm5 */
3286                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3287                 if (reg & BIT(6))
3288                         sio_data->skip_pwm |= BIT(4);
3289
3290                 /* Check for fan4, fan5 */
3291                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3292                 if (!(reg & BIT(5)))
3293                         sio_data->skip_fan |= BIT(3);
3294                 if (!(reg & BIT(4)))
3295                         sio_data->skip_fan |= BIT(4);
3296
3297                 /* Check for pwm3, fan3 */
3298                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3299                 if (reg & BIT(6))
3300                         sio_data->skip_pwm |= BIT(2);
3301                 if (reg & BIT(7))
3302                         sio_data->skip_fan |= BIT(2);
3303
3304                 /* Check for pwm4 */
3305                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3306                 if (reg & BIT(2))
3307                         sio_data->skip_pwm |= BIT(3);
3308
3309                 /* Check for pwm2, fan2 */
3310                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3311                 if (reg & BIT(1))
3312                         sio_data->skip_pwm |= BIT(1);
3313                 if (reg & BIT(2))
3314                         sio_data->skip_fan |= BIT(1);
3315                 /* Check for pwm6, fan6 */
3316                 if (!(reg & BIT(7))) {
3317                         sio_data->skip_pwm |= BIT(5);
3318                         sio_data->skip_fan |= BIT(5);
3319                 }
3320
3321                 /* Check if AVCC is on VIN3 */
3322                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3323                 if (reg & BIT(0)) {
3324                         /* For it8686, the bit just enables AVCC3 */
3325                         if (sio_data->type != it8686)
3326                                 sio_data->internal |= BIT(0);
3327                 } else {
3328                         sio_data->internal &= ~BIT(3);
3329                         sio_data->skip_in |= BIT(9);
3330                 }
3331
3332                 sio_data->beep_pin = superio_inb(sioaddr,
3333                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3334         } else if (sio_data->type == it8622) {
3335                 int reg;
3336
3337                 superio_select(sioaddr, GPIO);
3338
3339                 /* Check for pwm4, fan4 */
3340                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3341                 if (reg & BIT(6))
3342                         sio_data->skip_fan |= BIT(3);
3343                 if (reg & BIT(5))
3344                         sio_data->skip_pwm |= BIT(3);
3345
3346                 /* Check for pwm3, fan3, pwm5, fan5 */
3347                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3348                 if (reg & BIT(6))
3349                         sio_data->skip_pwm |= BIT(2);
3350                 if (reg & BIT(7))
3351                         sio_data->skip_fan |= BIT(2);
3352                 if (reg & BIT(3))
3353                         sio_data->skip_pwm |= BIT(4);
3354                 if (reg & BIT(1))
3355                         sio_data->skip_fan |= BIT(4);
3356
3357                 /* Check for pwm2, fan2 */
3358                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3359                 if (reg & BIT(1))
3360                         sio_data->skip_pwm |= BIT(1);
3361                 if (reg & BIT(2))
3362                         sio_data->skip_fan |= BIT(1);
3363
3364                 /* Check for AVCC */
3365                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3366                 if (!(reg & BIT(0)))
3367                         sio_data->skip_in |= BIT(9);
3368
3369                 sio_data->beep_pin = superio_inb(sioaddr,
3370                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3371         } else if (sio_data->type == it8732) {
3372                 int reg;
3373
3374                 superio_select(sioaddr, GPIO);
3375
3376                 /* Check for pwm2, fan2 */
3377                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3378                 if (reg & BIT(1))
3379                         sio_data->skip_pwm |= BIT(1);
3380                 if (reg & BIT(2))
3381                         sio_data->skip_fan |= BIT(1);
3382
3383                 /* Check for pwm3, fan3, fan4 */
3384                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3385                 if (reg & BIT(6))
3386                         sio_data->skip_pwm |= BIT(2);
3387                 if (reg & BIT(7))
3388                         sio_data->skip_fan |= BIT(2);
3389                 if (reg & BIT(5))
3390                         sio_data->skip_fan |= BIT(3);
3391
3392                 /* Check if AVCC is on VIN3 */
3393                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3394                 if (reg & BIT(0))
3395                         sio_data->internal |= BIT(0);
3396
3397                 sio_data->beep_pin = superio_inb(sioaddr,
3398                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3399         } else if (sio_data->type == it8655) {
3400                 int reg;
3401
3402                 superio_select(sioaddr, GPIO);
3403
3404                 /* Check for pwm2 */
3405                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3406                 if (reg & BIT(1))
3407                         sio_data->skip_pwm |= BIT(1);
3408
3409                 /* Check for fan2 */
3410                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3411                 if (reg & BIT(4))
3412                         sio_data->skip_fan |= BIT(1);
3413
3414                 /* Check for pwm3, fan3 */
3415                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3416                 if (reg & BIT(6))
3417                         sio_data->skip_pwm |= BIT(2);
3418                 if (reg & BIT(7))
3419                         sio_data->skip_fan |= BIT(2);
3420
3421                 sio_data->beep_pin = superio_inb(sioaddr,
3422                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3423         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3424                 int reg27, reg29, reg2d, regd3;
3425
3426                 superio_select(sioaddr, GPIO);
3427
3428                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3429                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3430                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3431                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3432
3433                 /* Check for pwm2, fan2 */
3434                 if (reg29 & BIT(1))
3435                         sio_data->skip_pwm |= BIT(1);
3436                 /*
3437                  * Note: Table 6-1 in datasheet claims that FAN_TAC2
3438                  * would be enabled with 29h[2]=0.
3439                  */
3440                 if (reg2d & BIT(4))
3441                         sio_data->skip_fan |= BIT(1);
3442
3443                 /* Check for pwm3, fan3 */
3444                 if (reg27 & BIT(6))
3445                         sio_data->skip_pwm |= BIT(2);
3446                 if (reg27 & BIT(7))
3447                         sio_data->skip_fan |= BIT(2);
3448
3449                 /* Check for pwm4, fan4, pwm5, fan5 */
3450                 if (sio_data->type == it8625) {
3451                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3452
3453                         if (reg25 & BIT(6))
3454                                 sio_data->skip_fan |= BIT(3);
3455                         if (reg25 & BIT(5))
3456                                 sio_data->skip_pwm |= BIT(3);
3457                         if (reg27 & BIT(3))
3458                                 sio_data->skip_pwm |= BIT(4);
3459                         if (reg27 & BIT(1))
3460                                 sio_data->skip_fan |= BIT(4);
3461                 } else {
3462                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3463
3464                         if (regd3 & BIT(2))
3465                                 sio_data->skip_pwm |= BIT(3);
3466                         if (regd3 & BIT(3))
3467                                 sio_data->skip_fan |= BIT(3);
3468                         if (reg26 & BIT(5))
3469                                 sio_data->skip_pwm |= BIT(4);
3470                         if (reg26 & BIT(4))
3471                                 sio_data->skip_fan |= BIT(4);
3472                 }
3473
3474                 /* Check for pwm6, fan6 */
3475                 if (regd3 & BIT(0))
3476                         sio_data->skip_pwm |= BIT(5);
3477                 if (regd3 & BIT(1))
3478                         sio_data->skip_fan |= BIT(5);
3479
3480                 sio_data->beep_pin = superio_inb(sioaddr,
3481                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3482         } else {
3483                 int reg;
3484                 bool uart6;
3485
3486                 superio_select(sioaddr, GPIO);
3487
3488                 /* Check for fan4, fan5 */
3489                 if (has_five_fans(config)) {
3490                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3491                         switch (sio_data->type) {
3492                         case it8718:
3493                                 if (reg & BIT(5))
3494                                         sio_data->skip_fan |= BIT(3);
3495                                 if (reg & BIT(4))
3496                                         sio_data->skip_fan |= BIT(4);
3497                                 break;
3498                         case it8720:
3499                         case it8721:
3500                         case it8728:
3501                                 if (!(reg & BIT(5)))
3502                                         sio_data->skip_fan |= BIT(3);
3503                                 if (!(reg & BIT(4)))
3504                                         sio_data->skip_fan |= BIT(4);
3505                                 break;
3506                         default:
3507                                 break;
3508                         }
3509                 }
3510
3511                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3512                 if (!sio_data->skip_vid) {
3513                         /* We need at least 4 VID pins */
3514                         if (reg & 0x0f) {
3515                                 pr_info("VID is disabled (pins used for GPIO)\n");
3516                                 sio_data->skip_vid = 1;
3517                         }
3518                 }
3519
3520                 /* Check if fan3 is there or not */
3521                 if (reg & BIT(6))
3522                         sio_data->skip_pwm |= BIT(2);
3523                 if (reg & BIT(7))
3524                         sio_data->skip_fan |= BIT(2);
3525
3526                 /* Check if fan2 is there or not */
3527                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3528                 if (reg & BIT(1))
3529                         sio_data->skip_pwm |= BIT(1);
3530                 if (reg & BIT(2))
3531                         sio_data->skip_fan |= BIT(1);
3532
3533                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3534                     !(sio_data->skip_vid))
3535                         sio_data->vid_value = superio_inb(sioaddr,
3536                                                           IT87_SIO_VID_REG);
3537
3538                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3539
3540                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3541
3542                 /*
3543                  * The IT8720F has no VIN7 pin, so VCCH should always be
3544                  * routed internally to VIN7 with an internal divider.
3545                  * Curiously, there still is a configuration bit to control
3546                  * this, which means it can be set incorrectly. And even
3547                  * more curiously, many boards out there are improperly
3548                  * configured, even though the IT8720F datasheet claims
3549                  * that the internal routing of VCCH to VIN7 is the default
3550                  * setting. So we force the internal routing in this case.
3551                  *
3552                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3553                  * If UART6 is enabled, re-route VIN7 to the internal divider
3554                  * if that is not already the case.
3555                  */
3556                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3557                         reg |= BIT(1);
3558                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3559                         pr_notice("Routing internal VCCH to in7\n");
3560                 }
3561                 if (reg & BIT(0))
3562                         sio_data->internal |= BIT(0);
3563                 if (reg & BIT(1))
3564                         sio_data->internal |= BIT(1);
3565
3566                 /*
3567                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3568                  * While VIN7 can be routed to the internal voltage divider,
3569                  * VIN5 and VIN6 are not available if UART6 is enabled.
3570                  *
3571                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3572                  * is the temperature source. Since we can not read the
3573                  * temperature source here, skip_temp is preliminary.
3574                  */
3575                 if (uart6) {
3576                         sio_data->skip_in |= BIT(5) | BIT(6);
3577                         sio_data->skip_temp |= BIT(2);
3578                 }
3579
3580                 sio_data->beep_pin = superio_inb(sioaddr,
3581                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3582         }
3583         if (sio_data->beep_pin)
3584                 pr_info("Beeping is supported\n");
3585
3586         if (config->smbus_bitmap && !base) {
3587                 u8 reg;
3588
3589                 superio_select(sioaddr, PME);
3590                 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3591                 sio_data->ec_special_config = reg;
3592                 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3593         }
3594
3595 exit:
3596         superio_exit(sioaddr, doexit);
3597         return err;
3598 }
3599
3600 static void it87_init_regs(struct platform_device *pdev)
3601 {
3602         struct it87_data *data = platform_get_drvdata(pdev);
3603
3604         /* Initialize chip specific register pointers */
3605         switch (data->type) {
3606         case it8628:
3607         case it8686:
3608                 data->REG_FAN = IT87_REG_FAN;
3609                 data->REG_FANX = IT87_REG_FANX;
3610                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3611                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3612                 data->REG_PWM = IT87_REG_PWM;
3613                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3614                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3615                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3616                 break;
3617         case it8625:
3618         case it8655:
3619         case it8665:
3620                 data->REG_FAN = IT87_REG_FAN_8665;
3621                 data->REG_FANX = IT87_REG_FANX_8665;
3622                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3623                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3624                 data->REG_PWM = IT87_REG_PWM_8665;
3625                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3626                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3627                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3628                 break;
3629         case it8622:
3630                 data->REG_FAN = IT87_REG_FAN;
3631                 data->REG_FANX = IT87_REG_FANX;
3632                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3633                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3634                 data->REG_PWM = IT87_REG_PWM_8665;
3635                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3636                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3637                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3638                 break;
3639         case it8613:
3640                 data->REG_FAN = IT87_REG_FAN;
3641                 data->REG_FANX = IT87_REG_FANX;
3642                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3643                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3644                 data->REG_PWM = IT87_REG_PWM_8665;
3645                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3646                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3647                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3648                 break;
3649         default:
3650                 data->REG_FAN = IT87_REG_FAN;
3651                 data->REG_FANX = IT87_REG_FANX;
3652                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3653                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3654                 data->REG_PWM = IT87_REG_PWM;
3655                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3656                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3657                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3658                 break;
3659         }
3660
3661         if (data->mmio) {
3662                 data->read = it87_mmio_read;
3663                 data->write = it87_mmio_write;
3664         } else if (has_bank_sel(data)) {
3665                 data->read = it87_io_read;
3666                 data->write = it87_io_write;
3667         } else {
3668                 data->read = _it87_io_read;
3669                 data->write = _it87_io_write;
3670         }
3671 }
3672
3673 /* Called when we have found a new IT87. */
3674 static void it87_init_device(struct platform_device *pdev)
3675 {
3676         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3677         struct it87_data *data = platform_get_drvdata(pdev);
3678         int tmp, i;
3679         u8 mask;
3680
3681         if (has_new_tempmap(data)) {
3682                 data->pwm_temp_map_shift = 3;
3683                 data->pwm_temp_map_mask = 0x07;
3684         } else {
3685                 data->pwm_temp_map_shift = 0;
3686                 data->pwm_temp_map_mask = 0x03;
3687         }
3688
3689         /*
3690          * For each PWM channel:
3691          * - If it is in automatic mode, setting to manual mode should set
3692          *   the fan to full speed by default.
3693          * - If it is in manual mode, we need a mapping to temperature
3694          *   channels to use when later setting to automatic mode later.
3695          *   Map to the first sensor by default (we are clueless.)
3696          * In both cases, the value can (and should) be changed by the user
3697          * prior to switching to a different mode.
3698          * Note that this is no longer needed for the IT8721F and later, as
3699          * these have separate registers for the temperature mapping and the
3700          * manual duty cycle.
3701          */
3702         for (i = 0; i < NUM_AUTO_PWM; i++) {
3703                 data->pwm_temp_map[i] = 0;
3704                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3705                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3706         }
3707
3708         /*
3709          * Some chips seem to have default value 0xff for all limit
3710          * registers. For low voltage limits it makes no sense and triggers
3711          * alarms, so change to 0 instead. For high temperature limits, it
3712          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3713          * but is still confusing, so change to 127 degrees C.
3714          */
3715         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3716                 tmp = data->read(data, IT87_REG_VIN_MIN(i));
3717                 if (tmp == 0xff)
3718                         data->write(data, IT87_REG_VIN_MIN(i), 0);
3719         }
3720         for (i = 0; i < data->num_temp_limit; i++) {
3721                 tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3722                 if (tmp == 0xff)
3723                         data->write(data, data->REG_TEMP_HIGH[i], 127);
3724         }
3725
3726         /*
3727          * Temperature channels are not forcibly enabled, as they can be
3728          * set to two different sensor types and we can't guess which one
3729          * is correct for a given system. These channels can be enabled at
3730          * run-time through the temp{1-3}_type sysfs accessors if needed.
3731          */
3732
3733         /* Check if voltage monitors are reset manually or by some reason */
3734         tmp = data->read(data, IT87_REG_VIN_ENABLE);
3735         if ((tmp & 0xff) == 0) {
3736                 /* Enable all voltage monitors */
3737                 data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3738         }
3739
3740         /* Check if tachometers are reset manually or by some reason */
3741         mask = 0x70 & ~(sio_data->skip_fan << 4);
3742         data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3743         if ((data->fan_main_ctrl & mask) == 0) {
3744                 /* Enable all fan tachometers */
3745                 data->fan_main_ctrl |= mask;
3746                 data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3747         }
3748         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3749
3750         tmp = data->read(data, IT87_REG_FAN_16BIT);
3751
3752         /* Set tachometers to 16-bit mode if needed */
3753         if (has_fan16_config(data)) {
3754                 if (~tmp & 0x07 & data->has_fan) {
3755                         dev_dbg(&pdev->dev,
3756                                 "Setting fan1-3 to 16-bit mode\n");
3757                         data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3758                 }
3759         }
3760
3761         /* Check for additional fans */
3762         if (has_four_fans(data) && (tmp & BIT(4)))
3763                 data->has_fan |= BIT(3); /* fan4 enabled */
3764         if (has_five_fans(data) && (tmp & BIT(5)))
3765                 data->has_fan |= BIT(4); /* fan5 enabled */
3766         if (has_six_fans(data)) {
3767                 switch (data->type) {
3768                 case it8620:
3769                 case it8628:
3770                 case it8686:
3771                         if (tmp & BIT(2))
3772                                 data->has_fan |= BIT(5); /* fan6 enabled */
3773                         break;
3774                 case it8625:
3775                 case it8665:
3776                         tmp = data->read(data, IT87_REG_FAN_DIV);
3777                         if (tmp & BIT(3))
3778                                 data->has_fan |= BIT(5); /* fan6 enabled */
3779                         break;
3780                 default:
3781                         break;
3782                 }
3783         }
3784
3785         /* Fan input pins may be used for alternative functions */
3786         data->has_fan &= ~sio_data->skip_fan;
3787
3788         /* Check if pwm6 is enabled */
3789         if (has_six_pwm(data)) {
3790                 switch (data->type) {
3791                 case it8620:
3792                 case it8686:
3793                         tmp = data->read(data, IT87_REG_FAN_DIV);
3794                         if (!(tmp & BIT(3)))
3795                                 sio_data->skip_pwm |= BIT(5);
3796                         break;
3797                 default:
3798                         break;
3799                 }
3800         }
3801
3802         if (has_bank_sel(data)) {
3803                 for (i = 0; i < 3; i++)
3804                         data->temp_src[i] =
3805                                 data->read(data, IT87_REG_TEMP_SRC1[i]);
3806                 data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3807         }
3808
3809         /* Start monitoring */
3810         data->write(data, IT87_REG_CONFIG,
3811                     (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3812                                         (update_vbat ? 0x41 : 0x01));
3813 }
3814
3815 /* Return 1 if and only if the PWM interface is safe to use */
3816 static int it87_check_pwm(struct device *dev)
3817 {
3818         struct it87_data *data = dev_get_drvdata(dev);
3819         /*
3820          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3821          * and polarity set to active low is sign that this is the case so we
3822          * disable pwm control to protect the user.
3823          */
3824         int tmp = data->read(data, IT87_REG_FAN_CTL);
3825
3826         if ((tmp & 0x87) == 0) {
3827                 if (fix_pwm_polarity) {
3828                         /*
3829                          * The user asks us to attempt a chip reconfiguration.
3830                          * This means switching to active high polarity and
3831                          * inverting all fan speed values.
3832                          */
3833                         int i;
3834                         u8 pwm[3];
3835
3836                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3837                                 pwm[i] = data->read(data,
3838                                                          data->REG_PWM[i]);
3839
3840                         /*
3841                          * If any fan is in automatic pwm mode, the polarity
3842                          * might be correct, as suspicious as it seems, so we
3843                          * better don't change anything (but still disable the
3844                          * PWM interface).
3845                          */
3846                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3847                                 dev_info(dev,
3848                                          "Reconfiguring PWM to active high polarity\n");
3849                                 data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3850                                 for (i = 0; i < 3; i++)
3851                                         data->write(data, data->REG_PWM[i],
3852                                                     0x7f & ~pwm[i]);
3853                                 return 1;
3854                         }
3855
3856                         dev_info(dev,
3857                                  "PWM configuration is too broken to be fixed\n");
3858                 }
3859
3860                 dev_info(dev,
3861                          "Detected broken BIOS defaults, disabling PWM interface\n");
3862                 return 0;
3863         } else if (fix_pwm_polarity) {
3864                 dev_info(dev,
3865                          "PWM configuration looks sane, won't touch\n");
3866         }
3867
3868         return 1;
3869 }
3870
3871 static int it87_probe(struct platform_device *pdev)
3872 {
3873         struct it87_data *data;
3874         struct resource *res;
3875         struct device *dev = &pdev->dev;
3876         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3877         int enable_pwm_interface;
3878         struct device *hwmon_dev;
3879         int err;
3880
3881         data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3882         if (!data)
3883                 return -ENOMEM;
3884
3885         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3886         if (res) {
3887                 if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3888                                          DRVNAME)) {
3889                         dev_err(dev, "Failed to request region %pR\n", res);
3890                         return -EBUSY;
3891                 }
3892         } else {
3893                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3894                 data->mmio = devm_ioremap_resource(dev, res);
3895                 if (IS_ERR(data->mmio))
3896                         return PTR_ERR(data->mmio);
3897         }
3898
3899         data->addr = res->start;
3900         data->type = sio_data->type;
3901         data->sioaddr = sio_data->sioaddr;
3902         data->smbus_bitmap = sio_data->smbus_bitmap;
3903         data->ec_special_config = sio_data->ec_special_config;
3904         data->doexit = sio_data->doexit;
3905         data->features = it87_devices[sio_data->type].features;
3906         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3907         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3908         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3909         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3910         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3911
3912         /*
3913          * IT8705F Datasheet 0.4.1, 3h == Version G.
3914          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3915          * These are the first revisions with 16-bit tachometer support.
3916          */
3917         switch (data->type) {
3918         case it87:
3919                 if (sio_data->revision >= 0x03) {
3920                         data->features &= ~FEAT_OLD_AUTOPWM;
3921                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3922                 }
3923                 break;
3924         case it8712:
3925                 if (sio_data->revision >= 0x08) {
3926                         data->features &= ~FEAT_OLD_AUTOPWM;
3927                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3928                                           FEAT_FIVE_FANS;
3929                 }
3930                 break;
3931         default:
3932                 break;
3933         }
3934
3935         platform_set_drvdata(pdev, data);
3936
3937         mutex_init(&data->update_lock);
3938
3939         /* Initialize register pointers */
3940         it87_init_regs(pdev);
3941
3942         err = smbus_disable(data);
3943         if (err)
3944                 return err;
3945
3946         /* Now, we do the remaining detection. */
3947         if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
3948             data->read(data, IT87_REG_CHIPID) != 0x90) {
3949                 smbus_enable(data);
3950                 return -ENODEV;
3951         }
3952
3953         /* Check PWM configuration */
3954         enable_pwm_interface = it87_check_pwm(dev);
3955
3956         /* Starting with IT8721F, we handle scaling of internal voltages */
3957         if (has_scaling(data)) {
3958                 if (sio_data->internal & BIT(0))
3959                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3960                 if (sio_data->internal & BIT(1))
3961                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3962                 if (sio_data->internal & BIT(2))
3963                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3964                 if (sio_data->internal & BIT(3))
3965                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3966         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3967                    sio_data->type == it8783) {
3968                 if (sio_data->internal & BIT(0))
3969                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3970                 if (sio_data->internal & BIT(1))
3971                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3972         }
3973
3974         data->has_temp = 0x07;
3975         if (sio_data->skip_temp & BIT(2)) {
3976                 if (sio_data->type == it8782 &&
3977                     !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
3978                         data->has_temp &= ~BIT(2);
3979         }
3980
3981         data->in_internal = sio_data->internal;
3982         data->has_in = 0x3ff & ~sio_data->skip_in;
3983
3984         if (has_four_temp(data)) {
3985                 data->has_temp |= BIT(3);
3986         } else if (has_six_temp(data)) {
3987                 u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
3988
3989                 /* Check for additional temperature sensors */
3990                 if ((reg & 0x03) >= 0x02)
3991                         data->has_temp |= BIT(3);
3992                 if (((reg >> 2) & 0x03) >= 0x02)
3993                         data->has_temp |= BIT(4);
3994                 if (((reg >> 4) & 0x03) >= 0x02)
3995                         data->has_temp |= BIT(5);
3996
3997                 /* Check for additional voltage sensors */
3998                 if ((reg & 0x03) == 0x01)
3999                         data->has_in |= BIT(10);
4000                 if (((reg >> 2) & 0x03) == 0x01)
4001                         data->has_in |= BIT(11);
4002                 if (((reg >> 4) & 0x03) == 0x01)
4003                         data->has_in |= BIT(12);
4004         }
4005
4006         data->has_beep = !!sio_data->beep_pin;
4007
4008         /* Initialize the IT87 chip */
4009         it87_init_device(pdev);
4010
4011         smbus_enable(data);
4012
4013         if (!sio_data->skip_vid) {
4014                 data->has_vid = true;
4015                 data->vrm = vid_which_vrm();
4016                 /* VID reading from Super-I/O config space if available */
4017                 data->vid = sio_data->vid_value;
4018         }
4019
4020         /* Prepare for sysfs hooks */
4021         data->groups[0] = &it87_group;
4022         data->groups[1] = &it87_group_in;
4023         data->groups[2] = &it87_group_temp;
4024         data->groups[3] = &it87_group_fan;
4025
4026         if (enable_pwm_interface) {
4027                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
4028                 data->has_pwm &= ~sio_data->skip_pwm;
4029
4030                 data->groups[4] = &it87_group_pwm;
4031                 if (has_old_autopwm(data) || has_newer_autopwm(data))
4032                         data->groups[5] = &it87_group_auto_pwm;
4033         }
4034
4035         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
4036                                         it87_devices[sio_data->type].name,
4037                                         data, data->groups);
4038         return PTR_ERR_OR_ZERO(hwmon_dev);
4039 }
4040
4041 static struct platform_driver it87_driver = {
4042         .driver = {
4043                 .name   = DRVNAME,
4044         },
4045         .probe  = it87_probe,
4046 };
4047
4048 static int __init it87_device_add(int index, unsigned short sio_address,
4049                                   phys_addr_t mmio_address,
4050                                   const struct it87_sio_data *sio_data)
4051 {
4052         struct platform_device *pdev;
4053         struct resource res = {
4054                 .name   = DRVNAME,
4055         };
4056         int err;
4057
4058         if (mmio_address) {
4059                 res.start = mmio_address;
4060                 res.end = mmio_address + 0x400 - 1;
4061                 res.flags = IORESOURCE_MEM;
4062         } else {
4063                 res.start = sio_address + IT87_EC_OFFSET;
4064                 res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
4065                 res.flags = IORESOURCE_IO;
4066         }
4067
4068         err = acpi_check_resource_conflict(&res);
4069         if (err) {
4070                 if (!ignore_resource_conflict)
4071                         return err;
4072         }
4073
4074         pdev = platform_device_alloc(DRVNAME, sio_address);
4075         if (!pdev)
4076                 return -ENOMEM;
4077
4078         err = platform_device_add_resources(pdev, &res, 1);
4079         if (err) {
4080                 pr_err("Device resource addition failed (%d)\n", err);
4081                 goto exit_device_put;
4082         }
4083
4084         err = platform_device_add_data(pdev, sio_data,
4085                                        sizeof(struct it87_sio_data));
4086         if (err) {
4087                 pr_err("Platform data allocation failed\n");
4088                 goto exit_device_put;
4089         }
4090
4091         err = platform_device_add(pdev);
4092         if (err) {
4093                 pr_err("Device addition failed (%d)\n", err);
4094                 goto exit_device_put;
4095         }
4096
4097         it87_pdev[index] = pdev;
4098         return 0;
4099
4100 exit_device_put:
4101         platform_device_put(pdev);
4102         return err;
4103 }
4104
4105 struct it87_dmi_data {
4106         bool sio2_force_config; /* force sio2 into configuration mode   */
4107         u8 skip_pwm;            /* pwm channels to skip for this board  */
4108 };
4109
4110 /*
4111  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4112  * (IT8792E) needs to be in configuration mode before accessing the first
4113  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4114  * This needs to be done before accessing the first Super-IO chip since
4115  * the second chip may have been accessed prior to loading this driver.
4116  *
4117  * The problem is also reported to affect IT8795E, which is used on X299 boards
4118  * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4119  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4120  * Z87X-OC.
4121  * DMI entries for those systems will be added as they become available and
4122  * as the problem is confirmed to affect those boards.
4123  */
4124 static struct it87_dmi_data gigabyte_sio2_force = {
4125         .sio2_force_config = true,
4126 };
4127
4128 /*
4129  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4130  * connected to a fan, but to something else. One user
4131  * has reported instant system power-off when changing
4132  * the PWM2 duty cycle, so we disable it.
4133  * I use the board name string as the trigger in case
4134  * the same board is ever used in other systems.
4135  */
4136 static struct it87_dmi_data nvidia_fn68pt = {
4137         .skip_pwm = BIT(1),
4138 };
4139
4140 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4141         {
4142                 .matches = {
4143                         DMI_MATCH(DMI_SYS_VENDOR,
4144                                   "Gigabyte Technology Co., Ltd."),
4145                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4146                 },
4147                 .driver_data = &gigabyte_sio2_force,
4148         },
4149         {
4150                 .matches = {
4151                         DMI_MATCH(DMI_SYS_VENDOR,
4152                                   "Gigabyte Technology Co., Ltd."),
4153                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4154                 },
4155                 .driver_data = &gigabyte_sio2_force,
4156         },
4157         {
4158                 .matches = {
4159                         DMI_MATCH(DMI_SYS_VENDOR,
4160                                   "Gigabyte Technology Co., Ltd."),
4161                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4162                 },
4163                 .driver_data = &gigabyte_sio2_force,
4164         },
4165         {
4166                 .matches = {
4167                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4168                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4169                 },
4170                 .driver_data = &nvidia_fn68pt,
4171         },
4172         { }
4173 };
4174
4175 static int __init sm_it87_init(void)
4176 {
4177         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4178         struct it87_dmi_data *dmi_data = NULL;
4179         int sioaddr[2] = { REG_2E, REG_4E };
4180         struct it87_sio_data sio_data;
4181         unsigned short isa_address;
4182         phys_addr_t mmio_address;
4183         bool found = false;
4184         int i, err;
4185
4186         pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4187
4188         if (dmi)
4189                 dmi_data = dmi->driver_data;
4190
4191         err = platform_driver_register(&it87_driver);
4192         if (err)
4193                 return err;
4194
4195         if (dmi_data && dmi_data->sio2_force_config)
4196                 __superio_enter(REG_4E);
4197
4198         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4199                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4200                 isa_address = 0;
4201                 mmio_address = 0;
4202                 err = it87_find(sioaddr[i], &isa_address, &mmio_address,
4203                                 &sio_data);
4204                 if (err || isa_address == 0)
4205                         continue;
4206
4207                 if (dmi_data)
4208                         sio_data.skip_pwm |= dmi_data->skip_pwm;
4209                 err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4210                 if (err)
4211                         goto exit_dev_unregister;
4212                 found = true;
4213         }
4214
4215         if (!found) {
4216                 err = -ENODEV;
4217                 goto exit_unregister;
4218         }
4219         return 0;
4220
4221 exit_dev_unregister:
4222         /* NULL check handled by platform_device_unregister */
4223         platform_device_unregister(it87_pdev[0]);
4224 exit_unregister:
4225         platform_driver_unregister(&it87_driver);
4226         return err;
4227 }
4228
4229 static void __exit sm_it87_exit(void)
4230 {
4231         /* NULL check handled by platform_device_unregister */
4232         platform_device_unregister(it87_pdev[1]);
4233         platform_device_unregister(it87_pdev[0]);
4234         platform_driver_unregister(&it87_driver);
4235 }
4236
4237 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4238 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4239 module_param(update_vbat, bool, 0000);
4240 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4241 module_param(fix_pwm_polarity, bool, 0000);
4242 MODULE_PARM_DESC(fix_pwm_polarity,
4243                  "Force PWM polarity to active high (DANGEROUS)");
4244 MODULE_LICENSE("GPL");
4245
4246 module_init(sm_it87_init);
4247 module_exit(sm_it87_exit);