git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77 #include "version.h"
  78
  79 #define DRVNAME "it87"
  80
  81 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  82              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  83              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  84              it8655, it8665, it8686 };
  85
  86 static unsigned short force_id;
  87 module_param(force_id, ushort, 0);
  88 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  89
  90 static bool ignore_resource_conflict;
  91 module_param(ignore_resource_conflict, bool, 0);
  92 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
  93
  94 static bool mmio;
  95 module_param(mmio, bool, 0);
  96 MODULE_PARM_DESC(mmio, "Use MMIO if available");
  97
  98 static struct platform_device *it87_pdev[2];
  99
 100 #define REG_2E  0x2e    /* The register to read/write */
 101 #define REG_4E  0x4e    /* Secondary register to read/write */
 102
 103 #define DEV     0x07    /* Register: Logical device select */
 104 #define PME     0x04    /* The device with the fan registers in it */
 105
 106 /* The device with the IT8718F/IT8720F VID value in it */
 107 #define GPIO    0x07
 108
 109 #define DEVID   0x20    /* Register: Device ID */
 110 #define DEVREV  0x22    /* Register: Device Revision */
 111
 112 static inline void __superio_enter(int ioreg)
 113 {
 114         outb(0x87, ioreg);
 115         outb(0x01, ioreg);
 116         outb(0x55, ioreg);
 117         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 118 }
 119
 120 static inline int superio_inb(int ioreg, int reg)
 121 {
 122         int val;
 123
 124         outb(reg, ioreg);
 125         val = inb(ioreg + 1);
 126
 127         return val;
 128 }
 129
 130 static inline void superio_outb(int ioreg, int reg, int val)
 131 {
 132         outb(reg, ioreg);
 133         outb(val, ioreg + 1);
 134 }
 135
 136 static int superio_inw(int ioreg, int reg)
 137 {
 138         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 139 }
 140
 141 static inline void superio_select(int ioreg, int ldn)
 142 {
 143         outb(DEV, ioreg);
 144         outb(ldn, ioreg + 1);
 145 }
 146
 147 static inline int superio_enter(int ioreg)
 148 {
 149         /*
 150          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 151          */
 152         if (!request_muxed_region(ioreg, 2, DRVNAME))
 153                 return -EBUSY;
 154
 155         __superio_enter(ioreg);
 156         return 0;
 157 }
 158
 159 static inline void superio_exit(int ioreg, bool doexit)
 160 {
 161         if (doexit) {
 162                 outb(0x02, ioreg);
 163                 outb(0x02, ioreg + 1);
 164         }
 165         release_region(ioreg, 2);
 166 }
 167
 168 /* Logical device 4 registers */
 169 #define IT8712F_DEVID 0x8712
 170 #define IT8705F_DEVID 0x8705
 171 #define IT8716F_DEVID 0x8716
 172 #define IT8718F_DEVID 0x8718
 173 #define IT8720F_DEVID 0x8720
 174 #define IT8721F_DEVID 0x8721
 175 #define IT8726F_DEVID 0x8726
 176 #define IT8728F_DEVID 0x8728
 177 #define IT8732F_DEVID 0x8732
 178 #define IT8792E_DEVID 0x8733
 179 #define IT8771E_DEVID 0x8771
 180 #define IT8772E_DEVID 0x8772
 181 #define IT8781F_DEVID 0x8781
 182 #define IT8782F_DEVID 0x8782
 183 #define IT8783E_DEVID 0x8783
 184 #define IT8786E_DEVID 0x8786
 185 #define IT8790E_DEVID 0x8790
 186 #define IT8603E_DEVID 0x8603
 187 #define IT8607E_DEVID 0x8607
 188 #define IT8613E_DEVID 0x8613
 189 #define IT8620E_DEVID 0x8620
 190 #define IT8622E_DEVID 0x8622
 191 #define IT8623E_DEVID 0x8623
 192 #define IT8625E_DEVID 0x8625
 193 #define IT8628E_DEVID 0x8628
 194 #define IT8655E_DEVID 0x8655
 195 #define IT8665E_DEVID 0x8665
 196 #define IT8686E_DEVID 0x8686
 197
 198 /* Logical device 4 (Environmental Monitor) registers */
 199 #define IT87_ACT_REG            0x30
 200 #define IT87_BASE_REG           0x60
 201 #define IT87_SPECIAL_CFG_REG    0xf3    /* special configuration register */
 202
 203 /* Global configuration registers (IT8712F and later) */
 204 #define IT87_EC_HWM_MIO_REG     0x24    /* MMIO configuration register */
 205 #define IT87_SIO_GPIO1_REG      0x25
 206 #define IT87_SIO_GPIO2_REG      0x26
 207 #define IT87_SIO_GPIO3_REG      0x27
 208 #define IT87_SIO_GPIO4_REG      0x28
 209 #define IT87_SIO_GPIO5_REG      0x29
 210 #define IT87_SIO_GPIO9_REG      0xd3
 211 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 212 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 213 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 214
 215 /* Logical device 7 (GPIO) registers (IT8712F and later) */
 216 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 217 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 218 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 219
 220 /* Update battery voltage after every reading if true */
 221 static bool update_vbat;
 222
 223 /* Not all BIOSes properly configure the PWM registers */
 224 static bool fix_pwm_polarity;
 225
 226 /* Many IT87 constants specified below */
 227
 228 /* Length of ISA address segment */
 229 #define IT87_EXTENT 8
 230
 231 /* Length of ISA address segment for Environmental Controller */
 232 #define IT87_EC_EXTENT 2
 233
 234 /* Offset of EC registers from ISA base address */
 235 #define IT87_EC_OFFSET 5
 236
 237 /* Where are the ISA address/data registers relative to the EC base address */
 238 #define IT87_ADDR_REG_OFFSET 0
 239 #define IT87_DATA_REG_OFFSET 1
 240
 241 /*----- The IT87 registers -----*/
 242
 243 #define IT87_REG_CONFIG        0x00
 244
 245 #define IT87_REG_ALARM1        0x01
 246 #define IT87_REG_ALARM2        0x02
 247 #define IT87_REG_ALARM3        0x03
 248
 249 #define IT87_REG_BANK           0x06
 250
 251 /*
 252  * The IT8718F and IT8720F have the VID value in a different register, in
 253  * Super-I/O configuration space.
 254  */
 255 #define IT87_REG_VID           0x0a
 256 /*
 257  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 258  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 259  * mode.
 260  */
 261 #define IT87_REG_FAN_DIV       0x0b
 262 #define IT87_REG_FAN_16BIT     0x0c
 263
 264 /*
 265  * Monitors:
 266  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 267  * - up to 6 temp (1 to 6)
 268  * - up to 6 fan (1 to 6)
 269  */
 270
 271 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 272 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 273 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 274 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 275
 276 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 277 static const u8 IT87_REG_FAN_MIN_8665[] =
 278                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 279 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 280 static const u8 IT87_REG_FANX_MIN_8665[] =
 281                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 282
 283 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 284
 285 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 286
 287 #define IT87_REG_FAN_MAIN_CTRL 0x13
 288 #define IT87_REG_FAN_CTL       0x14
 289
 290 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 291 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 292
 293 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 294
 295 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 296                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 297
 298 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 299
 300 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 301 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 302
 303 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 304 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 305
 306 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 307                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 308 static const u8 IT87_REG_TEMP_LOW_8686[] =
 309                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 310
 311 #define IT87_REG_VIN_ENABLE    0x50
 312 #define IT87_REG_TEMP_ENABLE   0x51
 313 #define IT87_REG_TEMP_EXTRA    0x55
 314 #define IT87_REG_BEEP_ENABLE   0x5c
 315
 316 #define IT87_REG_CHIPID        0x58
 317
 318 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 319
 320 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 321 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 322
 323 #define IT87_REG_TEMP456_ENABLE 0x77
 324
 325 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 326 #define IT87_REG_TEMP_SRC2      0x23d
 327
 328 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 329 #define NUM_VIN_LIMIT           8
 330 #define NUM_TEMP                6
 331 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 332 #define NUM_FAN_DIV             3
 333 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 334 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 335
 336 struct it87_devices {
 337         const char *name;
 338         const char * const suffix;
 339         u32 features;
 340         u8 num_temp_limit;
 341         u8 num_temp_offset;
 342         u8 num_temp_map;        /* Number of temperature sources for pwm */
 343         u8 peci_mask;
 344         u8 old_peci_mask;
 345         u8 smbus_bitmap;        /* SMBus enable bits in extra config register */
 346         u8 ec_special_config;
 347 };
 348
 349 #define FEAT_12MV_ADC           BIT(0)
 350 #define FEAT_NEWER_AUTOPWM      BIT(1)
 351 #define FEAT_OLD_AUTOPWM        BIT(2)
 352 #define FEAT_16BIT_FANS         BIT(3)
 353 #define FEAT_TEMP_PECI          BIT(5)
 354 #define FEAT_TEMP_OLD_PECI      BIT(6)
 355 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 356 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 357 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 358 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 359 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 360 #define FEAT_10_9MV_ADC         BIT(12)
 361 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 362 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 363 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 364 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 365 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 366 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 367 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 368 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 369 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 370 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 371 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 372 #define FEAT_11MV_ADC           BIT(24)
 373 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 374 #define FEAT_MMIO               BIT(26) /* Chip supports MMIO */
 375
 376 static const struct it87_devices it87_devices[] = {
 377         [it87] = {
 378                 .name = "it87",
 379                 .suffix = "F",
 380                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 381                                                 /* may need to overwrite */
 382                 .num_temp_limit = 3,
 383                 .num_temp_offset = 0,
 384                 .num_temp_map = 3,
 385         },
 386         [it8712] = {
 387                 .name = "it8712",
 388                 .suffix = "F",
 389                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 390                                                 /* may need to overwrite */
 391                 .num_temp_limit = 3,
 392                 .num_temp_offset = 0,
 393                 .num_temp_map = 3,
 394         },
 395         [it8716] = {
 396                 .name = "it8716",
 397                 .suffix = "F",
 398                 .features = FEAT_16BIT_FANS | FEAT_VID
 399                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 400                   | FEAT_FANCTL_ONOFF,
 401                 .num_temp_limit = 3,
 402                 .num_temp_offset = 3,
 403                 .num_temp_map = 3,
 404         },
 405         [it8718] = {
 406                 .name = "it8718",
 407                 .suffix = "F",
 408                 .features = FEAT_16BIT_FANS | FEAT_VID
 409                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 410                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 411                 .num_temp_limit = 3,
 412                 .num_temp_offset = 3,
 413                 .num_temp_map = 3,
 414                 .old_peci_mask = 0x4,
 415         },
 416         [it8720] = {
 417                 .name = "it8720",
 418                 .suffix = "F",
 419                 .features = FEAT_16BIT_FANS | FEAT_VID
 420                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 421                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 422                 .num_temp_limit = 3,
 423                 .num_temp_offset = 3,
 424                 .num_temp_map = 3,
 425                 .old_peci_mask = 0x4,
 426         },
 427         [it8721] = {
 428                 .name = "it8721",
 429                 .suffix = "F",
 430                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 431                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 432                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 433                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 434                 .num_temp_limit = 3,
 435                 .num_temp_offset = 3,
 436                 .num_temp_map = 3,
 437                 .peci_mask = 0x05,
 438                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 439         },
 440         [it8728] = {
 441                 .name = "it8728",
 442                 .suffix = "F",
 443                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 444                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 445                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 446                   | FEAT_FANCTL_ONOFF,
 447                 .num_temp_limit = 6,
 448                 .num_temp_offset = 3,
 449                 .num_temp_map = 3,
 450                 .peci_mask = 0x07,
 451         },
 452         [it8732] = {
 453                 .name = "it8732",
 454                 .suffix = "F",
 455                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 456                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 457                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 458                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 459                 .num_temp_limit = 3,
 460                 .num_temp_offset = 3,
 461                 .num_temp_map = 3,
 462                 .peci_mask = 0x07,
 463                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 464         },
 465         [it8771] = {
 466                 .name = "it8771",
 467                 .suffix = "E",
 468                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 469                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 470                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 471                                 /* PECI: guesswork */
 472                                 /* 12mV ADC (OHM) */
 473                                 /* 16 bit fans (OHM) */
 474                                 /* three fans, always 16 bit (guesswork) */
 475                 .num_temp_limit = 3,
 476                 .num_temp_offset = 3,
 477                 .num_temp_map = 3,
 478                 .peci_mask = 0x07,
 479         },
 480         [it8772] = {
 481                 .name = "it8772",
 482                 .suffix = "E",
 483                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 484                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 485                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 486                                 /* PECI (coreboot) */
 487                                 /* 12mV ADC (HWSensors4, OHM) */
 488                                 /* 16 bit fans (HWSensors4, OHM) */
 489                                 /* three fans, always 16 bit (datasheet) */
 490                 .num_temp_limit = 3,
 491                 .num_temp_offset = 3,
 492                 .num_temp_map = 3,
 493                 .peci_mask = 0x07,
 494         },
 495         [it8781] = {
 496                 .name = "it8781",
 497                 .suffix = "F",
 498                 .features = FEAT_16BIT_FANS
 499                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 500                   | FEAT_FANCTL_ONOFF,
 501                 .num_temp_limit = 3,
 502                 .num_temp_offset = 3,
 503                 .num_temp_map = 3,
 504                 .old_peci_mask = 0x4,
 505         },
 506         [it8782] = {
 507                 .name = "it8782",
 508                 .suffix = "F",
 509                 .features = FEAT_16BIT_FANS
 510                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 511                   | FEAT_FANCTL_ONOFF,
 512                 .num_temp_limit = 3,
 513                 .num_temp_offset = 3,
 514                 .num_temp_map = 3,
 515                 .old_peci_mask = 0x4,
 516         },
 517         [it8783] = {
 518                 .name = "it8783",
 519                 .suffix = "E/F",
 520                 .features = FEAT_16BIT_FANS
 521                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 522                   | FEAT_FANCTL_ONOFF,
 523                 .num_temp_limit = 3,
 524                 .num_temp_offset = 3,
 525                 .num_temp_map = 3,
 526                 .old_peci_mask = 0x4,
 527         },
 528         [it8786] = {
 529                 .name = "it8786",
 530                 .suffix = "E",
 531                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 532                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 533                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 534                 .num_temp_limit = 3,
 535                 .num_temp_offset = 3,
 536                 .num_temp_map = 3,
 537                 .peci_mask = 0x07,
 538         },
 539         [it8790] = {
 540                 .name = "it8790",
 541                 .suffix = "E",
 542                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 543                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 544                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 545                 .num_temp_limit = 3,
 546                 .num_temp_offset = 3,
 547                 .num_temp_map = 3,
 548                 .peci_mask = 0x07,
 549         },
 550         [it8792] = {
 551                 .name = "it8792",
 552                 .suffix = "E",
 553                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 554                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 555                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 556                 .num_temp_limit = 3,
 557                 .num_temp_offset = 3,
 558                 .num_temp_map = 3,
 559                 .peci_mask = 0x07,
 560         },
 561         [it8603] = {
 562                 .name = "it8603",
 563                 .suffix = "E",
 564                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 565                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 566                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 567                 .num_temp_limit = 3,
 568                 .num_temp_offset = 3,
 569                 .num_temp_map = 4,
 570                 .peci_mask = 0x07,
 571         },
 572         [it8607] = {
 573                 .name = "it8607",
 574                 .suffix = "E",
 575                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 576                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 577                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 578                   | FEAT_FANCTL_ONOFF,
 579                 .num_temp_limit = 3,
 580                 .num_temp_offset = 3,
 581                 .num_temp_map = 6,
 582                 .peci_mask = 0x07,
 583         },
 584         [it8613] = {
 585                 .name = "it8613",
 586                 .suffix = "E",
 587                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 588                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 589                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 590                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 591                 .num_temp_limit = 6,
 592                 .num_temp_offset = 6,
 593                 .num_temp_map = 6,
 594                 .peci_mask = 0x07,
 595         },
 596         [it8620] = {
 597                 .name = "it8620",
 598                 .suffix = "E",
 599                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 600                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 601                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 602                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 603                   | FEAT_FANCTL_ONOFF,
 604                 .num_temp_limit = 3,
 605                 .num_temp_offset = 3,
 606                 .num_temp_map = 3,
 607                 .peci_mask = 0x07,
 608         },
 609         [it8622] = {
 610                 .name = "it8622",
 611                 .suffix = "E",
 612                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 613                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 614                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 615                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 616                 .num_temp_limit = 3,
 617                 .num_temp_offset = 3,
 618                 .num_temp_map = 4,
 619                 .peci_mask = 0x07,
 620         },
 621         [it8625] = {
 622                 .name = "it8625",
 623                 .suffix = "E",
 624                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 625                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 626                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 627                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 628                 .num_temp_limit = 6,
 629                 .num_temp_offset = 6,
 630                 .num_temp_map = 6,
 631                 .smbus_bitmap = BIT(1) | BIT(2),
 632         },
 633         [it8628] = {
 634                 .name = "it8628",
 635                 .suffix = "E",
 636                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 637                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 638                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 639                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 640                   | FEAT_FANCTL_ONOFF,
 641                 .num_temp_limit = 6,
 642                 .num_temp_offset = 3,
 643                 .num_temp_map = 3,
 644                 .peci_mask = 0x07,
 645         },
 646         [it8655] = {
 647                 .name = "it8655",
 648                 .suffix = "E",
 649                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 650                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 651                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
 652                   | FEAT_MMIO,
 653                 .num_temp_limit = 6,
 654                 .num_temp_offset = 6,
 655                 .num_temp_map = 6,
 656                 .smbus_bitmap = BIT(2),
 657         },
 658         [it8665] = {
 659                 .name = "it8665",
 660                 .suffix = "E",
 661                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 662                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 663                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 664                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO,
 665                 .num_temp_limit = 6,
 666                 .num_temp_offset = 6,
 667                 .num_temp_map = 6,
 668                 .smbus_bitmap = BIT(2),
 669         },
 670         [it8686] = {
 671                 .name = "it8686",
 672                 .suffix = "E",
 673                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 674                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 675                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 676                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 677                 .num_temp_limit = 6,
 678                 .num_temp_offset = 6,
 679                 .num_temp_map = 7,
 680                 .smbus_bitmap = BIT(1) | BIT(2),
 681         },
 682 };
 683
 684 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 685 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 686 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 687 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 688 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 689 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 690                                  ((data)->peci_mask & BIT(nr)))
 691 #define has_temp_old_peci(data, nr) \
 692                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 693                                  ((data)->old_peci_mask & BIT(nr)))
 694 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 695 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 696                                                      FEAT_SIX_FANS))
 697 #define has_vid(data)           ((data)->features & FEAT_VID)
 698 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 699 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 700 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 701 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 702                                                      | FEAT_SIX_PWM))
 703 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 704 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 705 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 706 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 707 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 708                                                      FEAT_FIVE_FANS | \
 709                                                      FEAT_SIX_FANS))
 710 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 711                                                      FEAT_FIVE_PWM \
 712                                                      | FEAT_SIX_PWM))
 713 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 714 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 715 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 716 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 717 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 718 #define has_mmio(data)          ((data)->features & FEAT_MMIO)
 719
 720 struct it87_sio_data {
 721         enum chips type;
 722         u8 sioaddr;
 723         u8 doexit;
 724         /* Values read from Super-I/O config space */
 725         u8 revision;
 726         u8 vid_value;
 727         u8 beep_pin;
 728         u8 internal;    /* Internal sensors can be labeled */
 729         /* Features skipped based on config or DMI */
 730         u16 skip_in;
 731         u8 skip_vid;
 732         u8 skip_fan;
 733         u8 skip_pwm;
 734         u8 skip_temp;
 735         u8 smbus_bitmap;
 736         u8 ec_special_config;
 737 };
 738
 739 /*
 740  * For each registered chip, we need to keep some data in memory.
 741  * The structure is dynamically allocated.
 742  */
 743 struct it87_data {
 744         const struct attribute_group *groups[7];
 745         enum chips type;
 746         u32 features;
 747         u8 peci_mask;
 748         u8 old_peci_mask;
 749
 750         u8 smbus_bitmap;        /* !=0 if SMBus needs to be disabled */
 751         u8 ec_special_config;   /* EC special config register restore value */
 752         u8 sioaddr;             /* SIO port address */
 753         bool doexit;            /* true if exit from sio config is ok */
 754
 755         void __iomem *mmio;     /* Remapped MMIO address if available */
 756         int (*read)(struct it87_data *, u16);
 757         void (*write)(struct it87_data *, u16, u8);
 758
 759         const u8 *REG_FAN;
 760         const u8 *REG_FANX;
 761         const u8 *REG_FAN_MIN;
 762         const u8 *REG_FANX_MIN;
 763
 764         const u8 *REG_PWM;
 765
 766         const u8 *REG_TEMP_OFFSET;
 767         const u8 *REG_TEMP_LOW;
 768         const u8 *REG_TEMP_HIGH;
 769
 770         unsigned short addr;
 771         const char *name;
 772         struct mutex update_lock;
 773         char valid;             /* !=0 if following fields are valid */
 774         unsigned long last_updated;     /* In jiffies */
 775
 776         u16 in_scaled;          /* Internal voltage sensors are scaled */
 777         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 778         u16 has_in;             /* Bitfield, voltage sensors enabled */
 779         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 780         u8 has_fan;             /* Bitfield, fans enabled */
 781         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 782         u8 has_temp;            /* Bitfield, temp sensors enabled */
 783         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 784         u8 num_temp_limit;      /* Number of temperature limit registers */
 785         u8 num_temp_offset;     /* Number of temperature offset registers */
 786         u8 temp_src[4];         /* Up to 4 temperature source registers */
 787         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 788         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 789         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 790         bool has_vid;           /* True if VID supported */
 791         u8 vid;                 /* Register encoding, combined */
 792         u8 vrm;
 793         u32 alarms;             /* Register encoding, combined */
 794         bool has_beep;          /* true if beep supported */
 795         u8 beeps;               /* Register encoding */
 796         u8 fan_main_ctrl;       /* Register value */
 797         u8 fan_ctl;             /* Register value */
 798
 799         /*
 800          * The following 3 arrays correspond to the same registers up to
 801          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 802          * 7, and we want to preserve settings on mode changes, so we have
 803          * to track all values separately.
 804          * Starting with the IT8721F, the manual PWM duty cycles are stored
 805          * in separate registers (8-bit values), so the separate tracking
 806          * is no longer needed, but it is still done to keep the driver
 807          * simple.
 808          */
 809         u8 has_pwm;             /* Bitfield, pwm control enabled */
 810         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 811         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 812         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 813         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 814         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 815         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 816
 817         /* Automatic fan speed control registers */
 818         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 819         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 820 };
 821
 822 static int adc_lsb(const struct it87_data *data, int nr)
 823 {
 824         int lsb;
 825
 826         if (has_12mv_adc(data))
 827                 lsb = 120;
 828         else if (has_10_9mv_adc(data))
 829                 lsb = 109;
 830         else if (has_11mv_adc(data))
 831                 lsb = 110;
 832         else
 833                 lsb = 160;
 834         if (data->in_scaled & BIT(nr))
 835                 lsb <<= 1;
 836         return lsb;
 837 }
 838
 839 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 840 {
 841         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 842         return clamp_val(val, 0, 255);
 843 }
 844
 845 static int in_from_reg(const struct it87_data *data, int nr, int val)
 846 {
 847         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 848 }
 849
 850 static inline u8 FAN_TO_REG(long rpm, int div)
 851 {
 852         if (rpm == 0)
 853                 return 255;
 854         rpm = clamp_val(rpm, 1, 1000000);
 855         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 856 }
 857
 858 static inline u16 FAN16_TO_REG(long rpm)
 859 {
 860         if (rpm == 0)
 861                 return 0xffff;
 862         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 863 }
 864
 865 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 866                                 1350000 / ((val) * (div)))
 867 /* The divider is fixed to 2 in 16-bit mode */
 868 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 869                              1350000 / ((val) * 2))
 870
 871 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 872                                     ((val) + 500) / 1000), -128, 127))
 873 #define TEMP_FROM_REG(val) ((val) * 1000)
 874
 875 static u8 pwm_to_reg(const struct it87_data *data, long val)
 876 {
 877         if (has_newer_autopwm(data))
 878                 return val;
 879         else
 880                 return val >> 1;
 881 }
 882
 883 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 884 {
 885         if (has_newer_autopwm(data))
 886                 return reg;
 887         else
 888                 return (reg & 0x7f) << 1;
 889 }
 890
 891 static int DIV_TO_REG(int val)
 892 {
 893         int answer = 0;
 894
 895         while (answer < 7 && (val >>= 1))
 896                 answer++;
 897         return answer;
 898 }
 899
 900 #define DIV_FROM_REG(val) BIT(val)
 901
 902 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 903 {
 904         u8 map;
 905
 906         map  = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 907         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 908                 map = 0;
 909
 910         return map;
 911 }
 912
 913 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 914 {
 915         u8 ctrl = data->pwm_ctrl[nr];
 916
 917         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 918                (map << data->pwm_temp_map_shift);
 919 }
 920
 921 /*
 922  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 923  * depending on the chip type, to calculate the actual PWM frequency.
 924  *
 925  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 926  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 927  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 928  * sometimes just one. It is unknown if this is a datasheet error or real,
 929  * so this is ignored for now.
 930  */
 931 static const unsigned int pwm_freq[8] = {
 932         48000000,
 933         24000000,
 934         12000000,
 935         8000000,
 936         6000000,
 937         3000000,
 938         1500000,
 939         750000,
 940 };
 941
 942 static int smbus_disable(struct it87_data *data)
 943 {
 944         int err;
 945
 946         if (data->smbus_bitmap) {
 947                 err = superio_enter(data->sioaddr);
 948                 if (err)
 949                         return err;
 950                 superio_select(data->sioaddr, PME);
 951                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 952                              data->ec_special_config & ~data->smbus_bitmap);
 953                 superio_exit(data->sioaddr, data->doexit);
 954         }
 955         return 0;
 956 }
 957
 958 static int smbus_enable(struct it87_data *data)
 959 {
 960         int err;
 961
 962         if (data->smbus_bitmap) {
 963                 err = superio_enter(data->sioaddr);
 964                 if (err)
 965                         return err;
 966
 967                 superio_select(data->sioaddr, PME);
 968                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 969                              data->ec_special_config);
 970                 superio_exit(data->sioaddr, data->doexit);
 971         }
 972         return 0;
 973 }
 974
 975 static int _it87_io_read(struct it87_data *data, u16 reg)
 976 {
 977         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 978         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 979 }
 980
 981 static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
 982 {
 983         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 984         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 985 }
 986
 987 static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
 988 {
 989         u8 _bank = bank;
 990
 991         if (has_bank_sel(data)) {
 992                 u8 breg = _it87_io_read(data, IT87_REG_BANK);
 993
 994                 _bank = breg >> 5;
 995                 if (bank != _bank) {
 996                         breg &= 0x1f;
 997                         breg |= (bank << 5);
 998                         _it87_io_write(data, IT87_REG_BANK, breg);
 999                 }
1000         }
1001         return _bank;
1002 }
1003
1004 /*
1005  * Must be called with data->update_lock held, except during initialization.
1006  * Must be called with SMBus accesses disabled.
1007  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1008  * would slow down the IT87 access and should not be necessary.
1009  */
1010 static int it87_io_read(struct it87_data *data, u16 reg)
1011 {
1012         u8 bank;
1013         int val;
1014
1015         bank = it87_io_set_bank(data, reg >> 8);
1016         val = _it87_io_read(data, reg & 0xff);
1017         it87_io_set_bank(data, bank);
1018
1019         return val;
1020 }
1021
1022 /*
1023  * Must be called with data->update_lock held, except during initialization.
1024  * Must be called with SMBus accesses disabled
1025  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1026  * would slow down the IT87 access and should not be necessary.
1027  */
1028 static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1029 {
1030         u8 bank;
1031
1032         bank = it87_io_set_bank(data, reg >> 8);
1033         _it87_io_write(data, reg & 0xff, value);
1034         it87_io_set_bank(data, bank);
1035 }
1036
1037 static int it87_mmio_read(struct it87_data *data, u16 reg)
1038 {
1039         return readb(data->mmio + reg);
1040 }
1041
1042 static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1043 {
1044         writeb(value, data->mmio + reg);
1045 }
1046
1047 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1048 {
1049         u8 ctrl;
1050
1051         ctrl = data->read(data, data->REG_PWM[nr]);
1052         data->pwm_ctrl[nr] = ctrl;
1053         if (has_newer_autopwm(data)) {
1054                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1055                 data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1056         } else {
1057                 if (ctrl & 0x80)        /* Automatic mode */
1058                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1059                 else                            /* Manual mode */
1060                         data->pwm_duty[nr] = ctrl & 0x7f;
1061         }
1062
1063         if (has_old_autopwm(data)) {
1064                 int i;
1065
1066                 for (i = 0; i < 5 ; i++)
1067                         data->auto_temp[nr][i] = data->read(data,
1068                                                 IT87_REG_AUTO_TEMP(nr, i));
1069                 for (i = 0; i < 3 ; i++)
1070                         data->auto_pwm[nr][i] = data->read(data,
1071                                                 IT87_REG_AUTO_PWM(nr, i));
1072         } else if (has_newer_autopwm(data)) {
1073                 int i;
1074
1075                 /*
1076                  * 0: temperature hysteresis (base + 5)
1077                  * 1: fan off temperature (base + 0)
1078                  * 2: fan start temperature (base + 1)
1079                  * 3: fan max temperature (base + 2)
1080                  */
1081                 data->auto_temp[nr][0] =
1082                         data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1083
1084                 for (i = 0; i < 3 ; i++)
1085                         data->auto_temp[nr][i + 1] =
1086                                 data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1087                 /*
1088                  * 0: start pwm value (base + 3)
1089                  * 1: pwm slope (base + 4, 1/8th pwm)
1090                  */
1091                 data->auto_pwm[nr][0] =
1092                         data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1093                 data->auto_pwm[nr][1] =
1094                         data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1095         }
1096 }
1097
1098 static int it87_lock(struct it87_data *data)
1099 {
1100         int err;
1101
1102         mutex_lock(&data->update_lock);
1103         err = smbus_disable(data);
1104         if (err)
1105                 mutex_unlock(&data->update_lock);
1106         return err;
1107 }
1108
1109 static void it87_unlock(struct it87_data *data)
1110 {
1111         smbus_enable(data);
1112         mutex_unlock(&data->update_lock);
1113 }
1114
1115 static struct it87_data *it87_update_device(struct device *dev)
1116 {
1117         struct it87_data *data = dev_get_drvdata(dev);
1118         int err;
1119         int i;
1120
1121         err = it87_lock(data);
1122         if (err)
1123                 return ERR_PTR(err);
1124
1125         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1126             !data->valid) {
1127                 if (update_vbat) {
1128                         /*
1129                          * Cleared after each update, so reenable.  Value
1130                          * returned by this read will be previous value
1131                          */
1132                         data->write(data, IT87_REG_CONFIG,
1133                                     data->read(data, IT87_REG_CONFIG) | 0x40);
1134                 }
1135                 for (i = 0; i < NUM_VIN; i++) {
1136                         if (!(data->has_in & BIT(i)))
1137                                 continue;
1138
1139                         data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1140
1141                         /* VBAT and AVCC don't have limit registers */
1142                         if (i >= NUM_VIN_LIMIT)
1143                                 continue;
1144
1145                         data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1146                         data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1147                 }
1148
1149                 for (i = 0; i < NUM_FAN; i++) {
1150                         /* Skip disabled fans */
1151                         if (!(data->has_fan & BIT(i)))
1152                                 continue;
1153
1154                         data->fan[i][1] = data->read(data, data->REG_FAN_MIN[i]);
1155                         data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1156                         /* Add high byte if in 16-bit mode */
1157                         if (has_16bit_fans(data)) {
1158                                 data->fan[i][0] |= data->read(data,
1159                                                 data->REG_FANX[i]) << 8;
1160                                 data->fan[i][1] |= data->read(data,
1161                                                 data->REG_FANX_MIN[i]) << 8;
1162                         }
1163                 }
1164                 for (i = 0; i < NUM_TEMP; i++) {
1165                         if (!(data->has_temp & BIT(i)))
1166                                 continue;
1167                         data->temp[i][0] =
1168                                 data->read(data, IT87_REG_TEMP(i));
1169
1170                         if (i >= data->num_temp_limit)
1171                                 continue;
1172
1173                         if (i < data->num_temp_offset)
1174                                 data->temp[i][3] =
1175                                   data->read(data, data->REG_TEMP_OFFSET[i]);
1176
1177                         data->temp[i][1] =
1178                                 data->read(data, data->REG_TEMP_LOW[i]);
1179                         data->temp[i][2] =
1180                                 data->read(data, data->REG_TEMP_HIGH[i]);
1181                 }
1182
1183                 /* Newer chips don't have clock dividers */
1184                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1185                         i = data->read(data, IT87_REG_FAN_DIV);
1186                         data->fan_div[0] = i & 0x07;
1187                         data->fan_div[1] = (i >> 3) & 0x07;
1188                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1189                 }
1190
1191                 data->alarms =
1192                         data->read(data, IT87_REG_ALARM1) |
1193                         (data->read(data, IT87_REG_ALARM2) << 8) |
1194                         (data->read(data, IT87_REG_ALARM3) << 16);
1195                 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1196
1197                 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1198                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1199                 for (i = 0; i < NUM_PWM; i++) {
1200                         if (!(data->has_pwm & BIT(i)))
1201                                 continue;
1202                         it87_update_pwm_ctrl(data, i);
1203                 }
1204
1205                 data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1206                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1207                 /*
1208                  * The IT8705F does not have VID capability.
1209                  * The IT8718F and later don't use IT87_REG_VID for the
1210                  * same purpose.
1211                  */
1212                 if (data->type == it8712 || data->type == it8716) {
1213                         data->vid = data->read(data, IT87_REG_VID);
1214                         /*
1215                          * The older IT8712F revisions had only 5 VID pins,
1216                          * but we assume it is always safe to read 6 bits.
1217                          */
1218                         data->vid &= 0x3f;
1219                 }
1220                 data->last_updated = jiffies;
1221                 data->valid = 1;
1222         }
1223         it87_unlock(data);
1224         return data;
1225 }
1226
1227 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1228                        char *buf)
1229 {
1230         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1231         struct it87_data *data = it87_update_device(dev);
1232         int index = sattr->index;
1233         int nr = sattr->nr;
1234
1235         if (IS_ERR(data))
1236                 return PTR_ERR(data);
1237
1238         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1239 }
1240
1241 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1242                       const char *buf, size_t count)
1243 {
1244         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1245         struct it87_data *data = dev_get_drvdata(dev);
1246         int index = sattr->index;
1247         int nr = sattr->nr;
1248         unsigned long val;
1249         int err;
1250
1251         if (kstrtoul(buf, 10, &val) < 0)
1252                 return -EINVAL;
1253
1254         err = it87_lock(data);
1255         if (err)
1256                 return err;
1257
1258         data->in[nr][index] = in_to_reg(data, nr, val);
1259         data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1260                                      : IT87_REG_VIN_MAX(nr),
1261                     data->in[nr][index]);
1262         it87_unlock(data);
1263         return count;
1264 }
1265
1266 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1267 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1268                             0, 1);
1269 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1270                             0, 2);
1271
1272 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1273 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1274                             1, 1);
1275 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1276                             1, 2);
1277
1278 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1279 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1280                             2, 1);
1281 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1282                             2, 2);
1283
1284 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1285 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1286                             3, 1);
1287 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1288                             3, 2);
1289
1290 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1291 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1292                             4, 1);
1293 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1294                             4, 2);
1295
1296 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1297 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1298                             5, 1);
1299 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1300                             5, 2);
1301
1302 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1303 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1304                             6, 1);
1305 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1306                             6, 2);
1307
1308 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1309 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1310                             7, 1);
1311 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1312                             7, 2);
1313
1314 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1315 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1316 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1317 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1318 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1319
1320 /* Up to 6 temperatures */
1321 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1322                          char *buf)
1323 {
1324         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1325         int nr = sattr->nr;
1326         int index = sattr->index;
1327         struct it87_data *data = it87_update_device(dev);
1328
1329         if (IS_ERR(data))
1330                 return PTR_ERR(data);
1331
1332         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1333 }
1334
1335 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1336                         const char *buf, size_t count)
1337 {
1338         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1339         int nr = sattr->nr;
1340         int index = sattr->index;
1341         struct it87_data *data = dev_get_drvdata(dev);
1342         long val;
1343         u8 reg, regval;
1344         int err;
1345
1346         if (kstrtol(buf, 10, &val) < 0)
1347                 return -EINVAL;
1348
1349         err = it87_lock(data);
1350         if (err)
1351                 return err;
1352
1353         switch (index) {
1354         default:
1355         case 1:
1356                 reg = data->REG_TEMP_LOW[nr];
1357                 break;
1358         case 2:
1359                 reg = data->REG_TEMP_HIGH[nr];
1360                 break;
1361         case 3:
1362                 regval = data->read(data, IT87_REG_BEEP_ENABLE);
1363                 if (!(regval & 0x80)) {
1364                         regval |= 0x80;
1365                         data->write(data, IT87_REG_BEEP_ENABLE, regval);
1366                 }
1367                 data->valid = 0;
1368                 reg = data->REG_TEMP_OFFSET[nr];
1369                 break;
1370         }
1371
1372         data->temp[nr][index] = TEMP_TO_REG(val);
1373         data->write(data, reg, data->temp[nr][index]);
1374         it87_unlock(data);
1375         return count;
1376 }
1377
1378 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1379 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1380                             0, 1);
1381 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1382                             0, 2);
1383 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1384                             set_temp, 0, 3);
1385 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1386 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1387                             1, 1);
1388 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1389                             1, 2);
1390 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1391                             set_temp, 1, 3);
1392 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1393 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1394                             2, 1);
1395 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1396                             2, 2);
1397 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1398                             set_temp, 2, 3);
1399 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1400 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1401                             3, 1);
1402 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1403                             3, 2);
1404 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1405                             set_temp, 3, 3);
1406 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1407 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1408                             4, 1);
1409 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1410                             4, 2);
1411 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1412                             set_temp, 4, 3);
1413 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1414 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1415                             5, 1);
1416 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1417                             5, 2);
1418 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1419                             set_temp, 5, 3);
1420
1421 static const u8 temp_types_8686[NUM_TEMP][9] = {
1422         { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1423         { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1424         { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1425         { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1426         { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1427         { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1428 };
1429
1430 static int get_temp_type(struct it87_data *data, int index)
1431 {
1432         u8 reg, extra;
1433         int type = 0;
1434
1435         if (has_bank_sel(data)) {
1436                 u8 src1, src2;
1437
1438                 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1439
1440                 switch (data->type) {
1441                 case it8686:
1442                         if (src1 < 9)
1443                                 type = temp_types_8686[index][src1];
1444                         break;
1445                 case it8625:
1446                         if (index < 3)
1447                                 break;
1448                 case it8655:
1449                 case it8665:
1450                         if (src1 < 3) {
1451                                 index = src1;
1452                                 break;
1453                         }
1454                         src2 = data->temp_src[3];
1455                         switch(src1) {
1456                         case 3:
1457                                 type = (src2 & BIT(index)) ? 6 : 5;
1458                                 break;
1459                         case 4 ... 8:
1460                                 type = (src2 & BIT(index)) ? 4 : 6;
1461                                 break;
1462                         case 9:
1463                                 type = (src2 & BIT(index)) ? 5 : 0;
1464                                 break;
1465                         default:
1466                                 break;
1467                         }
1468                         return type;
1469                 default:
1470                         return 0;
1471                 }
1472         }
1473         if (type || index >= 3)
1474                 return type;
1475
1476         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1477         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1478
1479         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1480             (has_temp_old_peci(data, index) && (extra & 0x80)))
1481                 type = 6;               /* Intel PECI */
1482         if (reg & BIT(index))
1483                 type = 3;               /* thermal diode */
1484         else if (reg & BIT(index + 3))
1485                 type = 4;               /* thermistor */
1486
1487         return type;
1488 }
1489
1490 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1491                               char *buf)
1492 {
1493         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1494         struct it87_data *data = it87_update_device(dev);
1495         int type;
1496
1497         if (IS_ERR(data))
1498                 return PTR_ERR(data);
1499
1500         type = get_temp_type(data, sensor_attr->index);
1501         return sprintf(buf, "%d\n", type);
1502 }
1503
1504 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1505                              const char *buf, size_t count)
1506 {
1507         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1508         int nr = sensor_attr->index;
1509
1510         struct it87_data *data = dev_get_drvdata(dev);
1511         long val;
1512         u8 reg, extra;
1513         int err;
1514
1515         if (kstrtol(buf, 10, &val) < 0)
1516                 return -EINVAL;
1517
1518         err = it87_lock(data);
1519         if (err)
1520                 return err;
1521
1522         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1523         reg &= ~(1 << nr);
1524         reg &= ~(8 << nr);
1525         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1526                 reg &= 0x3f;
1527         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1528         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1529                 extra &= 0x7f;
1530         if (val == 2) { /* backwards compatibility */
1531                 dev_warn(dev,
1532                          "Sensor type 2 is deprecated, please use 4 instead\n");
1533                 val = 4;
1534         }
1535         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1536         if (val == 3)
1537                 reg |= 1 << nr;
1538         else if (val == 4)
1539                 reg |= 8 << nr;
1540         else if (has_temp_peci(data, nr) && val == 6)
1541                 reg |= (nr + 1) << 6;
1542         else if (has_temp_old_peci(data, nr) && val == 6)
1543                 extra |= 0x80;
1544         else if (val != 0) {
1545                 count = -EINVAL;
1546                 goto unlock;
1547         }
1548
1549         data->sensor = reg;
1550         data->extra = extra;
1551         data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1552         if (has_temp_old_peci(data, nr))
1553                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1554         data->valid = 0;        /* Force cache refresh */
1555 unlock:
1556         it87_unlock(data);
1557         return count;
1558 }
1559
1560 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1561                           set_temp_type, 0);
1562 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1563                           set_temp_type, 1);
1564 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1565                           set_temp_type, 2);
1566 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1567                           set_temp_type, 3);
1568 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1569                           set_temp_type, 4);
1570 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1571                           set_temp_type, 5);
1572
1573 /* 6 Fans */
1574
1575 static int pwm_mode(const struct it87_data *data, int nr)
1576 {
1577         if (has_fanctl_onoff(data) && nr < 3 &&
1578             !(data->fan_main_ctrl & BIT(nr)))
1579                 return 0;                               /* Full speed */
1580         if (data->pwm_ctrl[nr] & 0x80)
1581                 return 2;                               /* Automatic mode */
1582         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1583             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1584                 return 0;                       /* Full speed */
1585
1586         return 1;                               /* Manual mode */
1587 }
1588
1589 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1590                         char *buf)
1591 {
1592         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1593         int nr = sattr->nr;
1594         int index = sattr->index;
1595         int speed;
1596         struct it87_data *data = it87_update_device(dev);
1597
1598         if (IS_ERR(data))
1599                 return PTR_ERR(data);
1600
1601         speed = has_16bit_fans(data) ?
1602                 FAN16_FROM_REG(data->fan[nr][index]) :
1603                 FAN_FROM_REG(data->fan[nr][index],
1604                              DIV_FROM_REG(data->fan_div[nr]));
1605         return sprintf(buf, "%d\n", speed);
1606 }
1607
1608 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1609                             char *buf)
1610 {
1611         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1612         struct it87_data *data = it87_update_device(dev);
1613         int nr = sensor_attr->index;
1614
1615         if (IS_ERR(data))
1616                 return PTR_ERR(data);
1617
1618         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1619 }
1620
1621 static ssize_t show_pwm_enable(struct device *dev,
1622                                struct device_attribute *attr, char *buf)
1623 {
1624         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1625         struct it87_data *data = it87_update_device(dev);
1626         int nr = sensor_attr->index;
1627
1628         if (IS_ERR(data))
1629                 return PTR_ERR(data);
1630
1631         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1632 }
1633
1634 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1635                         char *buf)
1636 {
1637         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1638         struct it87_data *data = it87_update_device(dev);
1639         int nr = sensor_attr->index;
1640
1641         if (IS_ERR(data))
1642                 return PTR_ERR(data);
1643
1644         return sprintf(buf, "%d\n",
1645                        pwm_from_reg(data, data->pwm_duty[nr]));
1646 }
1647
1648 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1649                              char *buf)
1650 {
1651         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1652         struct it87_data *data = it87_update_device(dev);
1653         int nr = sensor_attr->index;
1654         unsigned int freq;
1655         int index;
1656
1657         if (IS_ERR(data))
1658                 return PTR_ERR(data);
1659
1660         if (has_pwm_freq2(data) && nr == 1)
1661                 index = (data->extra >> 4) & 0x07;
1662         else
1663                 index = (data->fan_ctl >> 4) & 0x07;
1664
1665         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1666
1667         return sprintf(buf, "%u\n", freq);
1668 }
1669
1670 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1671                        const char *buf, size_t count)
1672 {
1673         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1674         int nr = sattr->nr;
1675         int index = sattr->index;
1676
1677         struct it87_data *data = dev_get_drvdata(dev);
1678         long val;
1679         int err;
1680         u8 reg;
1681
1682         if (kstrtol(buf, 10, &val) < 0)
1683                 return -EINVAL;
1684
1685         err = it87_lock(data);
1686         if (err)
1687                 return err;
1688
1689         if (has_16bit_fans(data)) {
1690                 data->fan[nr][index] = FAN16_TO_REG(val);
1691                 data->write(data, data->REG_FAN_MIN[nr],
1692                             data->fan[nr][index] & 0xff);
1693                 data->write(data, data->REG_FANX_MIN[nr],
1694                             data->fan[nr][index] >> 8);
1695         } else {
1696                 reg = data->read(data, IT87_REG_FAN_DIV);
1697                 switch (nr) {
1698                 case 0:
1699                         data->fan_div[nr] = reg & 0x07;
1700                         break;
1701                 case 1:
1702                         data->fan_div[nr] = (reg >> 3) & 0x07;
1703                         break;
1704                 case 2:
1705                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1706                         break;
1707                 }
1708                 data->fan[nr][index] =
1709                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1710                 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1711         }
1712         it87_unlock(data);
1713         return count;
1714 }
1715
1716 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1717                            const char *buf, size_t count)
1718 {
1719         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1720         struct it87_data *data = dev_get_drvdata(dev);
1721         int nr = sensor_attr->index;
1722         unsigned long val;
1723         int min, err;
1724         u8 old;
1725
1726         if (kstrtoul(buf, 10, &val) < 0)
1727                 return -EINVAL;
1728
1729         err = it87_lock(data);
1730         if (err)
1731                 return err;
1732
1733         old = data->read(data, IT87_REG_FAN_DIV);
1734
1735         /* Save fan min limit */
1736         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1737
1738         switch (nr) {
1739         case 0:
1740         case 1:
1741                 data->fan_div[nr] = DIV_TO_REG(val);
1742                 break;
1743         case 2:
1744                 if (val < 8)
1745                         data->fan_div[nr] = 1;
1746                 else
1747                         data->fan_div[nr] = 3;
1748         }
1749         val = old & 0x80;
1750         val |= (data->fan_div[0] & 0x07);
1751         val |= (data->fan_div[1] & 0x07) << 3;
1752         if (data->fan_div[2] == 3)
1753                 val |= 0x1 << 6;
1754         data->write(data, IT87_REG_FAN_DIV, val);
1755
1756         /* Restore fan min limit */
1757         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1758         data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1759         it87_unlock(data);
1760         return count;
1761 }
1762
1763 /* Returns 0 if OK, -EINVAL otherwise */
1764 static int check_trip_points(struct device *dev, int nr)
1765 {
1766         const struct it87_data *data = dev_get_drvdata(dev);
1767         int i, err = 0;
1768
1769         if (has_old_autopwm(data)) {
1770                 for (i = 0; i < 3; i++) {
1771                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1772                                 err = -EINVAL;
1773                 }
1774                 for (i = 0; i < 2; i++) {
1775                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1776                                 err = -EINVAL;
1777                 }
1778         } else if (has_newer_autopwm(data)) {
1779                 for (i = 1; i < 3; i++) {
1780                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1781                                 err = -EINVAL;
1782                 }
1783         }
1784
1785         if (err) {
1786                 dev_err(dev,
1787                         "Inconsistent trip points, not switching to automatic mode\n");
1788                 dev_err(dev, "Adjust the trip points and try again\n");
1789         }
1790         return err;
1791 }
1792
1793 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1794                               const char *buf, size_t count)
1795 {
1796         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1797         struct it87_data *data = dev_get_drvdata(dev);
1798         int nr = sensor_attr->index;
1799         long val;
1800         int err;
1801
1802         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1803                 return -EINVAL;
1804
1805         /* Check trip points before switching to automatic mode */
1806         if (val == 2) {
1807                 if (check_trip_points(dev, nr) < 0)
1808                         return -EINVAL;
1809         }
1810
1811         err = it87_lock(data);
1812         if (err)
1813                 return err;;
1814
1815         it87_update_pwm_ctrl(data, nr);
1816
1817         if (val == 0) {
1818                 if (nr < 3 && has_fanctl_onoff(data)) {
1819                         int tmp;
1820                         /* make sure the fan is on when in on/off mode */
1821                         tmp = data->read(data, IT87_REG_FAN_CTL);
1822                         data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1823                         /* set on/off mode */
1824                         data->fan_main_ctrl &= ~BIT(nr);
1825                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1826                                     data->fan_main_ctrl);
1827                 } else {
1828                         u8 ctrl;
1829
1830                         /* No on/off mode, set maximum pwm value */
1831                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1832                         data->write(data, IT87_REG_PWM_DUTY[nr],
1833                                     data->pwm_duty[nr]);
1834                         /* and set manual mode */
1835                         if (has_newer_autopwm(data)) {
1836                                 ctrl = temp_map_to_reg(data, nr,
1837                                                        data->pwm_temp_map[nr]);
1838                                 ctrl &= 0x7f;
1839                         } else {
1840                                 ctrl = data->pwm_duty[nr];
1841                         }
1842                         data->pwm_ctrl[nr] = ctrl;
1843                         data->write(data, data->REG_PWM[nr], ctrl);
1844                 }
1845         } else {
1846                 u8 ctrl;
1847
1848                 if (has_newer_autopwm(data)) {
1849                         ctrl = temp_map_to_reg(data, nr,
1850                                                data->pwm_temp_map[nr]);
1851                         if (val == 1)
1852                                 ctrl &= 0x7f;
1853                         else
1854                                 ctrl |= 0x80;
1855                 } else {
1856                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1857                 }
1858                 data->pwm_ctrl[nr] = ctrl;
1859                 data->write(data, data->REG_PWM[nr], ctrl);
1860
1861                 if (has_fanctl_onoff(data) && nr < 3) {
1862                         /* set SmartGuardian mode */
1863                         data->fan_main_ctrl |= BIT(nr);
1864                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1865                                     data->fan_main_ctrl);
1866                 }
1867         }
1868         it87_unlock(data);
1869         return count;
1870 }
1871
1872 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1873                        const char *buf, size_t count)
1874 {
1875         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1876         struct it87_data *data = dev_get_drvdata(dev);
1877         int nr = sensor_attr->index;
1878         long val;
1879         int err;
1880
1881         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1882                 return -EINVAL;
1883
1884         err = it87_lock(data);
1885         if (err)
1886                 return err;
1887
1888         it87_update_pwm_ctrl(data, nr);
1889         if (has_newer_autopwm(data)) {
1890                 /*
1891                  * If we are in automatic mode, the PWM duty cycle register
1892                  * is read-only so we can't write the value.
1893                  */
1894                 if (data->pwm_ctrl[nr] & 0x80) {
1895                         count = -EBUSY;
1896                         goto unlock;
1897                 }
1898                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1899                 data->write(data, IT87_REG_PWM_DUTY[nr],
1900                             data->pwm_duty[nr]);
1901         } else {
1902                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1903                 /*
1904                  * If we are in manual mode, write the duty cycle immediately;
1905                  * otherwise, just store it for later use.
1906                  */
1907                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1908                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1909                         data->write(data, data->REG_PWM[nr],
1910                                     data->pwm_ctrl[nr]);
1911                 }
1912         }
1913 unlock:
1914         it87_unlock(data);
1915         return count;
1916 }
1917
1918 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1919                             const char *buf, size_t count)
1920 {
1921         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1922         struct it87_data *data = dev_get_drvdata(dev);
1923         int nr = sensor_attr->index;
1924         unsigned long val;
1925         int err;
1926         int i;
1927
1928         if (kstrtoul(buf, 10, &val) < 0)
1929                 return -EINVAL;
1930
1931         val = clamp_val(val, 0, 1000000);
1932         val *= has_newer_autopwm(data) ? 256 : 128;
1933
1934         /* Search for the nearest available frequency */
1935         for (i = 0; i < 7; i++) {
1936                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1937                         break;
1938         }
1939
1940         err = it87_lock(data);
1941         if (err)
1942                 return err;
1943
1944         if (nr == 0) {
1945                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1946                 data->fan_ctl |= i << 4;
1947                 data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
1948         } else {
1949                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1950                 data->extra |= i << 4;
1951                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1952         }
1953         it87_unlock(data);
1954         return count;
1955 }
1956
1957 static ssize_t show_pwm_temp_map(struct device *dev,
1958                                  struct device_attribute *attr, char *buf)
1959 {
1960         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1961         struct it87_data *data = it87_update_device(dev);
1962         int nr = sensor_attr->index;
1963
1964         if (IS_ERR(data))
1965                 return PTR_ERR(data);
1966
1967         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1968 }
1969
1970 static ssize_t set_pwm_temp_map(struct device *dev,
1971                                 struct device_attribute *attr, const char *buf,
1972                                 size_t count)
1973 {
1974         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1975         struct it87_data *data = dev_get_drvdata(dev);
1976         int nr = sensor_attr->index;
1977         unsigned long val;
1978         int err;
1979         u8 map;
1980
1981         if (kstrtoul(buf, 10, &val) < 0)
1982                 return -EINVAL;
1983
1984         if (!val || val > data->pwm_num_temp_map)
1985                 return -EINVAL;
1986
1987         map = val - 1;
1988
1989         err = it87_lock(data);
1990         if (err)
1991                 return err;
1992
1993         it87_update_pwm_ctrl(data, nr);
1994         data->pwm_temp_map[nr] = map;
1995         /*
1996          * If we are in automatic mode, write the temp mapping immediately;
1997          * otherwise, just store it for later use.
1998          */
1999         if (data->pwm_ctrl[nr] & 0x80) {
2000                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
2001                 data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
2002         }
2003         it87_unlock(data);
2004         return count;
2005 }
2006
2007 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
2008                              char *buf)
2009 {
2010         struct it87_data *data = it87_update_device(dev);
2011         struct sensor_device_attribute_2 *sensor_attr =
2012                         to_sensor_dev_attr_2(attr);
2013         int nr = sensor_attr->nr;
2014         int point = sensor_attr->index;
2015
2016         if (IS_ERR(data))
2017                 return PTR_ERR(data);
2018
2019         return sprintf(buf, "%d\n",
2020                        pwm_from_reg(data, data->auto_pwm[nr][point]));
2021 }
2022
2023 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2024                             const char *buf, size_t count)
2025 {
2026         struct it87_data *data = dev_get_drvdata(dev);
2027         struct sensor_device_attribute_2 *sensor_attr =
2028                         to_sensor_dev_attr_2(attr);
2029         int nr = sensor_attr->nr;
2030         int point = sensor_attr->index;
2031         int regaddr;
2032         long val;
2033         int err;
2034
2035         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2036                 return -EINVAL;
2037
2038         err = it87_lock(data);
2039         if (err)
2040                 return err;
2041
2042         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2043         if (has_newer_autopwm(data))
2044                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2045         else
2046                 regaddr = IT87_REG_AUTO_PWM(nr, point);
2047         data->write(data, regaddr, data->auto_pwm[nr][point]);
2048         it87_unlock(data);
2049         return count;
2050 }
2051
2052 static ssize_t show_auto_pwm_slope(struct device *dev,
2053                                    struct device_attribute *attr, char *buf)
2054 {
2055         struct it87_data *data = it87_update_device(dev);
2056         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2057         int nr = sensor_attr->index;
2058
2059         if (IS_ERR(data))
2060                 return PTR_ERR(data);
2061
2062         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2063 }
2064
2065 static ssize_t set_auto_pwm_slope(struct device *dev,
2066                                   struct device_attribute *attr,
2067                                   const char *buf, size_t count)
2068 {
2069         struct it87_data *data = dev_get_drvdata(dev);
2070         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2071         int nr = sensor_attr->index;
2072         unsigned long val;
2073         int err;
2074
2075         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2076                 return -EINVAL;
2077
2078         err = it87_lock(data);
2079         if (err)
2080                 return err;
2081
2082         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2083         data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2084         it87_unlock(data);
2085         return count;
2086 }
2087
2088 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2089                               char *buf)
2090 {
2091         struct it87_data *data = it87_update_device(dev);
2092         struct sensor_device_attribute_2 *sensor_attr =
2093                         to_sensor_dev_attr_2(attr);
2094         int nr = sensor_attr->nr;
2095         int point = sensor_attr->index;
2096         int reg;
2097
2098         if (IS_ERR(data))
2099                 return PTR_ERR(data);
2100
2101         if (has_old_autopwm(data) || point)
2102                 reg = data->auto_temp[nr][point];
2103         else
2104                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2105
2106         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2107 }
2108
2109 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2110                              const char *buf, size_t count)
2111 {
2112         struct it87_data *data = dev_get_drvdata(dev);
2113         struct sensor_device_attribute_2 *sensor_attr =
2114                         to_sensor_dev_attr_2(attr);
2115         int nr = sensor_attr->nr;
2116         int point = sensor_attr->index;
2117         long val;
2118         int reg;
2119         int err;
2120
2121         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2122                 return -EINVAL;
2123
2124         err = it87_lock(data);
2125         if (err)
2126                 return err;
2127
2128         if (has_newer_autopwm(data) && !point) {
2129                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2130                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2131                 data->auto_temp[nr][0] = reg;
2132                 data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2133         } else {
2134                 reg = TEMP_TO_REG(val);
2135                 data->auto_temp[nr][point] = reg;
2136                 if (has_newer_autopwm(data))
2137                         point--;
2138                 data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2139         }
2140         it87_unlock(data);
2141         return count;
2142 }
2143
2144 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
2145 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2146                             0, 1);
2147 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
2148                           set_fan_div, 0);
2149
2150 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
2151 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2152                             1, 1);
2153 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
2154                           set_fan_div, 1);
2155
2156 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
2157 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2158                             2, 1);
2159 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
2160                           set_fan_div, 2);
2161
2162 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2163 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2164                             3, 1);
2165
2166 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2167 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2168                             4, 1);
2169
2170 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2171 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2172                             5, 1);
2173
2174 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2175                           show_pwm_enable, set_pwm_enable, 0);
2176 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2177 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2178                           set_pwm_freq, 0);
2179 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2180                           show_pwm_temp_map, set_pwm_temp_map, 0);
2181 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2182                             show_auto_pwm, set_auto_pwm, 0, 0);
2183 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2184                             show_auto_pwm, set_auto_pwm, 0, 1);
2185 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2186                             show_auto_pwm, set_auto_pwm, 0, 2);
2187 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2188                             show_auto_pwm, NULL, 0, 3);
2189 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2190                             show_auto_temp, set_auto_temp, 0, 1);
2191 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2192                             show_auto_temp, set_auto_temp, 0, 0);
2193 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2194                             show_auto_temp, set_auto_temp, 0, 2);
2195 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2196                             show_auto_temp, set_auto_temp, 0, 3);
2197 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2198                             show_auto_temp, set_auto_temp, 0, 4);
2199 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2200                             show_auto_pwm, set_auto_pwm, 0, 0);
2201 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2202                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2203
2204 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2205                           show_pwm_enable, set_pwm_enable, 1);
2206 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2207 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2208 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2209                           show_pwm_temp_map, set_pwm_temp_map, 1);
2210 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2211                             show_auto_pwm, set_auto_pwm, 1, 0);
2212 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2213                             show_auto_pwm, set_auto_pwm, 1, 1);
2214 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2215                             show_auto_pwm, set_auto_pwm, 1, 2);
2216 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2217                             show_auto_pwm, NULL, 1, 3);
2218 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2219                             show_auto_temp, set_auto_temp, 1, 1);
2220 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2221                             show_auto_temp, set_auto_temp, 1, 0);
2222 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2223                             show_auto_temp, set_auto_temp, 1, 2);
2224 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2225                             show_auto_temp, set_auto_temp, 1, 3);
2226 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2227                             show_auto_temp, set_auto_temp, 1, 4);
2228 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2229                             show_auto_pwm, set_auto_pwm, 1, 0);
2230 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2231                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2232
2233 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2234                           show_pwm_enable, set_pwm_enable, 2);
2235 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2236 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2237 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2238                           show_pwm_temp_map, set_pwm_temp_map, 2);
2239 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2240                             show_auto_pwm, set_auto_pwm, 2, 0);
2241 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2242                             show_auto_pwm, set_auto_pwm, 2, 1);
2243 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2244                             show_auto_pwm, set_auto_pwm, 2, 2);
2245 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2246                             show_auto_pwm, NULL, 2, 3);
2247 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2248                             show_auto_temp, set_auto_temp, 2, 1);
2249 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2250                             show_auto_temp, set_auto_temp, 2, 0);
2251 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2252                             show_auto_temp, set_auto_temp, 2, 2);
2253 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2254                             show_auto_temp, set_auto_temp, 2, 3);
2255 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2256                             show_auto_temp, set_auto_temp, 2, 4);
2257 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2258                             show_auto_pwm, set_auto_pwm, 2, 0);
2259 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2260                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2261
2262 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2263                           show_pwm_enable, set_pwm_enable, 3);
2264 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2265 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2266 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2267                           show_pwm_temp_map, set_pwm_temp_map, 3);
2268 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2269                             show_auto_temp, set_auto_temp, 2, 1);
2270 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2271                             show_auto_temp, set_auto_temp, 2, 0);
2272 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2273                             show_auto_temp, set_auto_temp, 2, 2);
2274 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2275                             show_auto_temp, set_auto_temp, 2, 3);
2276 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2277                             show_auto_pwm, set_auto_pwm, 3, 0);
2278 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2279                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2280
2281 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2282                           show_pwm_enable, set_pwm_enable, 4);
2283 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2284 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2285 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2286                           show_pwm_temp_map, set_pwm_temp_map, 4);
2287 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2288                             show_auto_temp, set_auto_temp, 2, 1);
2289 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2290                             show_auto_temp, set_auto_temp, 2, 0);
2291 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2292                             show_auto_temp, set_auto_temp, 2, 2);
2293 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2294                             show_auto_temp, set_auto_temp, 2, 3);
2295 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2296                             show_auto_pwm, set_auto_pwm, 4, 0);
2297 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2298                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2299
2300 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2301                           show_pwm_enable, set_pwm_enable, 5);
2302 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2303 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2304 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2305                           show_pwm_temp_map, set_pwm_temp_map, 5);
2306 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2307                             show_auto_temp, set_auto_temp, 2, 1);
2308 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2309                             show_auto_temp, set_auto_temp, 2, 0);
2310 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2311                             show_auto_temp, set_auto_temp, 2, 2);
2312 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2313                             show_auto_temp, set_auto_temp, 2, 3);
2314 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2315                             show_auto_pwm, set_auto_pwm, 5, 0);
2316 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2317                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2318
2319 /* Alarms */
2320 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2321                            char *buf)
2322 {
2323         struct it87_data *data = it87_update_device(dev);
2324
2325         if (IS_ERR(data))
2326                 return PTR_ERR(data);
2327
2328         return sprintf(buf, "%u\n", data->alarms);
2329 }
2330 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2331
2332 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2333                           char *buf)
2334 {
2335         struct it87_data *data = it87_update_device(dev);
2336         int bitnr = to_sensor_dev_attr(attr)->index;
2337
2338         if (IS_ERR(data))
2339                 return PTR_ERR(data);
2340
2341         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2342 }
2343
2344 static ssize_t clear_intrusion(struct device *dev,
2345                                struct device_attribute *attr, const char *buf,
2346                                size_t count)
2347 {
2348         struct it87_data *data = dev_get_drvdata(dev);
2349         int err, config;
2350         long val;
2351
2352         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2353                 return -EINVAL;
2354
2355         err = it87_lock(data);
2356         if (err)
2357                 return err;
2358
2359         config = data->read(data, IT87_REG_CONFIG);
2360         config |= BIT(5);
2361         data->write(data, IT87_REG_CONFIG, config);
2362         /* Invalidate cache to force re-read */
2363         data->valid = 0;
2364         it87_unlock(data);
2365         return count;
2366 }
2367
2368 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2369 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2370 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2371 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2372 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2373 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2374 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2375 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2376 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2377 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2378 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2379 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2380 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2381 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2382 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2383 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2384 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2385 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2386 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2387 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2388 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2389                           show_alarm, clear_intrusion, 4);
2390
2391 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2392                          char *buf)
2393 {
2394         struct it87_data *data = it87_update_device(dev);
2395         int bitnr = to_sensor_dev_attr(attr)->index;
2396
2397         if (IS_ERR(data))
2398                 return PTR_ERR(data);
2399
2400         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2401 }
2402
2403 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2404                         const char *buf, size_t count)
2405 {
2406         int bitnr = to_sensor_dev_attr(attr)->index;
2407         struct it87_data *data = dev_get_drvdata(dev);
2408         long val;
2409         int err;
2410
2411         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2412                 return -EINVAL;
2413
2414         err = it87_lock(data);
2415         if (err)
2416                 return err;
2417
2418         data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2419         if (val)
2420                 data->beeps |= BIT(bitnr);
2421         else
2422                 data->beeps &= ~BIT(bitnr);
2423         data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2424         it87_unlock(data);
2425         return count;
2426 }
2427
2428 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2429                           show_beep, set_beep, 1);
2430 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2431 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2432 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2433 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2434 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2435 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2436 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2437 /* fanX_beep writability is set later */
2438 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2439 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2440 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2441 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2442 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2443 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2444 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2445                           show_beep, set_beep, 2);
2446 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2447 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2448 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2449 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2450 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2451
2452 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2453                             char *buf)
2454 {
2455         struct it87_data *data = dev_get_drvdata(dev);
2456
2457         return sprintf(buf, "%u\n", data->vrm);
2458 }
2459
2460 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2461                              const char *buf, size_t count)
2462 {
2463         struct it87_data *data = dev_get_drvdata(dev);
2464         unsigned long val;
2465
2466         if (kstrtoul(buf, 10, &val) < 0)
2467                 return -EINVAL;
2468
2469         data->vrm = val;
2470
2471         return count;
2472 }
2473 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2474
2475 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2476                             char *buf)
2477 {
2478         struct it87_data *data = it87_update_device(dev);
2479
2480         if (IS_ERR(data))
2481                 return PTR_ERR(data);
2482
2483         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2484 }
2485 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2486
2487 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2488                           char *buf)
2489 {
2490         static const char * const labels[] = {
2491                 "+5V",
2492                 "5VSB",
2493                 "Vbat",
2494                 "AVCC",
2495         };
2496         static const char * const labels_it8721[] = {
2497                 "+3.3V",
2498                 "3VSB",
2499                 "Vbat",
2500                 "+3.3V",
2501         };
2502         struct it87_data *data = dev_get_drvdata(dev);
2503         int nr = to_sensor_dev_attr(attr)->index;
2504         const char *label;
2505
2506         if (has_vin3_5v(data) && nr == 0)
2507                 label = labels[0];
2508         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2509                  has_11mv_adc(data))
2510                 label = labels_it8721[nr];
2511         else
2512                 label = labels[nr];
2513
2514         return sprintf(buf, "%s\n", label);
2515 }
2516 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2517 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2518 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2519 /* AVCC3 */
2520 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2521
2522 static umode_t it87_in_is_visible(struct kobject *kobj,
2523                                   struct attribute *attr, int index)
2524 {
2525         struct device *dev = container_of(kobj, struct device, kobj);
2526         struct it87_data *data = dev_get_drvdata(dev);
2527         int i = index / 5;      /* voltage index */
2528         int a = index % 5;      /* attribute index */
2529
2530         if (index >= 40) {      /* in8 and higher only have input attributes */
2531                 i = index - 40 + 8;
2532                 a = 0;
2533         }
2534
2535         if (!(data->has_in & BIT(i)))
2536                 return 0;
2537
2538         if (a == 4 && !data->has_beep)
2539                 return 0;
2540
2541         return attr->mode;
2542 }
2543
2544 static struct attribute *it87_attributes_in[] = {
2545         &sensor_dev_attr_in0_input.dev_attr.attr,
2546         &sensor_dev_attr_in0_min.dev_attr.attr,
2547         &sensor_dev_attr_in0_max.dev_attr.attr,
2548         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2549         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2550
2551         &sensor_dev_attr_in1_input.dev_attr.attr,
2552         &sensor_dev_attr_in1_min.dev_attr.attr,
2553         &sensor_dev_attr_in1_max.dev_attr.attr,
2554         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2555         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2556
2557         &sensor_dev_attr_in2_input.dev_attr.attr,
2558         &sensor_dev_attr_in2_min.dev_attr.attr,
2559         &sensor_dev_attr_in2_max.dev_attr.attr,
2560         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2561         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2562
2563         &sensor_dev_attr_in3_input.dev_attr.attr,
2564         &sensor_dev_attr_in3_min.dev_attr.attr,
2565         &sensor_dev_attr_in3_max.dev_attr.attr,
2566         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2567         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2568
2569         &sensor_dev_attr_in4_input.dev_attr.attr,
2570         &sensor_dev_attr_in4_min.dev_attr.attr,
2571         &sensor_dev_attr_in4_max.dev_attr.attr,
2572         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2573         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2574
2575         &sensor_dev_attr_in5_input.dev_attr.attr,
2576         &sensor_dev_attr_in5_min.dev_attr.attr,
2577         &sensor_dev_attr_in5_max.dev_attr.attr,
2578         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2579         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2580
2581         &sensor_dev_attr_in6_input.dev_attr.attr,
2582         &sensor_dev_attr_in6_min.dev_attr.attr,
2583         &sensor_dev_attr_in6_max.dev_attr.attr,
2584         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2585         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2586
2587         &sensor_dev_attr_in7_input.dev_attr.attr,
2588         &sensor_dev_attr_in7_min.dev_attr.attr,
2589         &sensor_dev_attr_in7_max.dev_attr.attr,
2590         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2591         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2592
2593         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2594         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2595         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2596         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2597         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2598         NULL
2599 };
2600
2601 static const struct attribute_group it87_group_in = {
2602         .attrs = it87_attributes_in,
2603         .is_visible = it87_in_is_visible,
2604 };
2605
2606 static umode_t it87_temp_is_visible(struct kobject *kobj,
2607                                     struct attribute *attr, int index)
2608 {
2609         struct device *dev = container_of(kobj, struct device, kobj);
2610         struct it87_data *data = dev_get_drvdata(dev);
2611         int i = index / 7;      /* temperature index */
2612         int a = index % 7;      /* attribute index */
2613
2614         if (!(data->has_temp & BIT(i)))
2615                 return 0;
2616
2617         if (a && i >= data->num_temp_limit)
2618                 return 0;
2619
2620         if (a == 3) {
2621                 int type = get_temp_type(data, i);
2622
2623                 if (type == 0)
2624                         return 0;
2625                 if (has_bank_sel(data))
2626                         return 0444;
2627                 return attr->mode;
2628         }
2629
2630         if (a == 5 && i >= data->num_temp_offset)
2631                 return 0;
2632
2633         if (a == 6 && !data->has_beep)
2634                 return 0;
2635
2636         return attr->mode;
2637 }
2638
2639 static struct attribute *it87_attributes_temp[] = {
2640         &sensor_dev_attr_temp1_input.dev_attr.attr,
2641         &sensor_dev_attr_temp1_max.dev_attr.attr,
2642         &sensor_dev_attr_temp1_min.dev_attr.attr,
2643         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2644         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2645         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2646         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2647
2648         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2649         &sensor_dev_attr_temp2_max.dev_attr.attr,
2650         &sensor_dev_attr_temp2_min.dev_attr.attr,
2651         &sensor_dev_attr_temp2_type.dev_attr.attr,
2652         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2653         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2654         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2655
2656         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2657         &sensor_dev_attr_temp3_max.dev_attr.attr,
2658         &sensor_dev_attr_temp3_min.dev_attr.attr,
2659         &sensor_dev_attr_temp3_type.dev_attr.attr,
2660         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2661         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2662         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2663
2664         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2665         &sensor_dev_attr_temp4_max.dev_attr.attr,
2666         &sensor_dev_attr_temp4_min.dev_attr.attr,
2667         &sensor_dev_attr_temp4_type.dev_attr.attr,
2668         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2669         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2670         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2671
2672         &sensor_dev_attr_temp5_input.dev_attr.attr,
2673         &sensor_dev_attr_temp5_max.dev_attr.attr,
2674         &sensor_dev_attr_temp5_min.dev_attr.attr,
2675         &sensor_dev_attr_temp5_type.dev_attr.attr,
2676         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2677         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2678         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2679
2680         &sensor_dev_attr_temp6_input.dev_attr.attr,
2681         &sensor_dev_attr_temp6_max.dev_attr.attr,
2682         &sensor_dev_attr_temp6_min.dev_attr.attr,
2683         &sensor_dev_attr_temp6_type.dev_attr.attr,
2684         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2685         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2686         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2687         NULL
2688 };
2689
2690 static const struct attribute_group it87_group_temp = {
2691         .attrs = it87_attributes_temp,
2692         .is_visible = it87_temp_is_visible,
2693 };
2694
2695 static umode_t it87_is_visible(struct kobject *kobj,
2696                                struct attribute *attr, int index)
2697 {
2698         struct device *dev = container_of(kobj, struct device, kobj);
2699         struct it87_data *data = dev_get_drvdata(dev);
2700
2701         if ((index == 2 || index == 3) && !data->has_vid)
2702                 return 0;
2703
2704         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2705                 return 0;
2706
2707         return attr->mode;
2708 }
2709
2710 static struct attribute *it87_attributes[] = {
2711         &dev_attr_alarms.attr,
2712         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2713         &dev_attr_vrm.attr,                             /* 2 */
2714         &dev_attr_cpu0_vid.attr,                        /* 3 */
2715         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2716         &sensor_dev_attr_in7_label.dev_attr.attr,
2717         &sensor_dev_attr_in8_label.dev_attr.attr,
2718         &sensor_dev_attr_in9_label.dev_attr.attr,
2719         NULL
2720 };
2721
2722 static const struct attribute_group it87_group = {
2723         .attrs = it87_attributes,
2724         .is_visible = it87_is_visible,
2725 };
2726
2727 static umode_t it87_fan_is_visible(struct kobject *kobj,
2728                                    struct attribute *attr, int index)
2729 {
2730         struct device *dev = container_of(kobj, struct device, kobj);
2731         struct it87_data *data = dev_get_drvdata(dev);
2732         int i = index / 5;      /* fan index */
2733         int a = index % 5;      /* attribute index */
2734
2735         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2736                 i = (index - 15) / 4 + 3;
2737                 a = (index - 15) % 4;
2738         }
2739
2740         if (!(data->has_fan & BIT(i)))
2741                 return 0;
2742
2743         if (a == 3) {                           /* beep */
2744                 if (!data->has_beep)
2745                         return 0;
2746                 /* first fan beep attribute is writable */
2747                 if (i == __ffs(data->has_fan))
2748                         return attr->mode | S_IWUSR;
2749         }
2750
2751         if (a == 4 && has_16bit_fans(data))     /* divisor */
2752                 return 0;
2753
2754         return attr->mode;
2755 }
2756
2757 static struct attribute *it87_attributes_fan[] = {
2758         &sensor_dev_attr_fan1_input.dev_attr.attr,
2759         &sensor_dev_attr_fan1_min.dev_attr.attr,
2760         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2761         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2762         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2763
2764         &sensor_dev_attr_fan2_input.dev_attr.attr,
2765         &sensor_dev_attr_fan2_min.dev_attr.attr,
2766         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2767         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2768         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2769
2770         &sensor_dev_attr_fan3_input.dev_attr.attr,
2771         &sensor_dev_attr_fan3_min.dev_attr.attr,
2772         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2773         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2774         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2775
2776         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2777         &sensor_dev_attr_fan4_min.dev_attr.attr,
2778         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2779         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2780
2781         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2782         &sensor_dev_attr_fan5_min.dev_attr.attr,
2783         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2784         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2785
2786         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2787         &sensor_dev_attr_fan6_min.dev_attr.attr,
2788         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2789         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2790         NULL
2791 };
2792
2793 static const struct attribute_group it87_group_fan = {
2794         .attrs = it87_attributes_fan,
2795         .is_visible = it87_fan_is_visible,
2796 };
2797
2798 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2799                                    struct attribute *attr, int index)
2800 {
2801         struct device *dev = container_of(kobj, struct device, kobj);
2802         struct it87_data *data = dev_get_drvdata(dev);
2803         int i = index / 4;      /* pwm index */
2804         int a = index % 4;      /* attribute index */
2805
2806         if (!(data->has_pwm & BIT(i)))
2807                 return 0;
2808
2809         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2810         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2811                 return attr->mode | S_IWUSR;
2812
2813         /* pwm2_freq is writable if there are two pwm frequency selects */
2814         if (has_pwm_freq2(data) && i == 1 && a == 2)
2815                 return attr->mode | S_IWUSR;
2816
2817         return attr->mode;
2818 }
2819
2820 static struct attribute *it87_attributes_pwm[] = {
2821         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2822         &sensor_dev_attr_pwm1.dev_attr.attr,
2823         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2824         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2825
2826         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2827         &sensor_dev_attr_pwm2.dev_attr.attr,
2828         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2829         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2830
2831         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2832         &sensor_dev_attr_pwm3.dev_attr.attr,
2833         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2834         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2835
2836         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2837         &sensor_dev_attr_pwm4.dev_attr.attr,
2838         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2839         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2840
2841         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2842         &sensor_dev_attr_pwm5.dev_attr.attr,
2843         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2844         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2845
2846         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2847         &sensor_dev_attr_pwm6.dev_attr.attr,
2848         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2849         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2850
2851         NULL
2852 };
2853
2854 static const struct attribute_group it87_group_pwm = {
2855         .attrs = it87_attributes_pwm,
2856         .is_visible = it87_pwm_is_visible,
2857 };
2858
2859 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2860                                         struct attribute *attr, int index)
2861 {
2862         struct device *dev = container_of(kobj, struct device, kobj);
2863         struct it87_data *data = dev_get_drvdata(dev);
2864         int i = index / 11;     /* pwm index */
2865         int a = index % 11;     /* attribute index */
2866
2867         if (index >= 33) {      /* pwm 4..6 */
2868                 i = (index - 33) / 6 + 3;
2869                 a = (index - 33) % 6 + 4;
2870         }
2871
2872         if (!(data->has_pwm & BIT(i)))
2873                 return 0;
2874
2875         if (has_newer_autopwm(data)) {
2876                 if (a < 4)      /* no auto point pwm */
2877                         return 0;
2878                 if (a == 8)     /* no auto_point4 */
2879                         return 0;
2880         }
2881         if (has_old_autopwm(data)) {
2882                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2883                         return 0;
2884         }
2885
2886         return attr->mode;
2887 }
2888
2889 static struct attribute *it87_attributes_auto_pwm[] = {
2890         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2891         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2892         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2893         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2894         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2895         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2896         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2897         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2898         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2899         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2900         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2901
2902         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2903         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2904         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2905         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2906         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2907         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2908         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2909         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2910         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2911         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2912         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2913
2914         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2915         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2916         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2917         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2918         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2919         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2920         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2921         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2922         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2923         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2924         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2925
2926         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2927         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2928         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2929         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2930         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2931         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2932
2933         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2934         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2935         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2936         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2937         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2938         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2939
2940         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2941         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2942         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2943         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2944         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2945         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2946
2947         NULL,
2948 };
2949
2950 static const struct attribute_group it87_group_auto_pwm = {
2951         .attrs = it87_attributes_auto_pwm,
2952         .is_visible = it87_auto_pwm_is_visible,
2953 };
2954
2955 /* SuperIO detection - will change isa_address if a chip is found */
2956 static int __init it87_find(int sioaddr, unsigned short *address,
2957                             phys_addr_t *mmio_address, struct it87_sio_data *sio_data)
2958 {
2959         const struct it87_devices *config;
2960         phys_addr_t base = 0;
2961         bool doexit = true;
2962         char mmio_str[32];
2963         u16 chip_type;
2964         int err;
2965
2966         err = superio_enter(sioaddr);
2967         if (err)
2968                 return err;
2969
2970         sio_data->sioaddr = sioaddr;
2971
2972         err = -ENODEV;
2973         chip_type = superio_inw(sioaddr, DEVID);
2974         if (chip_type == 0xffff)
2975                 goto exit;
2976
2977         if (force_id)
2978                 chip_type = force_id;
2979
2980         switch (chip_type) {
2981         case IT8705F_DEVID:
2982                 sio_data->type = it87;
2983                 break;
2984         case IT8712F_DEVID:
2985                 sio_data->type = it8712;
2986                 break;
2987         case IT8716F_DEVID:
2988         case IT8726F_DEVID:
2989                 sio_data->type = it8716;
2990                 break;
2991         case IT8718F_DEVID:
2992                 sio_data->type = it8718;
2993                 break;
2994         case IT8720F_DEVID:
2995                 sio_data->type = it8720;
2996                 break;
2997         case IT8721F_DEVID:
2998                 sio_data->type = it8721;
2999                 break;
3000         case IT8728F_DEVID:
3001                 sio_data->type = it8728;
3002                 break;
3003         case IT8732F_DEVID:
3004                 sio_data->type = it8732;
3005                 break;
3006         case IT8792E_DEVID:
3007                 sio_data->type = it8792;
3008                 /*
3009                  * Disabling configuration mode on IT8792E can result in system
3010                  * hang-ups and access failures to the Super-IO chip at the
3011                  * second SIO address. Never exit configuration mode on this
3012                  * chip to avoid the problem.
3013                  */
3014                 doexit = false;
3015                 break;
3016         case IT8771E_DEVID:
3017                 sio_data->type = it8771;
3018                 break;
3019         case IT8772E_DEVID:
3020                 sio_data->type = it8772;
3021                 break;
3022         case IT8781F_DEVID:
3023                 sio_data->type = it8781;
3024                 break;
3025         case IT8782F_DEVID:
3026                 sio_data->type = it8782;
3027                 break;
3028         case IT8783E_DEVID:
3029                 sio_data->type = it8783;
3030                 break;
3031         case IT8786E_DEVID:
3032                 sio_data->type = it8786;
3033                 break;
3034         case IT8790E_DEVID:
3035                 sio_data->type = it8790;
3036                 doexit = false;         /* See IT8792E comment above */
3037                 break;
3038         case IT8603E_DEVID:
3039         case IT8623E_DEVID:
3040                 sio_data->type = it8603;
3041                 break;
3042         case IT8607E_DEVID:
3043                 sio_data->type = it8607;
3044                 break;
3045         case IT8613E_DEVID:
3046                 sio_data->type = it8613;
3047                 break;
3048         case IT8620E_DEVID:
3049                 sio_data->type = it8620;
3050                 break;
3051         case IT8622E_DEVID:
3052                 sio_data->type = it8622;
3053                 break;
3054         case IT8625E_DEVID:
3055                 sio_data->type = it8625;
3056                 break;
3057         case IT8628E_DEVID:
3058                 sio_data->type = it8628;
3059                 break;
3060         case IT8655E_DEVID:
3061                 sio_data->type = it8655;
3062                 break;
3063         case IT8665E_DEVID:
3064                 sio_data->type = it8665;
3065                 break;
3066         case IT8686E_DEVID:
3067                 sio_data->type = it8686;
3068                 break;
3069         case 0xffff:    /* No device at all */
3070                 goto exit;
3071         default:
3072                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3073                 goto exit;
3074         }
3075
3076         superio_select(sioaddr, PME);
3077         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3078                 pr_info("Device not activated, skipping\n");
3079                 goto exit;
3080         }
3081
3082         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3083         if (*address == 0) {
3084                 pr_info("Base address not set, skipping\n");
3085                 goto exit;
3086         }
3087
3088         sio_data->doexit = doexit;
3089
3090         err = 0;
3091         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3092
3093         config = &it87_devices[sio_data->type];
3094
3095         if (has_mmio(config) && mmio) {
3096                 u8 reg;
3097
3098                 reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
3099                 if (reg & BIT(5)) {
3100                         base = 0xf0000000 + ((reg & 0x0f) << 24);
3101                         base += (reg & 0xc0) << 14;
3102                 }
3103         }
3104         *mmio_address = base;
3105
3106         mmio_str[0] = '\0';
3107         if (base)
3108                 snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
3109
3110         pr_info("Found IT%04x%s chip at 0x%x%s, revision %d\n", chip_type,
3111                 it87_devices[sio_data->type].suffix,
3112                 *address, mmio_str, sio_data->revision);
3113
3114         /* in7 (VSB or VCCH5V) is always internal on some chips */
3115         if (has_in7_internal(config))
3116                 sio_data->internal |= BIT(1);
3117
3118         /* in8 (Vbat) is always internal */
3119         sio_data->internal |= BIT(2);
3120
3121         /* in9 (AVCC3), always internal if supported */
3122         if (has_avcc3(config))
3123                 sio_data->internal |= BIT(3); /* in9 is AVCC */
3124         else
3125                 sio_data->skip_in |= BIT(9);
3126
3127         if (!has_four_pwm(config))
3128                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3129         else if (!has_five_pwm(config))
3130                 sio_data->skip_pwm |= BIT(4) | BIT(5);
3131         else if (!has_six_pwm(config))
3132                 sio_data->skip_pwm |= BIT(5);
3133
3134         if (!has_vid(config))
3135                 sio_data->skip_vid = 1;
3136
3137         /* Read GPIO config and VID value from LDN 7 (GPIO) */
3138         if (sio_data->type == it87) {
3139                 /* The IT8705F has a different LD number for GPIO */
3140                 superio_select(sioaddr, 5);
3141                 sio_data->beep_pin = superio_inb(sioaddr,
3142                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3143         } else if (sio_data->type == it8783) {
3144                 int reg25, reg27, reg2a, reg2c, regef;
3145
3146                 superio_select(sioaddr, GPIO);
3147
3148                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3149                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3150                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3151                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3152                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3153
3154                 /* Check if fan3 is there or not */
3155                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3156                         sio_data->skip_fan |= BIT(2);
3157                 if ((reg25 & BIT(4)) ||
3158                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
3159                         sio_data->skip_pwm |= BIT(2);
3160
3161                 /* Check if fan2 is there or not */
3162                 if (reg27 & BIT(7))
3163                         sio_data->skip_fan |= BIT(1);
3164                 if (reg27 & BIT(3))
3165                         sio_data->skip_pwm |= BIT(1);
3166
3167                 /* VIN5 */
3168                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3169                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3170
3171                 /* VIN6 */
3172                 if (reg27 & BIT(1))
3173                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3174
3175                 /*
3176                  * VIN7
3177                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3178                  */
3179                 if (reg27 & BIT(2)) {
3180                         /*
3181                          * The data sheet is a bit unclear regarding the
3182                          * internal voltage divider for VCCH5V. It says
3183                          * "This bit enables and switches VIN7 (pin 91) to the
3184                          * internal voltage divider for VCCH5V".
3185                          * This is different to other chips, where the internal
3186                          * voltage divider would connect VIN7 to an internal
3187                          * voltage source. Maybe that is the case here as well.
3188                          *
3189                          * Since we don't know for sure, re-route it if that is
3190                          * not the case, and ask the user to report if the
3191                          * resulting voltage is sane.
3192                          */
3193                         if (!(reg2c & BIT(1))) {
3194                                 reg2c |= BIT(1);
3195                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3196                                              reg2c);
3197                                 pr_notice("Routing internal VCCH5V to in7.\n");
3198                         }
3199                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3200                         pr_notice("Please report if it displays a reasonable voltage.\n");
3201                 }
3202
3203                 if (reg2c & BIT(0))
3204                         sio_data->internal |= BIT(0);
3205                 if (reg2c & BIT(1))
3206                         sio_data->internal |= BIT(1);
3207
3208                 sio_data->beep_pin = superio_inb(sioaddr,
3209                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3210         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3211                 int reg27, reg29;
3212
3213                 superio_select(sioaddr, GPIO);
3214
3215                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3216
3217                 /* Check if fan3 is there or not */
3218                 if (reg27 & BIT(6))
3219                         sio_data->skip_pwm |= BIT(2);
3220                 if (reg27 & BIT(7))
3221                         sio_data->skip_fan |= BIT(2);
3222
3223                 /* Check if fan2 is there or not */
3224                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3225                 if (reg29 & BIT(1))
3226                         sio_data->skip_pwm |= BIT(1);
3227                 if (reg29 & BIT(2))
3228                         sio_data->skip_fan |= BIT(1);
3229
3230                 switch (sio_data->type) {
3231                 case it8603:
3232                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3233                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3234                         break;
3235                 case it8607:
3236                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3237                         sio_data->skip_fan |= BIT(0);
3238                 default:
3239                         break;
3240                 }
3241
3242                 sio_data->beep_pin = superio_inb(sioaddr,
3243                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3244         } else if (sio_data->type == it8613) {
3245                 int reg27, reg29, reg2a;
3246
3247                 superio_select(sioaddr, GPIO);
3248
3249                 /* Check for pwm3, fan3, pwm5, fan5 */
3250                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3251                 if (reg27 & BIT(1))
3252                         sio_data->skip_fan |= BIT(4);
3253                 if (reg27 & BIT(3))
3254                         sio_data->skip_pwm |= BIT(4);
3255                 if (reg27 & BIT(6))
3256                         sio_data->skip_pwm |= BIT(2);
3257                 if (reg27 & BIT(7))
3258                         sio_data->skip_fan |= BIT(2);
3259
3260                 /* Check for pwm2, fan2 */
3261                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3262                 if (reg29 & BIT(1))
3263                         sio_data->skip_pwm |= BIT(1);
3264                 if (reg29 & BIT(2))
3265                         sio_data->skip_fan |= BIT(1);
3266
3267                 /* Check for pwm4, fan4 */
3268                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3269                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3270                         sio_data->skip_fan |= BIT(3);
3271                         sio_data->skip_pwm |= BIT(3);
3272                 }
3273
3274                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3275                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3276                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3277                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3278
3279                 sio_data->beep_pin = superio_inb(sioaddr,
3280                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3281         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3282                    sio_data->type == it8686) {
3283                 int reg;
3284
3285                 superio_select(sioaddr, GPIO);
3286
3287                 /* Check for pwm5 */
3288                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3289                 if (reg & BIT(6))
3290                         sio_data->skip_pwm |= BIT(4);
3291
3292                 /* Check for fan4, fan5 */
3293                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3294                 if (!(reg & BIT(5)))
3295                         sio_data->skip_fan |= BIT(3);
3296                 if (!(reg & BIT(4)))
3297                         sio_data->skip_fan |= BIT(4);
3298
3299                 /* Check for pwm3, fan3 */
3300                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3301                 if (reg & BIT(6))
3302                         sio_data->skip_pwm |= BIT(2);
3303                 if (reg & BIT(7))
3304                         sio_data->skip_fan |= BIT(2);
3305
3306                 /* Check for pwm4 */
3307                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3308                 if (reg & BIT(2))
3309                         sio_data->skip_pwm |= BIT(3);
3310
3311                 /* Check for pwm2, fan2 */
3312                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3313                 if (reg & BIT(1))
3314                         sio_data->skip_pwm |= BIT(1);
3315                 if (reg & BIT(2))
3316                         sio_data->skip_fan |= BIT(1);
3317                 /* Check for pwm6, fan6 */
3318                 if (!(reg & BIT(7))) {
3319                         sio_data->skip_pwm |= BIT(5);
3320                         sio_data->skip_fan |= BIT(5);
3321                 }
3322
3323                 /* Check if AVCC is on VIN3 */
3324                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3325                 if (reg & BIT(0)) {
3326                         /* For it8686, the bit just enables AVCC3 */
3327                         if (sio_data->type != it8686)
3328                                 sio_data->internal |= BIT(0);
3329                 } else {
3330                         sio_data->internal &= ~BIT(3);
3331                         sio_data->skip_in |= BIT(9);
3332                 }
3333
3334                 sio_data->beep_pin = superio_inb(sioaddr,
3335                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3336         } else if (sio_data->type == it8622) {
3337                 int reg;
3338
3339                 superio_select(sioaddr, GPIO);
3340
3341                 /* Check for pwm4, fan4 */
3342                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3343                 if (reg & BIT(6))
3344                         sio_data->skip_fan |= BIT(3);
3345                 if (reg & BIT(5))
3346                         sio_data->skip_pwm |= BIT(3);
3347
3348                 /* Check for pwm3, fan3, pwm5, fan5 */
3349                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3350                 if (reg & BIT(6))
3351                         sio_data->skip_pwm |= BIT(2);
3352                 if (reg & BIT(7))
3353                         sio_data->skip_fan |= BIT(2);
3354                 if (reg & BIT(3))
3355                         sio_data->skip_pwm |= BIT(4);
3356                 if (reg & BIT(1))
3357                         sio_data->skip_fan |= BIT(4);
3358
3359                 /* Check for pwm2, fan2 */
3360                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3361                 if (reg & BIT(1))
3362                         sio_data->skip_pwm |= BIT(1);
3363                 if (reg & BIT(2))
3364                         sio_data->skip_fan |= BIT(1);
3365
3366                 /* Check for AVCC */
3367                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3368                 if (!(reg & BIT(0)))
3369                         sio_data->skip_in |= BIT(9);
3370
3371                 sio_data->beep_pin = superio_inb(sioaddr,
3372                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3373         } else if (sio_data->type == it8732) {
3374                 int reg;
3375
3376                 superio_select(sioaddr, GPIO);
3377
3378                 /* Check for pwm2, fan2 */
3379                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3380                 if (reg & BIT(1))
3381                         sio_data->skip_pwm |= BIT(1);
3382                 if (reg & BIT(2))
3383                         sio_data->skip_fan |= BIT(1);
3384
3385                 /* Check for pwm3, fan3, fan4 */
3386                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3387                 if (reg & BIT(6))
3388                         sio_data->skip_pwm |= BIT(2);
3389                 if (reg & BIT(7))
3390                         sio_data->skip_fan |= BIT(2);
3391                 if (reg & BIT(5))
3392                         sio_data->skip_fan |= BIT(3);
3393
3394                 /* Check if AVCC is on VIN3 */
3395                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3396                 if (reg & BIT(0))
3397                         sio_data->internal |= BIT(0);
3398
3399                 sio_data->beep_pin = superio_inb(sioaddr,
3400                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3401         } else if (sio_data->type == it8655) {
3402                 int reg;
3403
3404                 superio_select(sioaddr, GPIO);
3405
3406                 /* Check for pwm2 */
3407                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3408                 if (reg & BIT(1))
3409                         sio_data->skip_pwm |= BIT(1);
3410
3411                 /* Check for fan2 */
3412                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3413                 if (reg & BIT(4))
3414                         sio_data->skip_fan |= BIT(1);
3415
3416                 /* Check for pwm3, fan3 */
3417                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3418                 if (reg & BIT(6))
3419                         sio_data->skip_pwm |= BIT(2);
3420                 if (reg & BIT(7))
3421                         sio_data->skip_fan |= BIT(2);
3422
3423                 sio_data->beep_pin = superio_inb(sioaddr,
3424                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3425         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3426                 int reg27, reg29, reg2d, regd3;
3427
3428                 superio_select(sioaddr, GPIO);
3429
3430                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3431                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3432                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3433                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3434
3435                 /* Check for pwm2, fan2 */
3436                 if (reg29 & BIT(1))
3437                         sio_data->skip_pwm |= BIT(1);
3438                 /*
3439                  * Note: Table 6-1 in datasheet claims that FAN_TAC2
3440                  * would be enabled with 29h[2]=0.
3441                  */
3442                 if (reg2d & BIT(4))
3443                         sio_data->skip_fan |= BIT(1);
3444
3445                 /* Check for pwm3, fan3 */
3446                 if (reg27 & BIT(6))
3447                         sio_data->skip_pwm |= BIT(2);
3448                 if (reg27 & BIT(7))
3449                         sio_data->skip_fan |= BIT(2);
3450
3451                 /* Check for pwm4, fan4, pwm5, fan5 */
3452                 if (sio_data->type == it8625) {
3453                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3454
3455                         if (reg25 & BIT(6))
3456                                 sio_data->skip_fan |= BIT(3);
3457                         if (reg25 & BIT(5))
3458                                 sio_data->skip_pwm |= BIT(3);
3459                         if (reg27 & BIT(3))
3460                                 sio_data->skip_pwm |= BIT(4);
3461                         if (reg27 & BIT(1))
3462                                 sio_data->skip_fan |= BIT(4);
3463                 } else {
3464                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3465
3466                         if (regd3 & BIT(2))
3467                                 sio_data->skip_pwm |= BIT(3);
3468                         if (regd3 & BIT(3))
3469                                 sio_data->skip_fan |= BIT(3);
3470                         if (reg26 & BIT(5))
3471                                 sio_data->skip_pwm |= BIT(4);
3472                         if (reg26 & BIT(4))
3473                                 sio_data->skip_fan |= BIT(4);
3474                 }
3475
3476                 /* Check for pwm6, fan6 */
3477                 if (regd3 & BIT(0))
3478                         sio_data->skip_pwm |= BIT(5);
3479                 if (regd3 & BIT(1))
3480                         sio_data->skip_fan |= BIT(5);
3481
3482                 sio_data->beep_pin = superio_inb(sioaddr,
3483                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3484         } else {
3485                 int reg;
3486                 bool uart6;
3487
3488                 superio_select(sioaddr, GPIO);
3489
3490                 /* Check for fan4, fan5 */
3491                 if (has_five_fans(config)) {
3492                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3493                         switch (sio_data->type) {
3494                         case it8718:
3495                                 if (reg & BIT(5))
3496                                         sio_data->skip_fan |= BIT(3);
3497                                 if (reg & BIT(4))
3498                                         sio_data->skip_fan |= BIT(4);
3499                                 break;
3500                         case it8720:
3501                         case it8721:
3502                         case it8728:
3503                                 if (!(reg & BIT(5)))
3504                                         sio_data->skip_fan |= BIT(3);
3505                                 if (!(reg & BIT(4)))
3506                                         sio_data->skip_fan |= BIT(4);
3507                                 break;
3508                         default:
3509                                 break;
3510                         }
3511                 }
3512
3513                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3514                 if (!sio_data->skip_vid) {
3515                         /* We need at least 4 VID pins */
3516                         if (reg & 0x0f) {
3517                                 pr_info("VID is disabled (pins used for GPIO)\n");
3518                                 sio_data->skip_vid = 1;
3519                         }
3520                 }
3521
3522                 /* Check if fan3 is there or not */
3523                 if (reg & BIT(6))
3524                         sio_data->skip_pwm |= BIT(2);
3525                 if (reg & BIT(7))
3526                         sio_data->skip_fan |= BIT(2);
3527
3528                 /* Check if fan2 is there or not */
3529                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3530                 if (reg & BIT(1))
3531                         sio_data->skip_pwm |= BIT(1);
3532                 if (reg & BIT(2))
3533                         sio_data->skip_fan |= BIT(1);
3534
3535                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3536                     !(sio_data->skip_vid))
3537                         sio_data->vid_value = superio_inb(sioaddr,
3538                                                           IT87_SIO_VID_REG);
3539
3540                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3541
3542                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3543
3544                 /*
3545                  * The IT8720F has no VIN7 pin, so VCCH should always be
3546                  * routed internally to VIN7 with an internal divider.
3547                  * Curiously, there still is a configuration bit to control
3548                  * this, which means it can be set incorrectly. And even
3549                  * more curiously, many boards out there are improperly
3550                  * configured, even though the IT8720F datasheet claims
3551                  * that the internal routing of VCCH to VIN7 is the default
3552                  * setting. So we force the internal routing in this case.
3553                  *
3554                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3555                  * If UART6 is enabled, re-route VIN7 to the internal divider
3556                  * if that is not already the case.
3557                  */
3558                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3559                         reg |= BIT(1);
3560                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3561                         pr_notice("Routing internal VCCH to in7\n");
3562                 }
3563                 if (reg & BIT(0))
3564                         sio_data->internal |= BIT(0);
3565                 if (reg & BIT(1))
3566                         sio_data->internal |= BIT(1);
3567
3568                 /*
3569                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3570                  * While VIN7 can be routed to the internal voltage divider,
3571                  * VIN5 and VIN6 are not available if UART6 is enabled.
3572                  *
3573                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3574                  * is the temperature source. Since we can not read the
3575                  * temperature source here, skip_temp is preliminary.
3576                  */
3577                 if (uart6) {
3578                         sio_data->skip_in |= BIT(5) | BIT(6);
3579                         sio_data->skip_temp |= BIT(2);
3580                 }
3581
3582                 sio_data->beep_pin = superio_inb(sioaddr,
3583                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3584         }
3585         if (sio_data->beep_pin)
3586                 pr_info("Beeping is supported\n");
3587
3588         if (config->smbus_bitmap && !base) {
3589                 u8 reg;
3590
3591                 superio_select(sioaddr, PME);
3592                 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3593                 sio_data->ec_special_config = reg;
3594                 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3595         }
3596
3597 exit:
3598         superio_exit(sioaddr, doexit);
3599         return err;
3600 }
3601
3602 static void it87_init_regs(struct platform_device *pdev)
3603 {
3604         struct it87_data *data = platform_get_drvdata(pdev);
3605
3606         /* Initialize chip specific register pointers */
3607         switch (data->type) {
3608         case it8628:
3609         case it8686:
3610                 data->REG_FAN = IT87_REG_FAN;
3611                 data->REG_FANX = IT87_REG_FANX;
3612                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3613                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3614                 data->REG_PWM = IT87_REG_PWM;
3615                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3616                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3617                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3618                 break;
3619         case it8625:
3620         case it8655:
3621         case it8665:
3622                 data->REG_FAN = IT87_REG_FAN_8665;
3623                 data->REG_FANX = IT87_REG_FANX_8665;
3624                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3625                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3626                 data->REG_PWM = IT87_REG_PWM_8665;
3627                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3628                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3629                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3630                 break;
3631         case it8622:
3632                 data->REG_FAN = IT87_REG_FAN;
3633                 data->REG_FANX = IT87_REG_FANX;
3634                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3635                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3636                 data->REG_PWM = IT87_REG_PWM_8665;
3637                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3638                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3639                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3640                 break;
3641         case it8613:
3642                 data->REG_FAN = IT87_REG_FAN;
3643                 data->REG_FANX = IT87_REG_FANX;
3644                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3645                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3646                 data->REG_PWM = IT87_REG_PWM_8665;
3647                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3648                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3649                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3650                 break;
3651         default:
3652                 data->REG_FAN = IT87_REG_FAN;
3653                 data->REG_FANX = IT87_REG_FANX;
3654                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3655                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3656                 data->REG_PWM = IT87_REG_PWM;
3657                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3658                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3659                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3660                 break;
3661         }
3662
3663         if (data->mmio) {
3664                 data->read = it87_mmio_read;
3665                 data->write = it87_mmio_write;
3666         } else if (has_bank_sel(data)) {
3667                 data->read = it87_io_read;
3668                 data->write = it87_io_write;
3669         } else {
3670                 data->read = _it87_io_read;
3671                 data->write = _it87_io_write;
3672         }
3673 }
3674
3675 /* Called when we have found a new IT87. */
3676 static void it87_init_device(struct platform_device *pdev)
3677 {
3678         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3679         struct it87_data *data = platform_get_drvdata(pdev);
3680         int tmp, i;
3681         u8 mask;
3682
3683         if (has_new_tempmap(data)) {
3684                 data->pwm_temp_map_shift = 3;
3685                 data->pwm_temp_map_mask = 0x07;
3686         } else {
3687                 data->pwm_temp_map_shift = 0;
3688                 data->pwm_temp_map_mask = 0x03;
3689         }
3690
3691         /*
3692          * For each PWM channel:
3693          * - If it is in automatic mode, setting to manual mode should set
3694          *   the fan to full speed by default.
3695          * - If it is in manual mode, we need a mapping to temperature
3696          *   channels to use when later setting to automatic mode later.
3697          *   Map to the first sensor by default (we are clueless.)
3698          * In both cases, the value can (and should) be changed by the user
3699          * prior to switching to a different mode.
3700          * Note that this is no longer needed for the IT8721F and later, as
3701          * these have separate registers for the temperature mapping and the
3702          * manual duty cycle.
3703          */
3704         for (i = 0; i < NUM_AUTO_PWM; i++) {
3705                 data->pwm_temp_map[i] = 0;
3706                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3707                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3708         }
3709
3710         /*
3711          * Some chips seem to have default value 0xff for all limit
3712          * registers. For low voltage limits it makes no sense and triggers
3713          * alarms, so change to 0 instead. For high temperature limits, it
3714          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3715          * but is still confusing, so change to 127 degrees C.
3716          */
3717         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3718                 tmp = data->read(data, IT87_REG_VIN_MIN(i));
3719                 if (tmp == 0xff)
3720                         data->write(data, IT87_REG_VIN_MIN(i), 0);
3721         }
3722         for (i = 0; i < data->num_temp_limit; i++) {
3723                 tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3724                 if (tmp == 0xff)
3725                         data->write(data, data->REG_TEMP_HIGH[i], 127);
3726         }
3727
3728         /*
3729          * Temperature channels are not forcibly enabled, as they can be
3730          * set to two different sensor types and we can't guess which one
3731          * is correct for a given system. These channels can be enabled at
3732          * run-time through the temp{1-3}_type sysfs accessors if needed.
3733          */
3734
3735         /* Check if voltage monitors are reset manually or by some reason */
3736         tmp = data->read(data, IT87_REG_VIN_ENABLE);
3737         if ((tmp & 0xff) == 0) {
3738                 /* Enable all voltage monitors */
3739                 data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3740         }
3741
3742         /* Check if tachometers are reset manually or by some reason */
3743         mask = 0x70 & ~(sio_data->skip_fan << 4);
3744         data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3745         if ((data->fan_main_ctrl & mask) == 0) {
3746                 /* Enable all fan tachometers */
3747                 data->fan_main_ctrl |= mask;
3748                 data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3749         }
3750         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3751
3752         tmp = data->read(data, IT87_REG_FAN_16BIT);
3753
3754         /* Set tachometers to 16-bit mode if needed */
3755         if (has_fan16_config(data)) {
3756                 if (~tmp & 0x07 & data->has_fan) {
3757                         dev_dbg(&pdev->dev,
3758                                 "Setting fan1-3 to 16-bit mode\n");
3759                         data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3760                 }
3761         }
3762
3763         /* Check for additional fans */
3764         if (has_four_fans(data) && (tmp & BIT(4)))
3765                 data->has_fan |= BIT(3); /* fan4 enabled */
3766         if (has_five_fans(data) && (tmp & BIT(5)))
3767                 data->has_fan |= BIT(4); /* fan5 enabled */
3768         if (has_six_fans(data)) {
3769                 switch (data->type) {
3770                 case it8620:
3771                 case it8628:
3772                 case it8686:
3773                         if (tmp & BIT(2))
3774                                 data->has_fan |= BIT(5); /* fan6 enabled */
3775                         break;
3776                 case it8625:
3777                 case it8665:
3778                         tmp = data->read(data, IT87_REG_FAN_DIV);
3779                         if (tmp & BIT(3))
3780                                 data->has_fan |= BIT(5); /* fan6 enabled */
3781                         break;
3782                 default:
3783                         break;
3784                 }
3785         }
3786
3787         /* Fan input pins may be used for alternative functions */
3788         data->has_fan &= ~sio_data->skip_fan;
3789
3790         /* Check if pwm6 is enabled */
3791         if (has_six_pwm(data)) {
3792                 switch (data->type) {
3793                 case it8620:
3794                 case it8686:
3795                         tmp = data->read(data, IT87_REG_FAN_DIV);
3796                         if (!(tmp & BIT(3)))
3797                                 sio_data->skip_pwm |= BIT(5);
3798                         break;
3799                 default:
3800                         break;
3801                 }
3802         }
3803
3804         if (has_bank_sel(data)) {
3805                 for (i = 0; i < 3; i++)
3806                         data->temp_src[i] =
3807                                 data->read(data, IT87_REG_TEMP_SRC1[i]);
3808                 data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3809         }
3810
3811         /* Start monitoring */
3812         data->write(data, IT87_REG_CONFIG,
3813                     (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3814                                         (update_vbat ? 0x41 : 0x01));
3815 }
3816
3817 /* Return 1 if and only if the PWM interface is safe to use */
3818 static int it87_check_pwm(struct device *dev)
3819 {
3820         struct it87_data *data = dev_get_drvdata(dev);
3821         /*
3822          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3823          * and polarity set to active low is sign that this is the case so we
3824          * disable pwm control to protect the user.
3825          */
3826         int tmp = data->read(data, IT87_REG_FAN_CTL);
3827
3828         if ((tmp & 0x87) == 0) {
3829                 if (fix_pwm_polarity) {
3830                         /*
3831                          * The user asks us to attempt a chip reconfiguration.
3832                          * This means switching to active high polarity and
3833                          * inverting all fan speed values.
3834                          */
3835                         int i;
3836                         u8 pwm[3];
3837
3838                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3839                                 pwm[i] = data->read(data,
3840                                                          data->REG_PWM[i]);
3841
3842                         /*
3843                          * If any fan is in automatic pwm mode, the polarity
3844                          * might be correct, as suspicious as it seems, so we
3845                          * better don't change anything (but still disable the
3846                          * PWM interface).
3847                          */
3848                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3849                                 dev_info(dev,
3850                                          "Reconfiguring PWM to active high polarity\n");
3851                                 data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3852                                 for (i = 0; i < 3; i++)
3853                                         data->write(data, data->REG_PWM[i],
3854                                                     0x7f & ~pwm[i]);
3855                                 return 1;
3856                         }
3857
3858                         dev_info(dev,
3859                                  "PWM configuration is too broken to be fixed\n");
3860                 }
3861
3862                 dev_info(dev,
3863                          "Detected broken BIOS defaults, disabling PWM interface\n");
3864                 return 0;
3865         } else if (fix_pwm_polarity) {
3866                 dev_info(dev,
3867                          "PWM configuration looks sane, won't touch\n");
3868         }
3869
3870         return 1;
3871 }
3872
3873 static int it87_probe(struct platform_device *pdev)
3874 {
3875         struct it87_data *data;
3876         struct resource *res;
3877         struct device *dev = &pdev->dev;
3878         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3879         int enable_pwm_interface;
3880         struct device *hwmon_dev;
3881         int err;
3882
3883         data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3884         if (!data)
3885                 return -ENOMEM;
3886
3887         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3888         if (!res)
3889                 return -EINVAL;
3890         if (res->flags & IORESOURCE_IO) {
3891                 if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3892                                          DRVNAME)) {
3893                         dev_err(dev, "Failed to request region %pR\n", res);
3894                         return -EBUSY;
3895                 }
3896         } else {
3897                 data->mmio = devm_ioremap_resource(dev, res);
3898                 if (IS_ERR(data->mmio))
3899                         return PTR_ERR(data->mmio);
3900         }
3901
3902         data->addr = res->start;
3903         data->type = sio_data->type;
3904         data->sioaddr = sio_data->sioaddr;
3905         data->smbus_bitmap = sio_data->smbus_bitmap;
3906         data->ec_special_config = sio_data->ec_special_config;
3907         data->doexit = sio_data->doexit;
3908         data->features = it87_devices[sio_data->type].features;
3909         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3910         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3911         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3912         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3913         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3914
3915         /*
3916          * IT8705F Datasheet 0.4.1, 3h == Version G.
3917          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3918          * These are the first revisions with 16-bit tachometer support.
3919          */
3920         switch (data->type) {
3921         case it87:
3922                 if (sio_data->revision >= 0x03) {
3923                         data->features &= ~FEAT_OLD_AUTOPWM;
3924                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3925                 }
3926                 break;
3927         case it8712:
3928                 if (sio_data->revision >= 0x08) {
3929                         data->features &= ~FEAT_OLD_AUTOPWM;
3930                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3931                                           FEAT_FIVE_FANS;
3932                 }
3933                 break;
3934         default:
3935                 break;
3936         }
3937
3938         platform_set_drvdata(pdev, data);
3939
3940         mutex_init(&data->update_lock);
3941
3942         /* Initialize register pointers */
3943         it87_init_regs(pdev);
3944
3945         err = smbus_disable(data);
3946         if (err)
3947                 return err;
3948
3949         /* Now, we do the remaining detection. */
3950         if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
3951             data->read(data, IT87_REG_CHIPID) != 0x90) {
3952                 smbus_enable(data);
3953                 return -ENODEV;
3954         }
3955
3956         /* Check PWM configuration */
3957         enable_pwm_interface = it87_check_pwm(dev);
3958
3959         /* Starting with IT8721F, we handle scaling of internal voltages */
3960         if (has_scaling(data)) {
3961                 if (sio_data->internal & BIT(0))
3962                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3963                 if (sio_data->internal & BIT(1))
3964                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3965                 if (sio_data->internal & BIT(2))
3966                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3967                 if (sio_data->internal & BIT(3))
3968                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3969         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3970                    sio_data->type == it8783) {
3971                 if (sio_data->internal & BIT(0))
3972                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3973                 if (sio_data->internal & BIT(1))
3974                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3975         }
3976
3977         data->has_temp = 0x07;
3978         if (sio_data->skip_temp & BIT(2)) {
3979                 if (sio_data->type == it8782 &&
3980                     !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
3981                         data->has_temp &= ~BIT(2);
3982         }
3983
3984         data->in_internal = sio_data->internal;
3985         data->has_in = 0x3ff & ~sio_data->skip_in;
3986
3987         if (has_six_temp(data)) {
3988                 u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
3989
3990                 /* Check for additional temperature sensors */
3991                 if ((reg & 0x03) >= 0x02)
3992                         data->has_temp |= BIT(3);
3993                 if (((reg >> 2) & 0x03) >= 0x02)
3994                         data->has_temp |= BIT(4);
3995                 if (((reg >> 4) & 0x03) >= 0x02)
3996                         data->has_temp |= BIT(5);
3997
3998                 /* Check for additional voltage sensors */
3999                 if ((reg & 0x03) == 0x01)
4000                         data->has_in |= BIT(10);
4001                 if (((reg >> 2) & 0x03) == 0x01)
4002                         data->has_in |= BIT(11);
4003                 if (((reg >> 4) & 0x03) == 0x01)
4004                         data->has_in |= BIT(12);
4005         }
4006
4007         data->has_beep = !!sio_data->beep_pin;
4008
4009         /* Initialize the IT87 chip */
4010         it87_init_device(pdev);
4011
4012         smbus_enable(data);
4013
4014         if (!sio_data->skip_vid) {
4015                 data->has_vid = true;
4016                 data->vrm = vid_which_vrm();
4017                 /* VID reading from Super-I/O config space if available */
4018                 data->vid = sio_data->vid_value;
4019         }
4020
4021         /* Prepare for sysfs hooks */
4022         data->groups[0] = &it87_group;
4023         data->groups[1] = &it87_group_in;
4024         data->groups[2] = &it87_group_temp;
4025         data->groups[3] = &it87_group_fan;
4026
4027         if (enable_pwm_interface) {
4028                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
4029                 data->has_pwm &= ~sio_data->skip_pwm;
4030
4031                 data->groups[4] = &it87_group_pwm;
4032                 if (has_old_autopwm(data) || has_newer_autopwm(data))
4033                         data->groups[5] = &it87_group_auto_pwm;
4034         }
4035
4036         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
4037                                         it87_devices[sio_data->type].name,
4038                                         data, data->groups);
4039         return PTR_ERR_OR_ZERO(hwmon_dev);
4040 }
4041
4042 static struct platform_driver it87_driver = {
4043         .driver = {
4044                 .name   = DRVNAME,
4045         },
4046         .probe  = it87_probe,
4047 };
4048
4049 static int __init it87_device_add(int index, unsigned short sio_address,
4050                                   phys_addr_t mmio_address,
4051                                   const struct it87_sio_data *sio_data)
4052 {
4053         struct platform_device *pdev;
4054         struct resource res = {
4055                 .name   = DRVNAME,
4056         };
4057         int err;
4058
4059         if (mmio_address) {
4060                 res.start = mmio_address;
4061                 res.end = mmio_address + 0x400 - 1;
4062                 res.flags = IORESOURCE_MEM;
4063         } else {
4064                 res.start = sio_address + IT87_EC_OFFSET;
4065                 res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
4066                 res.flags = IORESOURCE_IO;
4067         }
4068
4069         err = acpi_check_resource_conflict(&res);
4070         if (err) {
4071                 if (!ignore_resource_conflict)
4072                         return err;
4073         }
4074
4075         pdev = platform_device_alloc(DRVNAME, sio_address);
4076         if (!pdev)
4077                 return -ENOMEM;
4078
4079         err = platform_device_add_resources(pdev, &res, 1);
4080         if (err) {
4081                 pr_err("Device resource addition failed (%d)\n", err);
4082                 goto exit_device_put;
4083         }
4084
4085         err = platform_device_add_data(pdev, sio_data,
4086                                        sizeof(struct it87_sio_data));
4087         if (err) {
4088                 pr_err("Platform data allocation failed\n");
4089                 goto exit_device_put;
4090         }
4091
4092         err = platform_device_add(pdev);
4093         if (err) {
4094                 pr_err("Device addition failed (%d)\n", err);
4095                 goto exit_device_put;
4096         }
4097
4098         it87_pdev[index] = pdev;
4099         return 0;
4100
4101 exit_device_put:
4102         platform_device_put(pdev);
4103         return err;
4104 }
4105
4106 struct it87_dmi_data {
4107         bool sio2_force_config; /* force sio2 into configuration mode   */
4108         u8 skip_pwm;            /* pwm channels to skip for this board  */
4109 };
4110
4111 /*
4112  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4113  * (IT8792E) needs to be in configuration mode before accessing the first
4114  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4115  * This needs to be done before accessing the first Super-IO chip since
4116  * the second chip may have been accessed prior to loading this driver.
4117  *
4118  * The problem is also reported to affect IT8795E, which is used on X299 boards
4119  * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4120  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4121  * Z87X-OC.
4122  * DMI entries for those systems will be added as they become available and
4123  * as the problem is confirmed to affect those boards.
4124  */
4125 static struct it87_dmi_data gigabyte_sio2_force = {
4126         .sio2_force_config = true,
4127 };
4128
4129 /*
4130  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4131  * connected to a fan, but to something else. One user
4132  * has reported instant system power-off when changing
4133  * the PWM2 duty cycle, so we disable it.
4134  * I use the board name string as the trigger in case
4135  * the same board is ever used in other systems.
4136  */
4137 static struct it87_dmi_data nvidia_fn68pt = {
4138         .skip_pwm = BIT(1),
4139 };
4140
4141 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4142         {
4143                 .matches = {
4144                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4145                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4146                 },
4147                 .driver_data = &gigabyte_sio2_force,
4148         },
4149         {
4150                 .matches = {
4151                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4152                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4153                 },
4154                 .driver_data = &gigabyte_sio2_force,
4155         },
4156         {
4157                 .matches = {
4158                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4159                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4160                 },
4161                 .driver_data = &gigabyte_sio2_force,
4162         },
4163         {
4164                 .matches = {
4165                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4166                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4167                 },
4168                 .driver_data = &nvidia_fn68pt,
4169         },
4170         { }
4171 };
4172
4173 static int __init sm_it87_init(void)
4174 {
4175         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4176         struct it87_dmi_data *dmi_data = NULL;
4177         int sioaddr[2] = { REG_2E, REG_4E };
4178         struct it87_sio_data sio_data;
4179         unsigned short isa_address;
4180         phys_addr_t mmio_address;
4181         bool found = false;
4182         int i, err;
4183
4184         pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4185
4186         if (dmi)
4187                 dmi_data = dmi->driver_data;
4188
4189         err = platform_driver_register(&it87_driver);
4190         if (err)
4191                 return err;
4192
4193         if (dmi_data && dmi_data->sio2_force_config)
4194                 __superio_enter(REG_4E);
4195
4196         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4197                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4198                 isa_address = 0;
4199                 mmio_address = 0;
4200                 err = it87_find(sioaddr[i], &isa_address, &mmio_address,
4201                                 &sio_data);
4202                 if (err || isa_address == 0)
4203                         continue;
4204
4205                 if (dmi_data)
4206                         sio_data.skip_pwm |= dmi_data->skip_pwm;
4207                 err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4208                 if (err)
4209                         goto exit_dev_unregister;
4210                 found = true;
4211         }
4212
4213         if (!found) {
4214                 err = -ENODEV;
4215                 goto exit_unregister;
4216         }
4217         return 0;
4218
4219 exit_dev_unregister:
4220         /* NULL check handled by platform_device_unregister */
4221         platform_device_unregister(it87_pdev[0]);
4222 exit_unregister:
4223         platform_driver_unregister(&it87_driver);
4224         return err;
4225 }
4226
4227 static void __exit sm_it87_exit(void)
4228 {
4229         /* NULL check handled by platform_device_unregister */
4230         platform_device_unregister(it87_pdev[1]);
4231         platform_device_unregister(it87_pdev[0]);
4232         platform_driver_unregister(&it87_driver);
4233 }
4234
4235 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4236 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4237 module_param(update_vbat, bool, 0);
4238 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4239 module_param(fix_pwm_polarity, bool, 0);
4240 MODULE_PARM_DESC(fix_pwm_polarity,
4241                  "Force PWM polarity to active high (DANGEROUS)");
4242 MODULE_LICENSE("GPL");
4243
4244 module_init(sm_it87_init);
4245 module_exit(sm_it87_exit);