git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77 #include "version.h"
  78
  79 #define DRVNAME "it87"
  80
  81 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  82              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  83              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  84              it8655, it8665, it8686 };
  85
  86 static unsigned short force_id;
  87 module_param(force_id, ushort, 0);
  88 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  89
  90 static bool ignore_resource_conflict;
  91 module_param(ignore_resource_conflict, bool, 0);
  92 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
  93
  94 static struct platform_device *it87_pdev[2];
  95
  96 #define REG_2E  0x2e    /* The register to read/write */
  97 #define REG_4E  0x4e    /* Secondary register to read/write */
  98
  99 #define DEV     0x07    /* Register: Logical device select */
 100 #define PME     0x04    /* The device with the fan registers in it */
 101
 102 /* The device with the IT8718F/IT8720F VID value in it */
 103 #define GPIO    0x07
 104
 105 #define DEVID   0x20    /* Register: Device ID */
 106 #define DEVREV  0x22    /* Register: Device Revision */
 107
 108 static inline void __superio_enter(int ioreg)
 109 {
 110         outb(0x87, ioreg);
 111         outb(0x01, ioreg);
 112         outb(0x55, ioreg);
 113         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 114 }
 115
 116 static inline int superio_inb(int ioreg, int reg)
 117 {
 118         int val;
 119
 120         outb(reg, ioreg);
 121         val = inb(ioreg + 1);
 122
 123         return val;
 124 }
 125
 126 static inline void superio_outb(int ioreg, int reg, int val)
 127 {
 128         outb(reg, ioreg);
 129         outb(val, ioreg + 1);
 130 }
 131
 132 static int superio_inw(int ioreg, int reg)
 133 {
 134         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 135 }
 136
 137 static inline void superio_select(int ioreg, int ldn)
 138 {
 139         outb(DEV, ioreg);
 140         outb(ldn, ioreg + 1);
 141 }
 142
 143 static inline int superio_enter(int ioreg)
 144 {
 145         /*
 146          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 147          */
 148         if (!request_muxed_region(ioreg, 2, DRVNAME))
 149                 return -EBUSY;
 150
 151         __superio_enter(ioreg);
 152         return 0;
 153 }
 154
 155 static inline void superio_exit(int ioreg, bool doexit)
 156 {
 157         if (doexit) {
 158                 outb(0x02, ioreg);
 159                 outb(0x02, ioreg + 1);
 160         }
 161         release_region(ioreg, 2);
 162 }
 163
 164 /* Logical device 4 registers */
 165 #define IT8712F_DEVID 0x8712
 166 #define IT8705F_DEVID 0x8705
 167 #define IT8716F_DEVID 0x8716
 168 #define IT8718F_DEVID 0x8718
 169 #define IT8720F_DEVID 0x8720
 170 #define IT8721F_DEVID 0x8721
 171 #define IT8726F_DEVID 0x8726
 172 #define IT8728F_DEVID 0x8728
 173 #define IT8732F_DEVID 0x8732
 174 #define IT8792E_DEVID 0x8733
 175 #define IT8771E_DEVID 0x8771
 176 #define IT8772E_DEVID 0x8772
 177 #define IT8781F_DEVID 0x8781
 178 #define IT8782F_DEVID 0x8782
 179 #define IT8783E_DEVID 0x8783
 180 #define IT8786E_DEVID 0x8786
 181 #define IT8790E_DEVID 0x8790
 182 #define IT8603E_DEVID 0x8603
 183 #define IT8607E_DEVID 0x8607
 184 #define IT8613E_DEVID 0x8613
 185 #define IT8620E_DEVID 0x8620
 186 #define IT8622E_DEVID 0x8622
 187 #define IT8623E_DEVID 0x8623
 188 #define IT8625E_DEVID 0x8625
 189 #define IT8628E_DEVID 0x8628
 190 #define IT8655E_DEVID 0x8655
 191 #define IT8665E_DEVID 0x8665
 192 #define IT8686E_DEVID 0x8686
 193
 194 /* Logical device 4 (Environmental Monitor) registers */
 195 #define IT87_ACT_REG            0x30
 196 #define IT87_BASE_REG           0x60
 197 #define IT87_SPECIAL_CFG_REG    0xf3    /* special configuration register */
 198
 199 /* Logical device 7 (GPIO) registers (IT8712F and later) */
 200 #define IT87_SIO_GPIO1_REG      0x25
 201 #define IT87_SIO_GPIO2_REG      0x26
 202 #define IT87_SIO_GPIO3_REG      0x27
 203 #define IT87_SIO_GPIO4_REG      0x28
 204 #define IT87_SIO_GPIO5_REG      0x29
 205 #define IT87_SIO_GPIO9_REG      0xd3
 206 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 207 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 208 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 209 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 210 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 211 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 212
 213 /* Update battery voltage after every reading if true */
 214 static bool update_vbat;
 215
 216 /* Not all BIOSes properly configure the PWM registers */
 217 static bool fix_pwm_polarity;
 218
 219 /* Many IT87 constants specified below */
 220
 221 /* Length of ISA address segment */
 222 #define IT87_EXTENT 8
 223
 224 /* Length of ISA address segment for Environmental Controller */
 225 #define IT87_EC_EXTENT 2
 226
 227 /* Offset of EC registers from ISA base address */
 228 #define IT87_EC_OFFSET 5
 229
 230 /* Where are the ISA address/data registers relative to the EC base address */
 231 #define IT87_ADDR_REG_OFFSET 0
 232 #define IT87_DATA_REG_OFFSET 1
 233
 234 /*----- The IT87 registers -----*/
 235
 236 #define IT87_REG_CONFIG        0x00
 237
 238 #define IT87_REG_ALARM1        0x01
 239 #define IT87_REG_ALARM2        0x02
 240 #define IT87_REG_ALARM3        0x03
 241
 242 #define IT87_REG_BANK           0x06
 243
 244 /*
 245  * The IT8718F and IT8720F have the VID value in a different register, in
 246  * Super-I/O configuration space.
 247  */
 248 #define IT87_REG_VID           0x0a
 249 /*
 250  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 251  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 252  * mode.
 253  */
 254 #define IT87_REG_FAN_DIV       0x0b
 255 #define IT87_REG_FAN_16BIT     0x0c
 256
 257 /*
 258  * Monitors:
 259  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 260  * - up to 6 temp (1 to 6)
 261  * - up to 6 fan (1 to 6)
 262  */
 263
 264 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 265 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 266 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 267 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 268
 269 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 270 static const u8 IT87_REG_FAN_MIN_8665[] =
 271                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 272 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 273 static const u8 IT87_REG_FANX_MIN_8665[] =
 274                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 275
 276 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 277
 278 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 279
 280 #define IT87_REG_FAN_MAIN_CTRL 0x13
 281 #define IT87_REG_FAN_CTL       0x14
 282
 283 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 284 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 285
 286 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 287
 288 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 289                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 290
 291 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 292
 293 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 294 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 295
 296 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 297 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 298
 299 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 300                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 301 static const u8 IT87_REG_TEMP_LOW_8686[] =
 302                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 303
 304 #define IT87_REG_VIN_ENABLE    0x50
 305 #define IT87_REG_TEMP_ENABLE   0x51
 306 #define IT87_REG_TEMP_EXTRA    0x55
 307 #define IT87_REG_BEEP_ENABLE   0x5c
 308
 309 #define IT87_REG_CHIPID        0x58
 310
 311 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 312
 313 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 314 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 315
 316 #define IT87_REG_TEMP456_ENABLE 0x77
 317
 318 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 319 #define IT87_REG_TEMP_SRC2      0x23d
 320
 321 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 322 #define NUM_VIN_LIMIT           8
 323 #define NUM_TEMP                6
 324 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 325 #define NUM_FAN_DIV             3
 326 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 327 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 328
 329 struct it87_devices {
 330         const char *name;
 331         const char * const suffix;
 332         u32 features;
 333         u8 num_temp_limit;
 334         u8 num_temp_offset;
 335         u8 num_temp_map;        /* Number of temperature sources for pwm */
 336         u8 peci_mask;
 337         u8 old_peci_mask;
 338         u8 smbus_bitmap;        /* SMBus enable bits in extra config register */
 339         u8 ec_special_config;
 340 };
 341
 342 #define FEAT_12MV_ADC           BIT(0)
 343 #define FEAT_NEWER_AUTOPWM      BIT(1)
 344 #define FEAT_OLD_AUTOPWM        BIT(2)
 345 #define FEAT_16BIT_FANS         BIT(3)
 346 #define FEAT_TEMP_PECI          BIT(5)
 347 #define FEAT_TEMP_OLD_PECI      BIT(6)
 348 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 349 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 350 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 351 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 352 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 353 #define FEAT_10_9MV_ADC         BIT(12)
 354 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 355 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 356 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 357 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 358 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 359 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 360 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 361 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 362 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 363 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 364 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 365 #define FEAT_11MV_ADC           BIT(24)
 366 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 367
 368 static const struct it87_devices it87_devices[] = {
 369         [it87] = {
 370                 .name = "it87",
 371                 .suffix = "F",
 372                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 373                                                 /* may need to overwrite */
 374                 .num_temp_limit = 3,
 375                 .num_temp_offset = 0,
 376                 .num_temp_map = 3,
 377         },
 378         [it8712] = {
 379                 .name = "it8712",
 380                 .suffix = "F",
 381                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 382                                                 /* may need to overwrite */
 383                 .num_temp_limit = 3,
 384                 .num_temp_offset = 0,
 385                 .num_temp_map = 3,
 386         },
 387         [it8716] = {
 388                 .name = "it8716",
 389                 .suffix = "F",
 390                 .features = FEAT_16BIT_FANS | FEAT_VID
 391                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 392                   | FEAT_FANCTL_ONOFF,
 393                 .num_temp_limit = 3,
 394                 .num_temp_offset = 3,
 395                 .num_temp_map = 3,
 396         },
 397         [it8718] = {
 398                 .name = "it8718",
 399                 .suffix = "F",
 400                 .features = FEAT_16BIT_FANS | FEAT_VID
 401                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 402                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 403                 .num_temp_limit = 3,
 404                 .num_temp_offset = 3,
 405                 .num_temp_map = 3,
 406                 .old_peci_mask = 0x4,
 407         },
 408         [it8720] = {
 409                 .name = "it8720",
 410                 .suffix = "F",
 411                 .features = FEAT_16BIT_FANS | FEAT_VID
 412                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 413                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 414                 .num_temp_limit = 3,
 415                 .num_temp_offset = 3,
 416                 .num_temp_map = 3,
 417                 .old_peci_mask = 0x4,
 418         },
 419         [it8721] = {
 420                 .name = "it8721",
 421                 .suffix = "F",
 422                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 423                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 424                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 425                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 426                 .num_temp_limit = 3,
 427                 .num_temp_offset = 3,
 428                 .num_temp_map = 3,
 429                 .peci_mask = 0x05,
 430                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 431         },
 432         [it8728] = {
 433                 .name = "it8728",
 434                 .suffix = "F",
 435                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 436                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 437                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 438                   | FEAT_FANCTL_ONOFF,
 439                 .num_temp_limit = 6,
 440                 .num_temp_offset = 3,
 441                 .num_temp_map = 3,
 442                 .peci_mask = 0x07,
 443         },
 444         [it8732] = {
 445                 .name = "it8732",
 446                 .suffix = "F",
 447                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 448                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 449                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 450                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 451                 .num_temp_limit = 3,
 452                 .num_temp_offset = 3,
 453                 .num_temp_map = 3,
 454                 .peci_mask = 0x07,
 455                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 456         },
 457         [it8771] = {
 458                 .name = "it8771",
 459                 .suffix = "E",
 460                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 461                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 462                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 463                                 /* PECI: guesswork */
 464                                 /* 12mV ADC (OHM) */
 465                                 /* 16 bit fans (OHM) */
 466                                 /* three fans, always 16 bit (guesswork) */
 467                 .num_temp_limit = 3,
 468                 .num_temp_offset = 3,
 469                 .num_temp_map = 3,
 470                 .peci_mask = 0x07,
 471         },
 472         [it8772] = {
 473                 .name = "it8772",
 474                 .suffix = "E",
 475                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 476                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 477                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 478                                 /* PECI (coreboot) */
 479                                 /* 12mV ADC (HWSensors4, OHM) */
 480                                 /* 16 bit fans (HWSensors4, OHM) */
 481                                 /* three fans, always 16 bit (datasheet) */
 482                 .num_temp_limit = 3,
 483                 .num_temp_offset = 3,
 484                 .num_temp_map = 3,
 485                 .peci_mask = 0x07,
 486         },
 487         [it8781] = {
 488                 .name = "it8781",
 489                 .suffix = "F",
 490                 .features = FEAT_16BIT_FANS
 491                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 492                   | FEAT_FANCTL_ONOFF,
 493                 .num_temp_limit = 3,
 494                 .num_temp_offset = 3,
 495                 .num_temp_map = 3,
 496                 .old_peci_mask = 0x4,
 497         },
 498         [it8782] = {
 499                 .name = "it8782",
 500                 .suffix = "F",
 501                 .features = FEAT_16BIT_FANS
 502                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 503                   | FEAT_FANCTL_ONOFF,
 504                 .num_temp_limit = 3,
 505                 .num_temp_offset = 3,
 506                 .num_temp_map = 3,
 507                 .old_peci_mask = 0x4,
 508         },
 509         [it8783] = {
 510                 .name = "it8783",
 511                 .suffix = "E/F",
 512                 .features = FEAT_16BIT_FANS
 513                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 514                   | FEAT_FANCTL_ONOFF,
 515                 .num_temp_limit = 3,
 516                 .num_temp_offset = 3,
 517                 .num_temp_map = 3,
 518                 .old_peci_mask = 0x4,
 519         },
 520         [it8786] = {
 521                 .name = "it8786",
 522                 .suffix = "E",
 523                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 524                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 525                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 526                 .num_temp_limit = 3,
 527                 .num_temp_offset = 3,
 528                 .num_temp_map = 3,
 529                 .peci_mask = 0x07,
 530         },
 531         [it8790] = {
 532                 .name = "it8790",
 533                 .suffix = "E",
 534                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 535                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 536                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 537                 .num_temp_limit = 3,
 538                 .num_temp_offset = 3,
 539                 .num_temp_map = 3,
 540                 .peci_mask = 0x07,
 541         },
 542         [it8792] = {
 543                 .name = "it8792",
 544                 .suffix = "E",
 545                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 546                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 547                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 548                 .num_temp_limit = 3,
 549                 .num_temp_offset = 3,
 550                 .num_temp_map = 3,
 551                 .peci_mask = 0x07,
 552         },
 553         [it8603] = {
 554                 .name = "it8603",
 555                 .suffix = "E",
 556                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 557                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 558                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 559                 .num_temp_limit = 3,
 560                 .num_temp_offset = 3,
 561                 .num_temp_map = 4,
 562                 .peci_mask = 0x07,
 563         },
 564         [it8607] = {
 565                 .name = "it8607",
 566                 .suffix = "E",
 567                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 568                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 569                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 570                   | FEAT_FANCTL_ONOFF,
 571                 .num_temp_limit = 3,
 572                 .num_temp_offset = 3,
 573                 .num_temp_map = 6,
 574                 .peci_mask = 0x07,
 575         },
 576         [it8613] = {
 577                 .name = "it8613",
 578                 .suffix = "E",
 579                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 580                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 581                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 582                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 583                 .num_temp_limit = 6,
 584                 .num_temp_offset = 6,
 585                 .num_temp_map = 6,
 586                 .peci_mask = 0x07,
 587         },
 588         [it8620] = {
 589                 .name = "it8620",
 590                 .suffix = "E",
 591                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 592                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 593                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 594                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 595                   | FEAT_FANCTL_ONOFF,
 596                 .num_temp_limit = 3,
 597                 .num_temp_offset = 3,
 598                 .num_temp_map = 3,
 599                 .peci_mask = 0x07,
 600         },
 601         [it8622] = {
 602                 .name = "it8622",
 603                 .suffix = "E",
 604                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 605                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 606                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 607                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 608                 .num_temp_limit = 3,
 609                 .num_temp_offset = 3,
 610                 .num_temp_map = 4,
 611                 .peci_mask = 0x07,
 612         },
 613         [it8625] = {
 614                 .name = "it8625",
 615                 .suffix = "E",
 616                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 617                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 618                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 619                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 620                 .num_temp_limit = 6,
 621                 .num_temp_offset = 6,
 622                 .num_temp_map = 6,
 623                 .smbus_bitmap = BIT(1) | BIT(2),
 624         },
 625         [it8628] = {
 626                 .name = "it8628",
 627                 .suffix = "E",
 628                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 629                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 630                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 631                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 632                   | FEAT_FANCTL_ONOFF,
 633                 .num_temp_limit = 6,
 634                 .num_temp_offset = 3,
 635                 .num_temp_map = 3,
 636                 .peci_mask = 0x07,
 637         },
 638         [it8655] = {
 639                 .name = "it8655",
 640                 .suffix = "E",
 641                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 642                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 643                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 644                 .num_temp_limit = 6,
 645                 .num_temp_offset = 6,
 646                 .num_temp_map = 6,
 647                 .smbus_bitmap = BIT(2),
 648         },
 649         [it8665] = {
 650                 .name = "it8665",
 651                 .suffix = "E",
 652                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 653                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 654                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 655                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 656                 .num_temp_limit = 6,
 657                 .num_temp_offset = 6,
 658                 .num_temp_map = 6,
 659                 .smbus_bitmap = BIT(2),
 660         },
 661         [it8686] = {
 662                 .name = "it8686",
 663                 .suffix = "E",
 664                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 665                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 666                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 667                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 668                 .num_temp_limit = 6,
 669                 .num_temp_offset = 6,
 670                 .num_temp_map = 7,
 671                 .smbus_bitmap = BIT(1) | BIT(2),
 672         },
 673 };
 674
 675 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 676 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 677 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 678 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 679 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 680 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 681                                  ((data)->peci_mask & BIT(nr)))
 682 #define has_temp_old_peci(data, nr) \
 683                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 684                                  ((data)->old_peci_mask & BIT(nr)))
 685 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 686 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 687                                                      FEAT_SIX_FANS))
 688 #define has_vid(data)           ((data)->features & FEAT_VID)
 689 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 690 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 691 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 692 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 693                                                      | FEAT_SIX_PWM))
 694 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 695 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 696 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 697 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 698 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 699                                                      FEAT_FIVE_FANS | \
 700                                                      FEAT_SIX_FANS))
 701 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 702                                                      FEAT_FIVE_PWM \
 703                                                      | FEAT_SIX_PWM))
 704 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 705 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 706 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 707 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 708 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 709
 710 struct it87_sio_data {
 711         enum chips type;
 712         u8 sioaddr;
 713         u8 doexit;
 714         /* Values read from Super-I/O config space */
 715         u8 revision;
 716         u8 vid_value;
 717         u8 beep_pin;
 718         u8 internal;    /* Internal sensors can be labeled */
 719         /* Features skipped based on config or DMI */
 720         u16 skip_in;
 721         u8 skip_vid;
 722         u8 skip_fan;
 723         u8 skip_pwm;
 724         u8 skip_temp;
 725         u8 smbus_bitmap;
 726         u8 ec_special_config;
 727 };
 728
 729 /*
 730  * For each registered chip, we need to keep some data in memory.
 731  * The structure is dynamically allocated.
 732  */
 733 struct it87_data {
 734         const struct attribute_group *groups[7];
 735         enum chips type;
 736         u32 features;
 737         u8 peci_mask;
 738         u8 old_peci_mask;
 739
 740         u8 smbus_bitmap;        /* !=0 if SMBus needs to be disabled */
 741         u8 ec_special_config;   /* EC special config register restore value */
 742         u8 sioaddr;             /* SIO port address */
 743         bool doexit;            /* true if exit from sio config is ok */
 744
 745         const u8 *REG_FAN;
 746         const u8 *REG_FANX;
 747         const u8 *REG_FAN_MIN;
 748         const u8 *REG_FANX_MIN;
 749
 750         const u8 *REG_PWM;
 751
 752         const u8 *REG_TEMP_OFFSET;
 753         const u8 *REG_TEMP_LOW;
 754         const u8 *REG_TEMP_HIGH;
 755
 756         unsigned short addr;
 757         const char *name;
 758         struct mutex update_lock;
 759         char valid;             /* !=0 if following fields are valid */
 760         unsigned long last_updated;     /* In jiffies */
 761
 762         u16 in_scaled;          /* Internal voltage sensors are scaled */
 763         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 764         u16 has_in;             /* Bitfield, voltage sensors enabled */
 765         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 766         u8 has_fan;             /* Bitfield, fans enabled */
 767         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 768         u8 has_temp;            /* Bitfield, temp sensors enabled */
 769         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 770         u8 num_temp_limit;      /* Number of temperature limit registers */
 771         u8 num_temp_offset;     /* Number of temperature offset registers */
 772         u8 temp_src[4];         /* Up to 4 temperature source registers */
 773         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 774         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 775         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 776         bool has_vid;           /* True if VID supported */
 777         u8 vid;                 /* Register encoding, combined */
 778         u8 vrm;
 779         u32 alarms;             /* Register encoding, combined */
 780         bool has_beep;          /* true if beep supported */
 781         u8 beeps;               /* Register encoding */
 782         u8 fan_main_ctrl;       /* Register value */
 783         u8 fan_ctl;             /* Register value */
 784
 785         /*
 786          * The following 3 arrays correspond to the same registers up to
 787          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 788          * 7, and we want to preserve settings on mode changes, so we have
 789          * to track all values separately.
 790          * Starting with the IT8721F, the manual PWM duty cycles are stored
 791          * in separate registers (8-bit values), so the separate tracking
 792          * is no longer needed, but it is still done to keep the driver
 793          * simple.
 794          */
 795         u8 has_pwm;             /* Bitfield, pwm control enabled */
 796         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 797         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 798         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 799         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 800         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 801         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 802
 803         /* Automatic fan speed control registers */
 804         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 805         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 806 };
 807
 808 static int adc_lsb(const struct it87_data *data, int nr)
 809 {
 810         int lsb;
 811
 812         if (has_12mv_adc(data))
 813                 lsb = 120;
 814         else if (has_10_9mv_adc(data))
 815                 lsb = 109;
 816         else if (has_11mv_adc(data))
 817                 lsb = 110;
 818         else
 819                 lsb = 160;
 820         if (data->in_scaled & BIT(nr))
 821                 lsb <<= 1;
 822         return lsb;
 823 }
 824
 825 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 826 {
 827         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 828         return clamp_val(val, 0, 255);
 829 }
 830
 831 static int in_from_reg(const struct it87_data *data, int nr, int val)
 832 {
 833         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 834 }
 835
 836 static inline u8 FAN_TO_REG(long rpm, int div)
 837 {
 838         if (rpm == 0)
 839                 return 255;
 840         rpm = clamp_val(rpm, 1, 1000000);
 841         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 842 }
 843
 844 static inline u16 FAN16_TO_REG(long rpm)
 845 {
 846         if (rpm == 0)
 847                 return 0xffff;
 848         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 849 }
 850
 851 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 852                                 1350000 / ((val) * (div)))
 853 /* The divider is fixed to 2 in 16-bit mode */
 854 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 855                              1350000 / ((val) * 2))
 856
 857 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 858                                     ((val) + 500) / 1000), -128, 127))
 859 #define TEMP_FROM_REG(val) ((val) * 1000)
 860
 861 static u8 pwm_to_reg(const struct it87_data *data, long val)
 862 {
 863         if (has_newer_autopwm(data))
 864                 return val;
 865         else
 866                 return val >> 1;
 867 }
 868
 869 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 870 {
 871         if (has_newer_autopwm(data))
 872                 return reg;
 873         else
 874                 return (reg & 0x7f) << 1;
 875 }
 876
 877 static int DIV_TO_REG(int val)
 878 {
 879         int answer = 0;
 880
 881         while (answer < 7 && (val >>= 1))
 882                 answer++;
 883         return answer;
 884 }
 885
 886 #define DIV_FROM_REG(val) BIT(val)
 887
 888 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 889 {
 890         u8 map;
 891
 892         map  = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 893         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 894                 map = 0;
 895
 896         return map;
 897 }
 898
 899 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 900 {
 901         u8 ctrl = data->pwm_ctrl[nr];
 902
 903         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 904                (map << data->pwm_temp_map_shift);
 905 }
 906
 907 /*
 908  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 909  * depending on the chip type, to calculate the actual PWM frequency.
 910  *
 911  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 912  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 913  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 914  * sometimes just one. It is unknown if this is a datasheet error or real,
 915  * so this is ignored for now.
 916  */
 917 static const unsigned int pwm_freq[8] = {
 918         48000000,
 919         24000000,
 920         12000000,
 921         8000000,
 922         6000000,
 923         3000000,
 924         1500000,
 925         750000,
 926 };
 927
 928 static int smbus_disable(struct it87_data *data)
 929 {
 930         int err;
 931
 932         if (data->smbus_bitmap) {
 933                 err = superio_enter(data->sioaddr);
 934                 if (err)
 935                         return err;
 936                 superio_select(data->sioaddr, PME);
 937                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 938                              data->ec_special_config & ~data->smbus_bitmap);
 939                 superio_exit(data->sioaddr, data->doexit);
 940         }
 941         return 0;
 942 }
 943
 944 static int smbus_enable(struct it87_data *data)
 945 {
 946         int err;
 947
 948         if (data->smbus_bitmap) {
 949                 err = superio_enter(data->sioaddr);
 950                 if (err)
 951                         return err;
 952
 953                 superio_select(data->sioaddr, PME);
 954                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 955                              data->ec_special_config);
 956                 superio_exit(data->sioaddr, data->doexit);
 957         }
 958         return 0;
 959 }
 960
 961 static int _it87_read_value(struct it87_data *data, u8 reg)
 962 {
 963         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 964         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 965 }
 966
 967 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 968 {
 969         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 970         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 971 }
 972
 973 static u8 it87_set_bank(struct it87_data *data, u8 bank)
 974 {
 975         u8 _bank = bank;
 976
 977         if (has_bank_sel(data)) {
 978                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 979
 980                 _bank = breg >> 5;
 981                 if (bank != _bank) {
 982                         breg &= 0x1f;
 983                         breg |= (bank << 5);
 984                         _it87_write_value(data, IT87_REG_BANK, breg);
 985                 }
 986         }
 987         return _bank;
 988 }
 989
 990 /*
 991  * Must be called with data->update_lock held, except during initialization.
 992  * Must be called with SMBus accesses disabled.
 993  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 994  * would slow down the IT87 access and should not be necessary.
 995  */
 996 static int it87_read_value(struct it87_data *data, u16 reg)
 997 {
 998         u8 bank;
 999         int val;
1000
1001         bank = it87_set_bank(data, reg >> 8);
1002         val = _it87_read_value(data, reg & 0xff);
1003         it87_set_bank(data, bank);
1004
1005         return val;
1006 }
1007
1008 /*
1009  * Must be called with data->update_lock held, except during initialization.
1010  * Must be called with SMBus accesses disabled
1011  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1012  * would slow down the IT87 access and should not be necessary.
1013  */
1014 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
1015 {
1016         u8 bank;
1017
1018         bank = it87_set_bank(data, reg >> 8);
1019         _it87_write_value(data, reg & 0xff, value);
1020         it87_set_bank(data, bank);
1021 }
1022
1023 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1024 {
1025         u8 ctrl;
1026
1027         ctrl = it87_read_value(data, data->REG_PWM[nr]);
1028         data->pwm_ctrl[nr] = ctrl;
1029         if (has_newer_autopwm(data)) {
1030                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1031                 data->pwm_duty[nr] = it87_read_value(data,
1032                                                      IT87_REG_PWM_DUTY[nr]);
1033         } else {
1034                 if (ctrl & 0x80)        /* Automatic mode */
1035                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1036                 else                            /* Manual mode */
1037                         data->pwm_duty[nr] = ctrl & 0x7f;
1038         }
1039
1040         if (has_old_autopwm(data)) {
1041                 int i;
1042
1043                 for (i = 0; i < 5 ; i++)
1044                         data->auto_temp[nr][i] = it87_read_value(data,
1045                                                 IT87_REG_AUTO_TEMP(nr, i));
1046                 for (i = 0; i < 3 ; i++)
1047                         data->auto_pwm[nr][i] = it87_read_value(data,
1048                                                 IT87_REG_AUTO_PWM(nr, i));
1049         } else if (has_newer_autopwm(data)) {
1050                 int i;
1051
1052                 /*
1053                  * 0: temperature hysteresis (base + 5)
1054                  * 1: fan off temperature (base + 0)
1055                  * 2: fan start temperature (base + 1)
1056                  * 3: fan max temperature (base + 2)
1057                  */
1058                 data->auto_temp[nr][0] =
1059                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
1060
1061                 for (i = 0; i < 3 ; i++)
1062                         data->auto_temp[nr][i + 1] =
1063                                 it87_read_value(data,
1064                                                 IT87_REG_AUTO_TEMP(nr, i));
1065                 /*
1066                  * 0: start pwm value (base + 3)
1067                  * 1: pwm slope (base + 4, 1/8th pwm)
1068                  */
1069                 data->auto_pwm[nr][0] =
1070                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
1071                 data->auto_pwm[nr][1] =
1072                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
1073         }
1074 }
1075
1076 static int it87_lock(struct it87_data *data)
1077 {
1078         int err;
1079
1080         mutex_lock(&data->update_lock);
1081         err = smbus_disable(data);
1082         if (err)
1083                 mutex_unlock(&data->update_lock);
1084         return err;
1085 }
1086
1087 static void it87_unlock(struct it87_data *data)
1088 {
1089         smbus_enable(data);
1090         mutex_unlock(&data->update_lock);
1091 }
1092
1093 static struct it87_data *it87_update_device(struct device *dev)
1094 {
1095         struct it87_data *data = dev_get_drvdata(dev);
1096         int err;
1097         int i;
1098
1099         err = it87_lock(data);
1100         if (err)
1101                 return ERR_PTR(err);
1102
1103         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1104             !data->valid) {
1105                 if (update_vbat) {
1106                         /*
1107                          * Cleared after each update, so reenable.  Value
1108                          * returned by this read will be previous value
1109                          */
1110                         it87_write_value(data, IT87_REG_CONFIG,
1111                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1112                 }
1113                 for (i = 0; i < NUM_VIN; i++) {
1114                         if (!(data->has_in & BIT(i)))
1115                                 continue;
1116
1117                         data->in[i][0] =
1118                                 it87_read_value(data, IT87_REG_VIN[i]);
1119
1120                         /* VBAT and AVCC don't have limit registers */
1121                         if (i >= NUM_VIN_LIMIT)
1122                                 continue;
1123
1124                         data->in[i][1] =
1125                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
1126                         data->in[i][2] =
1127                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
1128                 }
1129
1130                 for (i = 0; i < NUM_FAN; i++) {
1131                         /* Skip disabled fans */
1132                         if (!(data->has_fan & BIT(i)))
1133                                 continue;
1134
1135                         data->fan[i][1] =
1136                                 it87_read_value(data, data->REG_FAN_MIN[i]);
1137                         data->fan[i][0] = it87_read_value(data,
1138                                        data->REG_FAN[i]);
1139                         /* Add high byte if in 16-bit mode */
1140                         if (has_16bit_fans(data)) {
1141                                 data->fan[i][0] |= it87_read_value(data,
1142                                                 data->REG_FANX[i]) << 8;
1143                                 data->fan[i][1] |= it87_read_value(data,
1144                                                 data->REG_FANX_MIN[i]) << 8;
1145                         }
1146                 }
1147                 for (i = 0; i < NUM_TEMP; i++) {
1148                         if (!(data->has_temp & BIT(i)))
1149                                 continue;
1150                         data->temp[i][0] =
1151                                 it87_read_value(data, IT87_REG_TEMP(i));
1152
1153                         if (i >= data->num_temp_limit)
1154                                 continue;
1155
1156                         if (i < data->num_temp_offset)
1157                                 data->temp[i][3] =
1158                                   it87_read_value(data,
1159                                                   data->REG_TEMP_OFFSET[i]);
1160
1161                         data->temp[i][1] =
1162                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1163                         data->temp[i][2] =
1164                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1165                 }
1166
1167                 /* Newer chips don't have clock dividers */
1168                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1169                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1170                         data->fan_div[0] = i & 0x07;
1171                         data->fan_div[1] = (i >> 3) & 0x07;
1172                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1173                 }
1174
1175                 data->alarms =
1176                         it87_read_value(data, IT87_REG_ALARM1) |
1177                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1178                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1179                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1180
1181                 data->fan_main_ctrl = it87_read_value(data,
1182                                 IT87_REG_FAN_MAIN_CTRL);
1183                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1184                 for (i = 0; i < NUM_PWM; i++) {
1185                         if (!(data->has_pwm & BIT(i)))
1186                                 continue;
1187                         it87_update_pwm_ctrl(data, i);
1188                 }
1189
1190                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1191                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1192                 /*
1193                  * The IT8705F does not have VID capability.
1194                  * The IT8718F and later don't use IT87_REG_VID for the
1195                  * same purpose.
1196                  */
1197                 if (data->type == it8712 || data->type == it8716) {
1198                         data->vid = it87_read_value(data, IT87_REG_VID);
1199                         /*
1200                          * The older IT8712F revisions had only 5 VID pins,
1201                          * but we assume it is always safe to read 6 bits.
1202                          */
1203                         data->vid &= 0x3f;
1204                 }
1205                 data->last_updated = jiffies;
1206                 data->valid = 1;
1207         }
1208         it87_unlock(data);
1209         return data;
1210 }
1211
1212 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1213                        char *buf)
1214 {
1215         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1216         struct it87_data *data = it87_update_device(dev);
1217         int index = sattr->index;
1218         int nr = sattr->nr;
1219
1220         if (IS_ERR(data))
1221                 return PTR_ERR(data);
1222
1223         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1224 }
1225
1226 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1227                       const char *buf, size_t count)
1228 {
1229         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1230         struct it87_data *data = dev_get_drvdata(dev);
1231         int index = sattr->index;
1232         int nr = sattr->nr;
1233         unsigned long val;
1234         int err;
1235
1236         if (kstrtoul(buf, 10, &val) < 0)
1237                 return -EINVAL;
1238
1239         err = it87_lock(data);
1240         if (err)
1241                 return err;
1242
1243         data->in[nr][index] = in_to_reg(data, nr, val);
1244         it87_write_value(data,
1245                          index == 1 ? IT87_REG_VIN_MIN(nr)
1246                                     : IT87_REG_VIN_MAX(nr),
1247                          data->in[nr][index]);
1248         it87_unlock(data);
1249         return count;
1250 }
1251
1252 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1253 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1254                             0, 1);
1255 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1256                             0, 2);
1257
1258 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1259 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1260                             1, 1);
1261 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1262                             1, 2);
1263
1264 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1265 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1266                             2, 1);
1267 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1268                             2, 2);
1269
1270 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1271 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1272                             3, 1);
1273 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1274                             3, 2);
1275
1276 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1277 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1278                             4, 1);
1279 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1280                             4, 2);
1281
1282 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1283 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1284                             5, 1);
1285 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1286                             5, 2);
1287
1288 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1289 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1290                             6, 1);
1291 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1292                             6, 2);
1293
1294 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1295 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1296                             7, 1);
1297 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1298                             7, 2);
1299
1300 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1301 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1302 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1303 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1304 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1305
1306 /* Up to 6 temperatures */
1307 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1308                          char *buf)
1309 {
1310         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1311         int nr = sattr->nr;
1312         int index = sattr->index;
1313         struct it87_data *data = it87_update_device(dev);
1314
1315         if (IS_ERR(data))
1316                 return PTR_ERR(data);
1317
1318         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1319 }
1320
1321 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1322                         const char *buf, size_t count)
1323 {
1324         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1325         int nr = sattr->nr;
1326         int index = sattr->index;
1327         struct it87_data *data = dev_get_drvdata(dev);
1328         long val;
1329         u8 reg, regval;
1330         int err;
1331
1332         if (kstrtol(buf, 10, &val) < 0)
1333                 return -EINVAL;
1334
1335         err = it87_lock(data);
1336         if (err)
1337                 return err;
1338
1339         switch (index) {
1340         default:
1341         case 1:
1342                 reg = data->REG_TEMP_LOW[nr];
1343                 break;
1344         case 2:
1345                 reg = data->REG_TEMP_HIGH[nr];
1346                 break;
1347         case 3:
1348                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1349                 if (!(regval & 0x80)) {
1350                         regval |= 0x80;
1351                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1352                 }
1353                 data->valid = 0;
1354                 reg = data->REG_TEMP_OFFSET[nr];
1355                 break;
1356         }
1357
1358         data->temp[nr][index] = TEMP_TO_REG(val);
1359         it87_write_value(data, reg, data->temp[nr][index]);
1360         it87_unlock(data);
1361         return count;
1362 }
1363
1364 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1365 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1366                             0, 1);
1367 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1368                             0, 2);
1369 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1370                             set_temp, 0, 3);
1371 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1372 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1373                             1, 1);
1374 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1375                             1, 2);
1376 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1377                             set_temp, 1, 3);
1378 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1379 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1380                             2, 1);
1381 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1382                             2, 2);
1383 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1384                             set_temp, 2, 3);
1385 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1386 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1387                             3, 1);
1388 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1389                             3, 2);
1390 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1391                             set_temp, 3, 3);
1392 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1393 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1394                             4, 1);
1395 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1396                             4, 2);
1397 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1398                             set_temp, 4, 3);
1399 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1400 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1401                             5, 1);
1402 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1403                             5, 2);
1404 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1405                             set_temp, 5, 3);
1406
1407 static const u8 temp_types_8686[NUM_TEMP][9] = {
1408         { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1409         { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1410         { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1411         { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1412         { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1413         { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1414 };
1415
1416 static int get_temp_type(struct it87_data *data, int index)
1417 {
1418         u8 reg, extra;
1419         int type = 0;
1420
1421         if (has_bank_sel(data)) {
1422                 u8 src1, src2;
1423
1424                 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1425
1426                 switch (data->type) {
1427                 case it8686:
1428                         if (src1 < 9)
1429                                 type = temp_types_8686[index][src1];
1430                         break;
1431                 case it8625:
1432                         if (index < 3)
1433                                 break;
1434                 case it8655:
1435                 case it8665:
1436                         if (src1 < 3) {
1437                                 index = src1;
1438                                 break;
1439                         }
1440                         src2 = data->temp_src[3];
1441                         switch(src1) {
1442                         case 3:
1443                                 type = (src2 & BIT(index)) ? 6 : 5;
1444                                 break;
1445                         case 4 ... 8:
1446                                 type = (src2 & BIT(index)) ? 4 : 6;
1447                                 break;
1448                         case 9:
1449                                 type = (src2 & BIT(index)) ? 5 : 0;
1450                                 break;
1451                         default:
1452                                 break;
1453                         }
1454                         return type;
1455                 default:
1456                         return 0;
1457                 }
1458         }
1459         if (type || index >= 3)
1460                 return type;
1461
1462         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1463         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1464
1465         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1466             (has_temp_old_peci(data, index) && (extra & 0x80)))
1467                 type = 6;               /* Intel PECI */
1468         if (reg & BIT(index))
1469                 type = 3;               /* thermal diode */
1470         else if (reg & BIT(index + 3))
1471                 type = 4;               /* thermistor */
1472
1473         return type;
1474 }
1475
1476 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1477                               char *buf)
1478 {
1479         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1480         struct it87_data *data = it87_update_device(dev);
1481         int type;
1482
1483         if (IS_ERR(data))
1484                 return PTR_ERR(data);
1485
1486         type = get_temp_type(data, sensor_attr->index);
1487         return sprintf(buf, "%d\n", type);
1488 }
1489
1490 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1491                              const char *buf, size_t count)
1492 {
1493         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1494         int nr = sensor_attr->index;
1495
1496         struct it87_data *data = dev_get_drvdata(dev);
1497         long val;
1498         u8 reg, extra;
1499         int err;
1500
1501         if (kstrtol(buf, 10, &val) < 0)
1502                 return -EINVAL;
1503
1504         err = it87_lock(data);
1505         if (err)
1506                 return err;
1507
1508         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1509         reg &= ~(1 << nr);
1510         reg &= ~(8 << nr);
1511         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1512                 reg &= 0x3f;
1513         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1514         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1515                 extra &= 0x7f;
1516         if (val == 2) { /* backwards compatibility */
1517                 dev_warn(dev,
1518                          "Sensor type 2 is deprecated, please use 4 instead\n");
1519                 val = 4;
1520         }
1521         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1522         if (val == 3)
1523                 reg |= 1 << nr;
1524         else if (val == 4)
1525                 reg |= 8 << nr;
1526         else if (has_temp_peci(data, nr) && val == 6)
1527                 reg |= (nr + 1) << 6;
1528         else if (has_temp_old_peci(data, nr) && val == 6)
1529                 extra |= 0x80;
1530         else if (val != 0) {
1531                 count = -EINVAL;
1532                 goto unlock;
1533         }
1534
1535         data->sensor = reg;
1536         data->extra = extra;
1537         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1538         if (has_temp_old_peci(data, nr))
1539                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1540         data->valid = 0;        /* Force cache refresh */
1541 unlock:
1542         it87_unlock(data);
1543         return count;
1544 }
1545
1546 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1547                           set_temp_type, 0);
1548 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1549                           set_temp_type, 1);
1550 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1551                           set_temp_type, 2);
1552 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1553                           set_temp_type, 3);
1554 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1555                           set_temp_type, 4);
1556 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1557                           set_temp_type, 5);
1558
1559 /* 6 Fans */
1560
1561 static int pwm_mode(const struct it87_data *data, int nr)
1562 {
1563         if (has_fanctl_onoff(data) && nr < 3 &&
1564             !(data->fan_main_ctrl & BIT(nr)))
1565                 return 0;                               /* Full speed */
1566         if (data->pwm_ctrl[nr] & 0x80)
1567                 return 2;                               /* Automatic mode */
1568         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1569             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1570                 return 0;                       /* Full speed */
1571
1572         return 1;                               /* Manual mode */
1573 }
1574
1575 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1576                         char *buf)
1577 {
1578         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1579         int nr = sattr->nr;
1580         int index = sattr->index;
1581         int speed;
1582         struct it87_data *data = it87_update_device(dev);
1583
1584         if (IS_ERR(data))
1585                 return PTR_ERR(data);
1586
1587         speed = has_16bit_fans(data) ?
1588                 FAN16_FROM_REG(data->fan[nr][index]) :
1589                 FAN_FROM_REG(data->fan[nr][index],
1590                              DIV_FROM_REG(data->fan_div[nr]));
1591         return sprintf(buf, "%d\n", speed);
1592 }
1593
1594 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1595                             char *buf)
1596 {
1597         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1598         struct it87_data *data = it87_update_device(dev);
1599         int nr = sensor_attr->index;
1600
1601         if (IS_ERR(data))
1602                 return PTR_ERR(data);
1603
1604         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1605 }
1606
1607 static ssize_t show_pwm_enable(struct device *dev,
1608                                struct device_attribute *attr, char *buf)
1609 {
1610         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1611         struct it87_data *data = it87_update_device(dev);
1612         int nr = sensor_attr->index;
1613
1614         if (IS_ERR(data))
1615                 return PTR_ERR(data);
1616
1617         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1618 }
1619
1620 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1621                         char *buf)
1622 {
1623         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1624         struct it87_data *data = it87_update_device(dev);
1625         int nr = sensor_attr->index;
1626
1627         if (IS_ERR(data))
1628                 return PTR_ERR(data);
1629
1630         return sprintf(buf, "%d\n",
1631                        pwm_from_reg(data, data->pwm_duty[nr]));
1632 }
1633
1634 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1635                              char *buf)
1636 {
1637         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1638         struct it87_data *data = it87_update_device(dev);
1639         int nr = sensor_attr->index;
1640         unsigned int freq;
1641         int index;
1642
1643         if (IS_ERR(data))
1644                 return PTR_ERR(data);
1645
1646         if (has_pwm_freq2(data) && nr == 1)
1647                 index = (data->extra >> 4) & 0x07;
1648         else
1649                 index = (data->fan_ctl >> 4) & 0x07;
1650
1651         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1652
1653         return sprintf(buf, "%u\n", freq);
1654 }
1655
1656 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1657                        const char *buf, size_t count)
1658 {
1659         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1660         int nr = sattr->nr;
1661         int index = sattr->index;
1662
1663         struct it87_data *data = dev_get_drvdata(dev);
1664         long val;
1665         int err;
1666         u8 reg;
1667
1668         if (kstrtol(buf, 10, &val) < 0)
1669                 return -EINVAL;
1670
1671         err = it87_lock(data);
1672         if (err)
1673                 return err;
1674
1675         if (has_16bit_fans(data)) {
1676                 data->fan[nr][index] = FAN16_TO_REG(val);
1677                 it87_write_value(data, data->REG_FAN_MIN[nr],
1678                                  data->fan[nr][index] & 0xff);
1679                 it87_write_value(data, data->REG_FANX_MIN[nr],
1680                                  data->fan[nr][index] >> 8);
1681         } else {
1682                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1683                 switch (nr) {
1684                 case 0:
1685                         data->fan_div[nr] = reg & 0x07;
1686                         break;
1687                 case 1:
1688                         data->fan_div[nr] = (reg >> 3) & 0x07;
1689                         break;
1690                 case 2:
1691                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1692                         break;
1693                 }
1694                 data->fan[nr][index] =
1695                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1696                 it87_write_value(data, data->REG_FAN_MIN[nr],
1697                                  data->fan[nr][index]);
1698         }
1699         it87_unlock(data);
1700         return count;
1701 }
1702
1703 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1704                            const char *buf, size_t count)
1705 {
1706         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1707         struct it87_data *data = dev_get_drvdata(dev);
1708         int nr = sensor_attr->index;
1709         unsigned long val;
1710         int min, err;
1711         u8 old;
1712
1713         if (kstrtoul(buf, 10, &val) < 0)
1714                 return -EINVAL;
1715
1716         err = it87_lock(data);
1717         if (err)
1718                 return err;
1719
1720         old = it87_read_value(data, IT87_REG_FAN_DIV);
1721
1722         /* Save fan min limit */
1723         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1724
1725         switch (nr) {
1726         case 0:
1727         case 1:
1728                 data->fan_div[nr] = DIV_TO_REG(val);
1729                 break;
1730         case 2:
1731                 if (val < 8)
1732                         data->fan_div[nr] = 1;
1733                 else
1734                         data->fan_div[nr] = 3;
1735         }
1736         val = old & 0x80;
1737         val |= (data->fan_div[0] & 0x07);
1738         val |= (data->fan_div[1] & 0x07) << 3;
1739         if (data->fan_div[2] == 3)
1740                 val |= 0x1 << 6;
1741         it87_write_value(data, IT87_REG_FAN_DIV, val);
1742
1743         /* Restore fan min limit */
1744         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1745         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1746         it87_unlock(data);
1747         return count;
1748 }
1749
1750 /* Returns 0 if OK, -EINVAL otherwise */
1751 static int check_trip_points(struct device *dev, int nr)
1752 {
1753         const struct it87_data *data = dev_get_drvdata(dev);
1754         int i, err = 0;
1755
1756         if (has_old_autopwm(data)) {
1757                 for (i = 0; i < 3; i++) {
1758                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1759                                 err = -EINVAL;
1760                 }
1761                 for (i = 0; i < 2; i++) {
1762                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1763                                 err = -EINVAL;
1764                 }
1765         } else if (has_newer_autopwm(data)) {
1766                 for (i = 1; i < 3; i++) {
1767                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1768                                 err = -EINVAL;
1769                 }
1770         }
1771
1772         if (err) {
1773                 dev_err(dev,
1774                         "Inconsistent trip points, not switching to automatic mode\n");
1775                 dev_err(dev, "Adjust the trip points and try again\n");
1776         }
1777         return err;
1778 }
1779
1780 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1781                               const char *buf, size_t count)
1782 {
1783         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1784         struct it87_data *data = dev_get_drvdata(dev);
1785         int nr = sensor_attr->index;
1786         long val;
1787         int err;
1788
1789         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1790                 return -EINVAL;
1791
1792         /* Check trip points before switching to automatic mode */
1793         if (val == 2) {
1794                 if (check_trip_points(dev, nr) < 0)
1795                         return -EINVAL;
1796         }
1797
1798         err = it87_lock(data);
1799         if (err)
1800                 return err;;
1801
1802         it87_update_pwm_ctrl(data, nr);
1803
1804         if (val == 0) {
1805                 if (nr < 3 && has_fanctl_onoff(data)) {
1806                         int tmp;
1807                         /* make sure the fan is on when in on/off mode */
1808                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1809                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1810                         /* set on/off mode */
1811                         data->fan_main_ctrl &= ~BIT(nr);
1812                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1813                                          data->fan_main_ctrl);
1814                 } else {
1815                         u8 ctrl;
1816
1817                         /* No on/off mode, set maximum pwm value */
1818                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1819                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1820                                          data->pwm_duty[nr]);
1821                         /* and set manual mode */
1822                         if (has_newer_autopwm(data)) {
1823                                 ctrl = temp_map_to_reg(data, nr,
1824                                                        data->pwm_temp_map[nr]);
1825                                 ctrl &= 0x7f;
1826                         } else {
1827                                 ctrl = data->pwm_duty[nr];
1828                         }
1829                         data->pwm_ctrl[nr] = ctrl;
1830                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1831                 }
1832         } else {
1833                 u8 ctrl;
1834
1835                 if (has_newer_autopwm(data)) {
1836                         ctrl = temp_map_to_reg(data, nr,
1837                                                data->pwm_temp_map[nr]);
1838                         if (val == 1)
1839                                 ctrl &= 0x7f;
1840                         else
1841                                 ctrl |= 0x80;
1842                 } else {
1843                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1844                 }
1845                 data->pwm_ctrl[nr] = ctrl;
1846                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1847
1848                 if (has_fanctl_onoff(data) && nr < 3) {
1849                         /* set SmartGuardian mode */
1850                         data->fan_main_ctrl |= BIT(nr);
1851                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1852                                          data->fan_main_ctrl);
1853                 }
1854         }
1855         it87_unlock(data);
1856         return count;
1857 }
1858
1859 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1860                        const char *buf, size_t count)
1861 {
1862         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1863         struct it87_data *data = dev_get_drvdata(dev);
1864         int nr = sensor_attr->index;
1865         long val;
1866         int err;
1867
1868         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1869                 return -EINVAL;
1870
1871         err = it87_lock(data);
1872         if (err)
1873                 return err;
1874
1875         it87_update_pwm_ctrl(data, nr);
1876         if (has_newer_autopwm(data)) {
1877                 /*
1878                  * If we are in automatic mode, the PWM duty cycle register
1879                  * is read-only so we can't write the value.
1880                  */
1881                 if (data->pwm_ctrl[nr] & 0x80) {
1882                         count = -EBUSY;
1883                         goto unlock;
1884                 }
1885                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1886                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1887                                  data->pwm_duty[nr]);
1888         } else {
1889                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1890                 /*
1891                  * If we are in manual mode, write the duty cycle immediately;
1892                  * otherwise, just store it for later use.
1893                  */
1894                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1895                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1896                         it87_write_value(data, data->REG_PWM[nr],
1897                                          data->pwm_ctrl[nr]);
1898                 }
1899         }
1900 unlock:
1901         it87_unlock(data);
1902         return count;
1903 }
1904
1905 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1906                             const char *buf, size_t count)
1907 {
1908         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1909         struct it87_data *data = dev_get_drvdata(dev);
1910         int nr = sensor_attr->index;
1911         unsigned long val;
1912         int err;
1913         int i;
1914
1915         if (kstrtoul(buf, 10, &val) < 0)
1916                 return -EINVAL;
1917
1918         val = clamp_val(val, 0, 1000000);
1919         val *= has_newer_autopwm(data) ? 256 : 128;
1920
1921         /* Search for the nearest available frequency */
1922         for (i = 0; i < 7; i++) {
1923                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1924                         break;
1925         }
1926
1927         err = it87_lock(data);
1928         if (err)
1929                 return err;
1930
1931         if (nr == 0) {
1932                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1933                 data->fan_ctl |= i << 4;
1934                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1935         } else {
1936                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1937                 data->extra |= i << 4;
1938                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1939         }
1940         it87_unlock(data);
1941         return count;
1942 }
1943
1944 static ssize_t show_pwm_temp_map(struct device *dev,
1945                                  struct device_attribute *attr, char *buf)
1946 {
1947         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1948         struct it87_data *data = it87_update_device(dev);
1949         int nr = sensor_attr->index;
1950
1951         if (IS_ERR(data))
1952                 return PTR_ERR(data);
1953
1954         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1955 }
1956
1957 static ssize_t set_pwm_temp_map(struct device *dev,
1958                                 struct device_attribute *attr, const char *buf,
1959                                 size_t count)
1960 {
1961         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1962         struct it87_data *data = dev_get_drvdata(dev);
1963         int nr = sensor_attr->index;
1964         unsigned long val;
1965         int err;
1966         u8 map;
1967
1968         if (kstrtoul(buf, 10, &val) < 0)
1969                 return -EINVAL;
1970
1971         if (!val || val > data->pwm_num_temp_map)
1972                 return -EINVAL;
1973
1974         map = val - 1;
1975
1976         err = it87_lock(data);
1977         if (err)
1978                 return err;
1979
1980         it87_update_pwm_ctrl(data, nr);
1981         data->pwm_temp_map[nr] = map;
1982         /*
1983          * If we are in automatic mode, write the temp mapping immediately;
1984          * otherwise, just store it for later use.
1985          */
1986         if (data->pwm_ctrl[nr] & 0x80) {
1987                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
1988                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1989         }
1990         it87_unlock(data);
1991         return count;
1992 }
1993
1994 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1995                              char *buf)
1996 {
1997         struct it87_data *data = it87_update_device(dev);
1998         struct sensor_device_attribute_2 *sensor_attr =
1999                         to_sensor_dev_attr_2(attr);
2000         int nr = sensor_attr->nr;
2001         int point = sensor_attr->index;
2002
2003         if (IS_ERR(data))
2004                 return PTR_ERR(data);
2005
2006         return sprintf(buf, "%d\n",
2007                        pwm_from_reg(data, data->auto_pwm[nr][point]));
2008 }
2009
2010 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2011                             const char *buf, size_t count)
2012 {
2013         struct it87_data *data = dev_get_drvdata(dev);
2014         struct sensor_device_attribute_2 *sensor_attr =
2015                         to_sensor_dev_attr_2(attr);
2016         int nr = sensor_attr->nr;
2017         int point = sensor_attr->index;
2018         int regaddr;
2019         long val;
2020         int err;
2021
2022         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2023                 return -EINVAL;
2024
2025         err = it87_lock(data);
2026         if (err)
2027                 return err;
2028
2029         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2030         if (has_newer_autopwm(data))
2031                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2032         else
2033                 regaddr = IT87_REG_AUTO_PWM(nr, point);
2034         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
2035         it87_unlock(data);
2036         return count;
2037 }
2038
2039 static ssize_t show_auto_pwm_slope(struct device *dev,
2040                                    struct device_attribute *attr, char *buf)
2041 {
2042         struct it87_data *data = it87_update_device(dev);
2043         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2044         int nr = sensor_attr->index;
2045
2046         if (IS_ERR(data))
2047                 return PTR_ERR(data);
2048
2049         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2050 }
2051
2052 static ssize_t set_auto_pwm_slope(struct device *dev,
2053                                   struct device_attribute *attr,
2054                                   const char *buf, size_t count)
2055 {
2056         struct it87_data *data = dev_get_drvdata(dev);
2057         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2058         int nr = sensor_attr->index;
2059         unsigned long val;
2060         int err;
2061
2062         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2063                 return -EINVAL;
2064
2065         err = it87_lock(data);
2066         if (err)
2067                 return err;
2068
2069         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2070         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
2071                          data->auto_pwm[nr][1]);
2072         it87_unlock(data);
2073         return count;
2074 }
2075
2076 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2077                               char *buf)
2078 {
2079         struct it87_data *data = it87_update_device(dev);
2080         struct sensor_device_attribute_2 *sensor_attr =
2081                         to_sensor_dev_attr_2(attr);
2082         int nr = sensor_attr->nr;
2083         int point = sensor_attr->index;
2084         int reg;
2085
2086         if (IS_ERR(data))
2087                 return PTR_ERR(data);
2088
2089         if (has_old_autopwm(data) || point)
2090                 reg = data->auto_temp[nr][point];
2091         else
2092                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2093
2094         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2095 }
2096
2097 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2098                              const char *buf, size_t count)
2099 {
2100         struct it87_data *data = dev_get_drvdata(dev);
2101         struct sensor_device_attribute_2 *sensor_attr =
2102                         to_sensor_dev_attr_2(attr);
2103         int nr = sensor_attr->nr;
2104         int point = sensor_attr->index;
2105         long val;
2106         int reg;
2107         int err;
2108
2109         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2110                 return -EINVAL;
2111
2112         err = it87_lock(data);
2113         if (err)
2114                 return err;
2115
2116         if (has_newer_autopwm(data) && !point) {
2117                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2118                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2119                 data->auto_temp[nr][0] = reg;
2120                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2121         } else {
2122                 reg = TEMP_TO_REG(val);
2123                 data->auto_temp[nr][point] = reg;
2124                 if (has_newer_autopwm(data))
2125                         point--;
2126                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2127         }
2128         it87_unlock(data);
2129         return count;
2130 }
2131
2132 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
2133 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2134                             0, 1);
2135 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
2136                           set_fan_div, 0);
2137
2138 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
2139 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2140                             1, 1);
2141 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
2142                           set_fan_div, 1);
2143
2144 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
2145 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2146                             2, 1);
2147 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
2148                           set_fan_div, 2);
2149
2150 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2151 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2152                             3, 1);
2153
2154 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2155 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2156                             4, 1);
2157
2158 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2159 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2160                             5, 1);
2161
2162 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2163                           show_pwm_enable, set_pwm_enable, 0);
2164 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2165 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2166                           set_pwm_freq, 0);
2167 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2168                           show_pwm_temp_map, set_pwm_temp_map, 0);
2169 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2170                             show_auto_pwm, set_auto_pwm, 0, 0);
2171 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2172                             show_auto_pwm, set_auto_pwm, 0, 1);
2173 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2174                             show_auto_pwm, set_auto_pwm, 0, 2);
2175 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2176                             show_auto_pwm, NULL, 0, 3);
2177 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2178                             show_auto_temp, set_auto_temp, 0, 1);
2179 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2180                             show_auto_temp, set_auto_temp, 0, 0);
2181 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2182                             show_auto_temp, set_auto_temp, 0, 2);
2183 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2184                             show_auto_temp, set_auto_temp, 0, 3);
2185 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2186                             show_auto_temp, set_auto_temp, 0, 4);
2187 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2188                             show_auto_pwm, set_auto_pwm, 0, 0);
2189 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2190                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2191
2192 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2193                           show_pwm_enable, set_pwm_enable, 1);
2194 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2195 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2196 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2197                           show_pwm_temp_map, set_pwm_temp_map, 1);
2198 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2199                             show_auto_pwm, set_auto_pwm, 1, 0);
2200 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2201                             show_auto_pwm, set_auto_pwm, 1, 1);
2202 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2203                             show_auto_pwm, set_auto_pwm, 1, 2);
2204 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2205                             show_auto_pwm, NULL, 1, 3);
2206 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2207                             show_auto_temp, set_auto_temp, 1, 1);
2208 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2209                             show_auto_temp, set_auto_temp, 1, 0);
2210 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2211                             show_auto_temp, set_auto_temp, 1, 2);
2212 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2213                             show_auto_temp, set_auto_temp, 1, 3);
2214 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2215                             show_auto_temp, set_auto_temp, 1, 4);
2216 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2217                             show_auto_pwm, set_auto_pwm, 1, 0);
2218 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2219                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2220
2221 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2222                           show_pwm_enable, set_pwm_enable, 2);
2223 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2224 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2225 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2226                           show_pwm_temp_map, set_pwm_temp_map, 2);
2227 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2228                             show_auto_pwm, set_auto_pwm, 2, 0);
2229 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2230                             show_auto_pwm, set_auto_pwm, 2, 1);
2231 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2232                             show_auto_pwm, set_auto_pwm, 2, 2);
2233 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2234                             show_auto_pwm, NULL, 2, 3);
2235 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2236                             show_auto_temp, set_auto_temp, 2, 1);
2237 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2238                             show_auto_temp, set_auto_temp, 2, 0);
2239 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2240                             show_auto_temp, set_auto_temp, 2, 2);
2241 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2242                             show_auto_temp, set_auto_temp, 2, 3);
2243 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2244                             show_auto_temp, set_auto_temp, 2, 4);
2245 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2246                             show_auto_pwm, set_auto_pwm, 2, 0);
2247 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2248                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2249
2250 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2251                           show_pwm_enable, set_pwm_enable, 3);
2252 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2253 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2254 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2255                           show_pwm_temp_map, set_pwm_temp_map, 3);
2256 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2257                             show_auto_temp, set_auto_temp, 2, 1);
2258 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2259                             show_auto_temp, set_auto_temp, 2, 0);
2260 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2261                             show_auto_temp, set_auto_temp, 2, 2);
2262 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2263                             show_auto_temp, set_auto_temp, 2, 3);
2264 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2265                             show_auto_pwm, set_auto_pwm, 3, 0);
2266 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2267                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2268
2269 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2270                           show_pwm_enable, set_pwm_enable, 4);
2271 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2272 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2273 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2274                           show_pwm_temp_map, set_pwm_temp_map, 4);
2275 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2276                             show_auto_temp, set_auto_temp, 2, 1);
2277 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2278                             show_auto_temp, set_auto_temp, 2, 0);
2279 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2280                             show_auto_temp, set_auto_temp, 2, 2);
2281 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2282                             show_auto_temp, set_auto_temp, 2, 3);
2283 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2284                             show_auto_pwm, set_auto_pwm, 4, 0);
2285 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2286                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2287
2288 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2289                           show_pwm_enable, set_pwm_enable, 5);
2290 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2291 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2292 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2293                           show_pwm_temp_map, set_pwm_temp_map, 5);
2294 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2295                             show_auto_temp, set_auto_temp, 2, 1);
2296 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2297                             show_auto_temp, set_auto_temp, 2, 0);
2298 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2299                             show_auto_temp, set_auto_temp, 2, 2);
2300 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2301                             show_auto_temp, set_auto_temp, 2, 3);
2302 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2303                             show_auto_pwm, set_auto_pwm, 5, 0);
2304 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2305                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2306
2307 /* Alarms */
2308 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2309                            char *buf)
2310 {
2311         struct it87_data *data = it87_update_device(dev);
2312
2313         if (IS_ERR(data))
2314                 return PTR_ERR(data);
2315
2316         return sprintf(buf, "%u\n", data->alarms);
2317 }
2318 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2319
2320 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2321                           char *buf)
2322 {
2323         struct it87_data *data = it87_update_device(dev);
2324         int bitnr = to_sensor_dev_attr(attr)->index;
2325
2326         if (IS_ERR(data))
2327                 return PTR_ERR(data);
2328
2329         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2330 }
2331
2332 static ssize_t clear_intrusion(struct device *dev,
2333                                struct device_attribute *attr, const char *buf,
2334                                size_t count)
2335 {
2336         struct it87_data *data = dev_get_drvdata(dev);
2337         int err, config;
2338         long val;
2339
2340         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2341                 return -EINVAL;
2342
2343         err = it87_lock(data);
2344         if (err)
2345                 return err;
2346
2347         config = it87_read_value(data, IT87_REG_CONFIG);
2348         config |= BIT(5);
2349         it87_write_value(data, IT87_REG_CONFIG, config);
2350         /* Invalidate cache to force re-read */
2351         data->valid = 0;
2352         it87_unlock(data);
2353         return count;
2354 }
2355
2356 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2357 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2358 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2359 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2360 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2361 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2362 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2363 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2364 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2365 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2366 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2367 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2368 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2369 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2370 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2371 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2372 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2373 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2374 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2375 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2376 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2377                           show_alarm, clear_intrusion, 4);
2378
2379 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2380                          char *buf)
2381 {
2382         struct it87_data *data = it87_update_device(dev);
2383         int bitnr = to_sensor_dev_attr(attr)->index;
2384
2385         if (IS_ERR(data))
2386                 return PTR_ERR(data);
2387
2388         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2389 }
2390
2391 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2392                         const char *buf, size_t count)
2393 {
2394         int bitnr = to_sensor_dev_attr(attr)->index;
2395         struct it87_data *data = dev_get_drvdata(dev);
2396         long val;
2397         int err;
2398
2399         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2400                 return -EINVAL;
2401
2402         err = it87_lock(data);
2403         if (err)
2404                 return err;
2405
2406         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2407         if (val)
2408                 data->beeps |= BIT(bitnr);
2409         else
2410                 data->beeps &= ~BIT(bitnr);
2411         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2412         it87_unlock(data);
2413         return count;
2414 }
2415
2416 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2417                           show_beep, set_beep, 1);
2418 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2419 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2420 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2421 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2422 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2423 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2424 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2425 /* fanX_beep writability is set later */
2426 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2427 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2428 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2429 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2430 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2431 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2432 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2433                           show_beep, set_beep, 2);
2434 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2435 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2436 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2437 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2438 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2439
2440 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2441                             char *buf)
2442 {
2443         struct it87_data *data = dev_get_drvdata(dev);
2444
2445         return sprintf(buf, "%u\n", data->vrm);
2446 }
2447
2448 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2449                              const char *buf, size_t count)
2450 {
2451         struct it87_data *data = dev_get_drvdata(dev);
2452         unsigned long val;
2453
2454         if (kstrtoul(buf, 10, &val) < 0)
2455                 return -EINVAL;
2456
2457         data->vrm = val;
2458
2459         return count;
2460 }
2461 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2462
2463 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2464                             char *buf)
2465 {
2466         struct it87_data *data = it87_update_device(dev);
2467
2468         if (IS_ERR(data))
2469                 return PTR_ERR(data);
2470
2471         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2472 }
2473 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2474
2475 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2476                           char *buf)
2477 {
2478         static const char * const labels[] = {
2479                 "+5V",
2480                 "5VSB",
2481                 "Vbat",
2482                 "AVCC",
2483         };
2484         static const char * const labels_it8721[] = {
2485                 "+3.3V",
2486                 "3VSB",
2487                 "Vbat",
2488                 "+3.3V",
2489         };
2490         struct it87_data *data = dev_get_drvdata(dev);
2491         int nr = to_sensor_dev_attr(attr)->index;
2492         const char *label;
2493
2494         if (has_vin3_5v(data) && nr == 0)
2495                 label = labels[0];
2496         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2497                  has_11mv_adc(data))
2498                 label = labels_it8721[nr];
2499         else
2500                 label = labels[nr];
2501
2502         return sprintf(buf, "%s\n", label);
2503 }
2504 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2505 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2506 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2507 /* AVCC3 */
2508 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2509
2510 static umode_t it87_in_is_visible(struct kobject *kobj,
2511                                   struct attribute *attr, int index)
2512 {
2513         struct device *dev = container_of(kobj, struct device, kobj);
2514         struct it87_data *data = dev_get_drvdata(dev);
2515         int i = index / 5;      /* voltage index */
2516         int a = index % 5;      /* attribute index */
2517
2518         if (index >= 40) {      /* in8 and higher only have input attributes */
2519                 i = index - 40 + 8;
2520                 a = 0;
2521         }
2522
2523         if (!(data->has_in & BIT(i)))
2524                 return 0;
2525
2526         if (a == 4 && !data->has_beep)
2527                 return 0;
2528
2529         return attr->mode;
2530 }
2531
2532 static struct attribute *it87_attributes_in[] = {
2533         &sensor_dev_attr_in0_input.dev_attr.attr,
2534         &sensor_dev_attr_in0_min.dev_attr.attr,
2535         &sensor_dev_attr_in0_max.dev_attr.attr,
2536         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2537         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2538
2539         &sensor_dev_attr_in1_input.dev_attr.attr,
2540         &sensor_dev_attr_in1_min.dev_attr.attr,
2541         &sensor_dev_attr_in1_max.dev_attr.attr,
2542         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2543         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2544
2545         &sensor_dev_attr_in2_input.dev_attr.attr,
2546         &sensor_dev_attr_in2_min.dev_attr.attr,
2547         &sensor_dev_attr_in2_max.dev_attr.attr,
2548         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2549         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2550
2551         &sensor_dev_attr_in3_input.dev_attr.attr,
2552         &sensor_dev_attr_in3_min.dev_attr.attr,
2553         &sensor_dev_attr_in3_max.dev_attr.attr,
2554         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2555         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2556
2557         &sensor_dev_attr_in4_input.dev_attr.attr,
2558         &sensor_dev_attr_in4_min.dev_attr.attr,
2559         &sensor_dev_attr_in4_max.dev_attr.attr,
2560         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2561         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2562
2563         &sensor_dev_attr_in5_input.dev_attr.attr,
2564         &sensor_dev_attr_in5_min.dev_attr.attr,
2565         &sensor_dev_attr_in5_max.dev_attr.attr,
2566         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2567         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2568
2569         &sensor_dev_attr_in6_input.dev_attr.attr,
2570         &sensor_dev_attr_in6_min.dev_attr.attr,
2571         &sensor_dev_attr_in6_max.dev_attr.attr,
2572         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2573         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2574
2575         &sensor_dev_attr_in7_input.dev_attr.attr,
2576         &sensor_dev_attr_in7_min.dev_attr.attr,
2577         &sensor_dev_attr_in7_max.dev_attr.attr,
2578         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2579         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2580
2581         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2582         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2583         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2584         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2585         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2586         NULL
2587 };
2588
2589 static const struct attribute_group it87_group_in = {
2590         .attrs = it87_attributes_in,
2591         .is_visible = it87_in_is_visible,
2592 };
2593
2594 static umode_t it87_temp_is_visible(struct kobject *kobj,
2595                                     struct attribute *attr, int index)
2596 {
2597         struct device *dev = container_of(kobj, struct device, kobj);
2598         struct it87_data *data = dev_get_drvdata(dev);
2599         int i = index / 7;      /* temperature index */
2600         int a = index % 7;      /* attribute index */
2601
2602         if (!(data->has_temp & BIT(i)))
2603                 return 0;
2604
2605         if (a && i >= data->num_temp_limit)
2606                 return 0;
2607
2608         if (a == 3) {
2609                 int type = get_temp_type(data, i);
2610
2611                 if (type == 0)
2612                         return 0;
2613                 if (has_bank_sel(data))
2614                         return 0444;
2615                 return attr->mode;
2616         }
2617
2618         if (a == 5 && i >= data->num_temp_offset)
2619                 return 0;
2620
2621         if (a == 6 && !data->has_beep)
2622                 return 0;
2623
2624         return attr->mode;
2625 }
2626
2627 static struct attribute *it87_attributes_temp[] = {
2628         &sensor_dev_attr_temp1_input.dev_attr.attr,
2629         &sensor_dev_attr_temp1_max.dev_attr.attr,
2630         &sensor_dev_attr_temp1_min.dev_attr.attr,
2631         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2632         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2633         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2634         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2635
2636         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2637         &sensor_dev_attr_temp2_max.dev_attr.attr,
2638         &sensor_dev_attr_temp2_min.dev_attr.attr,
2639         &sensor_dev_attr_temp2_type.dev_attr.attr,
2640         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2641         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2642         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2643
2644         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2645         &sensor_dev_attr_temp3_max.dev_attr.attr,
2646         &sensor_dev_attr_temp3_min.dev_attr.attr,
2647         &sensor_dev_attr_temp3_type.dev_attr.attr,
2648         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2649         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2650         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2651
2652         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2653         &sensor_dev_attr_temp4_max.dev_attr.attr,
2654         &sensor_dev_attr_temp4_min.dev_attr.attr,
2655         &sensor_dev_attr_temp4_type.dev_attr.attr,
2656         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2657         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2658         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2659
2660         &sensor_dev_attr_temp5_input.dev_attr.attr,
2661         &sensor_dev_attr_temp5_max.dev_attr.attr,
2662         &sensor_dev_attr_temp5_min.dev_attr.attr,
2663         &sensor_dev_attr_temp5_type.dev_attr.attr,
2664         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2665         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2666         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2667
2668         &sensor_dev_attr_temp6_input.dev_attr.attr,
2669         &sensor_dev_attr_temp6_max.dev_attr.attr,
2670         &sensor_dev_attr_temp6_min.dev_attr.attr,
2671         &sensor_dev_attr_temp6_type.dev_attr.attr,
2672         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2673         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2674         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2675         NULL
2676 };
2677
2678 static const struct attribute_group it87_group_temp = {
2679         .attrs = it87_attributes_temp,
2680         .is_visible = it87_temp_is_visible,
2681 };
2682
2683 static umode_t it87_is_visible(struct kobject *kobj,
2684                                struct attribute *attr, int index)
2685 {
2686         struct device *dev = container_of(kobj, struct device, kobj);
2687         struct it87_data *data = dev_get_drvdata(dev);
2688
2689         if ((index == 2 || index == 3) && !data->has_vid)
2690                 return 0;
2691
2692         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2693                 return 0;
2694
2695         return attr->mode;
2696 }
2697
2698 static struct attribute *it87_attributes[] = {
2699         &dev_attr_alarms.attr,
2700         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2701         &dev_attr_vrm.attr,                             /* 2 */
2702         &dev_attr_cpu0_vid.attr,                        /* 3 */
2703         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2704         &sensor_dev_attr_in7_label.dev_attr.attr,
2705         &sensor_dev_attr_in8_label.dev_attr.attr,
2706         &sensor_dev_attr_in9_label.dev_attr.attr,
2707         NULL
2708 };
2709
2710 static const struct attribute_group it87_group = {
2711         .attrs = it87_attributes,
2712         .is_visible = it87_is_visible,
2713 };
2714
2715 static umode_t it87_fan_is_visible(struct kobject *kobj,
2716                                    struct attribute *attr, int index)
2717 {
2718         struct device *dev = container_of(kobj, struct device, kobj);
2719         struct it87_data *data = dev_get_drvdata(dev);
2720         int i = index / 5;      /* fan index */
2721         int a = index % 5;      /* attribute index */
2722
2723         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2724                 i = (index - 15) / 4 + 3;
2725                 a = (index - 15) % 4;
2726         }
2727
2728         if (!(data->has_fan & BIT(i)))
2729                 return 0;
2730
2731         if (a == 3) {                           /* beep */
2732                 if (!data->has_beep)
2733                         return 0;
2734                 /* first fan beep attribute is writable */
2735                 if (i == __ffs(data->has_fan))
2736                         return attr->mode | S_IWUSR;
2737         }
2738
2739         if (a == 4 && has_16bit_fans(data))     /* divisor */
2740                 return 0;
2741
2742         return attr->mode;
2743 }
2744
2745 static struct attribute *it87_attributes_fan[] = {
2746         &sensor_dev_attr_fan1_input.dev_attr.attr,
2747         &sensor_dev_attr_fan1_min.dev_attr.attr,
2748         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2749         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2750         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2751
2752         &sensor_dev_attr_fan2_input.dev_attr.attr,
2753         &sensor_dev_attr_fan2_min.dev_attr.attr,
2754         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2755         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2756         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2757
2758         &sensor_dev_attr_fan3_input.dev_attr.attr,
2759         &sensor_dev_attr_fan3_min.dev_attr.attr,
2760         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2761         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2762         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2763
2764         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2765         &sensor_dev_attr_fan4_min.dev_attr.attr,
2766         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2767         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2768
2769         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2770         &sensor_dev_attr_fan5_min.dev_attr.attr,
2771         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2772         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2773
2774         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2775         &sensor_dev_attr_fan6_min.dev_attr.attr,
2776         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2777         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2778         NULL
2779 };
2780
2781 static const struct attribute_group it87_group_fan = {
2782         .attrs = it87_attributes_fan,
2783         .is_visible = it87_fan_is_visible,
2784 };
2785
2786 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2787                                    struct attribute *attr, int index)
2788 {
2789         struct device *dev = container_of(kobj, struct device, kobj);
2790         struct it87_data *data = dev_get_drvdata(dev);
2791         int i = index / 4;      /* pwm index */
2792         int a = index % 4;      /* attribute index */
2793
2794         if (!(data->has_pwm & BIT(i)))
2795                 return 0;
2796
2797         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2798         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2799                 return attr->mode | S_IWUSR;
2800
2801         /* pwm2_freq is writable if there are two pwm frequency selects */
2802         if (has_pwm_freq2(data) && i == 1 && a == 2)
2803                 return attr->mode | S_IWUSR;
2804
2805         return attr->mode;
2806 }
2807
2808 static struct attribute *it87_attributes_pwm[] = {
2809         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2810         &sensor_dev_attr_pwm1.dev_attr.attr,
2811         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2812         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2813
2814         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2815         &sensor_dev_attr_pwm2.dev_attr.attr,
2816         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2817         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2818
2819         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2820         &sensor_dev_attr_pwm3.dev_attr.attr,
2821         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2822         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2823
2824         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2825         &sensor_dev_attr_pwm4.dev_attr.attr,
2826         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2827         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2828
2829         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2830         &sensor_dev_attr_pwm5.dev_attr.attr,
2831         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2832         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2833
2834         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2835         &sensor_dev_attr_pwm6.dev_attr.attr,
2836         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2837         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2838
2839         NULL
2840 };
2841
2842 static const struct attribute_group it87_group_pwm = {
2843         .attrs = it87_attributes_pwm,
2844         .is_visible = it87_pwm_is_visible,
2845 };
2846
2847 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2848                                         struct attribute *attr, int index)
2849 {
2850         struct device *dev = container_of(kobj, struct device, kobj);
2851         struct it87_data *data = dev_get_drvdata(dev);
2852         int i = index / 11;     /* pwm index */
2853         int a = index % 11;     /* attribute index */
2854
2855         if (index >= 33) {      /* pwm 4..6 */
2856                 i = (index - 33) / 6 + 3;
2857                 a = (index - 33) % 6 + 4;
2858         }
2859
2860         if (!(data->has_pwm & BIT(i)))
2861                 return 0;
2862
2863         if (has_newer_autopwm(data)) {
2864                 if (a < 4)      /* no auto point pwm */
2865                         return 0;
2866                 if (a == 8)     /* no auto_point4 */
2867                         return 0;
2868         }
2869         if (has_old_autopwm(data)) {
2870                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2871                         return 0;
2872         }
2873
2874         return attr->mode;
2875 }
2876
2877 static struct attribute *it87_attributes_auto_pwm[] = {
2878         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2879         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2880         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2881         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2882         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2883         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2884         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2885         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2886         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2887         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2888         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2889
2890         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2891         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2892         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2893         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2894         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2895         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2896         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2897         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2898         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2899         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2900         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2901
2902         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2903         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2904         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2905         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2906         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2907         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2908         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2909         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2910         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2911         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2912         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2913
2914         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2915         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2916         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2917         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2918         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2919         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2920
2921         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2922         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2923         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2924         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2925         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2926         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2927
2928         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2929         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2930         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2931         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2932         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2933         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2934
2935         NULL,
2936 };
2937
2938 static const struct attribute_group it87_group_auto_pwm = {
2939         .attrs = it87_attributes_auto_pwm,
2940         .is_visible = it87_auto_pwm_is_visible,
2941 };
2942
2943 /* SuperIO detection - will change isa_address if a chip is found */
2944 static int __init it87_find(int sioaddr, unsigned short *address,
2945                             struct it87_sio_data *sio_data)
2946 {
2947         const struct it87_devices *config;
2948         bool doexit = true;
2949         u16 chip_type;
2950         int err;
2951
2952         err = superio_enter(sioaddr);
2953         if (err)
2954                 return err;
2955
2956         sio_data->sioaddr = sioaddr;
2957
2958         err = -ENODEV;
2959         chip_type = superio_inw(sioaddr, DEVID);
2960         if (chip_type == 0xffff)
2961                 goto exit;
2962
2963         if (force_id)
2964                 chip_type = force_id;
2965
2966         switch (chip_type) {
2967         case IT8705F_DEVID:
2968                 sio_data->type = it87;
2969                 break;
2970         case IT8712F_DEVID:
2971                 sio_data->type = it8712;
2972                 break;
2973         case IT8716F_DEVID:
2974         case IT8726F_DEVID:
2975                 sio_data->type = it8716;
2976                 break;
2977         case IT8718F_DEVID:
2978                 sio_data->type = it8718;
2979                 break;
2980         case IT8720F_DEVID:
2981                 sio_data->type = it8720;
2982                 break;
2983         case IT8721F_DEVID:
2984                 sio_data->type = it8721;
2985                 break;
2986         case IT8728F_DEVID:
2987                 sio_data->type = it8728;
2988                 break;
2989         case IT8732F_DEVID:
2990                 sio_data->type = it8732;
2991                 break;
2992         case IT8792E_DEVID:
2993                 sio_data->type = it8792;
2994                 /*
2995                  * Disabling configuration mode on IT8792E can result in system
2996                  * hang-ups and access failures to the Super-IO chip at the
2997                  * second SIO address. Never exit configuration mode on this
2998                  * chip to avoid the problem.
2999                  */
3000                 doexit = false;
3001                 break;
3002         case IT8771E_DEVID:
3003                 sio_data->type = it8771;
3004                 break;
3005         case IT8772E_DEVID:
3006                 sio_data->type = it8772;
3007                 break;
3008         case IT8781F_DEVID:
3009                 sio_data->type = it8781;
3010                 break;
3011         case IT8782F_DEVID:
3012                 sio_data->type = it8782;
3013                 break;
3014         case IT8783E_DEVID:
3015                 sio_data->type = it8783;
3016                 break;
3017         case IT8786E_DEVID:
3018                 sio_data->type = it8786;
3019                 break;
3020         case IT8790E_DEVID:
3021                 sio_data->type = it8790;
3022                 doexit = false;         /* See IT8792E comment above */
3023                 break;
3024         case IT8603E_DEVID:
3025         case IT8623E_DEVID:
3026                 sio_data->type = it8603;
3027                 break;
3028         case IT8607E_DEVID:
3029                 sio_data->type = it8607;
3030                 break;
3031         case IT8613E_DEVID:
3032                 sio_data->type = it8613;
3033                 break;
3034         case IT8620E_DEVID:
3035                 sio_data->type = it8620;
3036                 break;
3037         case IT8622E_DEVID:
3038                 sio_data->type = it8622;
3039                 break;
3040         case IT8625E_DEVID:
3041                 sio_data->type = it8625;
3042                 break;
3043         case IT8628E_DEVID:
3044                 sio_data->type = it8628;
3045                 break;
3046         case IT8655E_DEVID:
3047                 sio_data->type = it8655;
3048                 break;
3049         case IT8665E_DEVID:
3050                 sio_data->type = it8665;
3051                 break;
3052         case IT8686E_DEVID:
3053                 sio_data->type = it8686;
3054                 break;
3055         case 0xffff:    /* No device at all */
3056                 goto exit;
3057         default:
3058                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3059                 goto exit;
3060         }
3061
3062         superio_select(sioaddr, PME);
3063         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3064                 pr_info("Device not activated, skipping\n");
3065                 goto exit;
3066         }
3067
3068         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3069         if (*address == 0) {
3070                 pr_info("Base address not set, skipping\n");
3071                 goto exit;
3072         }
3073
3074         sio_data->doexit = doexit;
3075
3076         err = 0;
3077         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3078         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
3079                 it87_devices[sio_data->type].suffix,
3080                 *address, sio_data->revision);
3081
3082         config = &it87_devices[sio_data->type];
3083
3084         /* in7 (VSB or VCCH5V) is always internal on some chips */
3085         if (has_in7_internal(config))
3086                 sio_data->internal |= BIT(1);
3087
3088         /* in8 (Vbat) is always internal */
3089         sio_data->internal |= BIT(2);
3090
3091         /* in9 (AVCC3), always internal if supported */
3092         if (has_avcc3(config))
3093                 sio_data->internal |= BIT(3); /* in9 is AVCC */
3094         else
3095                 sio_data->skip_in |= BIT(9);
3096
3097         if (!has_four_pwm(config))
3098                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3099         else if (!has_five_pwm(config))
3100                 sio_data->skip_pwm |= BIT(4) | BIT(5);
3101         else if (!has_six_pwm(config))
3102                 sio_data->skip_pwm |= BIT(5);
3103
3104         if (!has_vid(config))
3105                 sio_data->skip_vid = 1;
3106
3107         /* Read GPIO config and VID value from LDN 7 (GPIO) */
3108         if (sio_data->type == it87) {
3109                 /* The IT8705F has a different LD number for GPIO */
3110                 superio_select(sioaddr, 5);
3111                 sio_data->beep_pin = superio_inb(sioaddr,
3112                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3113         } else if (sio_data->type == it8783) {
3114                 int reg25, reg27, reg2a, reg2c, regef;
3115
3116                 superio_select(sioaddr, GPIO);
3117
3118                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3119                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3120                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3121                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3122                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3123
3124                 /* Check if fan3 is there or not */
3125                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3126                         sio_data->skip_fan |= BIT(2);
3127                 if ((reg25 & BIT(4)) ||
3128                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
3129                         sio_data->skip_pwm |= BIT(2);
3130
3131                 /* Check if fan2 is there or not */
3132                 if (reg27 & BIT(7))
3133                         sio_data->skip_fan |= BIT(1);
3134                 if (reg27 & BIT(3))
3135                         sio_data->skip_pwm |= BIT(1);
3136
3137                 /* VIN5 */
3138                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3139                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3140
3141                 /* VIN6 */
3142                 if (reg27 & BIT(1))
3143                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3144
3145                 /*
3146                  * VIN7
3147                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3148                  */
3149                 if (reg27 & BIT(2)) {
3150                         /*
3151                          * The data sheet is a bit unclear regarding the
3152                          * internal voltage divider for VCCH5V. It says
3153                          * "This bit enables and switches VIN7 (pin 91) to the
3154                          * internal voltage divider for VCCH5V".
3155                          * This is different to other chips, where the internal
3156                          * voltage divider would connect VIN7 to an internal
3157                          * voltage source. Maybe that is the case here as well.
3158                          *
3159                          * Since we don't know for sure, re-route it if that is
3160                          * not the case, and ask the user to report if the
3161                          * resulting voltage is sane.
3162                          */
3163                         if (!(reg2c & BIT(1))) {
3164                                 reg2c |= BIT(1);
3165                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3166                                              reg2c);
3167                                 pr_notice("Routing internal VCCH5V to in7.\n");
3168                         }
3169                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3170                         pr_notice("Please report if it displays a reasonable voltage.\n");
3171                 }
3172
3173                 if (reg2c & BIT(0))
3174                         sio_data->internal |= BIT(0);
3175                 if (reg2c & BIT(1))
3176                         sio_data->internal |= BIT(1);
3177
3178                 sio_data->beep_pin = superio_inb(sioaddr,
3179                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3180         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3181                 int reg27, reg29;
3182
3183                 superio_select(sioaddr, GPIO);
3184
3185                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3186
3187                 /* Check if fan3 is there or not */
3188                 if (reg27 & BIT(6))
3189                         sio_data->skip_pwm |= BIT(2);
3190                 if (reg27 & BIT(7))
3191                         sio_data->skip_fan |= BIT(2);
3192
3193                 /* Check if fan2 is there or not */
3194                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3195                 if (reg29 & BIT(1))
3196                         sio_data->skip_pwm |= BIT(1);
3197                 if (reg29 & BIT(2))
3198                         sio_data->skip_fan |= BIT(1);
3199
3200                 switch (sio_data->type) {
3201                 case it8603:
3202                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3203                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3204                         break;
3205                 case it8607:
3206                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3207                         sio_data->skip_fan |= BIT(0);
3208                 default:
3209                         break;
3210                 }
3211
3212                 sio_data->beep_pin = superio_inb(sioaddr,
3213                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3214         } else if (sio_data->type == it8613) {
3215                 int reg27, reg29, reg2a;
3216
3217                 superio_select(sioaddr, GPIO);
3218
3219                 /* Check for pwm3, fan3, pwm5, fan5 */
3220                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3221                 if (reg27 & BIT(1))
3222                         sio_data->skip_fan |= BIT(4);
3223                 if (reg27 & BIT(3))
3224                         sio_data->skip_pwm |= BIT(4);
3225                 if (reg27 & BIT(6))
3226                         sio_data->skip_pwm |= BIT(2);
3227                 if (reg27 & BIT(7))
3228                         sio_data->skip_fan |= BIT(2);
3229
3230                 /* Check for pwm2, fan2 */
3231                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3232                 if (reg29 & BIT(1))
3233                         sio_data->skip_pwm |= BIT(1);
3234                 if (reg29 & BIT(2))
3235                         sio_data->skip_fan |= BIT(1);
3236
3237                 /* Check for pwm4, fan4 */
3238                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3239                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3240                         sio_data->skip_fan |= BIT(3);
3241                         sio_data->skip_pwm |= BIT(3);
3242                 }
3243
3244                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3245                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3246                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3247                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3248
3249                 sio_data->beep_pin = superio_inb(sioaddr,
3250                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3251         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3252                    sio_data->type == it8686) {
3253                 int reg;
3254
3255                 superio_select(sioaddr, GPIO);
3256
3257                 /* Check for pwm5 */
3258                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3259                 if (reg & BIT(6))
3260                         sio_data->skip_pwm |= BIT(4);
3261
3262                 /* Check for fan4, fan5 */
3263                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3264                 if (!(reg & BIT(5)))
3265                         sio_data->skip_fan |= BIT(3);
3266                 if (!(reg & BIT(4)))
3267                         sio_data->skip_fan |= BIT(4);
3268
3269                 /* Check for pwm3, fan3 */
3270                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3271                 if (reg & BIT(6))
3272                         sio_data->skip_pwm |= BIT(2);
3273                 if (reg & BIT(7))
3274                         sio_data->skip_fan |= BIT(2);
3275
3276                 /* Check for pwm4 */
3277                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3278                 if (reg & BIT(2))
3279                         sio_data->skip_pwm |= BIT(3);
3280
3281                 /* Check for pwm2, fan2 */
3282                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3283                 if (reg & BIT(1))
3284                         sio_data->skip_pwm |= BIT(1);
3285                 if (reg & BIT(2))
3286                         sio_data->skip_fan |= BIT(1);
3287                 /* Check for pwm6, fan6 */
3288                 if (!(reg & BIT(7))) {
3289                         sio_data->skip_pwm |= BIT(5);
3290                         sio_data->skip_fan |= BIT(5);
3291                 }
3292
3293                 /* Check if AVCC is on VIN3 */
3294                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3295                 if (reg & BIT(0)) {
3296                         /* For it8686, the bit just enables AVCC3 */
3297                         if (sio_data->type != it8686)
3298                                 sio_data->internal |= BIT(0);
3299                 } else {
3300                         sio_data->internal &= ~BIT(3);
3301                         sio_data->skip_in |= BIT(9);
3302                 }
3303
3304                 sio_data->beep_pin = superio_inb(sioaddr,
3305                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3306         } else if (sio_data->type == it8622) {
3307                 int reg;
3308
3309                 superio_select(sioaddr, GPIO);
3310
3311                 /* Check for pwm4, fan4 */
3312                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3313                 if (reg & BIT(6))
3314                         sio_data->skip_fan |= BIT(3);
3315                 if (reg & BIT(5))
3316                         sio_data->skip_pwm |= BIT(3);
3317
3318                 /* Check for pwm3, fan3, pwm5, fan5 */
3319                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3320                 if (reg & BIT(6))
3321                         sio_data->skip_pwm |= BIT(2);
3322                 if (reg & BIT(7))
3323                         sio_data->skip_fan |= BIT(2);
3324                 if (reg & BIT(3))
3325                         sio_data->skip_pwm |= BIT(4);
3326                 if (reg & BIT(1))
3327                         sio_data->skip_fan |= BIT(4);
3328
3329                 /* Check for pwm2, fan2 */
3330                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3331                 if (reg & BIT(1))
3332                         sio_data->skip_pwm |= BIT(1);
3333                 if (reg & BIT(2))
3334                         sio_data->skip_fan |= BIT(1);
3335
3336                 /* Check for AVCC */
3337                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3338                 if (!(reg & BIT(0)))
3339                         sio_data->skip_in |= BIT(9);
3340
3341                 sio_data->beep_pin = superio_inb(sioaddr,
3342                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3343         } else if (sio_data->type == it8732) {
3344                 int reg;
3345
3346                 superio_select(sioaddr, GPIO);
3347
3348                 /* Check for pwm2, fan2 */
3349                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3350                 if (reg & BIT(1))
3351                         sio_data->skip_pwm |= BIT(1);
3352                 if (reg & BIT(2))
3353                         sio_data->skip_fan |= BIT(1);
3354
3355                 /* Check for pwm3, fan3, fan4 */
3356                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3357                 if (reg & BIT(6))
3358                         sio_data->skip_pwm |= BIT(2);
3359                 if (reg & BIT(7))
3360                         sio_data->skip_fan |= BIT(2);
3361                 if (reg & BIT(5))
3362                         sio_data->skip_fan |= BIT(3);
3363
3364                 /* Check if AVCC is on VIN3 */
3365                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3366                 if (reg & BIT(0))
3367                         sio_data->internal |= BIT(0);
3368
3369                 sio_data->beep_pin = superio_inb(sioaddr,
3370                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3371         } else if (sio_data->type == it8655) {
3372                 int reg;
3373
3374                 superio_select(sioaddr, GPIO);
3375
3376                 /* Check for pwm2 */
3377                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3378                 if (reg & BIT(1))
3379                         sio_data->skip_pwm |= BIT(1);
3380
3381                 /* Check for fan2 */
3382                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3383                 if (reg & BIT(4))
3384                         sio_data->skip_fan |= BIT(1);
3385
3386                 /* Check for pwm3, fan3 */
3387                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3388                 if (reg & BIT(6))
3389                         sio_data->skip_pwm |= BIT(2);
3390                 if (reg & BIT(7))
3391                         sio_data->skip_fan |= BIT(2);
3392
3393                 sio_data->beep_pin = superio_inb(sioaddr,
3394                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3395         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3396                 int reg27, reg29, reg2d, regd3;
3397
3398                 superio_select(sioaddr, GPIO);
3399
3400                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3401                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3402                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3403                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3404
3405                 /* Check for pwm2, fan2 */
3406                 if (reg29 & BIT(1))
3407                         sio_data->skip_pwm |= BIT(1);
3408                 /*
3409                  * Note: Table 6-1 in datasheet claims that FAN_TAC2
3410                  * would be enabled with 29h[2]=0.
3411                  */
3412                 if (reg2d & BIT(4))
3413                         sio_data->skip_fan |= BIT(1);
3414
3415                 /* Check for pwm3, fan3 */
3416                 if (reg27 & BIT(6))
3417                         sio_data->skip_pwm |= BIT(2);
3418                 if (reg27 & BIT(7))
3419                         sio_data->skip_fan |= BIT(2);
3420
3421                 /* Check for pwm4, fan4, pwm5, fan5 */
3422                 if (sio_data->type == it8625) {
3423                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3424
3425                         if (reg25 & BIT(6))
3426                                 sio_data->skip_fan |= BIT(3);
3427                         if (reg25 & BIT(5))
3428                                 sio_data->skip_pwm |= BIT(3);
3429                         if (reg27 & BIT(3))
3430                                 sio_data->skip_pwm |= BIT(4);
3431                         if (reg27 & BIT(1))
3432                                 sio_data->skip_fan |= BIT(4);
3433                 } else {
3434                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3435
3436                         if (regd3 & BIT(2))
3437                                 sio_data->skip_pwm |= BIT(3);
3438                         if (regd3 & BIT(3))
3439                                 sio_data->skip_fan |= BIT(3);
3440                         if (reg26 & BIT(5))
3441                                 sio_data->skip_pwm |= BIT(4);
3442                         if (reg26 & BIT(4))
3443                                 sio_data->skip_fan |= BIT(4);
3444                 }
3445
3446                 /* Check for pwm6, fan6 */
3447                 if (regd3 & BIT(0))
3448                         sio_data->skip_pwm |= BIT(5);
3449                 if (regd3 & BIT(1))
3450                         sio_data->skip_fan |= BIT(5);
3451
3452                 sio_data->beep_pin = superio_inb(sioaddr,
3453                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3454         } else {
3455                 int reg;
3456                 bool uart6;
3457
3458                 superio_select(sioaddr, GPIO);
3459
3460                 /* Check for fan4, fan5 */
3461                 if (has_five_fans(config)) {
3462                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3463                         switch (sio_data->type) {
3464                         case it8718:
3465                                 if (reg & BIT(5))
3466                                         sio_data->skip_fan |= BIT(3);
3467                                 if (reg & BIT(4))
3468                                         sio_data->skip_fan |= BIT(4);
3469                                 break;
3470                         case it8720:
3471                         case it8721:
3472                         case it8728:
3473                                 if (!(reg & BIT(5)))
3474                                         sio_data->skip_fan |= BIT(3);
3475                                 if (!(reg & BIT(4)))
3476                                         sio_data->skip_fan |= BIT(4);
3477                                 break;
3478                         default:
3479                                 break;
3480                         }
3481                 }
3482
3483                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3484                 if (!sio_data->skip_vid) {
3485                         /* We need at least 4 VID pins */
3486                         if (reg & 0x0f) {
3487                                 pr_info("VID is disabled (pins used for GPIO)\n");
3488                                 sio_data->skip_vid = 1;
3489                         }
3490                 }
3491
3492                 /* Check if fan3 is there or not */
3493                 if (reg & BIT(6))
3494                         sio_data->skip_pwm |= BIT(2);
3495                 if (reg & BIT(7))
3496                         sio_data->skip_fan |= BIT(2);
3497
3498                 /* Check if fan2 is there or not */
3499                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3500                 if (reg & BIT(1))
3501                         sio_data->skip_pwm |= BIT(1);
3502                 if (reg & BIT(2))
3503                         sio_data->skip_fan |= BIT(1);
3504
3505                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3506                     !(sio_data->skip_vid))
3507                         sio_data->vid_value = superio_inb(sioaddr,
3508                                                           IT87_SIO_VID_REG);
3509
3510                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3511
3512                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3513
3514                 /*
3515                  * The IT8720F has no VIN7 pin, so VCCH should always be
3516                  * routed internally to VIN7 with an internal divider.
3517                  * Curiously, there still is a configuration bit to control
3518                  * this, which means it can be set incorrectly. And even
3519                  * more curiously, many boards out there are improperly
3520                  * configured, even though the IT8720F datasheet claims
3521                  * that the internal routing of VCCH to VIN7 is the default
3522                  * setting. So we force the internal routing in this case.
3523                  *
3524                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3525                  * If UART6 is enabled, re-route VIN7 to the internal divider
3526                  * if that is not already the case.
3527                  */
3528                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3529                         reg |= BIT(1);
3530                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3531                         pr_notice("Routing internal VCCH to in7\n");
3532                 }
3533                 if (reg & BIT(0))
3534                         sio_data->internal |= BIT(0);
3535                 if (reg & BIT(1))
3536                         sio_data->internal |= BIT(1);
3537
3538                 /*
3539                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3540                  * While VIN7 can be routed to the internal voltage divider,
3541                  * VIN5 and VIN6 are not available if UART6 is enabled.
3542                  *
3543                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3544                  * is the temperature source. Since we can not read the
3545                  * temperature source here, skip_temp is preliminary.
3546                  */
3547                 if (uart6) {
3548                         sio_data->skip_in |= BIT(5) | BIT(6);
3549                         sio_data->skip_temp |= BIT(2);
3550                 }
3551
3552                 sio_data->beep_pin = superio_inb(sioaddr,
3553                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3554         }
3555         if (sio_data->beep_pin)
3556                 pr_info("Beeping is supported\n");
3557
3558         if (config->smbus_bitmap) {
3559                 u8 reg;
3560
3561                 superio_select(sioaddr, PME);
3562                 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3563                 sio_data->ec_special_config = reg;
3564                 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3565         }
3566
3567 exit:
3568         superio_exit(sioaddr, doexit);
3569         return err;
3570 }
3571
3572 static void it87_init_regs(struct platform_device *pdev)
3573 {
3574         struct it87_data *data = platform_get_drvdata(pdev);
3575
3576         /* Initialize chip specific register pointers */
3577         switch (data->type) {
3578         case it8628:
3579         case it8686:
3580                 data->REG_FAN = IT87_REG_FAN;
3581                 data->REG_FANX = IT87_REG_FANX;
3582                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3583                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3584                 data->REG_PWM = IT87_REG_PWM;
3585                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3586                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3587                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3588                 break;
3589         case it8625:
3590         case it8655:
3591         case it8665:
3592                 data->REG_FAN = IT87_REG_FAN_8665;
3593                 data->REG_FANX = IT87_REG_FANX_8665;
3594                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3595                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3596                 data->REG_PWM = IT87_REG_PWM_8665;
3597                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3598                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3599                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3600                 break;
3601         case it8622:
3602                 data->REG_FAN = IT87_REG_FAN;
3603                 data->REG_FANX = IT87_REG_FANX;
3604                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3605                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3606                 data->REG_PWM = IT87_REG_PWM_8665;
3607                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3608                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3609                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3610                 break;
3611         case it8613:
3612                 data->REG_FAN = IT87_REG_FAN;
3613                 data->REG_FANX = IT87_REG_FANX;
3614                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3615                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3616                 data->REG_PWM = IT87_REG_PWM_8665;
3617                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3618                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3619                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3620                 break;
3621         default:
3622                 data->REG_FAN = IT87_REG_FAN;
3623                 data->REG_FANX = IT87_REG_FANX;
3624                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3625                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3626                 data->REG_PWM = IT87_REG_PWM;
3627                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3628                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3629                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3630                 break;
3631         }
3632 }
3633
3634 /* Called when we have found a new IT87. */
3635 static void it87_init_device(struct platform_device *pdev)
3636 {
3637         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3638         struct it87_data *data = platform_get_drvdata(pdev);
3639         int tmp, i;
3640         u8 mask;
3641
3642         if (has_new_tempmap(data)) {
3643                 data->pwm_temp_map_shift = 3;
3644                 data->pwm_temp_map_mask = 0x07;
3645         } else {
3646                 data->pwm_temp_map_shift = 0;
3647                 data->pwm_temp_map_mask = 0x03;
3648         }
3649
3650         /*
3651          * For each PWM channel:
3652          * - If it is in automatic mode, setting to manual mode should set
3653          *   the fan to full speed by default.
3654          * - If it is in manual mode, we need a mapping to temperature
3655          *   channels to use when later setting to automatic mode later.
3656          *   Map to the first sensor by default (we are clueless.)
3657          * In both cases, the value can (and should) be changed by the user
3658          * prior to switching to a different mode.
3659          * Note that this is no longer needed for the IT8721F and later, as
3660          * these have separate registers for the temperature mapping and the
3661          * manual duty cycle.
3662          */
3663         for (i = 0; i < NUM_AUTO_PWM; i++) {
3664                 data->pwm_temp_map[i] = 0;
3665                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3666                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3667         }
3668
3669         /*
3670          * Some chips seem to have default value 0xff for all limit
3671          * registers. For low voltage limits it makes no sense and triggers
3672          * alarms, so change to 0 instead. For high temperature limits, it
3673          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3674          * but is still confusing, so change to 127 degrees C.
3675          */
3676         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3677                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3678                 if (tmp == 0xff)
3679                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3680         }
3681         for (i = 0; i < data->num_temp_limit; i++) {
3682                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3683                 if (tmp == 0xff)
3684                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3685         }
3686
3687         /*
3688          * Temperature channels are not forcibly enabled, as they can be
3689          * set to two different sensor types and we can't guess which one
3690          * is correct for a given system. These channels can be enabled at
3691          * run-time through the temp{1-3}_type sysfs accessors if needed.
3692          */
3693
3694         /* Check if voltage monitors are reset manually or by some reason */
3695         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3696         if ((tmp & 0xff) == 0) {
3697                 /* Enable all voltage monitors */
3698                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3699         }
3700
3701         /* Check if tachometers are reset manually or by some reason */
3702         mask = 0x70 & ~(sio_data->skip_fan << 4);
3703         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3704         if ((data->fan_main_ctrl & mask) == 0) {
3705                 /* Enable all fan tachometers */
3706                 data->fan_main_ctrl |= mask;
3707                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3708                                  data->fan_main_ctrl);
3709         }
3710         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3711
3712         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3713
3714         /* Set tachometers to 16-bit mode if needed */
3715         if (has_fan16_config(data)) {
3716                 if (~tmp & 0x07 & data->has_fan) {
3717                         dev_dbg(&pdev->dev,
3718                                 "Setting fan1-3 to 16-bit mode\n");
3719                         it87_write_value(data, IT87_REG_FAN_16BIT,
3720                                          tmp | 0x07);
3721                 }
3722         }
3723
3724         /* Check for additional fans */
3725         if (has_four_fans(data) && (tmp & BIT(4)))
3726                 data->has_fan |= BIT(3); /* fan4 enabled */
3727         if (has_five_fans(data) && (tmp & BIT(5)))
3728                 data->has_fan |= BIT(4); /* fan5 enabled */
3729         if (has_six_fans(data)) {
3730                 switch (data->type) {
3731                 case it8620:
3732                 case it8628:
3733                 case it8686:
3734                         if (tmp & BIT(2))
3735                                 data->has_fan |= BIT(5); /* fan6 enabled */
3736                         break;
3737                 case it8625:
3738                 case it8665:
3739                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3740                         if (tmp & BIT(3))
3741                                 data->has_fan |= BIT(5); /* fan6 enabled */
3742                         break;
3743                 default:
3744                         break;
3745                 }
3746         }
3747
3748         /* Fan input pins may be used for alternative functions */
3749         data->has_fan &= ~sio_data->skip_fan;
3750
3751         /* Check if pwm6 is enabled */
3752         if (has_six_pwm(data)) {
3753                 switch (data->type) {
3754                 case it8620:
3755                 case it8686:
3756                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3757                         if (!(tmp & BIT(3)))
3758                                 sio_data->skip_pwm |= BIT(5);
3759                         break;
3760                 default:
3761                         break;
3762                 }
3763         }
3764
3765         if (has_bank_sel(data)) {
3766                 for (i = 0; i < 3; i++)
3767                         data->temp_src[i] =
3768                                 it87_read_value(data, IT87_REG_TEMP_SRC1[i]);
3769                 data->temp_src[3] = it87_read_value(data, IT87_REG_TEMP_SRC2);
3770         }
3771
3772         /* Start monitoring */
3773         it87_write_value(data, IT87_REG_CONFIG,
3774                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3775                          | (update_vbat ? 0x41 : 0x01));
3776 }
3777
3778 /* Return 1 if and only if the PWM interface is safe to use */
3779 static int it87_check_pwm(struct device *dev)
3780 {
3781         struct it87_data *data = dev_get_drvdata(dev);
3782         /*
3783          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3784          * and polarity set to active low is sign that this is the case so we
3785          * disable pwm control to protect the user.
3786          */
3787         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3788
3789         if ((tmp & 0x87) == 0) {
3790                 if (fix_pwm_polarity) {
3791                         /*
3792                          * The user asks us to attempt a chip reconfiguration.
3793                          * This means switching to active high polarity and
3794                          * inverting all fan speed values.
3795                          */
3796                         int i;
3797                         u8 pwm[3];
3798
3799                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3800                                 pwm[i] = it87_read_value(data,
3801                                                          data->REG_PWM[i]);
3802
3803                         /*
3804                          * If any fan is in automatic pwm mode, the polarity
3805                          * might be correct, as suspicious as it seems, so we
3806                          * better don't change anything (but still disable the
3807                          * PWM interface).
3808                          */
3809                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3810                                 dev_info(dev,
3811                                          "Reconfiguring PWM to active high polarity\n");
3812                                 it87_write_value(data, IT87_REG_FAN_CTL,
3813                                                  tmp | 0x87);
3814                                 for (i = 0; i < 3; i++)
3815                                         it87_write_value(data,
3816                                                          data->REG_PWM[i],
3817                                                          0x7f & ~pwm[i]);
3818                                 return 1;
3819                         }
3820
3821                         dev_info(dev,
3822                                  "PWM configuration is too broken to be fixed\n");
3823                 }
3824
3825                 dev_info(dev,
3826                          "Detected broken BIOS defaults, disabling PWM interface\n");
3827                 return 0;
3828         } else if (fix_pwm_polarity) {
3829                 dev_info(dev,
3830                          "PWM configuration looks sane, won't touch\n");
3831         }
3832
3833         return 1;
3834 }
3835
3836 static int it87_probe(struct platform_device *pdev)
3837 {
3838         struct it87_data *data;
3839         struct resource *res;
3840         struct device *dev = &pdev->dev;
3841         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3842         int enable_pwm_interface;
3843         struct device *hwmon_dev;
3844         int err;
3845
3846         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3847         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3848                                  DRVNAME)) {
3849                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3850                         (unsigned long)res->start,
3851                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3852                 return -EBUSY;
3853         }
3854
3855         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3856         if (!data)
3857                 return -ENOMEM;
3858
3859         data->addr = res->start;
3860         data->type = sio_data->type;
3861         data->sioaddr = sio_data->sioaddr;
3862         data->smbus_bitmap = sio_data->smbus_bitmap;
3863         data->ec_special_config = sio_data->ec_special_config;
3864         data->doexit = sio_data->doexit;
3865         data->features = it87_devices[sio_data->type].features;
3866         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3867         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3868         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3869         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3870         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3871
3872         /*
3873          * IT8705F Datasheet 0.4.1, 3h == Version G.
3874          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3875          * These are the first revisions with 16-bit tachometer support.
3876          */
3877         switch (data->type) {
3878         case it87:
3879                 if (sio_data->revision >= 0x03) {
3880                         data->features &= ~FEAT_OLD_AUTOPWM;
3881                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3882                 }
3883                 break;
3884         case it8712:
3885                 if (sio_data->revision >= 0x08) {
3886                         data->features &= ~FEAT_OLD_AUTOPWM;
3887                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3888                                           FEAT_FIVE_FANS;
3889                 }
3890                 break;
3891         default:
3892                 break;
3893         }
3894
3895         platform_set_drvdata(pdev, data);
3896
3897         mutex_init(&data->update_lock);
3898
3899         /* Initialize register pointers */
3900         it87_init_regs(pdev);
3901
3902         err = smbus_disable(data);
3903         if (err)
3904                 return err;
3905
3906         /* Now, we do the remaining detection. */
3907         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3908             it87_read_value(data, IT87_REG_CHIPID) != 0x90) {
3909                 smbus_enable(data);
3910                 return -ENODEV;
3911         }
3912
3913         /* Check PWM configuration */
3914         enable_pwm_interface = it87_check_pwm(dev);
3915
3916         /* Starting with IT8721F, we handle scaling of internal voltages */
3917         if (has_scaling(data)) {
3918                 if (sio_data->internal & BIT(0))
3919                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3920                 if (sio_data->internal & BIT(1))
3921                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3922                 if (sio_data->internal & BIT(2))
3923                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3924                 if (sio_data->internal & BIT(3))
3925                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3926         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3927                    sio_data->type == it8783) {
3928                 if (sio_data->internal & BIT(0))
3929                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3930                 if (sio_data->internal & BIT(1))
3931                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3932         }
3933
3934         data->has_temp = 0x07;
3935         if (sio_data->skip_temp & BIT(2)) {
3936                 if (sio_data->type == it8782 &&
3937                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3938                         data->has_temp &= ~BIT(2);
3939         }
3940
3941         data->in_internal = sio_data->internal;
3942         data->has_in = 0x3ff & ~sio_data->skip_in;
3943
3944         if (has_six_temp(data)) {
3945                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3946
3947                 /* Check for additional temperature sensors */
3948                 if ((reg & 0x03) >= 0x02)
3949                         data->has_temp |= BIT(3);
3950                 if (((reg >> 2) & 0x03) >= 0x02)
3951                         data->has_temp |= BIT(4);
3952                 if (((reg >> 4) & 0x03) >= 0x02)
3953                         data->has_temp |= BIT(5);
3954
3955                 /* Check for additional voltage sensors */
3956                 if ((reg & 0x03) == 0x01)
3957                         data->has_in |= BIT(10);
3958                 if (((reg >> 2) & 0x03) == 0x01)
3959                         data->has_in |= BIT(11);
3960                 if (((reg >> 4) & 0x03) == 0x01)
3961                         data->has_in |= BIT(12);
3962         }
3963
3964         data->has_beep = !!sio_data->beep_pin;
3965
3966         /* Initialize the IT87 chip */
3967         it87_init_device(pdev);
3968
3969         smbus_enable(data);
3970
3971         if (!sio_data->skip_vid) {
3972                 data->has_vid = true;
3973                 data->vrm = vid_which_vrm();
3974                 /* VID reading from Super-I/O config space if available */
3975                 data->vid = sio_data->vid_value;
3976         }
3977
3978         /* Prepare for sysfs hooks */
3979         data->groups[0] = &it87_group;
3980         data->groups[1] = &it87_group_in;
3981         data->groups[2] = &it87_group_temp;
3982         data->groups[3] = &it87_group_fan;
3983
3984         if (enable_pwm_interface) {
3985                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3986                 data->has_pwm &= ~sio_data->skip_pwm;
3987
3988                 data->groups[4] = &it87_group_pwm;
3989                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3990                         data->groups[5] = &it87_group_auto_pwm;
3991         }
3992
3993         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3994                                         it87_devices[sio_data->type].name,
3995                                         data, data->groups);
3996         return PTR_ERR_OR_ZERO(hwmon_dev);
3997 }
3998
3999 static struct platform_driver it87_driver = {
4000         .driver = {
4001                 .name   = DRVNAME,
4002         },
4003         .probe  = it87_probe,
4004 };
4005
4006 static int __init it87_device_add(int index, unsigned short address,
4007                                   const struct it87_sio_data *sio_data)
4008 {
4009         struct platform_device *pdev;
4010         struct resource res = {
4011                 .start  = address + IT87_EC_OFFSET,
4012                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
4013                 .name   = DRVNAME,
4014                 .flags  = IORESOURCE_IO,
4015         };
4016         int err;
4017
4018         err = acpi_check_resource_conflict(&res);
4019         if (err) {
4020                 if (!ignore_resource_conflict)
4021                         return err;
4022         }
4023
4024         pdev = platform_device_alloc(DRVNAME, address);
4025         if (!pdev)
4026                 return -ENOMEM;
4027
4028         err = platform_device_add_resources(pdev, &res, 1);
4029         if (err) {
4030                 pr_err("Device resource addition failed (%d)\n", err);
4031                 goto exit_device_put;
4032         }
4033
4034         err = platform_device_add_data(pdev, sio_data,
4035                                        sizeof(struct it87_sio_data));
4036         if (err) {
4037                 pr_err("Platform data allocation failed\n");
4038                 goto exit_device_put;
4039         }
4040
4041         err = platform_device_add(pdev);
4042         if (err) {
4043                 pr_err("Device addition failed (%d)\n", err);
4044                 goto exit_device_put;
4045         }
4046
4047         it87_pdev[index] = pdev;
4048         return 0;
4049
4050 exit_device_put:
4051         platform_device_put(pdev);
4052         return err;
4053 }
4054
4055 struct it87_dmi_data {
4056         bool sio2_force_config; /* force sio2 into configuration mode   */
4057         u8 skip_pwm;            /* pwm channels to skip for this board  */
4058 };
4059
4060 /*
4061  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4062  * (IT8792E) needs to be in configuration mode before accessing the first
4063  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4064  * This needs to be done before accessing the first Super-IO chip since
4065  * the second chip may have been accessed prior to loading this driver.
4066  *
4067  * The problem is also reported to affect IT8795E, which is used on X299 boards
4068  * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4069  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4070  * Z87X-OC.
4071  * DMI entries for those systems will be added as they become available and
4072  * as the problem is confirmed to affect those boards.
4073  */
4074 static struct it87_dmi_data gigabyte_sio2_force = {
4075         .sio2_force_config = true,
4076 };
4077
4078 /*
4079  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4080  * connected to a fan, but to something else. One user
4081  * has reported instant system power-off when changing
4082  * the PWM2 duty cycle, so we disable it.
4083  * I use the board name string as the trigger in case
4084  * the same board is ever used in other systems.
4085  */
4086 static struct it87_dmi_data nvidia_fn68pt = {
4087         .skip_pwm = BIT(1),
4088 };
4089
4090 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4091         {
4092                 .matches = {
4093                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4094                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4095                 },
4096                 .driver_data = &gigabyte_sio2_force,
4097         },
4098         {
4099                 .matches = {
4100                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4101                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4102                 },
4103                 .driver_data = &gigabyte_sio2_force,
4104         },
4105         {
4106                 .matches = {
4107                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4108                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4109                 },
4110                 .driver_data = &gigabyte_sio2_force,
4111         },
4112         {
4113                 .matches = {
4114                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4115                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4116                 },
4117                 .driver_data = &nvidia_fn68pt,
4118         },
4119         { }
4120 };
4121
4122 static int __init sm_it87_init(void)
4123 {
4124         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4125         struct it87_dmi_data *dmi_data = NULL;
4126         int sioaddr[2] = { REG_2E, REG_4E };
4127         struct it87_sio_data sio_data;
4128         unsigned short isa_address;
4129         bool found = false;
4130         int i, err;
4131
4132         pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4133
4134         if (dmi)
4135                 dmi_data = dmi->driver_data;
4136
4137         err = platform_driver_register(&it87_driver);
4138         if (err)
4139                 return err;
4140
4141         if (dmi_data && dmi_data->sio2_force_config)
4142                 __superio_enter(REG_4E);
4143
4144         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4145                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4146                 isa_address = 0;
4147                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
4148                 if (err || isa_address == 0)
4149                         continue;
4150
4151                 if (dmi_data)
4152                         sio_data.skip_pwm |= dmi_data->skip_pwm;
4153                 err = it87_device_add(i, isa_address, &sio_data);
4154                 if (err)
4155                         goto exit_dev_unregister;
4156                 found = true;
4157         }
4158
4159         if (!found) {
4160                 err = -ENODEV;
4161                 goto exit_unregister;
4162         }
4163         return 0;
4164
4165 exit_dev_unregister:
4166         /* NULL check handled by platform_device_unregister */
4167         platform_device_unregister(it87_pdev[0]);
4168 exit_unregister:
4169         platform_driver_unregister(&it87_driver);
4170         return err;
4171 }
4172
4173 static void __exit sm_it87_exit(void)
4174 {
4175         /* NULL check handled by platform_device_unregister */
4176         platform_device_unregister(it87_pdev[1]);
4177         platform_device_unregister(it87_pdev[0]);
4178         platform_driver_unregister(&it87_driver);
4179 }
4180
4181 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4182 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4183 module_param(update_vbat, bool, 0);
4184 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4185 module_param(fix_pwm_polarity, bool, 0);
4186 MODULE_PARM_DESC(fix_pwm_polarity,
4187                  "Force PWM polarity to active high (DANGEROUS)");
4188 MODULE_LICENSE("GPL");
4189
4190 module_init(sm_it87_init);
4191 module_exit(sm_it87_exit);