git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8620E  Super I/O chip w/LPC interface
  16  *            IT8622E  Super I/O chip w/LPC interface
  17  *            IT8623E  Super I/O chip w/LPC interface
  18  *            IT8628E  Super I/O chip w/LPC interface
  19  *            IT8655E  Super I/O chip w/LPC interface
  20  *            IT8665E  Super I/O chip w/LPC interface
  21  *            IT8686E  Super I/O chip w/LPC interface
  22  *            IT8705F  Super I/O chip w/LPC interface
  23  *            IT8712F  Super I/O chip w/LPC interface
  24  *            IT8716F  Super I/O chip w/LPC interface
  25  *            IT8718F  Super I/O chip w/LPC interface
  26  *            IT8720F  Super I/O chip w/LPC interface
  27  *            IT8721F  Super I/O chip w/LPC interface
  28  *            IT8726F  Super I/O chip w/LPC interface
  29  *            IT8728F  Super I/O chip w/LPC interface
  30  *            IT8732F  Super I/O chip w/LPC interface
  31  *            IT8758E  Super I/O chip w/LPC interface
  32  *            IT8771E  Super I/O chip w/LPC interface
  33  *            IT8772E  Super I/O chip w/LPC interface
  34  *            IT8781F  Super I/O chip w/LPC interface
  35  *            IT8782F  Super I/O chip w/LPC interface
  36  *            IT8783E/F Super I/O chip w/LPC interface
  37  *            IT8786E  Super I/O chip w/LPC interface
  38  *            IT8790E  Super I/O chip w/LPC interface
  39  *            IT8792E  Super I/O chip w/LPC interface
  40  *            Sis950   A clone of the IT8705F
  41  *
  42  *  Copyright (C) 2001 Chris Gauthron
  43  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  44  *
  45  *  This program is free software; you can redistribute it and/or modify
  46  *  it under the terms of the GNU General Public License as published by
  47  *  the Free Software Foundation; either version 2 of the License, or
  48  *  (at your option) any later version.
  49  *
  50  *  This program is distributed in the hope that it will be useful,
  51  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  52  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  53  *  GNU General Public License for more details.
  54  */
  55
  56 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  57
  58 #include <linux/bitops.h>
  59 #include <linux/module.h>
  60 #include <linux/init.h>
  61 #include <linux/slab.h>
  62 #include <linux/jiffies.h>
  63 #include <linux/platform_device.h>
  64 #include <linux/hwmon.h>
  65 #include <linux/hwmon-sysfs.h>
  66 #include <linux/hwmon-vid.h>
  67 #include <linux/err.h>
  68 #include <linux/mutex.h>
  69 #include <linux/sysfs.h>
  70 #include <linux/string.h>
  71 #include <linux/dmi.h>
  72 #include <linux/acpi.h>
  73 #include <linux/io.h>
  74 #include "compat.h"
  75
  76 #define DRVNAME "it87"
  77
  78 /* Necessary API not (yet) exported in upstream kernel */
  79 /* #define __IT87_USE_ACPI_MUTEX */
  80
  81 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  82              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  83              it8792, it8603, it8607, it8620, it8622, it8628, it8655, it8665,
  84              it8686 };
  85
  86 static unsigned short force_id;
  87 module_param(force_id, ushort, 0);
  88 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  89
  90 static struct platform_device *it87_pdev[2];
  91 static bool it87_sio4e_broken;
  92 #ifdef __IT87_USE_ACPI_MUTEX
  93 static acpi_handle it87_acpi_sio_handle;
  94 static char *it87_acpi_sio_mutex;
  95 #endif
  96
  97 #define REG_2E  0x2e    /* The register to read/write */
  98 #define REG_4E  0x4e    /* Secondary register to read/write */
  99
 100 #define DEV     0x07    /* Register: Logical device select */
 101 #define PME     0x04    /* The device with the fan registers in it */
 102
 103 /* The device with the IT8718F/IT8720F VID value in it */
 104 #define GPIO    0x07
 105
 106 #define DEVID   0x20    /* Register: Device ID */
 107 #define DEVREV  0x22    /* Register: Device Revision */
 108
 109 static inline void __superio_enter(int ioreg)
 110 {
 111         outb(0x87, ioreg);
 112         outb(0x01, ioreg);
 113         outb(0x55, ioreg);
 114         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 115 }
 116
 117 static inline int superio_inb(int ioreg, int reg)
 118 {
 119         int val;
 120
 121         outb(reg, ioreg);
 122         val = inb(ioreg + 1);
 123         if (it87_sio4e_broken && ioreg == 0x4e && val == 0xff) {
 124                 __superio_enter(ioreg);
 125                 outb(reg, ioreg);
 126                 val = inb(ioreg + 1);
 127                 pr_warn("Retry access 0x4e:0x%x -> 0x%x\n", reg, val);
 128         }
 129
 130         return val;
 131 }
 132
 133 static inline void superio_outb(int ioreg, int reg, int val)
 134 {
 135         outb(reg, ioreg);
 136         outb(val, ioreg + 1);
 137 }
 138
 139 static int superio_inw(int ioreg, int reg)
 140 {
 141         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 142 }
 143
 144 static inline void superio_select(int ioreg, int ldn)
 145 {
 146         outb(DEV, ioreg);
 147         outb(ldn, ioreg + 1);
 148 }
 149
 150 static inline int superio_enter(int ioreg)
 151 {
 152 #ifdef __IT87_USE_ACPI_MUTEX
 153         if (it87_acpi_sio_mutex) {
 154                 acpi_status status;
 155
 156                 status = acpi_acquire_mutex(NULL, it87_acpi_sio_mutex, 0x10);
 157                 if (ACPI_FAILURE(status)) {
 158                         pr_err("Failed to acquire ACPI mutex\n");
 159                         return -EBUSY;
 160                 }
 161         }
 162 #endif
 163         /*
 164          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 165          */
 166         if (!request_muxed_region(ioreg, 2, DRVNAME))
 167                 goto error;
 168
 169         __superio_enter(ioreg);
 170         return 0;
 171
 172 error:
 173 #ifdef __IT87_USE_ACPI_MUTEX
 174         if (it87_acpi_sio_mutex)
 175                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 176 #endif
 177         return -EBUSY;
 178 }
 179
 180 static inline void superio_exit(int ioreg)
 181 {
 182         if (!it87_sio4e_broken || ioreg != 0x4e) {
 183                 outb(0x02, ioreg);
 184                 outb(0x02, ioreg + 1);
 185         }
 186         release_region(ioreg, 2);
 187 #ifdef __IT87_USE_ACPI_MUTEX
 188         if (it87_acpi_sio_mutex)
 189                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 190 #endif
 191 }
 192
 193 /* Logical device 4 registers */
 194 #define IT8712F_DEVID 0x8712
 195 #define IT8705F_DEVID 0x8705
 196 #define IT8716F_DEVID 0x8716
 197 #define IT8718F_DEVID 0x8718
 198 #define IT8720F_DEVID 0x8720
 199 #define IT8721F_DEVID 0x8721
 200 #define IT8726F_DEVID 0x8726
 201 #define IT8728F_DEVID 0x8728
 202 #define IT8732F_DEVID 0x8732
 203 #define IT8792E_DEVID 0x8733
 204 #define IT8771E_DEVID 0x8771
 205 #define IT8772E_DEVID 0x8772
 206 #define IT8781F_DEVID 0x8781
 207 #define IT8782F_DEVID 0x8782
 208 #define IT8783E_DEVID 0x8783
 209 #define IT8786E_DEVID 0x8786
 210 #define IT8790E_DEVID 0x8790
 211 #define IT8603E_DEVID 0x8603
 212 #define IT8607E_DEVID 0x8607
 213 #define IT8620E_DEVID 0x8620
 214 #define IT8622E_DEVID 0x8622
 215 #define IT8623E_DEVID 0x8623
 216 #define IT8628E_DEVID 0x8628
 217 #define IT8655E_DEVID 0x8655
 218 #define IT8665E_DEVID 0x8665
 219 #define IT8686E_DEVID 0x8686
 220 #define IT87_ACT_REG  0x30
 221 #define IT87_BASE_REG 0x60
 222
 223 /* Logical device 7 registers (IT8712F and later) */
 224 #define IT87_SIO_GPIO1_REG      0x25
 225 #define IT87_SIO_GPIO2_REG      0x26
 226 #define IT87_SIO_GPIO3_REG      0x27
 227 #define IT87_SIO_GPIO4_REG      0x28
 228 #define IT87_SIO_GPIO5_REG      0x29
 229 #define IT87_SIO_GPIO9_REG      0xd3
 230 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 231 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 232 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 233 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 234 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 235 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 236
 237 /* Update battery voltage after every reading if true */
 238 static bool update_vbat;
 239
 240 /* Not all BIOSes properly configure the PWM registers */
 241 static bool fix_pwm_polarity;
 242
 243 /* Many IT87 constants specified below */
 244
 245 /* Length of ISA address segment */
 246 #define IT87_EXTENT 8
 247
 248 /* Length of ISA address segment for Environmental Controller */
 249 #define IT87_EC_EXTENT 2
 250
 251 /* Offset of EC registers from ISA base address */
 252 #define IT87_EC_OFFSET 5
 253
 254 /* Where are the ISA address/data registers relative to the EC base address */
 255 #define IT87_ADDR_REG_OFFSET 0
 256 #define IT87_DATA_REG_OFFSET 1
 257
 258 /*----- The IT87 registers -----*/
 259
 260 #define IT87_REG_CONFIG        0x00
 261
 262 #define IT87_REG_ALARM1        0x01
 263 #define IT87_REG_ALARM2        0x02
 264 #define IT87_REG_ALARM3        0x03
 265
 266 #define IT87_REG_BANK           0x06
 267
 268 /*
 269  * The IT8718F and IT8720F have the VID value in a different register, in
 270  * Super-I/O configuration space.
 271  */
 272 #define IT87_REG_VID           0x0a
 273 /*
 274  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 275  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 276  * mode.
 277  */
 278 #define IT87_REG_FAN_DIV       0x0b
 279 #define IT87_REG_FAN_16BIT     0x0c
 280
 281 /*
 282  * Monitors:
 283  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 284  * - up to 6 temp (1 to 6)
 285  * - up to 6 fan (1 to 6)
 286  */
 287
 288 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 289 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 290 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 291 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 292
 293 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 294 static const u8 IT87_REG_FAN_MIN_8665[] =
 295                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 296 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 297 static const u8 IT87_REG_FANX_MIN_8665[] =
 298                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 299
 300 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 301
 302 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 303
 304 #define IT87_REG_FAN_MAIN_CTRL 0x13
 305 #define IT87_REG_FAN_CTL       0x14
 306
 307 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 308 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 309
 310 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 311
 312 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 313                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 314
 315 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 316
 317 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 318 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 319
 320 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 321 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 322
 323 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 324                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 325 static const u8 IT87_REG_TEMP_LOW_8686[] =
 326                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 327
 328 #define IT87_REG_VIN_ENABLE    0x50
 329 #define IT87_REG_TEMP_ENABLE   0x51
 330 #define IT87_REG_TEMP_EXTRA    0x55
 331 #define IT87_REG_BEEP_ENABLE   0x5c
 332
 333 #define IT87_REG_CHIPID        0x58
 334
 335 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 336
 337 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 338 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 339
 340 #define IT87_REG_TEMP456_ENABLE 0x77
 341
 342 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 343 #define IT87_REG_TEMP_SRC2      0x23d
 344
 345 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 346 #define NUM_VIN_LIMIT           8
 347 #define NUM_TEMP                6
 348 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 349 #define NUM_FAN_DIV             3
 350 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 351 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 352
 353 struct it87_devices {
 354         const char *name;
 355         const char * const suffix;
 356         u32 features;
 357         u8 num_temp_limit;
 358         u8 peci_mask;
 359         u8 old_peci_mask;
 360 };
 361
 362 #define FEAT_12MV_ADC           BIT(0)
 363 #define FEAT_NEWER_AUTOPWM      BIT(1)
 364 #define FEAT_OLD_AUTOPWM        BIT(2)
 365 #define FEAT_16BIT_FANS         BIT(3)
 366 #define FEAT_TEMP_OFFSET        BIT(4)
 367 #define FEAT_TEMP_PECI          BIT(5)
 368 #define FEAT_TEMP_OLD_PECI      BIT(6)
 369 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 370 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 371 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 372 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 373 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 374 #define FEAT_10_9MV_ADC         BIT(12)
 375 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 376 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 377 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 378 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 379 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 380 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 381 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 382 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 383 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 384 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 385 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 386 #define FEAT_11MV_ADC           BIT(24)
 387
 388 static const struct it87_devices it87_devices[] = {
 389         [it87] = {
 390                 .name = "it87",
 391                 .suffix = "F",
 392                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 393                                                 /* may need to overwrite */
 394                 .num_temp_limit = 3,
 395         },
 396         [it8712] = {
 397                 .name = "it8712",
 398                 .suffix = "F",
 399                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 400                                                 /* may need to overwrite */
 401                 .num_temp_limit = 3,
 402         },
 403         [it8716] = {
 404                 .name = "it8716",
 405                 .suffix = "F",
 406                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 407                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 408                   | FEAT_FANCTL_ONOFF,
 409                 .num_temp_limit = 3,
 410         },
 411         [it8718] = {
 412                 .name = "it8718",
 413                 .suffix = "F",
 414                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 415                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 416                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 417                 .num_temp_limit = 3,
 418                 .old_peci_mask = 0x4,
 419         },
 420         [it8720] = {
 421                 .name = "it8720",
 422                 .suffix = "F",
 423                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 424                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 425                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 426                 .num_temp_limit = 3,
 427                 .old_peci_mask = 0x4,
 428         },
 429         [it8721] = {
 430                 .name = "it8721",
 431                 .suffix = "F",
 432                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 433                   | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 434                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 435                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 436                 .num_temp_limit = 3,
 437                 .peci_mask = 0x05,
 438                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 439         },
 440         [it8728] = {
 441                 .name = "it8728",
 442                 .suffix = "F",
 443                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 444                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 445                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 446                   | FEAT_FANCTL_ONOFF,
 447                 .num_temp_limit = 3,
 448                 .peci_mask = 0x07,
 449         },
 450         [it8732] = {
 451                 .name = "it8732",
 452                 .suffix = "F",
 453                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 454                   | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 455                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 456                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 457                 .num_temp_limit = 3,
 458                 .peci_mask = 0x07,
 459                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 460         },
 461         [it8771] = {
 462                 .name = "it8771",
 463                 .suffix = "E",
 464                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 465                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 466                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 467                                 /* PECI: guesswork */
 468                                 /* 12mV ADC (OHM) */
 469                                 /* 16 bit fans (OHM) */
 470                                 /* three fans, always 16 bit (guesswork) */
 471                 .num_temp_limit = 3,
 472                 .peci_mask = 0x07,
 473         },
 474         [it8772] = {
 475                 .name = "it8772",
 476                 .suffix = "E",
 477                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 478                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 479                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 480                                 /* PECI (coreboot) */
 481                                 /* 12mV ADC (HWSensors4, OHM) */
 482                                 /* 16 bit fans (HWSensors4, OHM) */
 483                                 /* three fans, always 16 bit (datasheet) */
 484                 .num_temp_limit = 3,
 485                 .peci_mask = 0x07,
 486         },
 487         [it8781] = {
 488                 .name = "it8781",
 489                 .suffix = "F",
 490                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 491                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 492                   | FEAT_FANCTL_ONOFF,
 493                 .num_temp_limit = 3,
 494                 .old_peci_mask = 0x4,
 495         },
 496         [it8782] = {
 497                 .name = "it8782",
 498                 .suffix = "F",
 499                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 500                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 501                   | FEAT_FANCTL_ONOFF,
 502                 .num_temp_limit = 3,
 503                 .old_peci_mask = 0x4,
 504         },
 505         [it8783] = {
 506                 .name = "it8783",
 507                 .suffix = "E/F",
 508                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 509                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 510                   | FEAT_FANCTL_ONOFF,
 511                 .num_temp_limit = 3,
 512                 .old_peci_mask = 0x4,
 513         },
 514         [it8786] = {
 515                 .name = "it8786",
 516                 .suffix = "E",
 517                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 518                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 519                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 520                 .num_temp_limit = 3,
 521                 .peci_mask = 0x07,
 522         },
 523         [it8790] = {
 524                 .name = "it8790",
 525                 .suffix = "E",
 526                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 527                   | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
 528                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 529                 .num_temp_limit = 3,
 530                 .peci_mask = 0x07,
 531         },
 532         [it8792] = {
 533                 .name = "it8792",
 534                 .suffix = "E",
 535                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 536                   | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
 537                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 538                 .num_temp_limit = 3,
 539                 .peci_mask = 0x07,
 540         },
 541         [it8603] = {
 542                 .name = "it8603",
 543                 .suffix = "E",
 544                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 545                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 546                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 547                 .num_temp_limit = 3,
 548                 .peci_mask = 0x07,
 549         },
 550         [it8607] = {
 551                 .name = "it8607",
 552                 .suffix = "E",
 553                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 554                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 555                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 556                   | FEAT_FANCTL_ONOFF,
 557                 .num_temp_limit = 3,
 558                 .peci_mask = 0x07,
 559         },
 560         [it8620] = {
 561                 .name = "it8620",
 562                 .suffix = "E",
 563                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 564                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 565                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 566                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 567                   | FEAT_FANCTL_ONOFF,
 568                 .num_temp_limit = 3,
 569                 .peci_mask = 0x07,
 570         },
 571         [it8622] = {
 572                 .name = "it8622",
 573                 .suffix = "E",
 574                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 575                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 576                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 577                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 578                 .num_temp_limit = 3,
 579                 .peci_mask = 0x07,
 580         },
 581         [it8628] = {
 582                 .name = "it8628",
 583                 .suffix = "E",
 584                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 585                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 586                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 587                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 588                   | FEAT_FANCTL_ONOFF,
 589                 .num_temp_limit = 3,
 590                 .peci_mask = 0x07,
 591         },
 592         [it8655] = {
 593                 .name = "it8655",
 594                 .suffix = "E",
 595                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 596                   | FEAT_TEMP_OFFSET | FEAT_AVCC3
 597                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 598                 .num_temp_limit = 6,
 599         },
 600         [it8665] = {
 601                 .name = "it8665",
 602                 .suffix = "E",
 603                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 604                   | FEAT_TEMP_OFFSET | FEAT_AVCC3
 605                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 606                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 607                 .num_temp_limit = 6,
 608         },
 609         [it8686] = {
 610                 .name = "it8686",
 611                 .suffix = "E",
 612                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 613                   | FEAT_TEMP_OFFSET | FEAT_SIX_FANS
 614                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 615                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 616                 .num_temp_limit = 6,
 617         },
 618 };
 619
 620 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 621 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 622 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 623 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 624 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 625 #define has_temp_offset(data)   ((data)->features & FEAT_TEMP_OFFSET)
 626 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 627                                  ((data)->peci_mask & BIT(nr)))
 628 #define has_temp_old_peci(data, nr) \
 629                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 630                                  ((data)->old_peci_mask & BIT(nr)))
 631 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 632 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 633                                                      FEAT_SIX_FANS))
 634 #define has_vid(data)           ((data)->features & FEAT_VID)
 635 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 636 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 637 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 638 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 639                                                      | FEAT_SIX_PWM))
 640 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 641 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 642 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 643 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 644 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 645                                                      FEAT_FIVE_FANS | \
 646                                                      FEAT_SIX_FANS))
 647 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 648                                                      FEAT_FIVE_PWM \
 649                                                      | FEAT_SIX_PWM))
 650 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 651 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 652 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 653 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 654
 655 struct it87_sio_data {
 656         enum chips type;
 657         /* Values read from Super-I/O config space */
 658         u8 revision;
 659         u8 vid_value;
 660         u8 beep_pin;
 661         u8 internal;    /* Internal sensors can be labeled */
 662         /* Features skipped based on config or DMI */
 663         u16 skip_in;
 664         u8 skip_vid;
 665         u8 skip_fan;
 666         u8 skip_pwm;
 667         u8 skip_temp;
 668 };
 669
 670 /*
 671  * For each registered chip, we need to keep some data in memory.
 672  * The structure is dynamically allocated.
 673  */
 674 struct it87_data {
 675         const struct attribute_group *groups[7];
 676         enum chips type;
 677         u32 features;
 678         u8 bank;
 679         u8 peci_mask;
 680         u8 old_peci_mask;
 681
 682         const u8 *REG_FAN;
 683         const u8 *REG_FANX;
 684         const u8 *REG_FAN_MIN;
 685         const u8 *REG_FANX_MIN;
 686
 687         const u8 *REG_PWM;
 688
 689         const u8 *REG_TEMP_OFFSET;
 690         const u8 *REG_TEMP_LOW;
 691         const u8 *REG_TEMP_HIGH;
 692
 693         unsigned short addr;
 694         const char *name;
 695         struct mutex update_lock;
 696         char valid;             /* !=0 if following fields are valid */
 697         unsigned long last_updated;     /* In jiffies */
 698
 699         u16 in_scaled;          /* Internal voltage sensors are scaled */
 700         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 701         u16 has_in;             /* Bitfield, voltage sensors enabled */
 702         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 703         u8 has_fan;             /* Bitfield, fans enabled */
 704         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 705         u8 has_temp;            /* Bitfield, temp sensors enabled */
 706         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 707         u8 num_temp_limit;      /* Number of temp limit/offset registers */
 708         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 709         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 710         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 711         bool has_vid;           /* True if VID supported */
 712         u8 vid;                 /* Register encoding, combined */
 713         u8 vrm;
 714         u32 alarms;             /* Register encoding, combined */
 715         bool has_beep;          /* true if beep supported */
 716         u8 beeps;               /* Register encoding */
 717         u8 fan_main_ctrl;       /* Register value */
 718         u8 fan_ctl;             /* Register value */
 719
 720         /*
 721          * The following 3 arrays correspond to the same registers up to
 722          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 723          * 7, and we want to preserve settings on mode changes, so we have
 724          * to track all values separately.
 725          * Starting with the IT8721F, the manual PWM duty cycles are stored
 726          * in separate registers (8-bit values), so the separate tracking
 727          * is no longer needed, but it is still done to keep the driver
 728          * simple.
 729          */
 730         u8 has_pwm;             /* Bitfield, pwm control enabled */
 731         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 732         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 733         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 734
 735         /* Automatic fan speed control registers */
 736         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 737         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 738 };
 739
 740 static int adc_lsb(const struct it87_data *data, int nr)
 741 {
 742         int lsb;
 743
 744         if (has_12mv_adc(data))
 745                 lsb = 120;
 746         else if (has_10_9mv_adc(data))
 747                 lsb = 109;
 748         else if (has_11mv_adc(data))
 749                 lsb = 110;
 750         else
 751                 lsb = 160;
 752         if (data->in_scaled & BIT(nr))
 753                 lsb <<= 1;
 754         return lsb;
 755 }
 756
 757 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 758 {
 759         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 760         return clamp_val(val, 0, 255);
 761 }
 762
 763 static int in_from_reg(const struct it87_data *data, int nr, int val)
 764 {
 765         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 766 }
 767
 768 static inline u8 FAN_TO_REG(long rpm, int div)
 769 {
 770         if (rpm == 0)
 771                 return 255;
 772         rpm = clamp_val(rpm, 1, 1000000);
 773         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 774 }
 775
 776 static inline u16 FAN16_TO_REG(long rpm)
 777 {
 778         if (rpm == 0)
 779                 return 0xffff;
 780         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 781 }
 782
 783 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 784                                 1350000 / ((val) * (div)))
 785 /* The divider is fixed to 2 in 16-bit mode */
 786 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 787                              1350000 / ((val) * 2))
 788
 789 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 790                                     ((val) + 500) / 1000), -128, 127))
 791 #define TEMP_FROM_REG(val) ((val) * 1000)
 792
 793 static u8 pwm_to_reg(const struct it87_data *data, long val)
 794 {
 795         if (has_newer_autopwm(data))
 796                 return val;
 797         else
 798                 return val >> 1;
 799 }
 800
 801 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 802 {
 803         if (has_newer_autopwm(data))
 804                 return reg;
 805         else
 806                 return (reg & 0x7f) << 1;
 807 }
 808
 809 static int DIV_TO_REG(int val)
 810 {
 811         int answer = 0;
 812
 813         while (answer < 7 && (val >>= 1))
 814                 answer++;
 815         return answer;
 816 }
 817
 818 #define DIV_FROM_REG(val) BIT(val)
 819
 820 /*
 821  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 822  * depending on the chip type, to calculate the actual PWM frequency.
 823  *
 824  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 825  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 826  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 827  * sometimes just one. It is unknown if this is a datasheet error or real,
 828  * so this is ignored for now.
 829  */
 830 static const unsigned int pwm_freq[8] = {
 831         48000000,
 832         24000000,
 833         12000000,
 834         8000000,
 835         6000000,
 836         3000000,
 837         1500000,
 838         750000,
 839 };
 840
 841 static int _it87_read_value(struct it87_data *data, u8 reg)
 842 {
 843         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 844         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 845 }
 846
 847 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 848 {
 849         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 850         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 851 }
 852
 853 static void it87_set_bank(struct it87_data *data, u8 bank)
 854 {
 855         if (has_bank_sel(data) && bank != data->bank) {
 856                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 857
 858                 breg &= 0x1f;
 859                 breg |= (bank << 5);
 860                 data->bank = bank;
 861                 _it87_write_value(data, IT87_REG_BANK, breg);
 862         }
 863 }
 864
 865 /*
 866  * Must be called with data->update_lock held, except during initialization.
 867  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 868  * would slow down the IT87 access and should not be necessary.
 869  */
 870 static int it87_read_value(struct it87_data *data, u16 reg)
 871 {
 872         it87_set_bank(data, reg >> 8);
 873         return _it87_read_value(data, reg & 0xff);
 874 }
 875
 876 /*
 877  * Must be called with data->update_lock held, except during initialization.
 878  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 879  * would slow down the IT87 access and should not be necessary.
 880  */
 881 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
 882 {
 883         it87_set_bank(data, reg >> 8);
 884         _it87_write_value(data, reg & 0xff, value);
 885 }
 886
 887 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 888 {
 889         data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]);
 890         if (has_newer_autopwm(data)) {
 891                 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 892                 data->pwm_duty[nr] = it87_read_value(data,
 893                                                      IT87_REG_PWM_DUTY[nr]);
 894         } else {
 895                 if (data->pwm_ctrl[nr] & 0x80)  /* Automatic mode */
 896                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 897                 else                            /* Manual mode */
 898                         data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
 899         }
 900
 901         if (has_old_autopwm(data)) {
 902                 int i;
 903
 904                 for (i = 0; i < 5 ; i++)
 905                         data->auto_temp[nr][i] = it87_read_value(data,
 906                                                 IT87_REG_AUTO_TEMP(nr, i));
 907                 for (i = 0; i < 3 ; i++)
 908                         data->auto_pwm[nr][i] = it87_read_value(data,
 909                                                 IT87_REG_AUTO_PWM(nr, i));
 910         } else if (has_newer_autopwm(data)) {
 911                 int i;
 912
 913                 /*
 914                  * 0: temperature hysteresis (base + 5)
 915                  * 1: fan off temperature (base + 0)
 916                  * 2: fan start temperature (base + 1)
 917                  * 3: fan max temperature (base + 2)
 918                  */
 919                 data->auto_temp[nr][0] =
 920                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
 921
 922                 for (i = 0; i < 3 ; i++)
 923                         data->auto_temp[nr][i + 1] =
 924                                 it87_read_value(data,
 925                                                 IT87_REG_AUTO_TEMP(nr, i));
 926                 /*
 927                  * 0: start pwm value (base + 3)
 928                  * 1: pwm slope (base + 4, 1/8th pwm)
 929                  */
 930                 data->auto_pwm[nr][0] =
 931                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
 932                 data->auto_pwm[nr][1] =
 933                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
 934         }
 935 }
 936
 937 static struct it87_data *it87_update_device(struct device *dev)
 938 {
 939         struct it87_data *data = dev_get_drvdata(dev);
 940         int i;
 941
 942         mutex_lock(&data->update_lock);
 943
 944         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
 945             !data->valid) {
 946                 if (update_vbat) {
 947                         /*
 948                          * Cleared after each update, so reenable.  Value
 949                          * returned by this read will be previous value
 950                          */
 951                         it87_write_value(data, IT87_REG_CONFIG,
 952                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
 953                 }
 954                 for (i = 0; i < NUM_VIN; i++) {
 955                         if (!(data->has_in & BIT(i)))
 956                                 continue;
 957
 958                         data->in[i][0] =
 959                                 it87_read_value(data, IT87_REG_VIN[i]);
 960
 961                         /* VBAT and AVCC don't have limit registers */
 962                         if (i >= NUM_VIN_LIMIT)
 963                                 continue;
 964
 965                         data->in[i][1] =
 966                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
 967                         data->in[i][2] =
 968                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
 969                 }
 970
 971                 for (i = 0; i < NUM_FAN; i++) {
 972                         /* Skip disabled fans */
 973                         if (!(data->has_fan & BIT(i)))
 974                                 continue;
 975
 976                         data->fan[i][1] =
 977                                 it87_read_value(data, data->REG_FAN_MIN[i]);
 978                         data->fan[i][0] = it87_read_value(data,
 979                                        data->REG_FAN[i]);
 980                         /* Add high byte if in 16-bit mode */
 981                         if (has_16bit_fans(data)) {
 982                                 data->fan[i][0] |= it87_read_value(data,
 983                                                 data->REG_FANX[i]) << 8;
 984                                 data->fan[i][1] |= it87_read_value(data,
 985                                                 data->REG_FANX_MIN[i]) << 8;
 986                         }
 987                 }
 988                 for (i = 0; i < NUM_TEMP; i++) {
 989                         if (!(data->has_temp & BIT(i)))
 990                                 continue;
 991                         data->temp[i][0] =
 992                                 it87_read_value(data, IT87_REG_TEMP(i));
 993
 994                         if (i >= data->num_temp_limit)
 995                                 continue;
 996
 997                         if (has_temp_offset(data))
 998                                 data->temp[i][3] =
 999                                   it87_read_value(data,
1000                                                   data->REG_TEMP_OFFSET[i]);
1001
1002                         data->temp[i][1] =
1003                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1004                         data->temp[i][2] =
1005                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1006                 }
1007
1008                 /* Newer chips don't have clock dividers */
1009                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1010                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1011                         data->fan_div[0] = i & 0x07;
1012                         data->fan_div[1] = (i >> 3) & 0x07;
1013                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1014                 }
1015
1016                 data->alarms =
1017                         it87_read_value(data, IT87_REG_ALARM1) |
1018                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1019                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1020                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1021
1022                 data->fan_main_ctrl = it87_read_value(data,
1023                                 IT87_REG_FAN_MAIN_CTRL);
1024                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1025                 for (i = 0; i < NUM_PWM; i++) {
1026                         if (!(data->has_pwm & BIT(i)))
1027                                 continue;
1028                         it87_update_pwm_ctrl(data, i);
1029                 }
1030
1031                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1032                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1033                 /*
1034                  * The IT8705F does not have VID capability.
1035                  * The IT8718F and later don't use IT87_REG_VID for the
1036                  * same purpose.
1037                  */
1038                 if (data->type == it8712 || data->type == it8716) {
1039                         data->vid = it87_read_value(data, IT87_REG_VID);
1040                         /*
1041                          * The older IT8712F revisions had only 5 VID pins,
1042                          * but we assume it is always safe to read 6 bits.
1043                          */
1044                         data->vid &= 0x3f;
1045                 }
1046                 data->last_updated = jiffies;
1047                 data->valid = 1;
1048         }
1049
1050         mutex_unlock(&data->update_lock);
1051
1052         return data;
1053 }
1054
1055 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1056                        char *buf)
1057 {
1058         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1059         struct it87_data *data = it87_update_device(dev);
1060         int index = sattr->index;
1061         int nr = sattr->nr;
1062
1063         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1064 }
1065
1066 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1067                       const char *buf, size_t count)
1068 {
1069         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1070         struct it87_data *data = dev_get_drvdata(dev);
1071         int index = sattr->index;
1072         int nr = sattr->nr;
1073         unsigned long val;
1074
1075         if (kstrtoul(buf, 10, &val) < 0)
1076                 return -EINVAL;
1077
1078         mutex_lock(&data->update_lock);
1079         data->in[nr][index] = in_to_reg(data, nr, val);
1080         it87_write_value(data,
1081                          index == 1 ? IT87_REG_VIN_MIN(nr)
1082                                     : IT87_REG_VIN_MAX(nr),
1083                          data->in[nr][index]);
1084         mutex_unlock(&data->update_lock);
1085         return count;
1086 }
1087
1088 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1089 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1090                             0, 1);
1091 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1092                             0, 2);
1093
1094 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1095 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1096                             1, 1);
1097 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1098                             1, 2);
1099
1100 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1101 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1102                             2, 1);
1103 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1104                             2, 2);
1105
1106 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1107 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1108                             3, 1);
1109 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1110                             3, 2);
1111
1112 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1113 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1114                             4, 1);
1115 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1116                             4, 2);
1117
1118 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1119 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1120                             5, 1);
1121 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1122                             5, 2);
1123
1124 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1125 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1126                             6, 1);
1127 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1128                             6, 2);
1129
1130 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1131 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1132                             7, 1);
1133 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1134                             7, 2);
1135
1136 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1137 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1138 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1139 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1140 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1141
1142 /* Up to 6 temperatures */
1143 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1144                          char *buf)
1145 {
1146         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1147         int nr = sattr->nr;
1148         int index = sattr->index;
1149         struct it87_data *data = it87_update_device(dev);
1150
1151         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1152 }
1153
1154 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1155                         const char *buf, size_t count)
1156 {
1157         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1158         int nr = sattr->nr;
1159         int index = sattr->index;
1160         struct it87_data *data = dev_get_drvdata(dev);
1161         long val;
1162         u8 reg, regval;
1163
1164         if (kstrtol(buf, 10, &val) < 0)
1165                 return -EINVAL;
1166
1167         mutex_lock(&data->update_lock);
1168
1169         switch (index) {
1170         default:
1171         case 1:
1172                 reg = data->REG_TEMP_LOW[nr];
1173                 break;
1174         case 2:
1175                 reg = data->REG_TEMP_HIGH[nr];
1176                 break;
1177         case 3:
1178                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1179                 if (!(regval & 0x80)) {
1180                         regval |= 0x80;
1181                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1182                 }
1183                 data->valid = 0;
1184                 reg = data->REG_TEMP_OFFSET[nr];
1185                 break;
1186         }
1187
1188         data->temp[nr][index] = TEMP_TO_REG(val);
1189         it87_write_value(data, reg, data->temp[nr][index]);
1190         mutex_unlock(&data->update_lock);
1191         return count;
1192 }
1193
1194 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1195 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1196                             0, 1);
1197 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1198                             0, 2);
1199 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1200                             set_temp, 0, 3);
1201 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1202 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1203                             1, 1);
1204 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1205                             1, 2);
1206 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1207                             set_temp, 1, 3);
1208 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1209 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1210                             2, 1);
1211 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1212                             2, 2);
1213 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1214                             set_temp, 2, 3);
1215 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1216 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1217                             3, 1);
1218 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1219                             3, 2);
1220 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1221                             set_temp, 3, 3);
1222 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1223 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1224                             4, 1);
1225 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1226                             4, 2);
1227 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1228                             set_temp, 4, 3);
1229 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1230 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1231                             5, 1);
1232 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1233                             5, 2);
1234 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1235                             set_temp, 5, 3);
1236
1237 static int get_temp_type(struct it87_data *data, int index)
1238 {
1239         u8 reg, extra;
1240         int type = 0;
1241
1242         if (has_bank_sel(data)) {
1243                 int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
1244                 u8 src1, src2;
1245
1246                 src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
1247                 src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
1248
1249                 switch (data->type) {
1250                 case it8686:
1251                         switch (src1) {
1252                         case 0:
1253                                 if (index >= 3)
1254                                         return 4;
1255                                 break;
1256                         case 1:
1257                                 if (index == 1 || index == 2 ||
1258                                           index == 4 || index == 5)
1259                                         return 6;
1260                                 break;
1261                         case 2:
1262                                 if (index == 2 || index == 6)
1263                                         return 5;
1264                                 break;
1265                         default:
1266                                 break;
1267                         }
1268                         break;
1269                 case it8655:
1270                 case it8665:
1271                         if (src1 < 3) {
1272                                 index = src1;
1273                                 break;
1274                         }
1275                         switch(src1) {
1276                         case 3:
1277                                 type = (src2 & BIT(index)) ? 6 : 5;
1278                                 break;
1279                         case 4 ... 8:
1280                                 type = (src2 & BIT(index)) ? 4 : 6;
1281                                 break;
1282                         case 9:
1283                                 type = (src2 & BIT(index)) ? 5 : 0;
1284                                 break;
1285                         default:
1286                                 break;
1287                         }
1288                         return type;
1289                 default:
1290                         return 0;
1291                 }
1292         }
1293         if (index >= 3)
1294                 return 0;
1295
1296         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1297         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1298
1299         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1300             (has_temp_old_peci(data, index) && (extra & 0x80)))
1301                 type = 6;               /* Intel PECI */
1302         if (reg & BIT(index))
1303                 type = 3;               /* thermal diode */
1304         else if (reg & BIT(index + 3))
1305                 type = 4;               /* thermistor */
1306
1307         return type;
1308 }
1309
1310 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1311                               char *buf)
1312 {
1313         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1314         struct it87_data *data = it87_update_device(dev);
1315         int type = get_temp_type(data, sensor_attr->index);
1316
1317         return sprintf(buf, "%d\n", type);
1318 }
1319
1320 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1321                              const char *buf, size_t count)
1322 {
1323         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1324         int nr = sensor_attr->index;
1325
1326         struct it87_data *data = dev_get_drvdata(dev);
1327         long val;
1328         u8 reg, extra;
1329
1330         if (kstrtol(buf, 10, &val) < 0)
1331                 return -EINVAL;
1332
1333         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1334         reg &= ~(1 << nr);
1335         reg &= ~(8 << nr);
1336         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1337                 reg &= 0x3f;
1338         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1339         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1340                 extra &= 0x7f;
1341         if (val == 2) { /* backwards compatibility */
1342                 dev_warn(dev,
1343                          "Sensor type 2 is deprecated, please use 4 instead\n");
1344                 val = 4;
1345         }
1346         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1347         if (val == 3)
1348                 reg |= 1 << nr;
1349         else if (val == 4)
1350                 reg |= 8 << nr;
1351         else if (has_temp_peci(data, nr) && val == 6)
1352                 reg |= (nr + 1) << 6;
1353         else if (has_temp_old_peci(data, nr) && val == 6)
1354                 extra |= 0x80;
1355         else if (val != 0)
1356                 return -EINVAL;
1357
1358         mutex_lock(&data->update_lock);
1359         data->sensor = reg;
1360         data->extra = extra;
1361         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1362         if (has_temp_old_peci(data, nr))
1363                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1364         data->valid = 0;        /* Force cache refresh */
1365         mutex_unlock(&data->update_lock);
1366         return count;
1367 }
1368
1369 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1370                           set_temp_type, 0);
1371 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1372                           set_temp_type, 1);
1373 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1374                           set_temp_type, 2);
1375 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1376                           set_temp_type, 3);
1377 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1378                           set_temp_type, 4);
1379 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1380                           set_temp_type, 5);
1381
1382 /* 6 Fans */
1383
1384 static int pwm_mode(const struct it87_data *data, int nr)
1385 {
1386         if (has_fanctl_onoff(data) && nr < 3 &&
1387             !(data->fan_main_ctrl & BIT(nr)))
1388                 return 0;                               /* Full speed */
1389         if (data->pwm_ctrl[nr] & 0x80)
1390                 return 2;                               /* Automatic mode */
1391         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1392             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1393                 return 0;                       /* Full speed */
1394
1395         return 1;                               /* Manual mode */
1396 }
1397
1398 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1399                         char *buf)
1400 {
1401         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1402         int nr = sattr->nr;
1403         int index = sattr->index;
1404         int speed;
1405         struct it87_data *data = it87_update_device(dev);
1406
1407         speed = has_16bit_fans(data) ?
1408                 FAN16_FROM_REG(data->fan[nr][index]) :
1409                 FAN_FROM_REG(data->fan[nr][index],
1410                              DIV_FROM_REG(data->fan_div[nr]));
1411         return sprintf(buf, "%d\n", speed);
1412 }
1413
1414 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1415                             char *buf)
1416 {
1417         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1418         struct it87_data *data = it87_update_device(dev);
1419         int nr = sensor_attr->index;
1420
1421         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1422 }
1423
1424 static ssize_t show_pwm_enable(struct device *dev,
1425                                struct device_attribute *attr, char *buf)
1426 {
1427         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1428         struct it87_data *data = it87_update_device(dev);
1429         int nr = sensor_attr->index;
1430
1431         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1432 }
1433
1434 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1435                         char *buf)
1436 {
1437         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1438         struct it87_data *data = it87_update_device(dev);
1439         int nr = sensor_attr->index;
1440
1441         return sprintf(buf, "%d\n",
1442                        pwm_from_reg(data, data->pwm_duty[nr]));
1443 }
1444
1445 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1446                              char *buf)
1447 {
1448         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1449         struct it87_data *data = it87_update_device(dev);
1450         int nr = sensor_attr->index;
1451         unsigned int freq;
1452         int index;
1453
1454         if (has_pwm_freq2(data) && nr == 1)
1455                 index = (data->extra >> 4) & 0x07;
1456         else
1457                 index = (data->fan_ctl >> 4) & 0x07;
1458
1459         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1460
1461         return sprintf(buf, "%u\n", freq);
1462 }
1463
1464 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1465                        const char *buf, size_t count)
1466 {
1467         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1468         int nr = sattr->nr;
1469         int index = sattr->index;
1470
1471         struct it87_data *data = dev_get_drvdata(dev);
1472         long val;
1473         u8 reg;
1474
1475         if (kstrtol(buf, 10, &val) < 0)
1476                 return -EINVAL;
1477
1478         mutex_lock(&data->update_lock);
1479
1480         if (has_16bit_fans(data)) {
1481                 data->fan[nr][index] = FAN16_TO_REG(val);
1482                 it87_write_value(data, data->REG_FAN_MIN[nr],
1483                                  data->fan[nr][index] & 0xff);
1484                 it87_write_value(data, data->REG_FANX_MIN[nr],
1485                                  data->fan[nr][index] >> 8);
1486         } else {
1487                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1488                 switch (nr) {
1489                 case 0:
1490                         data->fan_div[nr] = reg & 0x07;
1491                         break;
1492                 case 1:
1493                         data->fan_div[nr] = (reg >> 3) & 0x07;
1494                         break;
1495                 case 2:
1496                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1497                         break;
1498                 }
1499                 data->fan[nr][index] =
1500                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1501                 it87_write_value(data, data->REG_FAN_MIN[nr],
1502                                  data->fan[nr][index]);
1503         }
1504
1505         mutex_unlock(&data->update_lock);
1506         return count;
1507 }
1508
1509 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1510                            const char *buf, size_t count)
1511 {
1512         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1513         struct it87_data *data = dev_get_drvdata(dev);
1514         int nr = sensor_attr->index;
1515         unsigned long val;
1516         int min;
1517         u8 old;
1518
1519         if (kstrtoul(buf, 10, &val) < 0)
1520                 return -EINVAL;
1521
1522         mutex_lock(&data->update_lock);
1523         old = it87_read_value(data, IT87_REG_FAN_DIV);
1524
1525         /* Save fan min limit */
1526         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1527
1528         switch (nr) {
1529         case 0:
1530         case 1:
1531                 data->fan_div[nr] = DIV_TO_REG(val);
1532                 break;
1533         case 2:
1534                 if (val < 8)
1535                         data->fan_div[nr] = 1;
1536                 else
1537                         data->fan_div[nr] = 3;
1538         }
1539         val = old & 0x80;
1540         val |= (data->fan_div[0] & 0x07);
1541         val |= (data->fan_div[1] & 0x07) << 3;
1542         if (data->fan_div[2] == 3)
1543                 val |= 0x1 << 6;
1544         it87_write_value(data, IT87_REG_FAN_DIV, val);
1545
1546         /* Restore fan min limit */
1547         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1548         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1549
1550         mutex_unlock(&data->update_lock);
1551         return count;
1552 }
1553
1554 /* Returns 0 if OK, -EINVAL otherwise */
1555 static int check_trip_points(struct device *dev, int nr)
1556 {
1557         const struct it87_data *data = dev_get_drvdata(dev);
1558         int i, err = 0;
1559
1560         if (has_old_autopwm(data)) {
1561                 for (i = 0; i < 3; i++) {
1562                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1563                                 err = -EINVAL;
1564                 }
1565                 for (i = 0; i < 2; i++) {
1566                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1567                                 err = -EINVAL;
1568                 }
1569         } else if (has_newer_autopwm(data)) {
1570                 for (i = 1; i < 3; i++) {
1571                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1572                                 err = -EINVAL;
1573                 }
1574         }
1575
1576         if (err) {
1577                 dev_err(dev,
1578                         "Inconsistent trip points, not switching to automatic mode\n");
1579                 dev_err(dev, "Adjust the trip points and try again\n");
1580         }
1581         return err;
1582 }
1583
1584 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1585                               const char *buf, size_t count)
1586 {
1587         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1588         struct it87_data *data = dev_get_drvdata(dev);
1589         int nr = sensor_attr->index;
1590         long val;
1591
1592         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1593                 return -EINVAL;
1594
1595         /* Check trip points before switching to automatic mode */
1596         if (val == 2) {
1597                 if (check_trip_points(dev, nr) < 0)
1598                         return -EINVAL;
1599         }
1600
1601         mutex_lock(&data->update_lock);
1602
1603         if (val == 0) {
1604                 if (nr < 3 && has_fanctl_onoff(data)) {
1605                         int tmp;
1606                         /* make sure the fan is on when in on/off mode */
1607                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1608                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1609                         /* set on/off mode */
1610                         data->fan_main_ctrl &= ~BIT(nr);
1611                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1612                                          data->fan_main_ctrl);
1613                 } else {
1614                         u8 ctrl;
1615
1616                         /* No on/off mode, set maximum pwm value */
1617                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1618                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1619                                          data->pwm_duty[nr]);
1620                         /* and set manual mode */
1621                         if (has_newer_autopwm(data)) {
1622                                 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1623                                         data->pwm_temp_map[nr];
1624                         } else {
1625                                 ctrl = data->pwm_duty[nr];
1626                         }
1627                         data->pwm_ctrl[nr] = ctrl;
1628                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1629                 }
1630         } else {
1631                 u8 ctrl;
1632
1633                 if (has_newer_autopwm(data)) {
1634                         ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1635                                 data->pwm_temp_map[nr];
1636                         if (val != 1)
1637                                 ctrl |= 0x80;
1638                 } else {
1639                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1640                 }
1641                 data->pwm_ctrl[nr] = ctrl;
1642                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1643
1644                 if (has_fanctl_onoff(data) && nr < 3) {
1645                         /* set SmartGuardian mode */
1646                         data->fan_main_ctrl |= BIT(nr);
1647                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1648                                          data->fan_main_ctrl);
1649                 }
1650         }
1651
1652         mutex_unlock(&data->update_lock);
1653         return count;
1654 }
1655
1656 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1657                        const char *buf, size_t count)
1658 {
1659         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1660         struct it87_data *data = dev_get_drvdata(dev);
1661         int nr = sensor_attr->index;
1662         long val;
1663
1664         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1665                 return -EINVAL;
1666
1667         mutex_lock(&data->update_lock);
1668         it87_update_pwm_ctrl(data, nr);
1669         if (has_newer_autopwm(data)) {
1670                 /*
1671                  * If we are in automatic mode, the PWM duty cycle register
1672                  * is read-only so we can't write the value.
1673                  */
1674                 if (data->pwm_ctrl[nr] & 0x80) {
1675                         mutex_unlock(&data->update_lock);
1676                         return -EBUSY;
1677                 }
1678                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1679                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1680                                  data->pwm_duty[nr]);
1681         } else {
1682                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1683                 /*
1684                  * If we are in manual mode, write the duty cycle immediately;
1685                  * otherwise, just store it for later use.
1686                  */
1687                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1688                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1689                         it87_write_value(data, data->REG_PWM[nr],
1690                                          data->pwm_ctrl[nr]);
1691                 }
1692         }
1693         mutex_unlock(&data->update_lock);
1694         return count;
1695 }
1696
1697 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1698                             const char *buf, size_t count)
1699 {
1700         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1701         struct it87_data *data = dev_get_drvdata(dev);
1702         int nr = sensor_attr->index;
1703         unsigned long val;
1704         int i;
1705
1706         if (kstrtoul(buf, 10, &val) < 0)
1707                 return -EINVAL;
1708
1709         val = clamp_val(val, 0, 1000000);
1710         val *= has_newer_autopwm(data) ? 256 : 128;
1711
1712         /* Search for the nearest available frequency */
1713         for (i = 0; i < 7; i++) {
1714                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1715                         break;
1716         }
1717
1718         mutex_lock(&data->update_lock);
1719         if (nr == 0) {
1720                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1721                 data->fan_ctl |= i << 4;
1722                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1723         } else {
1724                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1725                 data->extra |= i << 4;
1726                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1727         }
1728         mutex_unlock(&data->update_lock);
1729
1730         return count;
1731 }
1732
1733 static ssize_t show_pwm_temp_map(struct device *dev,
1734                                  struct device_attribute *attr, char *buf)
1735 {
1736         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1737         struct it87_data *data = it87_update_device(dev);
1738         int nr = sensor_attr->index;
1739         int map;
1740
1741         map = data->pwm_temp_map[nr];
1742         if (map >= 3)
1743                 map = 0;        /* Should never happen */
1744         if (nr >= 3)            /* pwm channels 3..6 map to temp4..6 */
1745                 map += 3;
1746
1747         return sprintf(buf, "%d\n", (int)BIT(map));
1748 }
1749
1750 static ssize_t set_pwm_temp_map(struct device *dev,
1751                                 struct device_attribute *attr, const char *buf,
1752                                 size_t count)
1753 {
1754         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1755         struct it87_data *data = dev_get_drvdata(dev);
1756         int nr = sensor_attr->index;
1757         long val;
1758         u8 reg;
1759
1760         if (kstrtol(buf, 10, &val) < 0)
1761                 return -EINVAL;
1762
1763         if (nr >= 3)
1764                 val -= 3;
1765
1766         switch (val) {
1767         case BIT(0):
1768                 reg = 0x00;
1769                 break;
1770         case BIT(1):
1771                 reg = 0x01;
1772                 break;
1773         case BIT(2):
1774                 reg = 0x02;
1775                 break;
1776         default:
1777                 return -EINVAL;
1778         }
1779
1780         mutex_lock(&data->update_lock);
1781         it87_update_pwm_ctrl(data, nr);
1782         data->pwm_temp_map[nr] = reg;
1783         /*
1784          * If we are in automatic mode, write the temp mapping immediately;
1785          * otherwise, just store it for later use.
1786          */
1787         if (data->pwm_ctrl[nr] & 0x80) {
1788                 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
1789                                                 data->pwm_temp_map[nr];
1790                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1791         }
1792         mutex_unlock(&data->update_lock);
1793         return count;
1794 }
1795
1796 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1797                              char *buf)
1798 {
1799         struct it87_data *data = it87_update_device(dev);
1800         struct sensor_device_attribute_2 *sensor_attr =
1801                         to_sensor_dev_attr_2(attr);
1802         int nr = sensor_attr->nr;
1803         int point = sensor_attr->index;
1804
1805         return sprintf(buf, "%d\n",
1806                        pwm_from_reg(data, data->auto_pwm[nr][point]));
1807 }
1808
1809 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1810                             const char *buf, size_t count)
1811 {
1812         struct it87_data *data = dev_get_drvdata(dev);
1813         struct sensor_device_attribute_2 *sensor_attr =
1814                         to_sensor_dev_attr_2(attr);
1815         int nr = sensor_attr->nr;
1816         int point = sensor_attr->index;
1817         int regaddr;
1818         long val;
1819
1820         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1821                 return -EINVAL;
1822
1823         mutex_lock(&data->update_lock);
1824         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1825         if (has_newer_autopwm(data))
1826                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1827         else
1828                 regaddr = IT87_REG_AUTO_PWM(nr, point);
1829         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1830         mutex_unlock(&data->update_lock);
1831         return count;
1832 }
1833
1834 static ssize_t show_auto_pwm_slope(struct device *dev,
1835                                    struct device_attribute *attr, char *buf)
1836 {
1837         struct it87_data *data = it87_update_device(dev);
1838         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1839         int nr = sensor_attr->index;
1840
1841         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1842 }
1843
1844 static ssize_t set_auto_pwm_slope(struct device *dev,
1845                                   struct device_attribute *attr,
1846                                   const char *buf, size_t count)
1847 {
1848         struct it87_data *data = dev_get_drvdata(dev);
1849         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1850         int nr = sensor_attr->index;
1851         unsigned long val;
1852
1853         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1854                 return -EINVAL;
1855
1856         mutex_lock(&data->update_lock);
1857         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1858         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1859                          data->auto_pwm[nr][1]);
1860         mutex_unlock(&data->update_lock);
1861         return count;
1862 }
1863
1864 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1865                               char *buf)
1866 {
1867         struct it87_data *data = it87_update_device(dev);
1868         struct sensor_device_attribute_2 *sensor_attr =
1869                         to_sensor_dev_attr_2(attr);
1870         int nr = sensor_attr->nr;
1871         int point = sensor_attr->index;
1872         int reg;
1873
1874         if (has_old_autopwm(data) || point)
1875                 reg = data->auto_temp[nr][point];
1876         else
1877                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1878
1879         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1880 }
1881
1882 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1883                              const char *buf, size_t count)
1884 {
1885         struct it87_data *data = dev_get_drvdata(dev);
1886         struct sensor_device_attribute_2 *sensor_attr =
1887                         to_sensor_dev_attr_2(attr);
1888         int nr = sensor_attr->nr;
1889         int point = sensor_attr->index;
1890         long val;
1891         int reg;
1892
1893         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1894                 return -EINVAL;
1895
1896         mutex_lock(&data->update_lock);
1897         if (has_newer_autopwm(data) && !point) {
1898                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1899                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1900                 data->auto_temp[nr][0] = reg;
1901                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1902         } else {
1903                 reg = TEMP_TO_REG(val);
1904                 data->auto_temp[nr][point] = reg;
1905                 if (has_newer_autopwm(data))
1906                         point--;
1907                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1908         }
1909         mutex_unlock(&data->update_lock);
1910         return count;
1911 }
1912
1913 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1914 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1915                             0, 1);
1916 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1917                           set_fan_div, 0);
1918
1919 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1920 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1921                             1, 1);
1922 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1923                           set_fan_div, 1);
1924
1925 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1926 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1927                             2, 1);
1928 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1929                           set_fan_div, 2);
1930
1931 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1932 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1933                             3, 1);
1934
1935 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1936 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1937                             4, 1);
1938
1939 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1940 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1941                             5, 1);
1942
1943 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1944                           show_pwm_enable, set_pwm_enable, 0);
1945 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1946 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1947                           set_pwm_freq, 0);
1948 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
1949                           show_pwm_temp_map, set_pwm_temp_map, 0);
1950 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1951                             show_auto_pwm, set_auto_pwm, 0, 0);
1952 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1953                             show_auto_pwm, set_auto_pwm, 0, 1);
1954 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1955                             show_auto_pwm, set_auto_pwm, 0, 2);
1956 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1957                             show_auto_pwm, NULL, 0, 3);
1958 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1959                             show_auto_temp, set_auto_temp, 0, 1);
1960 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1961                             show_auto_temp, set_auto_temp, 0, 0);
1962 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1963                             show_auto_temp, set_auto_temp, 0, 2);
1964 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1965                             show_auto_temp, set_auto_temp, 0, 3);
1966 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1967                             show_auto_temp, set_auto_temp, 0, 4);
1968 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
1969                             show_auto_pwm, set_auto_pwm, 0, 0);
1970 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
1971                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
1972
1973 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1974                           show_pwm_enable, set_pwm_enable, 1);
1975 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1976 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
1977 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
1978                           show_pwm_temp_map, set_pwm_temp_map, 1);
1979 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1980                             show_auto_pwm, set_auto_pwm, 1, 0);
1981 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1982                             show_auto_pwm, set_auto_pwm, 1, 1);
1983 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1984                             show_auto_pwm, set_auto_pwm, 1, 2);
1985 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1986                             show_auto_pwm, NULL, 1, 3);
1987 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1988                             show_auto_temp, set_auto_temp, 1, 1);
1989 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1990                             show_auto_temp, set_auto_temp, 1, 0);
1991 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1992                             show_auto_temp, set_auto_temp, 1, 2);
1993 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1994                             show_auto_temp, set_auto_temp, 1, 3);
1995 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1996                             show_auto_temp, set_auto_temp, 1, 4);
1997 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
1998                             show_auto_pwm, set_auto_pwm, 1, 0);
1999 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2000                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2001
2002 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2003                           show_pwm_enable, set_pwm_enable, 2);
2004 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2005 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2006 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2007                           show_pwm_temp_map, set_pwm_temp_map, 2);
2008 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2009                             show_auto_pwm, set_auto_pwm, 2, 0);
2010 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2011                             show_auto_pwm, set_auto_pwm, 2, 1);
2012 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2013                             show_auto_pwm, set_auto_pwm, 2, 2);
2014 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2015                             show_auto_pwm, NULL, 2, 3);
2016 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2017                             show_auto_temp, set_auto_temp, 2, 1);
2018 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2019                             show_auto_temp, set_auto_temp, 2, 0);
2020 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2021                             show_auto_temp, set_auto_temp, 2, 2);
2022 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2023                             show_auto_temp, set_auto_temp, 2, 3);
2024 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2025                             show_auto_temp, set_auto_temp, 2, 4);
2026 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2027                             show_auto_pwm, set_auto_pwm, 2, 0);
2028 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2029                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2030
2031 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2032                           show_pwm_enable, set_pwm_enable, 3);
2033 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2034 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2035 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2036                           show_pwm_temp_map, set_pwm_temp_map, 3);
2037 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2038                             show_auto_temp, set_auto_temp, 2, 1);
2039 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2040                             show_auto_temp, set_auto_temp, 2, 0);
2041 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2042                             show_auto_temp, set_auto_temp, 2, 2);
2043 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2044                             show_auto_temp, set_auto_temp, 2, 3);
2045 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2046                             show_auto_pwm, set_auto_pwm, 3, 0);
2047 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2048                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2049
2050 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2051                           show_pwm_enable, set_pwm_enable, 4);
2052 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2053 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2054 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2055                           show_pwm_temp_map, set_pwm_temp_map, 4);
2056 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2057                             show_auto_temp, set_auto_temp, 2, 1);
2058 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2059                             show_auto_temp, set_auto_temp, 2, 0);
2060 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2061                             show_auto_temp, set_auto_temp, 2, 2);
2062 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2063                             show_auto_temp, set_auto_temp, 2, 3);
2064 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2065                             show_auto_pwm, set_auto_pwm, 4, 0);
2066 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2067                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2068
2069 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2070                           show_pwm_enable, set_pwm_enable, 5);
2071 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2072 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2073 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2074                           show_pwm_temp_map, set_pwm_temp_map, 5);
2075 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2076                             show_auto_temp, set_auto_temp, 2, 1);
2077 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2078                             show_auto_temp, set_auto_temp, 2, 0);
2079 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2080                             show_auto_temp, set_auto_temp, 2, 2);
2081 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2082                             show_auto_temp, set_auto_temp, 2, 3);
2083 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2084                             show_auto_pwm, set_auto_pwm, 5, 0);
2085 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2086                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2087
2088 /* Alarms */
2089 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2090                            char *buf)
2091 {
2092         struct it87_data *data = it87_update_device(dev);
2093
2094         return sprintf(buf, "%u\n", data->alarms);
2095 }
2096 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2097
2098 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2099                           char *buf)
2100 {
2101         struct it87_data *data = it87_update_device(dev);
2102         int bitnr = to_sensor_dev_attr(attr)->index;
2103
2104         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2105 }
2106
2107 static ssize_t clear_intrusion(struct device *dev,
2108                                struct device_attribute *attr, const char *buf,
2109                                size_t count)
2110 {
2111         struct it87_data *data = dev_get_drvdata(dev);
2112         int config;
2113         long val;
2114
2115         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2116                 return -EINVAL;
2117
2118         mutex_lock(&data->update_lock);
2119         config = it87_read_value(data, IT87_REG_CONFIG);
2120         if (config < 0) {
2121                 count = config;
2122         } else {
2123                 config |= BIT(5);
2124                 it87_write_value(data, IT87_REG_CONFIG, config);
2125                 /* Invalidate cache to force re-read */
2126                 data->valid = 0;
2127         }
2128         mutex_unlock(&data->update_lock);
2129
2130         return count;
2131 }
2132
2133 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2134 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2135 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2136 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2137 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2138 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2139 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2140 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2141 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2142 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2143 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2144 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2145 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2146 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2147 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2148 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2149 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2150 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2151 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2152 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2153 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2154                           show_alarm, clear_intrusion, 4);
2155
2156 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2157                          char *buf)
2158 {
2159         struct it87_data *data = it87_update_device(dev);
2160         int bitnr = to_sensor_dev_attr(attr)->index;
2161
2162         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2163 }
2164
2165 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2166                         const char *buf, size_t count)
2167 {
2168         int bitnr = to_sensor_dev_attr(attr)->index;
2169         struct it87_data *data = dev_get_drvdata(dev);
2170         long val;
2171
2172         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2173                 return -EINVAL;
2174
2175         mutex_lock(&data->update_lock);
2176         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2177         if (val)
2178                 data->beeps |= BIT(bitnr);
2179         else
2180                 data->beeps &= ~BIT(bitnr);
2181         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2182         mutex_unlock(&data->update_lock);
2183         return count;
2184 }
2185
2186 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2187                           show_beep, set_beep, 1);
2188 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2189 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2190 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2191 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2192 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2193 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2194 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2195 /* fanX_beep writability is set later */
2196 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2197 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2198 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2199 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2200 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2201 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2202 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2203                           show_beep, set_beep, 2);
2204 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2205 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2206 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2207 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2208 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2209
2210 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2211                             char *buf)
2212 {
2213         struct it87_data *data = dev_get_drvdata(dev);
2214
2215         return sprintf(buf, "%u\n", data->vrm);
2216 }
2217
2218 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2219                              const char *buf, size_t count)
2220 {
2221         struct it87_data *data = dev_get_drvdata(dev);
2222         unsigned long val;
2223
2224         if (kstrtoul(buf, 10, &val) < 0)
2225                 return -EINVAL;
2226
2227         data->vrm = val;
2228
2229         return count;
2230 }
2231 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2232
2233 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2234                             char *buf)
2235 {
2236         struct it87_data *data = it87_update_device(dev);
2237
2238         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2239 }
2240 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2241
2242 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2243                           char *buf)
2244 {
2245         static const char * const labels[] = {
2246                 "+5V",
2247                 "5VSB",
2248                 "Vbat",
2249                 "AVCC",
2250         };
2251         static const char * const labels_it8721[] = {
2252                 "+3.3V",
2253                 "3VSB",
2254                 "Vbat",
2255                 "+3.3V",
2256         };
2257         struct it87_data *data = dev_get_drvdata(dev);
2258         int nr = to_sensor_dev_attr(attr)->index;
2259         const char *label;
2260
2261         if (has_vin3_5v(data) && nr == 0)
2262                 label = labels[0];
2263         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2264                  has_11mv_adc(data))
2265                 label = labels_it8721[nr];
2266         else
2267                 label = labels[nr];
2268
2269         return sprintf(buf, "%s\n", label);
2270 }
2271 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2272 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2273 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2274 /* AVCC3 */
2275 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2276
2277 static umode_t it87_in_is_visible(struct kobject *kobj,
2278                                   struct attribute *attr, int index)
2279 {
2280         struct device *dev = container_of(kobj, struct device, kobj);
2281         struct it87_data *data = dev_get_drvdata(dev);
2282         int i = index / 5;      /* voltage index */
2283         int a = index % 5;      /* attribute index */
2284
2285         if (index >= 40) {      /* in8 and higher only have input attributes */
2286                 i = index - 40 + 8;
2287                 a = 0;
2288         }
2289
2290         if (!(data->has_in & BIT(i)))
2291                 return 0;
2292
2293         if (a == 4 && !data->has_beep)
2294                 return 0;
2295
2296         return attr->mode;
2297 }
2298
2299 static struct attribute *it87_attributes_in[] = {
2300         &sensor_dev_attr_in0_input.dev_attr.attr,
2301         &sensor_dev_attr_in0_min.dev_attr.attr,
2302         &sensor_dev_attr_in0_max.dev_attr.attr,
2303         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2304         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2305
2306         &sensor_dev_attr_in1_input.dev_attr.attr,
2307         &sensor_dev_attr_in1_min.dev_attr.attr,
2308         &sensor_dev_attr_in1_max.dev_attr.attr,
2309         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2310         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2311
2312         &sensor_dev_attr_in2_input.dev_attr.attr,
2313         &sensor_dev_attr_in2_min.dev_attr.attr,
2314         &sensor_dev_attr_in2_max.dev_attr.attr,
2315         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2316         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2317
2318         &sensor_dev_attr_in3_input.dev_attr.attr,
2319         &sensor_dev_attr_in3_min.dev_attr.attr,
2320         &sensor_dev_attr_in3_max.dev_attr.attr,
2321         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2322         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2323
2324         &sensor_dev_attr_in4_input.dev_attr.attr,
2325         &sensor_dev_attr_in4_min.dev_attr.attr,
2326         &sensor_dev_attr_in4_max.dev_attr.attr,
2327         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2328         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2329
2330         &sensor_dev_attr_in5_input.dev_attr.attr,
2331         &sensor_dev_attr_in5_min.dev_attr.attr,
2332         &sensor_dev_attr_in5_max.dev_attr.attr,
2333         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2334         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2335
2336         &sensor_dev_attr_in6_input.dev_attr.attr,
2337         &sensor_dev_attr_in6_min.dev_attr.attr,
2338         &sensor_dev_attr_in6_max.dev_attr.attr,
2339         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2340         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2341
2342         &sensor_dev_attr_in7_input.dev_attr.attr,
2343         &sensor_dev_attr_in7_min.dev_attr.attr,
2344         &sensor_dev_attr_in7_max.dev_attr.attr,
2345         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2346         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2347
2348         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2349         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2350         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2351         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2352         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2353         NULL
2354 };
2355
2356 static const struct attribute_group it87_group_in = {
2357         .attrs = it87_attributes_in,
2358         .is_visible = it87_in_is_visible,
2359 };
2360
2361 static umode_t it87_temp_is_visible(struct kobject *kobj,
2362                                     struct attribute *attr, int index)
2363 {
2364         struct device *dev = container_of(kobj, struct device, kobj);
2365         struct it87_data *data = dev_get_drvdata(dev);
2366         int i = index / 7;      /* temperature index */
2367         int a = index % 7;      /* attribute index */
2368
2369         if (!(data->has_temp & BIT(i)))
2370                 return 0;
2371
2372         if (a && i >= data->num_temp_limit)
2373                 return 0;
2374
2375         if (a == 3) {
2376                 int type = get_temp_type(data, i);
2377
2378                 if (type == 0)
2379                         return 0;
2380                 if (has_bank_sel(data))
2381                         return 0444;
2382                 return attr->mode;
2383         }
2384
2385         if (a == 5 && !has_temp_offset(data))
2386                 return 0;
2387
2388         if (a == 6 && !data->has_beep)
2389                 return 0;
2390
2391         return attr->mode;
2392 }
2393
2394 static struct attribute *it87_attributes_temp[] = {
2395         &sensor_dev_attr_temp1_input.dev_attr.attr,
2396         &sensor_dev_attr_temp1_max.dev_attr.attr,
2397         &sensor_dev_attr_temp1_min.dev_attr.attr,
2398         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2399         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2400         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2401         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2402
2403         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2404         &sensor_dev_attr_temp2_max.dev_attr.attr,
2405         &sensor_dev_attr_temp2_min.dev_attr.attr,
2406         &sensor_dev_attr_temp2_type.dev_attr.attr,
2407         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2408         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2409         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2410
2411         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2412         &sensor_dev_attr_temp3_max.dev_attr.attr,
2413         &sensor_dev_attr_temp3_min.dev_attr.attr,
2414         &sensor_dev_attr_temp3_type.dev_attr.attr,
2415         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2416         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2417         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2418
2419         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2420         &sensor_dev_attr_temp4_max.dev_attr.attr,
2421         &sensor_dev_attr_temp4_min.dev_attr.attr,
2422         &sensor_dev_attr_temp4_type.dev_attr.attr,
2423         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2424         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2425         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2426
2427         &sensor_dev_attr_temp5_input.dev_attr.attr,
2428         &sensor_dev_attr_temp5_max.dev_attr.attr,
2429         &sensor_dev_attr_temp5_min.dev_attr.attr,
2430         &sensor_dev_attr_temp5_type.dev_attr.attr,
2431         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2432         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2433         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2434
2435         &sensor_dev_attr_temp6_input.dev_attr.attr,
2436         &sensor_dev_attr_temp6_max.dev_attr.attr,
2437         &sensor_dev_attr_temp6_min.dev_attr.attr,
2438         &sensor_dev_attr_temp6_type.dev_attr.attr,
2439         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2440         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2441         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2442         NULL
2443 };
2444
2445 static const struct attribute_group it87_group_temp = {
2446         .attrs = it87_attributes_temp,
2447         .is_visible = it87_temp_is_visible,
2448 };
2449
2450 static umode_t it87_is_visible(struct kobject *kobj,
2451                                struct attribute *attr, int index)
2452 {
2453         struct device *dev = container_of(kobj, struct device, kobj);
2454         struct it87_data *data = dev_get_drvdata(dev);
2455
2456         if ((index == 2 || index == 3) && !data->has_vid)
2457                 return 0;
2458
2459         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2460                 return 0;
2461
2462         return attr->mode;
2463 }
2464
2465 static struct attribute *it87_attributes[] = {
2466         &dev_attr_alarms.attr,
2467         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2468         &dev_attr_vrm.attr,                             /* 2 */
2469         &dev_attr_cpu0_vid.attr,                        /* 3 */
2470         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2471         &sensor_dev_attr_in7_label.dev_attr.attr,
2472         &sensor_dev_attr_in8_label.dev_attr.attr,
2473         &sensor_dev_attr_in9_label.dev_attr.attr,
2474         NULL
2475 };
2476
2477 static const struct attribute_group it87_group = {
2478         .attrs = it87_attributes,
2479         .is_visible = it87_is_visible,
2480 };
2481
2482 static umode_t it87_fan_is_visible(struct kobject *kobj,
2483                                    struct attribute *attr, int index)
2484 {
2485         struct device *dev = container_of(kobj, struct device, kobj);
2486         struct it87_data *data = dev_get_drvdata(dev);
2487         int i = index / 5;      /* fan index */
2488         int a = index % 5;      /* attribute index */
2489
2490         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2491                 i = (index - 15) / 4 + 3;
2492                 a = (index - 15) % 4;
2493         }
2494
2495         if (!(data->has_fan & BIT(i)))
2496                 return 0;
2497
2498         if (a == 3) {                           /* beep */
2499                 if (!data->has_beep)
2500                         return 0;
2501                 /* first fan beep attribute is writable */
2502                 if (i == __ffs(data->has_fan))
2503                         return attr->mode | S_IWUSR;
2504         }
2505
2506         if (a == 4 && has_16bit_fans(data))     /* divisor */
2507                 return 0;
2508
2509         return attr->mode;
2510 }
2511
2512 static struct attribute *it87_attributes_fan[] = {
2513         &sensor_dev_attr_fan1_input.dev_attr.attr,
2514         &sensor_dev_attr_fan1_min.dev_attr.attr,
2515         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2516         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2517         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2518
2519         &sensor_dev_attr_fan2_input.dev_attr.attr,
2520         &sensor_dev_attr_fan2_min.dev_attr.attr,
2521         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2522         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2523         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2524
2525         &sensor_dev_attr_fan3_input.dev_attr.attr,
2526         &sensor_dev_attr_fan3_min.dev_attr.attr,
2527         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2528         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2529         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2530
2531         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2532         &sensor_dev_attr_fan4_min.dev_attr.attr,
2533         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2534         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2535
2536         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2537         &sensor_dev_attr_fan5_min.dev_attr.attr,
2538         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2539         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2540
2541         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2542         &sensor_dev_attr_fan6_min.dev_attr.attr,
2543         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2544         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2545         NULL
2546 };
2547
2548 static const struct attribute_group it87_group_fan = {
2549         .attrs = it87_attributes_fan,
2550         .is_visible = it87_fan_is_visible,
2551 };
2552
2553 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2554                                    struct attribute *attr, int index)
2555 {
2556         struct device *dev = container_of(kobj, struct device, kobj);
2557         struct it87_data *data = dev_get_drvdata(dev);
2558         int i = index / 4;      /* pwm index */
2559         int a = index % 4;      /* attribute index */
2560
2561         if (!(data->has_pwm & BIT(i)))
2562                 return 0;
2563
2564         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2565         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2566                 return attr->mode | S_IWUSR;
2567
2568         /* pwm2_freq is writable if there are two pwm frequency selects */
2569         if (has_pwm_freq2(data) && i == 1 && a == 2)
2570                 return attr->mode | S_IWUSR;
2571
2572         return attr->mode;
2573 }
2574
2575 static struct attribute *it87_attributes_pwm[] = {
2576         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2577         &sensor_dev_attr_pwm1.dev_attr.attr,
2578         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2579         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2580
2581         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2582         &sensor_dev_attr_pwm2.dev_attr.attr,
2583         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2584         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2585
2586         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2587         &sensor_dev_attr_pwm3.dev_attr.attr,
2588         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2589         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2590
2591         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2592         &sensor_dev_attr_pwm4.dev_attr.attr,
2593         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2594         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2595
2596         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2597         &sensor_dev_attr_pwm5.dev_attr.attr,
2598         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2599         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2600
2601         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2602         &sensor_dev_attr_pwm6.dev_attr.attr,
2603         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2604         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2605
2606         NULL
2607 };
2608
2609 static const struct attribute_group it87_group_pwm = {
2610         .attrs = it87_attributes_pwm,
2611         .is_visible = it87_pwm_is_visible,
2612 };
2613
2614 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2615                                         struct attribute *attr, int index)
2616 {
2617         struct device *dev = container_of(kobj, struct device, kobj);
2618         struct it87_data *data = dev_get_drvdata(dev);
2619         int i = index / 11;     /* pwm index */
2620         int a = index % 11;     /* attribute index */
2621
2622         if (index >= 33) {      /* pwm 4..6 */
2623                 i = (index - 33) / 6 + 3;
2624                 a = (index - 33) % 6 + 4;
2625         }
2626
2627         if (!(data->has_pwm & BIT(i)))
2628                 return 0;
2629
2630         if (has_newer_autopwm(data)) {
2631                 if (a < 4)      /* no auto point pwm */
2632                         return 0;
2633                 if (a == 8)     /* no auto_point4 */
2634                         return 0;
2635         }
2636         if (has_old_autopwm(data)) {
2637                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2638                         return 0;
2639         }
2640
2641         return attr->mode;
2642 }
2643
2644 static struct attribute *it87_attributes_auto_pwm[] = {
2645         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2646         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2647         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2648         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2649         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2650         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2651         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2652         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2653         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2654         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2655         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2656
2657         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2658         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2659         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2660         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2661         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2662         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2663         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2664         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2665         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2666         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2667         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2668
2669         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2670         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2671         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2672         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2673         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2674         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2675         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2676         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2677         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2678         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2679         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2680
2681         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2682         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2683         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2684         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2685         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2686         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2687
2688         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2689         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2690         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2691         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2692         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2693         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2694
2695         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2696         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2697         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2698         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2699         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2700         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2701
2702         NULL,
2703 };
2704
2705 static const struct attribute_group it87_group_auto_pwm = {
2706         .attrs = it87_attributes_auto_pwm,
2707         .is_visible = it87_auto_pwm_is_visible,
2708 };
2709
2710 /* SuperIO detection - will change isa_address if a chip is found */
2711 static int __init it87_find(int sioaddr, unsigned short *address,
2712                             struct it87_sio_data *sio_data)
2713 {
2714         int err;
2715         u16 chip_type;
2716         const struct it87_devices *config;
2717
2718         err = superio_enter(sioaddr);
2719         if (err)
2720                 return err;
2721
2722         err = -ENODEV;
2723         chip_type = superio_inw(sioaddr, DEVID);
2724         if (chip_type == 0xffff)
2725                 goto exit;
2726
2727         if (force_id)
2728                 chip_type = force_id;
2729
2730         switch (chip_type) {
2731         case IT8705F_DEVID:
2732                 sio_data->type = it87;
2733                 break;
2734         case IT8712F_DEVID:
2735                 sio_data->type = it8712;
2736                 break;
2737         case IT8716F_DEVID:
2738         case IT8726F_DEVID:
2739                 sio_data->type = it8716;
2740                 break;
2741         case IT8718F_DEVID:
2742                 sio_data->type = it8718;
2743                 break;
2744         case IT8720F_DEVID:
2745                 sio_data->type = it8720;
2746                 break;
2747         case IT8721F_DEVID:
2748                 sio_data->type = it8721;
2749                 break;
2750         case IT8728F_DEVID:
2751                 sio_data->type = it8728;
2752                 break;
2753         case IT8732F_DEVID:
2754                 sio_data->type = it8732;
2755                 break;
2756         case IT8792E_DEVID:
2757                 sio_data->type = it8792;
2758                 break;
2759         case IT8771E_DEVID:
2760                 sio_data->type = it8771;
2761                 break;
2762         case IT8772E_DEVID:
2763                 sio_data->type = it8772;
2764                 break;
2765         case IT8781F_DEVID:
2766                 sio_data->type = it8781;
2767                 break;
2768         case IT8782F_DEVID:
2769                 sio_data->type = it8782;
2770                 break;
2771         case IT8783E_DEVID:
2772                 sio_data->type = it8783;
2773                 break;
2774         case IT8786E_DEVID:
2775                 sio_data->type = it8786;
2776                 break;
2777         case IT8790E_DEVID:
2778                 sio_data->type = it8790;
2779                 break;
2780         case IT8603E_DEVID:
2781         case IT8623E_DEVID:
2782                 sio_data->type = it8603;
2783                 break;
2784         case IT8607E_DEVID:
2785                 sio_data->type = it8607;
2786                 break;
2787         case IT8620E_DEVID:
2788                 sio_data->type = it8620;
2789                 break;
2790         case IT8622E_DEVID:
2791                 sio_data->type = it8622;
2792                 break;
2793         case IT8628E_DEVID:
2794                 sio_data->type = it8628;
2795                 break;
2796         case IT8655E_DEVID:
2797                 sio_data->type = it8655;
2798                 break;
2799         case IT8665E_DEVID:
2800                 sio_data->type = it8665;
2801                 break;
2802         case IT8686E_DEVID:
2803                 sio_data->type = it8686;
2804                 break;
2805         case 0xffff:    /* No device at all */
2806                 goto exit;
2807         default:
2808                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2809                 goto exit;
2810         }
2811
2812         superio_select(sioaddr, PME);
2813         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2814                 pr_info("Device not activated, skipping\n");
2815                 goto exit;
2816         }
2817
2818         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2819         if (*address == 0) {
2820                 pr_info("Base address not set, skipping\n");
2821                 goto exit;
2822         }
2823
2824         err = 0;
2825         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2826         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2827                 it87_devices[sio_data->type].suffix,
2828                 *address, sio_data->revision);
2829
2830         config = &it87_devices[sio_data->type];
2831
2832         /* in7 (VSB or VCCH5V) is always internal on some chips */
2833         if (has_in7_internal(config))
2834                 sio_data->internal |= BIT(1);
2835
2836         /* in8 (Vbat) is always internal */
2837         sio_data->internal |= BIT(2);
2838
2839         /* in9 (AVCC3), always internal if supported */
2840         if (has_avcc3(config))
2841                 sio_data->internal |= BIT(3); /* in9 is AVCC */
2842         else
2843                 sio_data->skip_in |= BIT(9);
2844
2845         if (!has_four_pwm(config))
2846                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2847         else if (!has_five_pwm(config))
2848                 sio_data->skip_pwm |= BIT(4) | BIT(5);
2849         else if (!has_six_pwm(config))
2850                 sio_data->skip_pwm |= BIT(5);
2851
2852         if (!has_vid(config))
2853                 sio_data->skip_vid = 1;
2854
2855         /* Read GPIO config and VID value from LDN 7 (GPIO) */
2856         if (sio_data->type == it87) {
2857                 /* The IT8705F has a different LD number for GPIO */
2858                 superio_select(sioaddr, 5);
2859                 sio_data->beep_pin = superio_inb(sioaddr,
2860                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2861         } else if (sio_data->type == it8783) {
2862                 int reg25, reg27, reg2a, reg2c, regef;
2863
2864                 superio_select(sioaddr, GPIO);
2865
2866                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2867                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2868                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2869                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2870                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2871
2872                 /* Check if fan3 is there or not */
2873                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2874                         sio_data->skip_fan |= BIT(2);
2875                 if ((reg25 & BIT(4)) ||
2876                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
2877                         sio_data->skip_pwm |= BIT(2);
2878
2879                 /* Check if fan2 is there or not */
2880                 if (reg27 & BIT(7))
2881                         sio_data->skip_fan |= BIT(1);
2882                 if (reg27 & BIT(3))
2883                         sio_data->skip_pwm |= BIT(1);
2884
2885                 /* VIN5 */
2886                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2887                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2888
2889                 /* VIN6 */
2890                 if (reg27 & BIT(1))
2891                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2892
2893                 /*
2894                  * VIN7
2895                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2896                  */
2897                 if (reg27 & BIT(2)) {
2898                         /*
2899                          * The data sheet is a bit unclear regarding the
2900                          * internal voltage divider for VCCH5V. It says
2901                          * "This bit enables and switches VIN7 (pin 91) to the
2902                          * internal voltage divider for VCCH5V".
2903                          * This is different to other chips, where the internal
2904                          * voltage divider would connect VIN7 to an internal
2905                          * voltage source. Maybe that is the case here as well.
2906                          *
2907                          * Since we don't know for sure, re-route it if that is
2908                          * not the case, and ask the user to report if the
2909                          * resulting voltage is sane.
2910                          */
2911                         if (!(reg2c & BIT(1))) {
2912                                 reg2c |= BIT(1);
2913                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2914                                              reg2c);
2915                                 pr_notice("Routing internal VCCH5V to in7.\n");
2916                         }
2917                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2918                         pr_notice("Please report if it displays a reasonable voltage.\n");
2919                 }
2920
2921                 if (reg2c & BIT(0))
2922                         sio_data->internal |= BIT(0);
2923                 if (reg2c & BIT(1))
2924                         sio_data->internal |= BIT(1);
2925
2926                 sio_data->beep_pin = superio_inb(sioaddr,
2927                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2928         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
2929                 int reg27, reg29;
2930
2931                 superio_select(sioaddr, GPIO);
2932
2933                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2934
2935                 /* Check if fan3 is there or not */
2936                 if (reg27 & BIT(6))
2937                         sio_data->skip_pwm |= BIT(2);
2938                 if (reg27 & BIT(7))
2939                         sio_data->skip_fan |= BIT(2);
2940
2941                 /* Check if fan2 is there or not */
2942                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2943                 if (reg29 & BIT(1))
2944                         sio_data->skip_pwm |= BIT(1);
2945                 if (reg29 & BIT(2))
2946                         sio_data->skip_fan |= BIT(1);
2947
2948                 if (sio_data->type == it8603) {
2949                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2950                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2951                 }
2952
2953                 sio_data->beep_pin = superio_inb(sioaddr,
2954                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2955         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
2956                    sio_data->type == it8686) {
2957                 int reg;
2958
2959                 superio_select(sioaddr, GPIO);
2960
2961                 /* Check for pwm5 */
2962                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2963                 if (reg & BIT(6))
2964                         sio_data->skip_pwm |= BIT(4);
2965
2966                 /* Check for fan4, fan5 */
2967                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2968                 if (!(reg & BIT(5)))
2969                         sio_data->skip_fan |= BIT(3);
2970                 if (!(reg & BIT(4)))
2971                         sio_data->skip_fan |= BIT(4);
2972
2973                 /* Check for pwm3, fan3 */
2974                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2975                 if (reg & BIT(6))
2976                         sio_data->skip_pwm |= BIT(2);
2977                 if (reg & BIT(7))
2978                         sio_data->skip_fan |= BIT(2);
2979
2980                 /* Check for pwm4 */
2981                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
2982                 if (reg & BIT(2))
2983                         sio_data->skip_pwm |= BIT(3);
2984
2985                 /* Check for pwm2, fan2 */
2986                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2987                 if (reg & BIT(1))
2988                         sio_data->skip_pwm |= BIT(1);
2989                 if (reg & BIT(2))
2990                         sio_data->skip_fan |= BIT(1);
2991                 /* Check for pwm6, fan6 */
2992                 if (!(reg & BIT(7))) {
2993                         sio_data->skip_pwm |= BIT(5);
2994                         sio_data->skip_fan |= BIT(5);
2995                 }
2996
2997                 /* Check if AVCC is on VIN3 */
2998                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2999                 if (reg & BIT(0)) {
3000                         /* For it8686, the bit just enables AVCC3 */
3001                         if (sio_data->type != it8686)
3002                                 sio_data->internal |= BIT(0);
3003                 } else {
3004                         sio_data->internal &= ~BIT(3);
3005                         sio_data->skip_in |= BIT(9);
3006                 }
3007
3008                 sio_data->beep_pin = superio_inb(sioaddr,
3009                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3010         } else if (sio_data->type == it8622) {
3011                 int reg;
3012
3013                 superio_select(sioaddr, GPIO);
3014
3015                 /* Check for pwm4, fan4 */
3016                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3017                 if (reg & BIT(6))
3018                         sio_data->skip_fan |= BIT(3);
3019                 if (reg & BIT(5))
3020                         sio_data->skip_pwm |= BIT(3);
3021
3022                 /* Check for pwm3, fan3, pwm5, fan5 */
3023                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3024                 if (reg & BIT(6))
3025                         sio_data->skip_pwm |= BIT(2);
3026                 if (reg & BIT(7))
3027                         sio_data->skip_fan |= BIT(2);
3028                 if (reg & BIT(3))
3029                         sio_data->skip_pwm |= BIT(4);
3030                 if (reg & BIT(1))
3031                         sio_data->skip_fan |= BIT(4);
3032
3033                 /* Check for pwm2, fan2 */
3034                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3035                 if (reg & BIT(1))
3036                         sio_data->skip_pwm |= BIT(1);
3037                 if (reg & BIT(2))
3038                         sio_data->skip_fan |= BIT(1);
3039
3040                 /* Check for AVCC */
3041                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3042                 if (!(reg & BIT(0)))
3043                         sio_data->skip_in |= BIT(9);
3044
3045                 sio_data->beep_pin = superio_inb(sioaddr,
3046                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3047         } else if (sio_data->type == it8732) {
3048                 int reg;
3049
3050                 superio_select(sioaddr, GPIO);
3051
3052                 /* Check for pwm2, fan2 */
3053                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3054                 if (reg & BIT(1))
3055                         sio_data->skip_pwm |= BIT(1);
3056                 if (reg & BIT(2))
3057                         sio_data->skip_fan |= BIT(1);
3058
3059                 /* Check for pwm3, fan3, fan4 */
3060                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3061                 if (reg & BIT(6))
3062                         sio_data->skip_pwm |= BIT(2);
3063                 if (reg & BIT(7))
3064                         sio_data->skip_fan |= BIT(2);
3065                 if (reg & BIT(5))
3066                         sio_data->skip_fan |= BIT(3);
3067
3068                 /* Check if AVCC is on VIN3 */
3069                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3070                 if (reg & BIT(0))
3071                         sio_data->internal |= BIT(0);
3072
3073                 sio_data->beep_pin = superio_inb(sioaddr,
3074                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3075         } else if (sio_data->type == it8655) {
3076                 int reg;
3077
3078                 superio_select(sioaddr, GPIO);
3079
3080                 /* Check for pwm2 */
3081                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3082                 if (reg & BIT(1))
3083                         sio_data->skip_pwm |= BIT(1);
3084
3085                 /* Check for fan2 */
3086                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3087                 if (reg & BIT(4))
3088                         sio_data->skip_fan |= BIT(1);
3089
3090                 /* Check for pwm3, fan3 */
3091                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3092                 if (reg & BIT(6))
3093                         sio_data->skip_pwm |= BIT(2);
3094                 if (reg & BIT(7))
3095                         sio_data->skip_fan |= BIT(2);
3096
3097                 sio_data->beep_pin = superio_inb(sioaddr,
3098                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3099         } else if (sio_data->type == it8665) {
3100                 int reg;
3101
3102                 superio_select(sioaddr, GPIO);
3103
3104                 /* Check for pwm2 */
3105                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3106                 if (reg & BIT(1))
3107                         sio_data->skip_pwm |= BIT(1);
3108
3109                 /* Check for fan2 */
3110                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3111                 if (reg & BIT(4))
3112                         sio_data->skip_fan |= BIT(1);
3113
3114                 /* Check for pwm3, fan3 */
3115                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3116                 if (reg & BIT(6))
3117                         sio_data->skip_pwm |= BIT(2);
3118                 if (reg & BIT(7))
3119                         sio_data->skip_fan |= BIT(2);
3120
3121                 /* Check for pwm5, fan5 */
3122                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3123                 if (reg & BIT(5))
3124                         sio_data->skip_pwm |= BIT(4);
3125                 if (!(reg & BIT(4)))
3126                         sio_data->skip_fan |= BIT(4);
3127
3128                 /* Check for pwm4, fan4, pwm6, fan6 */
3129                 reg = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3130                 if (reg & BIT(2))
3131                         sio_data->skip_pwm |= BIT(3);
3132                 if (reg & BIT(3))
3133                         sio_data->skip_fan |= BIT(3);
3134                 if (reg & BIT(0))
3135                         sio_data->skip_pwm |= BIT(5);
3136                 if (reg & BIT(1))
3137                         sio_data->skip_fan |= BIT(5);
3138
3139                 sio_data->beep_pin = superio_inb(sioaddr,
3140                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3141         } else {
3142                 int reg;
3143                 bool uart6;
3144
3145                 superio_select(sioaddr, GPIO);
3146
3147                 /* Check for fan4, fan5 */
3148                 if (has_five_fans(config)) {
3149                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3150                         switch (sio_data->type) {
3151                         case it8718:
3152                                 if (reg & BIT(5))
3153                                         sio_data->skip_fan |= BIT(3);
3154                                 if (reg & BIT(4))
3155                                         sio_data->skip_fan |= BIT(4);
3156                                 break;
3157                         case it8720:
3158                         case it8721:
3159                         case it8728:
3160                                 if (!(reg & BIT(5)))
3161                                         sio_data->skip_fan |= BIT(3);
3162                                 if (!(reg & BIT(4)))
3163                                         sio_data->skip_fan |= BIT(4);
3164                                 break;
3165                         default:
3166                                 break;
3167                         }
3168                 }
3169
3170                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3171                 if (!sio_data->skip_vid) {
3172                         /* We need at least 4 VID pins */
3173                         if (reg & 0x0f) {
3174                                 pr_info("VID is disabled (pins used for GPIO)\n");
3175                                 sio_data->skip_vid = 1;
3176                         }
3177                 }
3178
3179                 /* Check if fan3 is there or not */
3180                 if (reg & BIT(6))
3181                         sio_data->skip_pwm |= BIT(2);
3182                 if (reg & BIT(7))
3183                         sio_data->skip_fan |= BIT(2);
3184
3185                 /* Check if fan2 is there or not */
3186                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3187                 if (reg & BIT(1))
3188                         sio_data->skip_pwm |= BIT(1);
3189                 if (reg & BIT(2))
3190                         sio_data->skip_fan |= BIT(1);
3191
3192                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3193                     !(sio_data->skip_vid))
3194                         sio_data->vid_value = superio_inb(sioaddr,
3195                                                           IT87_SIO_VID_REG);
3196
3197                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3198
3199                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3200
3201                 /*
3202                  * The IT8720F has no VIN7 pin, so VCCH should always be
3203                  * routed internally to VIN7 with an internal divider.
3204                  * Curiously, there still is a configuration bit to control
3205                  * this, which means it can be set incorrectly. And even
3206                  * more curiously, many boards out there are improperly
3207                  * configured, even though the IT8720F datasheet claims
3208                  * that the internal routing of VCCH to VIN7 is the default
3209                  * setting. So we force the internal routing in this case.
3210                  *
3211                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3212                  * If UART6 is enabled, re-route VIN7 to the internal divider
3213                  * if that is not already the case.
3214                  */
3215                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3216                         reg |= BIT(1);
3217                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3218                         pr_notice("Routing internal VCCH to in7\n");
3219                 }
3220                 if (reg & BIT(0))
3221                         sio_data->internal |= BIT(0);
3222                 if (reg & BIT(1))
3223                         sio_data->internal |= BIT(1);
3224
3225                 /*
3226                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3227                  * While VIN7 can be routed to the internal voltage divider,
3228                  * VIN5 and VIN6 are not available if UART6 is enabled.
3229                  *
3230                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3231                  * is the temperature source. Since we can not read the
3232                  * temperature source here, skip_temp is preliminary.
3233                  */
3234                 if (uart6) {
3235                         sio_data->skip_in |= BIT(5) | BIT(6);
3236                         sio_data->skip_temp |= BIT(2);
3237                 }
3238
3239                 sio_data->beep_pin = superio_inb(sioaddr,
3240                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3241         }
3242         if (sio_data->beep_pin)
3243                 pr_info("Beeping is supported\n");
3244
3245 exit:
3246         superio_exit(sioaddr);
3247         return err;
3248 }
3249
3250 /* Called when we have found a new IT87. */
3251 static void it87_init_device(struct platform_device *pdev)
3252 {
3253         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3254         struct it87_data *data = platform_get_drvdata(pdev);
3255         int tmp, i;
3256         u8 mask;
3257
3258         /* Initialize chip specific register pointers */
3259         switch (data->type) {
3260         case it8686:
3261                 data->REG_FAN = IT87_REG_FAN;
3262                 data->REG_FANX = IT87_REG_FANX;
3263                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3264                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3265                 data->REG_PWM = IT87_REG_PWM;
3266                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3267                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3268                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3269                 break;
3270         case it8655:
3271         case it8665:
3272                 data->REG_FAN = IT87_REG_FAN_8665;
3273                 data->REG_FANX = IT87_REG_FANX_8665;
3274                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3275                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3276                 data->REG_PWM = IT87_REG_PWM_8665;
3277                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3278                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3279                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3280                 break;
3281         case it8622:
3282                 data->REG_FAN = IT87_REG_FAN;
3283                 data->REG_FANX = IT87_REG_FANX;
3284                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3285                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3286                 data->REG_PWM = IT87_REG_PWM_8665;
3287                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3288                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3289                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3290                 break;
3291         default:
3292                 data->REG_FAN = IT87_REG_FAN;
3293                 data->REG_FANX = IT87_REG_FANX;
3294                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3295                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3296                 data->REG_PWM = IT87_REG_PWM;
3297                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3298                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3299                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3300                 break;
3301         }
3302
3303         /*
3304          * For each PWM channel:
3305          * - If it is in automatic mode, setting to manual mode should set
3306          *   the fan to full speed by default.
3307          * - If it is in manual mode, we need a mapping to temperature
3308          *   channels to use when later setting to automatic mode later.
3309          *   Use a 1:1 mapping by default (we are clueless.)
3310          * In both cases, the value can (and should) be changed by the user
3311          * prior to switching to a different mode.
3312          * Note that this is no longer needed for the IT8721F and later, as
3313          * these have separate registers for the temperature mapping and the
3314          * manual duty cycle.
3315          */
3316         for (i = 0; i < NUM_AUTO_PWM; i++) {
3317                 data->pwm_temp_map[i] = i;
3318                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3319                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3320         }
3321
3322         /*
3323          * Some chips seem to have default value 0xff for all limit
3324          * registers. For low voltage limits it makes no sense and triggers
3325          * alarms, so change to 0 instead. For high temperature limits, it
3326          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3327          * but is still confusing, so change to 127 degrees C.
3328          */
3329         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3330                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3331                 if (tmp == 0xff)
3332                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3333         }
3334         for (i = 0; i < data->num_temp_limit; i++) {
3335                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3336                 if (tmp == 0xff)
3337                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3338         }
3339
3340         /*
3341          * Temperature channels are not forcibly enabled, as they can be
3342          * set to two different sensor types and we can't guess which one
3343          * is correct for a given system. These channels can be enabled at
3344          * run-time through the temp{1-3}_type sysfs accessors if needed.
3345          */
3346
3347         /* Check if voltage monitors are reset manually or by some reason */
3348         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3349         if ((tmp & 0xff) == 0) {
3350                 /* Enable all voltage monitors */
3351                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3352         }
3353
3354         /* Check if tachometers are reset manually or by some reason */
3355         mask = 0x70 & ~(sio_data->skip_fan << 4);
3356         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3357         if ((data->fan_main_ctrl & mask) == 0) {
3358                 /* Enable all fan tachometers */
3359                 data->fan_main_ctrl |= mask;
3360                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3361                                  data->fan_main_ctrl);
3362         }
3363         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3364
3365         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3366
3367         /* Set tachometers to 16-bit mode if needed */
3368         if (has_fan16_config(data)) {
3369                 if (~tmp & 0x07 & data->has_fan) {
3370                         dev_dbg(&pdev->dev,
3371                                 "Setting fan1-3 to 16-bit mode\n");
3372                         it87_write_value(data, IT87_REG_FAN_16BIT,
3373                                          tmp | 0x07);
3374                 }
3375         }
3376
3377         /* Check for additional fans */
3378         if (has_four_fans(data) && (tmp & BIT(4)))
3379                 data->has_fan |= BIT(3); /* fan4 enabled */
3380         if (has_five_fans(data) && (tmp & BIT(5)))
3381                 data->has_fan |= BIT(4); /* fan5 enabled */
3382         if (has_six_fans(data)) {
3383                 switch (data->type) {
3384                 case it8620:
3385                 case it8628:
3386                 case it8686:
3387                         if (tmp & BIT(2))
3388                                 data->has_fan |= BIT(5); /* fan6 enabled */
3389                         break;
3390                 case it8665:
3391                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3392                         if (tmp & BIT(3))
3393                                 data->has_fan |= BIT(5); /* fan6 enabled */
3394                         break;
3395                 default:
3396                         break;
3397                 }
3398         }
3399
3400         /* Fan input pins may be used for alternative functions */
3401         data->has_fan &= ~sio_data->skip_fan;
3402
3403         /* Check if pwm6 is enabled */
3404         if (has_six_pwm(data)) {
3405                 switch (data->type) {
3406                 case it8620:
3407                 case it8686:
3408                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3409                         if (!(tmp & BIT(3)))
3410                                 sio_data->skip_pwm |= BIT(5);
3411                         break;
3412                 default:
3413                         break;
3414                 }
3415         }
3416
3417         /* Start monitoring */
3418         it87_write_value(data, IT87_REG_CONFIG,
3419                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3420                          | (update_vbat ? 0x41 : 0x01));
3421 }
3422
3423 /* Return 1 if and only if the PWM interface is safe to use */
3424 static int it87_check_pwm(struct device *dev)
3425 {
3426         struct it87_data *data = dev_get_drvdata(dev);
3427         /*
3428          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3429          * and polarity set to active low is sign that this is the case so we
3430          * disable pwm control to protect the user.
3431          */
3432         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3433
3434         if ((tmp & 0x87) == 0) {
3435                 if (fix_pwm_polarity) {
3436                         /*
3437                          * The user asks us to attempt a chip reconfiguration.
3438                          * This means switching to active high polarity and
3439                          * inverting all fan speed values.
3440                          */
3441                         int i;
3442                         u8 pwm[3];
3443
3444                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3445                                 pwm[i] = it87_read_value(data,
3446                                                          data->REG_PWM[i]);
3447
3448                         /*
3449                          * If any fan is in automatic pwm mode, the polarity
3450                          * might be correct, as suspicious as it seems, so we
3451                          * better don't change anything (but still disable the
3452                          * PWM interface).
3453                          */
3454                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3455                                 dev_info(dev,
3456                                          "Reconfiguring PWM to active high polarity\n");
3457                                 it87_write_value(data, IT87_REG_FAN_CTL,
3458                                                  tmp | 0x87);
3459                                 for (i = 0; i < 3; i++)
3460                                         it87_write_value(data,
3461                                                          data->REG_PWM[i],
3462                                                          0x7f & ~pwm[i]);
3463                                 return 1;
3464                         }
3465
3466                         dev_info(dev,
3467                                  "PWM configuration is too broken to be fixed\n");
3468                 }
3469
3470                 dev_info(dev,
3471                          "Detected broken BIOS defaults, disabling PWM interface\n");
3472                 return 0;
3473         } else if (fix_pwm_polarity) {
3474                 dev_info(dev,
3475                          "PWM configuration looks sane, won't touch\n");
3476         }
3477
3478         return 1;
3479 }
3480
3481 static int it87_probe(struct platform_device *pdev)
3482 {
3483         struct it87_data *data;
3484         struct resource *res;
3485         struct device *dev = &pdev->dev;
3486         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3487         int enable_pwm_interface;
3488         struct device *hwmon_dev;
3489
3490         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3491         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3492                                  DRVNAME)) {
3493                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3494                         (unsigned long)res->start,
3495                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3496                 return -EBUSY;
3497         }
3498
3499         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3500         if (!data)
3501                 return -ENOMEM;
3502
3503         data->addr = res->start;
3504         data->type = sio_data->type;
3505         data->features = it87_devices[sio_data->type].features;
3506         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3507         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3508         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3509         data->bank = 0xff;
3510
3511         /*
3512          * IT8705F Datasheet 0.4.1, 3h == Version G.
3513          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3514          * These are the first revisions with 16-bit tachometer support.
3515          */
3516         switch (data->type) {
3517         case it87:
3518                 if (sio_data->revision >= 0x03) {
3519                         data->features &= ~FEAT_OLD_AUTOPWM;
3520                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3521                 }
3522                 break;
3523         case it8712:
3524                 if (sio_data->revision >= 0x08) {
3525                         data->features &= ~FEAT_OLD_AUTOPWM;
3526                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3527                                           FEAT_FIVE_FANS;
3528                 }
3529                 break;
3530         default:
3531                 break;
3532         }
3533
3534         /* Now, we do the remaining detection. */
3535         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3536             it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3537                 return -ENODEV;
3538
3539         platform_set_drvdata(pdev, data);
3540
3541         mutex_init(&data->update_lock);
3542
3543         /* Check PWM configuration */
3544         enable_pwm_interface = it87_check_pwm(dev);
3545
3546         /* Starting with IT8721F, we handle scaling of internal voltages */
3547         if (has_scaling(data)) {
3548                 if (sio_data->internal & BIT(0))
3549                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3550                 if (sio_data->internal & BIT(1))
3551                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3552                 if (sio_data->internal & BIT(2))
3553                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3554                 if (sio_data->internal & BIT(3))
3555                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3556         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3557                    sio_data->type == it8783) {
3558                 if (sio_data->internal & BIT(0))
3559                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3560                 if (sio_data->internal & BIT(1))
3561                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3562         }
3563
3564         data->has_temp = 0x07;
3565         if (sio_data->skip_temp & BIT(2)) {
3566                 if (sio_data->type == it8782 &&
3567                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3568                         data->has_temp &= ~BIT(2);
3569         }
3570
3571         data->in_internal = sio_data->internal;
3572         data->has_in = 0x3ff & ~sio_data->skip_in;
3573
3574         if (has_six_temp(data)) {
3575                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3576
3577                 /* Check for additional temperature sensors */
3578                 if ((reg & 0x03) >= 0x02)
3579                         data->has_temp |= BIT(3);
3580                 if (((reg >> 2) & 0x03) >= 0x02)
3581                         data->has_temp |= BIT(4);
3582                 if (((reg >> 4) & 0x03) >= 0x02)
3583                         data->has_temp |= BIT(5);
3584
3585                 /* Check for additional voltage sensors */
3586                 if ((reg & 0x03) == 0x01)
3587                         data->has_in |= BIT(10);
3588                 if (((reg >> 2) & 0x03) == 0x01)
3589                         data->has_in |= BIT(11);
3590                 if (((reg >> 4) & 0x03) == 0x01)
3591                         data->has_in |= BIT(12);
3592         }
3593
3594         data->has_beep = !!sio_data->beep_pin;
3595
3596         /* Initialize the IT87 chip */
3597         it87_init_device(pdev);
3598
3599         if (!sio_data->skip_vid) {
3600                 data->has_vid = true;
3601                 data->vrm = vid_which_vrm();
3602                 /* VID reading from Super-I/O config space if available */
3603                 data->vid = sio_data->vid_value;
3604         }
3605
3606         /* Prepare for sysfs hooks */
3607         data->groups[0] = &it87_group;
3608         data->groups[1] = &it87_group_in;
3609         data->groups[2] = &it87_group_temp;
3610         data->groups[3] = &it87_group_fan;
3611
3612         if (enable_pwm_interface) {
3613                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3614                 data->has_pwm &= ~sio_data->skip_pwm;
3615
3616                 data->groups[4] = &it87_group_pwm;
3617                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3618                         data->groups[5] = &it87_group_auto_pwm;
3619         }
3620
3621         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3622                                         it87_devices[sio_data->type].name,
3623                                         data, data->groups);
3624         return PTR_ERR_OR_ZERO(hwmon_dev);
3625 }
3626
3627 static struct platform_driver it87_driver = {
3628         .driver = {
3629                 .name   = DRVNAME,
3630         },
3631         .probe  = it87_probe,
3632 };
3633
3634 static int __init it87_device_add(int index, unsigned short address,
3635                                   const struct it87_sio_data *sio_data)
3636 {
3637         struct platform_device *pdev;
3638         struct resource res = {
3639                 .start  = address + IT87_EC_OFFSET,
3640                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3641                 .name   = DRVNAME,
3642                 .flags  = IORESOURCE_IO,
3643         };
3644         int err;
3645
3646         err = acpi_check_resource_conflict(&res);
3647         if (err)
3648                 return err;
3649
3650         pdev = platform_device_alloc(DRVNAME, address);
3651         if (!pdev)
3652                 return -ENOMEM;
3653
3654         err = platform_device_add_resources(pdev, &res, 1);
3655         if (err) {
3656                 pr_err("Device resource addition failed (%d)\n", err);
3657                 goto exit_device_put;
3658         }
3659
3660         err = platform_device_add_data(pdev, sio_data,
3661                                        sizeof(struct it87_sio_data));
3662         if (err) {
3663                 pr_err("Platform data allocation failed\n");
3664                 goto exit_device_put;
3665         }
3666
3667         err = platform_device_add(pdev);
3668         if (err) {
3669                 pr_err("Device addition failed (%d)\n", err);
3670                 goto exit_device_put;
3671         }
3672
3673         it87_pdev[index] = pdev;
3674         return 0;
3675
3676 exit_device_put:
3677         platform_device_put(pdev);
3678         return err;
3679 }
3680
3681 struct it87_dmi_data {
3682         bool sio4e_broken;      /* SIO accesses @ 0x4e are broken       */
3683         char *sio_mutex;        /* SIO ACPI mutex                       */
3684         u8 skip_pwm;            /* pwm channels to skip for this board  */
3685 };
3686
3687 /*
3688  * On Gigabyte AB350 and AX370 boards, accesses to the Super-IO chip
3689  * at address 0x4e/0x4f can result in a system hang.
3690  * Accesses to address 0x2e/0x2f need to be mutex protected.
3691  */
3692 static struct it87_dmi_data gigabyte_ab350_gaming = {
3693         .sio4e_broken = true,
3694         .sio_mutex = "\\_SB.PCI0.SBRG.SIO1.MUT0",
3695 };
3696
3697 /*
3698  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3699  * connected to a fan, but to something else. One user
3700  * has reported instant system power-off when changing
3701  * the PWM2 duty cycle, so we disable it.
3702  * I use the board name string as the trigger in case
3703  * the same board is ever used in other systems.
3704  */
3705 static struct it87_dmi_data nvidia_fn68pt = {
3706         .skip_pwm = BIT(1),
3707 };
3708
3709 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3710         {
3711                 .matches = {
3712                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3713                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming-CF"),
3714                 },
3715                 .driver_data = &gigabyte_ab350_gaming,
3716         },
3717         {
3718                 .matches = {
3719                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3720                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming 3-CF"),
3721                 },
3722                 .driver_data = &gigabyte_ab350_gaming,
3723         },
3724         {
3725                 .matches = {
3726                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3727                         DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming K7"),
3728                 },
3729                 .driver_data = &gigabyte_ab350_gaming,
3730         },
3731         {
3732                 .matches = {
3733                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3734                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3735                 },
3736                 .driver_data = &nvidia_fn68pt,
3737         },
3738         { }
3739 };
3740
3741 static int __init sm_it87_init(void)
3742 {
3743         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3744         struct it87_dmi_data *dmi_data = NULL;
3745         int sioaddr[2] = { REG_2E, REG_4E };
3746         struct it87_sio_data sio_data;
3747         unsigned short isa_address;
3748         bool found = false;
3749         int i, err;
3750
3751         if (dmi)
3752                 dmi_data = dmi->driver_data;
3753
3754         if (dmi_data) {
3755                 it87_sio4e_broken = dmi_data->sio4e_broken;
3756 #ifdef __IT87_USE_ACPI_MUTEX
3757                 if (dmi_data->sio_mutex) {
3758                         static acpi_status status;
3759
3760                         status = acpi_get_handle(NULL, dmi_data->sio_mutex,
3761                                                  &it87_acpi_sio_handle);
3762                         if (ACPI_SUCCESS(status)) {
3763                                 it87_acpi_sio_mutex = dmi_data->sio_mutex;
3764                                 pr_debug("Found ACPI SIO mutex %s\n",
3765                                          dmi_data->sio_mutex);
3766                         } else {
3767                                 pr_warn("ACPI SIO mutex %s not found\n",
3768                                         dmi_data->sio_mutex);
3769                         }
3770                 }
3771 #endif /* __IT87_USE_ACPI_MUTEX */
3772         }
3773
3774         err = platform_driver_register(&it87_driver);
3775         if (err)
3776                 return err;
3777
3778         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3779                 /*
3780                  * Accessing the second Super-IO chi can result in board
3781                  * hangs. Disable until we figure out what is going on.
3782                  */
3783                 if (it87_sio4e_broken && sioaddr[i] == 0x4e)
3784                         continue;
3785                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3786                 isa_address = 0;
3787                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3788                 if (err || isa_address == 0)
3789                         continue;
3790
3791                 if (dmi_data)
3792                         sio_data.skip_pwm |= dmi_data->skip_pwm;
3793                 err = it87_device_add(i, isa_address, &sio_data);
3794                 if (err)
3795                         goto exit_dev_unregister;
3796                 found = true;
3797         }
3798
3799         if (!found) {
3800                 err = -ENODEV;
3801                 goto exit_unregister;
3802         }
3803         return 0;
3804
3805 exit_dev_unregister:
3806         /* NULL check handled by platform_device_unregister */
3807         platform_device_unregister(it87_pdev[0]);
3808 exit_unregister:
3809         platform_driver_unregister(&it87_driver);
3810         return err;
3811 }
3812
3813 static void __exit sm_it87_exit(void)
3814 {
3815         /* NULL check handled by platform_device_unregister */
3816         platform_device_unregister(it87_pdev[1]);
3817         platform_device_unregister(it87_pdev[0]);
3818         platform_driver_unregister(&it87_driver);
3819 }
3820
3821 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3822 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3823 module_param(update_vbat, bool, 0);
3824 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3825 module_param(fix_pwm_polarity, bool, 0);
3826 MODULE_PARM_DESC(fix_pwm_polarity,
3827                  "Force PWM polarity to active high (DANGEROUS)");
3828 MODULE_LICENSE("GPL");
3829
3830 module_init(sm_it87_init);
3831 module_exit(sm_it87_exit);